1 //===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PowerPC specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/PPCMCTargetDesc.h"
14 #include "MCTargetDesc/PPCInstPrinter.h"
15 #include "MCTargetDesc/PPCMCAsmInfo.h"
16 #include "PPCELFStreamer.h"
17 #include "PPCTargetStreamer.h"
18 #include "PPCXCOFFStreamer.h"
19 #include "TargetInfo/PowerPCTargetInfo.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/BinaryFormat/ELF.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCAssembler.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDwarf.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInstrAnalysis.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCObjectWriter.h"
33 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/MC/MCSectionXCOFF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/MC/MCSymbolELF.h"
39 #include "llvm/MC/MCSymbolXCOFF.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/FormattedStream.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/TargetParser/Triple.h"
47
48 using namespace llvm;
49
50 #define GET_INSTRINFO_MC_DESC
51 #define ENABLE_INSTR_PREDICATE_VERIFIER
52 #include "PPCGenInstrInfo.inc"
53
54 #define GET_SUBTARGETINFO_MC_DESC
55 #include "PPCGenSubtargetInfo.inc"
56
57 #define GET_REGINFO_MC_DESC
58 #include "PPCGenRegisterInfo.inc"
59
60 /// stripRegisterPrefix - This method strips the character prefix from a
61 /// register name so that only the number is left. Used by for linux asm.
stripRegisterPrefix(const char * RegName)62 const char *PPC::stripRegisterPrefix(const char *RegName) {
63 switch (RegName[0]) {
64 case 'a':
65 if (RegName[1] == 'c' && RegName[2] == 'c')
66 return RegName + 3;
67 break;
68 case 'f':
69 if (RegName[1] == 'p')
70 return RegName + 2;
71 [[fallthrough]];
72 case 'r':
73 case 'v':
74 if (RegName[1] == 's') {
75 if (RegName[2] == 'p')
76 return RegName + 3;
77 return RegName + 2;
78 }
79 return RegName + 1;
80 case 'c':
81 if (RegName[1] == 'r')
82 return RegName + 2;
83 break;
84 case 'w':
85 // For wacc and wacc_hi
86 if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
87 if (RegName[4] == '_')
88 return RegName + 7;
89 else
90 return RegName + 4;
91 }
92 break;
93 case 'd':
94 // For dmr, dmrp, dmrrow, dmrrowp
95 if (RegName[1] == 'm' && RegName[2] == 'r') {
96 if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
97 RegName[6] == 'p')
98 return RegName + 7;
99 else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
100 return RegName + 6;
101 else if (RegName[3] == 'p')
102 return RegName + 4;
103 else
104 return RegName + 3;
105 }
106 break;
107 }
108
109 return RegName;
110 }
111
112 /// getRegNumForOperand - some operands use different numbering schemes
113 /// for the same registers. For example, a VSX instruction may have any of
114 /// vs0-vs63 allocated whereas an Altivec instruction could only have
115 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
116 /// register number needed for the opcode/operand number combination.
117 /// The operand number argument will be useful when we need to extend this
118 /// to instructions that use both Altivec and VSX numbering (for different
119 /// operands).
getRegNumForOperand(const MCInstrDesc & Desc,unsigned Reg,unsigned OpNo)120 unsigned PPC::getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
121 unsigned OpNo) {
122 int16_t regClass = Desc.operands()[OpNo].RegClass;
123 switch (regClass) {
124 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
125 // VSX32-VSX63 during encoding/disassembling
126 case PPC::VSSRCRegClassID:
127 case PPC::VSFRCRegClassID:
128 if (PPC::isVFRegister(Reg))
129 return PPC::VSX32 + (Reg - PPC::VF0);
130 break;
131 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
132 // VSX32-VSX63 during encoding/disassembling
133 case PPC::VSRCRegClassID:
134 if (PPC::isVRRegister(Reg))
135 return PPC::VSX32 + (Reg - PPC::V0);
136 break;
137 // Other RegClass doesn't need mapping
138 default:
139 break;
140 }
141 return Reg;
142 }
143
PPCTargetStreamer(MCStreamer & S)144 PPCTargetStreamer::PPCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
145
146 // Pin the vtable to this file.
147 PPCTargetStreamer::~PPCTargetStreamer() = default;
148
createPPCMCInstrInfo()149 static MCInstrInfo *createPPCMCInstrInfo() {
150 MCInstrInfo *X = new MCInstrInfo();
151 InitPPCMCInstrInfo(X);
152 return X;
153 }
154
createPPCMCRegisterInfo(const Triple & TT)155 static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
156 bool isPPC64 =
157 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
158 unsigned Flavour = isPPC64 ? 0 : 1;
159 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
160
161 MCRegisterInfo *X = new MCRegisterInfo();
162 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
163 return X;
164 }
165
createPPCMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)166 static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
167 StringRef CPU, StringRef FS) {
168 // Set some default feature to MC layer.
169 std::string FullFS = std::string(FS);
170
171 if (TT.isOSAIX()) {
172 if (!FullFS.empty())
173 FullFS = "+aix," + FullFS;
174 else
175 FullFS = "+aix";
176 }
177
178 return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FullFS);
179 }
180
createPPCMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TheTriple,const MCTargetOptions & Options)181 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
182 const Triple &TheTriple,
183 const MCTargetOptions &Options) {
184 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
185 TheTriple.getArch() == Triple::ppc64le);
186
187 MCAsmInfo *MAI;
188 if (TheTriple.isOSBinFormatXCOFF())
189 MAI = new PPCXCOFFMCAsmInfo(isPPC64, TheTriple);
190 else
191 MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
192
193 // Initial state of the frame pointer is R1.
194 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
195 MCCFIInstruction Inst =
196 MCCFIInstruction::cfiDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
197 MAI->addInitialFrameState(Inst);
198
199 return MAI;
200 }
201
202 static MCStreamer *
createPPCELFStreamer(const Triple & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)203 createPPCELFStreamer(const Triple &T, MCContext &Context,
204 std::unique_ptr<MCAsmBackend> &&MAB,
205 std::unique_ptr<MCObjectWriter> &&OW,
206 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll) {
207 return createPPCELFStreamer(Context, std::move(MAB), std::move(OW),
208 std::move(Emitter));
209 }
210
createPPCXCOFFStreamer(const Triple & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)211 static MCStreamer *createPPCXCOFFStreamer(
212 const Triple &T, MCContext &Context, std::unique_ptr<MCAsmBackend> &&MAB,
213 std::unique_ptr<MCObjectWriter> &&OW,
214 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll) {
215 return createPPCXCOFFStreamer(Context, std::move(MAB), std::move(OW),
216 std::move(Emitter));
217 }
218
219 namespace {
220
221 class PPCTargetAsmStreamer : public PPCTargetStreamer {
222 formatted_raw_ostream &OS;
223
224 public:
PPCTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS)225 PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
226 : PPCTargetStreamer(S), OS(OS) {}
227
emitTCEntry(const MCSymbol & S,MCSymbolRefExpr::VariantKind Kind)228 void emitTCEntry(const MCSymbol &S,
229 MCSymbolRefExpr::VariantKind Kind) override {
230 if (const MCSymbolXCOFF *XSym = dyn_cast<MCSymbolXCOFF>(&S)) {
231 MCSymbolXCOFF *TCSym =
232 cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly())
233 ->getQualNameSymbol();
234 // On AIX, we have a region handle (symbol@m) and the variable offset
235 // (symbol@{gd|ie|le}) for TLS variables, depending on the TLS model.
236 if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD ||
237 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM ||
238 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE ||
239 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE)
240 OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@"
241 << MCSymbolRefExpr::getVariantKindName(Kind) << '\n';
242 else
243 OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n';
244
245 if (TCSym->hasRename())
246 Streamer.emitXCOFFRenameDirective(TCSym, TCSym->getSymbolTableName());
247 return;
248 }
249
250 OS << "\t.tc " << S.getName() << "[TC]," << S.getName() << '\n';
251 }
252
emitMachine(StringRef CPU)253 void emitMachine(StringRef CPU) override {
254 OS << "\t.machine " << CPU << '\n';
255 }
256
emitAbiVersion(int AbiVersion)257 void emitAbiVersion(int AbiVersion) override {
258 OS << "\t.abiversion " << AbiVersion << '\n';
259 }
260
emitLocalEntry(MCSymbolELF * S,const MCExpr * LocalOffset)261 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
262 const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
263
264 OS << "\t.localentry\t";
265 S->print(OS, MAI);
266 OS << ", ";
267 LocalOffset->print(OS, MAI);
268 OS << '\n';
269 }
270 };
271
272 class PPCTargetELFStreamer : public PPCTargetStreamer {
273 public:
PPCTargetELFStreamer(MCStreamer & S)274 PPCTargetELFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
275
getStreamer()276 MCELFStreamer &getStreamer() {
277 return static_cast<MCELFStreamer &>(Streamer);
278 }
279
emitTCEntry(const MCSymbol & S,MCSymbolRefExpr::VariantKind Kind)280 void emitTCEntry(const MCSymbol &S,
281 MCSymbolRefExpr::VariantKind Kind) override {
282 // Creates a R_PPC64_TOC relocation
283 Streamer.emitValueToAlignment(Align(8));
284 Streamer.emitSymbolValue(&S, 8);
285 }
286
emitMachine(StringRef CPU)287 void emitMachine(StringRef CPU) override {
288 // FIXME: Is there anything to do in here or does this directive only
289 // limit the parser?
290 }
291
emitAbiVersion(int AbiVersion)292 void emitAbiVersion(int AbiVersion) override {
293 MCAssembler &MCA = getStreamer().getAssembler();
294 unsigned Flags = MCA.getELFHeaderEFlags();
295 Flags &= ~ELF::EF_PPC64_ABI;
296 Flags |= (AbiVersion & ELF::EF_PPC64_ABI);
297 MCA.setELFHeaderEFlags(Flags);
298 }
299
emitLocalEntry(MCSymbolELF * S,const MCExpr * LocalOffset)300 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
301 MCAssembler &MCA = getStreamer().getAssembler();
302
303 // encodePPC64LocalEntryOffset will report an error if it cannot
304 // encode LocalOffset.
305 unsigned Encoded = encodePPC64LocalEntryOffset(LocalOffset);
306
307 unsigned Other = S->getOther();
308 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
309 Other |= Encoded;
310 S->setOther(Other);
311
312 // For GAS compatibility, unless we already saw a .abiversion directive,
313 // set e_flags to indicate ELFv2 ABI.
314 unsigned Flags = MCA.getELFHeaderEFlags();
315 if ((Flags & ELF::EF_PPC64_ABI) == 0)
316 MCA.setELFHeaderEFlags(Flags | 2);
317 }
318
emitAssignment(MCSymbol * S,const MCExpr * Value)319 void emitAssignment(MCSymbol *S, const MCExpr *Value) override {
320 auto *Symbol = cast<MCSymbolELF>(S);
321
322 // When encoding an assignment to set symbol A to symbol B, also copy
323 // the st_other bits encoding the local entry point offset.
324 if (copyLocalEntry(Symbol, Value))
325 UpdateOther.insert(Symbol);
326 else
327 UpdateOther.erase(Symbol);
328 }
329
finish()330 void finish() override {
331 for (auto *Sym : UpdateOther)
332 if (Sym->isVariable())
333 copyLocalEntry(Sym, Sym->getVariableValue());
334
335 // Clear the set of symbols that needs to be updated so the streamer can
336 // be reused without issues.
337 UpdateOther.clear();
338 }
339
340 private:
341 SmallPtrSet<MCSymbolELF *, 32> UpdateOther;
342
copyLocalEntry(MCSymbolELF * D,const MCExpr * S)343 bool copyLocalEntry(MCSymbolELF *D, const MCExpr *S) {
344 auto *Ref = dyn_cast<const MCSymbolRefExpr>(S);
345 if (!Ref)
346 return false;
347 const auto &RhsSym = cast<MCSymbolELF>(Ref->getSymbol());
348 unsigned Other = D->getOther();
349 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
350 Other |= RhsSym.getOther() & ELF::STO_PPC64_LOCAL_MASK;
351 D->setOther(Other);
352 return true;
353 }
354
encodePPC64LocalEntryOffset(const MCExpr * LocalOffset)355 unsigned encodePPC64LocalEntryOffset(const MCExpr *LocalOffset) {
356 MCAssembler &MCA = getStreamer().getAssembler();
357 int64_t Offset;
358 if (!LocalOffset->evaluateAsAbsolute(Offset, MCA))
359 MCA.getContext().reportError(LocalOffset->getLoc(),
360 ".localentry expression must be absolute");
361
362 switch (Offset) {
363 default:
364 MCA.getContext().reportError(
365 LocalOffset->getLoc(), ".localentry expression must be a power of 2");
366 return 0;
367 case 0:
368 return 0;
369 case 1:
370 return 1 << ELF::STO_PPC64_LOCAL_BIT;
371 case 4:
372 case 8:
373 case 16:
374 case 32:
375 case 64:
376 return Log2_32(Offset) << ELF::STO_PPC64_LOCAL_BIT;
377 }
378 }
379 };
380
381 class PPCTargetMachOStreamer : public PPCTargetStreamer {
382 public:
PPCTargetMachOStreamer(MCStreamer & S)383 PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
384
emitTCEntry(const MCSymbol & S,MCSymbolRefExpr::VariantKind Kind)385 void emitTCEntry(const MCSymbol &S,
386 MCSymbolRefExpr::VariantKind Kind) override {
387 llvm_unreachable("Unknown pseudo-op: .tc");
388 }
389
emitMachine(StringRef CPU)390 void emitMachine(StringRef CPU) override {
391 // FIXME: We should update the CPUType, CPUSubType in the Object file if
392 // the new values are different from the defaults.
393 }
394
emitAbiVersion(int AbiVersion)395 void emitAbiVersion(int AbiVersion) override {
396 llvm_unreachable("Unknown pseudo-op: .abiversion");
397 }
398
emitLocalEntry(MCSymbolELF * S,const MCExpr * LocalOffset)399 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
400 llvm_unreachable("Unknown pseudo-op: .localentry");
401 }
402 };
403
404 class PPCTargetXCOFFStreamer : public PPCTargetStreamer {
405 public:
PPCTargetXCOFFStreamer(MCStreamer & S)406 PPCTargetXCOFFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
407
emitTCEntry(const MCSymbol & S,MCSymbolRefExpr::VariantKind Kind)408 void emitTCEntry(const MCSymbol &S,
409 MCSymbolRefExpr::VariantKind Kind) override {
410 const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
411 const unsigned PointerSize = MAI->getCodePointerSize();
412 Streamer.emitValueToAlignment(Align(PointerSize));
413 Streamer.emitValue(MCSymbolRefExpr::create(&S, Kind, Streamer.getContext()),
414 PointerSize);
415 }
416
emitMachine(StringRef CPU)417 void emitMachine(StringRef CPU) override {
418 llvm_unreachable("Machine pseudo-ops are invalid for XCOFF.");
419 }
420
emitAbiVersion(int AbiVersion)421 void emitAbiVersion(int AbiVersion) override {
422 llvm_unreachable("ABI-version pseudo-ops are invalid for XCOFF.");
423 }
424
emitLocalEntry(MCSymbolELF * S,const MCExpr * LocalOffset)425 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
426 llvm_unreachable("Local-entry pseudo-ops are invalid for XCOFF.");
427 }
428 };
429
430 } // end anonymous namespace
431
createAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint,bool isVerboseAsm)432 static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
433 formatted_raw_ostream &OS,
434 MCInstPrinter *InstPrint,
435 bool isVerboseAsm) {
436 return new PPCTargetAsmStreamer(S, OS);
437 }
438
createNullTargetStreamer(MCStreamer & S)439 static MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) {
440 return new PPCTargetStreamer(S);
441 }
442
443 static MCTargetStreamer *
createObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)444 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
445 const Triple &TT = STI.getTargetTriple();
446 if (TT.isOSBinFormatELF())
447 return new PPCTargetELFStreamer(S);
448 if (TT.isOSBinFormatXCOFF())
449 return new PPCTargetXCOFFStreamer(S);
450 return new PPCTargetMachOStreamer(S);
451 }
452
createPPCMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)453 static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
454 unsigned SyntaxVariant,
455 const MCAsmInfo &MAI,
456 const MCInstrInfo &MII,
457 const MCRegisterInfo &MRI) {
458 return new PPCInstPrinter(MAI, MII, MRI, T);
459 }
460
461 namespace {
462
463 class PPCMCInstrAnalysis : public MCInstrAnalysis {
464 public:
PPCMCInstrAnalysis(const MCInstrInfo * Info)465 explicit PPCMCInstrAnalysis(const MCInstrInfo *Info)
466 : MCInstrAnalysis(Info) {}
467
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const468 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
469 uint64_t &Target) const override {
470 unsigned NumOps = Inst.getNumOperands();
471 if (NumOps == 0 ||
472 Info->get(Inst.getOpcode()).operands()[NumOps - 1].OperandType !=
473 MCOI::OPERAND_PCREL)
474 return false;
475 Target = Addr + Inst.getOperand(NumOps - 1).getImm() * Size;
476 return true;
477 }
478 };
479
480 } // end anonymous namespace
481
createPPCMCInstrAnalysis(const MCInstrInfo * Info)482 static MCInstrAnalysis *createPPCMCInstrAnalysis(const MCInstrInfo *Info) {
483 return new PPCMCInstrAnalysis(Info);
484 }
485
LLVMInitializePowerPCTargetMC()486 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTargetMC() {
487 for (Target *T : {&getThePPC32Target(), &getThePPC32LETarget(),
488 &getThePPC64Target(), &getThePPC64LETarget()}) {
489 // Register the MC asm info.
490 RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
491
492 // Register the MC instruction info.
493 TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo);
494
495 // Register the MC register info.
496 TargetRegistry::RegisterMCRegInfo(*T, createPPCMCRegisterInfo);
497
498 // Register the MC subtarget info.
499 TargetRegistry::RegisterMCSubtargetInfo(*T, createPPCMCSubtargetInfo);
500
501 // Register the MC instruction analyzer.
502 TargetRegistry::RegisterMCInstrAnalysis(*T, createPPCMCInstrAnalysis);
503
504 // Register the MC Code Emitter
505 TargetRegistry::RegisterMCCodeEmitter(*T, createPPCMCCodeEmitter);
506
507 // Register the asm backend.
508 TargetRegistry::RegisterMCAsmBackend(*T, createPPCAsmBackend);
509
510 // Register the elf streamer.
511 TargetRegistry::RegisterELFStreamer(*T, createPPCELFStreamer);
512
513 // Register the XCOFF streamer.
514 TargetRegistry::RegisterXCOFFStreamer(*T, createPPCXCOFFStreamer);
515
516 // Register the object target streamer.
517 TargetRegistry::RegisterObjectTargetStreamer(*T,
518 createObjectTargetStreamer);
519
520 // Register the asm target streamer.
521 TargetRegistry::RegisterAsmTargetStreamer(*T, createAsmTargetStreamer);
522
523 // Register the null target streamer.
524 TargetRegistry::RegisterNullTargetStreamer(*T, createNullTargetStreamer);
525
526 // Register the MCInstPrinter.
527 TargetRegistry::RegisterMCInstPrinter(*T, createPPCMCInstPrinter);
528 }
529 }
530