1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/TargetRegistry.h"
25 
26 using namespace llvm;
27 
getUnconditionalBranch(const MipsSubtarget & STI)28 static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
29   if (STI.inMicroMipsMode())
30     return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
31   return STI.isPositionIndependent() ? Mips::B : Mips::J;
32 }
33 
MipsSEInstrInfo(const MipsSubtarget & STI)34 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
35     : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
36 
getRegisterInfo() const37 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
38   return RI;
39 }
40 
41 /// isLoadFromStackSlot - If the specified machine instruction is a direct
42 /// load from a stack slot, return the virtual or physical register number of
43 /// the destination along with the FrameIndex of the loaded stack slot.  If
44 /// not, return 0.  This predicate must return 0 if the instruction has
45 /// any side effects other than loading from the stack slot.
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const46 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
47                                               int &FrameIndex) const {
48   unsigned Opc = MI.getOpcode();
49 
50   if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
51       (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
52     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
53         (MI.getOperand(2).isImm()) && // the imm is zero
54         (isZeroImm(MI.getOperand(2)))) {
55       FrameIndex = MI.getOperand(1).getIndex();
56       return MI.getOperand(0).getReg();
57     }
58   }
59 
60   return 0;
61 }
62 
63 /// isStoreToStackSlot - If the specified machine instruction is a direct
64 /// store to a stack slot, return the virtual or physical register number of
65 /// the source reg along with the FrameIndex of the loaded stack slot.  If
66 /// not, return 0.  This predicate must return 0 if the instruction has
67 /// any side effects other than storing to the stack slot.
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const68 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
69                                              int &FrameIndex) const {
70   unsigned Opc = MI.getOpcode();
71 
72   if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
73       (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
74     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
75         (MI.getOperand(2).isImm()) && // the imm is zero
76         (isZeroImm(MI.getOperand(2)))) {
77       FrameIndex = MI.getOperand(1).getIndex();
78       return MI.getOperand(0).getReg();
79     }
80   }
81   return 0;
82 }
83 
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const84 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
85                                   MachineBasicBlock::iterator I,
86                                   const DebugLoc &DL, unsigned DestReg,
87                                   unsigned SrcReg, bool KillSrc) const {
88   unsigned Opc = 0, ZeroReg = 0;
89   bool isMicroMips = Subtarget.inMicroMipsMode();
90 
91   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
92     if (Mips::GPR32RegClass.contains(SrcReg)) {
93       if (isMicroMips)
94         Opc = Mips::MOVE16_MM;
95       else
96         Opc = Mips::OR, ZeroReg = Mips::ZERO;
97     } else if (Mips::CCRRegClass.contains(SrcReg))
98       Opc = Mips::CFC1;
99     else if (Mips::FGR32RegClass.contains(SrcReg))
100       Opc = Mips::MFC1;
101     else if (Mips::HI32RegClass.contains(SrcReg)) {
102       Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
103       SrcReg = 0;
104     } else if (Mips::LO32RegClass.contains(SrcReg)) {
105       Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
106       SrcReg = 0;
107     } else if (Mips::HI32DSPRegClass.contains(SrcReg))
108       Opc = Mips::MFHI_DSP;
109     else if (Mips::LO32DSPRegClass.contains(SrcReg))
110       Opc = Mips::MFLO_DSP;
111     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
112       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
113         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
114       return;
115     }
116     else if (Mips::MSACtrlRegClass.contains(SrcReg))
117       Opc = Mips::CFCMSA;
118   }
119   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
120     if (Mips::CCRRegClass.contains(DestReg))
121       Opc = Mips::CTC1;
122     else if (Mips::FGR32RegClass.contains(DestReg))
123       Opc = Mips::MTC1;
124     else if (Mips::HI32RegClass.contains(DestReg))
125       Opc = Mips::MTHI, DestReg = 0;
126     else if (Mips::LO32RegClass.contains(DestReg))
127       Opc = Mips::MTLO, DestReg = 0;
128     else if (Mips::HI32DSPRegClass.contains(DestReg))
129       Opc = Mips::MTHI_DSP;
130     else if (Mips::LO32DSPRegClass.contains(DestReg))
131       Opc = Mips::MTLO_DSP;
132     else if (Mips::DSPCCRegClass.contains(DestReg)) {
133       BuildMI(MBB, I, DL, get(Mips::WRDSP))
134         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
135         .addReg(DestReg, RegState::ImplicitDefine);
136       return;
137     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
138       BuildMI(MBB, I, DL, get(Mips::CTCMSA))
139           .addReg(DestReg)
140           .addReg(SrcReg, getKillRegState(KillSrc));
141       return;
142     }
143   }
144   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
145     Opc = Mips::FMOV_S;
146   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
147     Opc = Mips::FMOV_D32;
148   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
149     Opc = Mips::FMOV_D64;
150   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
151     if (Mips::GPR64RegClass.contains(SrcReg))
152       Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
153     else if (Mips::HI64RegClass.contains(SrcReg))
154       Opc = Mips::MFHI64, SrcReg = 0;
155     else if (Mips::LO64RegClass.contains(SrcReg))
156       Opc = Mips::MFLO64, SrcReg = 0;
157     else if (Mips::FGR64RegClass.contains(SrcReg))
158       Opc = Mips::DMFC1;
159   }
160   else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
161     if (Mips::HI64RegClass.contains(DestReg))
162       Opc = Mips::MTHI64, DestReg = 0;
163     else if (Mips::LO64RegClass.contains(DestReg))
164       Opc = Mips::MTLO64, DestReg = 0;
165     else if (Mips::FGR64RegClass.contains(DestReg))
166       Opc = Mips::DMTC1;
167   }
168   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
169     if (Mips::MSA128BRegClass.contains(SrcReg))
170       Opc = Mips::MOVE_V;
171   }
172 
173   assert(Opc && "Cannot copy registers");
174 
175   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
176 
177   if (DestReg)
178     MIB.addReg(DestReg, RegState::Define);
179 
180   if (SrcReg)
181     MIB.addReg(SrcReg, getKillRegState(KillSrc));
182 
183   if (ZeroReg)
184     MIB.addReg(ZeroReg);
185 }
186 
isORCopyInst(const MachineInstr & MI)187 static bool isORCopyInst(const MachineInstr &MI) {
188   switch (MI.getOpcode()) {
189   default:
190     break;
191   case Mips::OR_MM:
192   case Mips::OR:
193     if (MI.getOperand(2).getReg() == Mips::ZERO)
194       return true;
195     break;
196   case Mips::OR64:
197     if (MI.getOperand(2).getReg() == Mips::ZERO_64)
198       return true;
199     break;
200   }
201   return false;
202 }
203 
204 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
205 /// if it is WRDSP instruction.
isReadOrWriteToDSPReg(const MachineInstr & MI,bool & isWrite)206 static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
207   switch (MI.getOpcode()) {
208   default:
209    return false;
210   case Mips::WRDSP:
211   case Mips::WRDSP_MM:
212     isWrite = true;
213     break;
214   case Mips::RDDSP:
215   case Mips::RDDSP_MM:
216     isWrite = false;
217     break;
218   }
219   return true;
220 }
221 
222 /// We check for the common case of 'or', as it's MIPS' preferred instruction
223 /// for GPRs but we have to check the operands to ensure that is the case.
224 /// Other move instructions for MIPS are directly identifiable.
isCopyInstrImpl(const MachineInstr & MI,const MachineOperand * & Src,const MachineOperand * & Dest) const225 bool MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
226                                       const MachineOperand *&Src,
227                                       const MachineOperand *&Dest) const {
228   bool isDSPControlWrite = false;
229   // Condition is made to match the creation of WRDSP/RDDSP copy instruction
230   // from copyPhysReg function.
231   if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
232     if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
233       return false;
234     else if (isDSPControlWrite) {
235       Src = &MI.getOperand(0);
236       Dest = &MI.getOperand(2);
237     } else {
238       Dest = &MI.getOperand(0);
239       Src = &MI.getOperand(2);
240     }
241     return true;
242   } else if (MI.isMoveReg() || isORCopyInst(MI)) {
243     Dest = &MI.getOperand(0);
244     Src = &MI.getOperand(1);
245     return true;
246   }
247   return false;
248 }
249 
250 void MipsSEInstrInfo::
storeRegToStack(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,int64_t Offset) const251 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
252                 unsigned SrcReg, bool isKill, int FI,
253                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
254                 int64_t Offset) const {
255   DebugLoc DL;
256   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
257 
258   unsigned Opc = 0;
259 
260   if (Mips::GPR32RegClass.hasSubClassEq(RC))
261     Opc = Mips::SW;
262   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
263     Opc = Mips::SD;
264   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
265     Opc = Mips::STORE_ACC64;
266   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
267     Opc = Mips::STORE_ACC64DSP;
268   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
269     Opc = Mips::STORE_ACC128;
270   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
271     Opc = Mips::STORE_CCOND_DSP;
272   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
273     Opc = Mips::SWC1;
274   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
275     Opc = Mips::SDC1;
276   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
277     Opc = Mips::SDC164;
278   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
279     Opc = Mips::ST_B;
280   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
281            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
282     Opc = Mips::ST_H;
283   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
284            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
285     Opc = Mips::ST_W;
286   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
287            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
288     Opc = Mips::ST_D;
289   else if (Mips::LO32RegClass.hasSubClassEq(RC))
290     Opc = Mips::SW;
291   else if (Mips::LO64RegClass.hasSubClassEq(RC))
292     Opc = Mips::SD;
293   else if (Mips::HI32RegClass.hasSubClassEq(RC))
294     Opc = Mips::SW;
295   else if (Mips::HI64RegClass.hasSubClassEq(RC))
296     Opc = Mips::SD;
297   else if (Mips::DSPRRegClass.hasSubClassEq(RC))
298     Opc = Mips::SWDSP;
299 
300   // Hi, Lo are normally caller save but they are callee save
301   // for interrupt handling.
302   const Function &Func = MBB.getParent()->getFunction();
303   if (Func.hasFnAttribute("interrupt")) {
304     if (Mips::HI32RegClass.hasSubClassEq(RC)) {
305       BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
306       SrcReg = Mips::K0;
307     } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
308       BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
309       SrcReg = Mips::K0_64;
310     } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
311       BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
312       SrcReg = Mips::K0;
313     } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
314       BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
315       SrcReg = Mips::K0_64;
316     }
317   }
318 
319   assert(Opc && "Register class not handled!");
320   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
321     .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
322 }
323 
324 void MipsSEInstrInfo::
loadRegFromStack(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,int64_t Offset) const325 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
326                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
327                  const TargetRegisterInfo *TRI, int64_t Offset) const {
328   DebugLoc DL;
329   if (I != MBB.end()) DL = I->getDebugLoc();
330   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
331   unsigned Opc = 0;
332 
333   const Function &Func = MBB.getParent()->getFunction();
334   bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
335                          (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
336                           DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
337 
338   if (Mips::GPR32RegClass.hasSubClassEq(RC))
339     Opc = Mips::LW;
340   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
341     Opc = Mips::LD;
342   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
343     Opc = Mips::LOAD_ACC64;
344   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
345     Opc = Mips::LOAD_ACC64DSP;
346   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
347     Opc = Mips::LOAD_ACC128;
348   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
349     Opc = Mips::LOAD_CCOND_DSP;
350   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
351     Opc = Mips::LWC1;
352   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
353     Opc = Mips::LDC1;
354   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
355     Opc = Mips::LDC164;
356   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
357     Opc = Mips::LD_B;
358   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
359            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
360     Opc = Mips::LD_H;
361   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
362            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
363     Opc = Mips::LD_W;
364   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
365            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
366     Opc = Mips::LD_D;
367   else if (Mips::HI32RegClass.hasSubClassEq(RC))
368     Opc = Mips::LW;
369   else if (Mips::HI64RegClass.hasSubClassEq(RC))
370     Opc = Mips::LD;
371   else if (Mips::LO32RegClass.hasSubClassEq(RC))
372     Opc = Mips::LW;
373   else if (Mips::LO64RegClass.hasSubClassEq(RC))
374     Opc = Mips::LD;
375   else if (Mips::DSPRRegClass.hasSubClassEq(RC))
376     Opc = Mips::LWDSP;
377 
378   assert(Opc && "Register class not handled!");
379 
380   if (!ReqIndirectLoad)
381     BuildMI(MBB, I, DL, get(Opc), DestReg)
382         .addFrameIndex(FI)
383         .addImm(Offset)
384         .addMemOperand(MMO);
385   else {
386     // Load HI/LO through K0. Notably the DestReg is encoded into the
387     // instruction itself.
388     unsigned Reg = Mips::K0;
389     unsigned LdOp = Mips::MTLO;
390     if (DestReg == Mips::HI0)
391       LdOp = Mips::MTHI;
392 
393     if (Subtarget.getABI().ArePtrs64bit()) {
394       Reg = Mips::K0_64;
395       if (DestReg == Mips::HI0_64)
396         LdOp = Mips::MTHI64;
397       else
398         LdOp = Mips::MTLO64;
399     }
400 
401     BuildMI(MBB, I, DL, get(Opc), Reg)
402         .addFrameIndex(FI)
403         .addImm(Offset)
404         .addMemOperand(MMO);
405     BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
406   }
407 }
408 
expandPostRAPseudo(MachineInstr & MI) const409 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
410   MachineBasicBlock &MBB = *MI.getParent();
411   bool isMicroMips = Subtarget.inMicroMipsMode();
412   unsigned Opc;
413 
414   switch (MI.getDesc().getOpcode()) {
415   default:
416     return false;
417   case Mips::RetRA:
418     expandRetRA(MBB, MI);
419     break;
420   case Mips::ERet:
421     expandERet(MBB, MI);
422     break;
423   case Mips::PseudoMFHI:
424     expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
425     break;
426   case Mips::PseudoMFHI_MM:
427     expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
428     break;
429   case Mips::PseudoMFLO:
430     expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
431     break;
432   case Mips::PseudoMFLO_MM:
433     expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
434     break;
435   case Mips::PseudoMFHI64:
436     expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
437     break;
438   case Mips::PseudoMFLO64:
439     expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
440     break;
441   case Mips::PseudoMTLOHI:
442     expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
443     break;
444   case Mips::PseudoMTLOHI64:
445     expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
446     break;
447   case Mips::PseudoMTLOHI_DSP:
448     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
449     break;
450   case Mips::PseudoMTLOHI_MM:
451     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
452     break;
453   case Mips::PseudoCVT_S_W:
454     expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
455     break;
456   case Mips::PseudoCVT_D32_W:
457     Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
458     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
459     break;
460   case Mips::PseudoCVT_S_L:
461     expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
462     break;
463   case Mips::PseudoCVT_D64_W:
464     Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
465     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
466     break;
467   case Mips::PseudoCVT_D64_L:
468     expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
469     break;
470   case Mips::BuildPairF64:
471     expandBuildPairF64(MBB, MI, isMicroMips, false);
472     break;
473   case Mips::BuildPairF64_64:
474     expandBuildPairF64(MBB, MI, isMicroMips, true);
475     break;
476   case Mips::ExtractElementF64:
477     expandExtractElementF64(MBB, MI, isMicroMips, false);
478     break;
479   case Mips::ExtractElementF64_64:
480     expandExtractElementF64(MBB, MI, isMicroMips, true);
481     break;
482   case Mips::MIPSeh_return32:
483   case Mips::MIPSeh_return64:
484     expandEhReturn(MBB, MI);
485     break;
486   }
487 
488   MBB.erase(MI);
489   return true;
490 }
491 
492 /// getOppositeBranchOpc - Return the inverse of the specified
493 /// opcode, e.g. turning BEQ to BNE.
getOppositeBranchOpc(unsigned Opc) const494 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
495   switch (Opc) {
496   default:           llvm_unreachable("Illegal opcode!");
497   case Mips::BEQ:    return Mips::BNE;
498   case Mips::BEQ_MM: return Mips::BNE_MM;
499   case Mips::BNE:    return Mips::BEQ;
500   case Mips::BNE_MM: return Mips::BEQ_MM;
501   case Mips::BGTZ:   return Mips::BLEZ;
502   case Mips::BGEZ:   return Mips::BLTZ;
503   case Mips::BLTZ:   return Mips::BGEZ;
504   case Mips::BLEZ:   return Mips::BGTZ;
505   case Mips::BGTZ_MM:   return Mips::BLEZ_MM;
506   case Mips::BGEZ_MM:   return Mips::BLTZ_MM;
507   case Mips::BLTZ_MM:   return Mips::BGEZ_MM;
508   case Mips::BLEZ_MM:   return Mips::BGTZ_MM;
509   case Mips::BEQ64:  return Mips::BNE64;
510   case Mips::BNE64:  return Mips::BEQ64;
511   case Mips::BGTZ64: return Mips::BLEZ64;
512   case Mips::BGEZ64: return Mips::BLTZ64;
513   case Mips::BLTZ64: return Mips::BGEZ64;
514   case Mips::BLEZ64: return Mips::BGTZ64;
515   case Mips::BC1T:   return Mips::BC1F;
516   case Mips::BC1F:   return Mips::BC1T;
517   case Mips::BC1T_MM:   return Mips::BC1F_MM;
518   case Mips::BC1F_MM:   return Mips::BC1T_MM;
519   case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
520   case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
521   case Mips::BEQZC_MM:  return Mips::BNEZC_MM;
522   case Mips::BNEZC_MM:  return Mips::BEQZC_MM;
523   case Mips::BEQZC:  return Mips::BNEZC;
524   case Mips::BNEZC:  return Mips::BEQZC;
525   case Mips::BLEZC:  return Mips::BGTZC;
526   case Mips::BGEZC:  return Mips::BLTZC;
527   case Mips::BGEC:   return Mips::BLTC;
528   case Mips::BGTZC:  return Mips::BLEZC;
529   case Mips::BLTZC:  return Mips::BGEZC;
530   case Mips::BLTC:   return Mips::BGEC;
531   case Mips::BGEUC:  return Mips::BLTUC;
532   case Mips::BLTUC:  return Mips::BGEUC;
533   case Mips::BEQC:   return Mips::BNEC;
534   case Mips::BNEC:   return Mips::BEQC;
535   case Mips::BC1EQZ: return Mips::BC1NEZ;
536   case Mips::BC1NEZ: return Mips::BC1EQZ;
537   case Mips::BEQZC_MMR6:  return Mips::BNEZC_MMR6;
538   case Mips::BNEZC_MMR6:  return Mips::BEQZC_MMR6;
539   case Mips::BLEZC_MMR6:  return Mips::BGTZC_MMR6;
540   case Mips::BGEZC_MMR6:  return Mips::BLTZC_MMR6;
541   case Mips::BGEC_MMR6:   return Mips::BLTC_MMR6;
542   case Mips::BGTZC_MMR6:  return Mips::BLEZC_MMR6;
543   case Mips::BLTZC_MMR6:  return Mips::BGEZC_MMR6;
544   case Mips::BLTC_MMR6:   return Mips::BGEC_MMR6;
545   case Mips::BGEUC_MMR6:  return Mips::BLTUC_MMR6;
546   case Mips::BLTUC_MMR6:  return Mips::BGEUC_MMR6;
547   case Mips::BEQC_MMR6:   return Mips::BNEC_MMR6;
548   case Mips::BNEC_MMR6:   return Mips::BEQC_MMR6;
549   case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
550   case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
551   case Mips::BEQZC64:  return Mips::BNEZC64;
552   case Mips::BNEZC64:  return Mips::BEQZC64;
553   case Mips::BEQC64:   return Mips::BNEC64;
554   case Mips::BNEC64:   return Mips::BEQC64;
555   case Mips::BGEC64:   return Mips::BLTC64;
556   case Mips::BGEUC64:  return Mips::BLTUC64;
557   case Mips::BLTC64:   return Mips::BGEC64;
558   case Mips::BLTUC64:  return Mips::BGEUC64;
559   case Mips::BGTZC64:  return Mips::BLEZC64;
560   case Mips::BGEZC64:  return Mips::BLTZC64;
561   case Mips::BLTZC64:  return Mips::BGEZC64;
562   case Mips::BLEZC64:  return Mips::BGTZC64;
563   case Mips::BBIT0:  return Mips::BBIT1;
564   case Mips::BBIT1:  return Mips::BBIT0;
565   case Mips::BBIT032:  return Mips::BBIT132;
566   case Mips::BBIT132:  return Mips::BBIT032;
567   case Mips::BZ_B:   return Mips::BNZ_B;
568   case Mips::BZ_H:   return Mips::BNZ_H;
569   case Mips::BZ_W:   return Mips::BNZ_W;
570   case Mips::BZ_D:   return Mips::BNZ_D;
571   case Mips::BZ_V:   return Mips::BNZ_V;
572   case Mips::BNZ_B:  return Mips::BZ_B;
573   case Mips::BNZ_H:  return Mips::BZ_H;
574   case Mips::BNZ_W:  return Mips::BZ_W;
575   case Mips::BNZ_D:  return Mips::BZ_D;
576   case Mips::BNZ_V:  return Mips::BZ_V;
577   }
578 }
579 
580 /// Adjust SP by Amount bytes.
adjustStackPtr(unsigned SP,int64_t Amount,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const581 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
582                                      MachineBasicBlock &MBB,
583                                      MachineBasicBlock::iterator I) const {
584   MipsABIInfo ABI = Subtarget.getABI();
585   DebugLoc DL;
586   unsigned ADDiu = ABI.GetPtrAddiuOp();
587 
588   if (Amount == 0)
589     return;
590 
591   if (isInt<16>(Amount)) {
592     // addi sp, sp, amount
593     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
594   } else {
595     // For numbers which are not 16bit integers we synthesize Amount inline
596     // then add or subtract it from sp.
597     unsigned Opc = ABI.GetPtrAdduOp();
598     if (Amount < 0) {
599       Opc = ABI.GetPtrSubuOp();
600       Amount = -Amount;
601     }
602     unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
603     BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
604   }
605 }
606 
607 /// This function generates the sequence of instructions needed to get the
608 /// result of adding register REG and immediate IMM.
loadImmediate(int64_t Imm,MachineBasicBlock & MBB,MachineBasicBlock::iterator II,const DebugLoc & DL,unsigned * NewImm) const609 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
610                                         MachineBasicBlock::iterator II,
611                                         const DebugLoc &DL,
612                                         unsigned *NewImm) const {
613   MipsAnalyzeImmediate AnalyzeImm;
614   const MipsSubtarget &STI = Subtarget;
615   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
616   unsigned Size = STI.isABI_N64() ? 64 : 32;
617   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
618   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
619   const TargetRegisterClass *RC = STI.isABI_N64() ?
620     &Mips::GPR64RegClass : &Mips::GPR32RegClass;
621   bool LastInstrIsADDiu = NewImm;
622 
623   const MipsAnalyzeImmediate::InstSeq &Seq =
624     AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
625   MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
626 
627   assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
628 
629   // The first instruction can be a LUi, which is different from other
630   // instructions (ADDiu, ORI and SLL) in that it does not have a register
631   // operand.
632   unsigned Reg = RegInfo.createVirtualRegister(RC);
633 
634   if (Inst->Opc == LUi)
635     BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
636   else
637     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
638       .addImm(SignExtend64<16>(Inst->ImmOpnd));
639 
640   // Build the remaining instructions in Seq.
641   for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
642     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
643       .addImm(SignExtend64<16>(Inst->ImmOpnd));
644 
645   if (LastInstrIsADDiu)
646     *NewImm = Inst->ImmOpnd;
647 
648   return Reg;
649 }
650 
getAnalyzableBrOpc(unsigned Opc) const651 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
652   return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||
653           Opc == Mips::BNE_MM || Opc == Mips::BGTZ   || Opc == Mips::BGEZ   ||
654           Opc == Mips::BLTZ   || Opc == Mips::BLEZ   || Opc == Mips::BEQ64  ||
655           Opc == Mips::BNE64  || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
656           Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T   ||
657           Opc == Mips::BC1F   || Opc == Mips::B      || Opc == Mips::J      ||
658           Opc == Mips::J_MM   || Opc == Mips::B_MM   || Opc == Mips::BEQZC_MM ||
659           Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC   ||
660           Opc == Mips::BLTC   || Opc == Mips::BGEC   || Opc == Mips::BLTUC  ||
661           Opc == Mips::BGEUC  || Opc == Mips::BGTZC  || Opc == Mips::BLEZC  ||
662           Opc == Mips::BGEZC  || Opc == Mips::BLTZC  || Opc == Mips::BEQZC  ||
663           Opc == Mips::BNEZC  || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
664           Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
665           Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
666           Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
667           Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
668           Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
669           Opc == Mips::BBIT132 ||  Opc == Mips::BC_MMR6 ||
670           Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
671           Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
672           Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
673           Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
674           Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
675           Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
676 }
677 
expandRetRA(MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const678 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
679                                   MachineBasicBlock::iterator I) const {
680 
681   MachineInstrBuilder MIB;
682   if (Subtarget.isGP64bit())
683     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
684               .addReg(Mips::RA_64, RegState::Undef);
685   else
686     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
687               .addReg(Mips::RA, RegState::Undef);
688 
689   // Retain any imp-use flags.
690   for (auto & MO : I->operands()) {
691     if (MO.isImplicit())
692       MIB.add(MO);
693   }
694 }
695 
expandERet(MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const696 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
697                                  MachineBasicBlock::iterator I) const {
698   BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
699 }
700 
701 std::pair<bool, bool>
compareOpndSize(unsigned Opc,const MachineFunction & MF) const702 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
703                                  const MachineFunction &MF) const {
704   const MCInstrDesc &Desc = get(Opc);
705   assert(Desc.NumOperands == 2 && "Unary instruction expected.");
706   const MipsRegisterInfo *RI = &getRegisterInfo();
707   unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
708   unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
709 
710   return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
711 }
712 
expandPseudoMFHiLo(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned NewOpc) const713 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
714                                          MachineBasicBlock::iterator I,
715                                          unsigned NewOpc) const {
716   BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
717 }
718 
expandPseudoMTLoHi(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned LoOpc,unsigned HiOpc,bool HasExplicitDef) const719 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
720                                          MachineBasicBlock::iterator I,
721                                          unsigned LoOpc,
722                                          unsigned HiOpc,
723                                          bool HasExplicitDef) const {
724   // Expand
725   //  lo_hi pseudomtlohi $gpr0, $gpr1
726   // to these two instructions:
727   //  mtlo $gpr0
728   //  mthi $gpr1
729 
730   DebugLoc DL = I->getDebugLoc();
731   const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
732   MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
733   MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
734 
735   // Add lo/hi registers if the mtlo/hi instructions created have explicit
736   // def registers.
737   if (HasExplicitDef) {
738     unsigned DstReg = I->getOperand(0).getReg();
739     unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
740     unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
741     LoInst.addReg(DstLo, RegState::Define);
742     HiInst.addReg(DstHi, RegState::Define);
743   }
744 
745   LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
746   HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
747 }
748 
expandCvtFPInt(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned CvtOpc,unsigned MovOpc,bool IsI64) const749 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
750                                      MachineBasicBlock::iterator I,
751                                      unsigned CvtOpc, unsigned MovOpc,
752                                      bool IsI64) const {
753   const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
754   const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
755   unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
756   unsigned KillSrc =  getKillRegState(Src.isKill());
757   DebugLoc DL = I->getDebugLoc();
758   bool DstIsLarger, SrcIsLarger;
759 
760   std::tie(DstIsLarger, SrcIsLarger) =
761       compareOpndSize(CvtOpc, *MBB.getParent());
762 
763   if (DstIsLarger)
764     TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
765 
766   if (SrcIsLarger)
767     DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
768 
769   BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
770   BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
771 }
772 
expandExtractElementF64(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,bool isMicroMips,bool FP64) const773 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
774                                               MachineBasicBlock::iterator I,
775                                               bool isMicroMips,
776                                               bool FP64) const {
777   unsigned DstReg = I->getOperand(0).getReg();
778   unsigned SrcReg = I->getOperand(1).getReg();
779   unsigned N = I->getOperand(2).getImm();
780   DebugLoc dl = I->getDebugLoc();
781 
782   assert(N < 2 && "Invalid immediate");
783   unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
784   unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
785 
786   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
787   // in MipsSEFrameLowering.cpp.
788   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
789 
790   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
791   // in MipsSEFrameLowering.cpp.
792   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
793 
794   if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
795     // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
796     //        claim to read the whole 64-bits as part of a white lie used to
797     //        temporarily work around a widespread bug in the -mfp64 support.
798     //        The problem is that none of the 32-bit fpu ops mention the fact
799     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
800     //        requires a major overhaul of the FPU implementation which can't
801     //        be done right now due to time constraints.
802     //        MFHC1 is one of two instructions that are affected since they are
803     //        the only instructions that don't read the lower 32-bits.
804     //        We therefore pretend that it reads the bottom 32-bits to
805     //        artificially create a dependency and prevent the scheduler
806     //        changing the behaviour of the code.
807     BuildMI(MBB, I, dl,
808             get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
809                             : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
810             DstReg)
811         .addReg(SrcReg);
812   } else
813     BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
814 }
815 
expandBuildPairF64(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,bool isMicroMips,bool FP64) const816 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
817                                          MachineBasicBlock::iterator I,
818                                          bool isMicroMips, bool FP64) const {
819   unsigned DstReg = I->getOperand(0).getReg();
820   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
821   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
822   DebugLoc dl = I->getDebugLoc();
823   const TargetRegisterInfo &TRI = getRegisterInfo();
824 
825   // When mthc1 is available, use:
826   //   mtc1 Lo, $fp
827   //   mthc1 Hi, $fp
828   //
829   // Otherwise, for O32 FPXX ABI:
830   //   spill + reload via ldc1
831   // This case is handled by the frame lowering code.
832   //
833   // Otherwise, for FP32:
834   //   mtc1 Lo, $fp
835   //   mtc1 Hi, $fp + 1
836   //
837   // The case where dmtc1 is available doesn't need to be handled here
838   // because it never creates a BuildPairF64 node.
839 
840   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
841   // in MipsSEFrameLowering.cpp.
842   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
843 
844   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
845   // in MipsSEFrameLowering.cpp.
846   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
847 
848   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
849     .addReg(LoReg);
850 
851   if (Subtarget.hasMTHC1()) {
852     // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
853     //        around a widespread bug in the -mfp64 support.
854     //        The problem is that none of the 32-bit fpu ops mention the fact
855     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
856     //        requires a major overhaul of the FPU implementation which can't
857     //        be done right now due to time constraints.
858     //        MTHC1 is one of two instructions that are affected since they are
859     //        the only instructions that don't read the lower 32-bits.
860     //        We therefore pretend that it reads the bottom 32-bits to
861     //        artificially create a dependency and prevent the scheduler
862     //        changing the behaviour of the code.
863     BuildMI(MBB, I, dl,
864             get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
865                             : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
866             DstReg)
867         .addReg(DstReg)
868         .addReg(HiReg);
869   } else if (Subtarget.isABI_FPXX())
870     llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
871   else
872     BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
873       .addReg(HiReg);
874 }
875 
expandEhReturn(MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const876 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
877                                      MachineBasicBlock::iterator I) const {
878   // This pseudo instruction is generated as part of the lowering of
879   // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
880   // indirect jump to TargetReg
881   MipsABIInfo ABI = Subtarget.getABI();
882   unsigned ADDU = ABI.GetPtrAdduOp();
883   unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
884   unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
885   unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
886   unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
887   unsigned OffsetReg = I->getOperand(0).getReg();
888   unsigned TargetReg = I->getOperand(1).getReg();
889 
890   // addu $ra, $v0, $zero
891   // addu $sp, $sp, $v1
892   // jr   $ra (via RetRA)
893   const TargetMachine &TM = MBB.getParent()->getTarget();
894   if (TM.isPositionIndependent())
895     BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
896         .addReg(TargetReg)
897         .addReg(ZERO);
898   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
899       .addReg(TargetReg)
900       .addReg(ZERO);
901   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
902   expandRetRA(MBB, I);
903 }
904 
createMipsSEInstrInfo(const MipsSubtarget & STI)905 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
906   return new MipsSEInstrInfo(STI);
907 }
908