1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips MSA ASE instructions.
11//
12//===----------------------------------------------------------------------===//
13
14def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
16                                      SDTCisInt<1>,
17                                      SDTCisSameAs<1, 2>,
18                                      SDTCisVT<3, OtherVT>]>;
19def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
20                                       SDTCisFP<1>,
21                                       SDTCisSameAs<1, 2>,
22                                       SDTCisVT<3, OtherVT>]>;
23def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24                                    SDTCisInt<1>, SDTCisVec<1>,
25                                    SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27                                   SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29                                   SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
30def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
31                                     SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
32                                     SDTCisVT<4, i32>]>;
33
34def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
35def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
36def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
37def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
38def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
39                      [SDNPCommutative, SDNPAssociative]>;
40def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
41def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
42def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
43def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
44def MipsILVL  : SDNode<"MipsISD::ILVL",  SDT_ILV>;
45def MipsILVR  : SDNode<"MipsISD::ILVR",  SDT_ILV>;
46def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
47def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
48def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
49def MipsFMS   : SDNode<"MipsISD::FMS", SDTFPTernaryOp>;
50
51def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
52def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
53
54def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
55    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
56def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
57    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
58
59def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
60def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
61def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
62def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
63
64// Operands
65
66def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
67
68// Pattern fragments
69def vextract_sext_i8  : PatFrag<(ops node:$vec, node:$idx),
70                                (MipsVExtractSExt node:$vec, node:$idx, i8)>;
71def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
72                                (MipsVExtractSExt node:$vec, node:$idx, i16)>;
73def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
74                                (MipsVExtractSExt node:$vec, node:$idx, i32)>;
75def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
76                                (MipsVExtractSExt node:$vec, node:$idx, i64)>;
77
78def vextract_zext_i8  : PatFrag<(ops node:$vec, node:$idx),
79                                (MipsVExtractZExt node:$vec, node:$idx, i8)>;
80def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
81                                (MipsVExtractZExt node:$vec, node:$idx, i16)>;
82def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
83                                (MipsVExtractZExt node:$vec, node:$idx, i32)>;
84def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
85                                (MipsVExtractZExt node:$vec, node:$idx, i64)>;
86
87def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
88    (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
89def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
90    (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
91def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
92    (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
93def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
94    (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
95
96def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
97    (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
98def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
99    (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
100def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
101    (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
102def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
103    (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
104
105class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
106  PatFrag<(ops node:$lhs, node:$rhs),
107          (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
108
109// ISD::SETFALSE cannot occur
110def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
111def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
112def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
113def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
114def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
115def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
116def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
117def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
118def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
119def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
120def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
121def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
122def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
123def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
124def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
125def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
126def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
127def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
128def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
129def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
130def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
131def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
132def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
133def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
134def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
135def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
136def vfsetun_v4f32  : vfsetcc_type<v4i32, v4f32, SETUO>;
137def vfsetun_v2f64  : vfsetcc_type<v2i64, v2f64, SETUO>;
138def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
139def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
140def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
141def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
142def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
143def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
144def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
145def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
146def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
147def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
148def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
149def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
150// ISD::SETTRUE cannot occur
151// ISD::SETFALSE2 cannot occur
152// ISD::SETTRUE2 cannot occur
153
154class vsetcc_type<ValueType ResTy, CondCode CC> :
155  PatFrag<(ops node:$lhs, node:$rhs),
156          (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
157
158def vseteq_v16i8  : vsetcc_type<v16i8, SETEQ>;
159def vseteq_v8i16  : vsetcc_type<v8i16, SETEQ>;
160def vseteq_v4i32  : vsetcc_type<v4i32, SETEQ>;
161def vseteq_v2i64  : vsetcc_type<v2i64, SETEQ>;
162def vsetle_v16i8  : vsetcc_type<v16i8, SETLE>;
163def vsetle_v8i16  : vsetcc_type<v8i16, SETLE>;
164def vsetle_v4i32  : vsetcc_type<v4i32, SETLE>;
165def vsetle_v2i64  : vsetcc_type<v2i64, SETLE>;
166def vsetlt_v16i8  : vsetcc_type<v16i8, SETLT>;
167def vsetlt_v8i16  : vsetcc_type<v8i16, SETLT>;
168def vsetlt_v4i32  : vsetcc_type<v4i32, SETLT>;
169def vsetlt_v2i64  : vsetcc_type<v2i64, SETLT>;
170def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
171def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
172def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
173def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
174def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
175def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
176def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
177def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
178
179def vsplati8  : PatFrag<(ops node:$e0),
180                        (v16i8 (build_vector node:$e0, node:$e0,
181                                             node:$e0, node:$e0,
182                                             node:$e0, node:$e0,
183                                             node:$e0, node:$e0,
184                                             node:$e0, node:$e0,
185                                             node:$e0, node:$e0,
186                                             node:$e0, node:$e0,
187                                             node:$e0, node:$e0))>;
188def vsplati16 : PatFrag<(ops node:$e0),
189                        (v8i16 (build_vector node:$e0, node:$e0,
190                                             node:$e0, node:$e0,
191                                             node:$e0, node:$e0,
192                                             node:$e0, node:$e0))>;
193def vsplati32 : PatFrag<(ops node:$e0),
194                        (v4i32 (build_vector node:$e0, node:$e0,
195                                             node:$e0, node:$e0))>;
196
197def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
198  APInt Imm;
199  SDNode *BV = N->getOperand(0).getNode();
200  EVT EltTy = N->getValueType(0).getVectorElementType();
201
202  return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
203         Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
204}]>;
205
206def vsplati64 : PatFrag<(ops node:$e0),
207                        (v2i64 (build_vector node:$e0, node:$e0))>;
208
209def vsplati64_splat_d : PatFrag<(ops node:$e0),
210                                (v2i64 (bitconvert
211                                         (v4i32 (and
212                                           (v4i32 (build_vector node:$e0,
213                                                                node:$e0,
214                                                                node:$e0,
215                                                                node:$e0)),
216                                           vsplati64_imm_eq_1))))>;
217
218def vsplatf32 : PatFrag<(ops node:$e0),
219                        (v4f32 (build_vector node:$e0, node:$e0,
220                                             node:$e0, node:$e0))>;
221def vsplatf64 : PatFrag<(ops node:$e0),
222                        (v2f64 (build_vector node:$e0, node:$e0))>;
223
224def vsplati8_elt  : PatFrag<(ops node:$v, node:$i),
225                            (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
226def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
227                            (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
228def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
229                            (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
230def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
231                            (MipsVSHF (vsplati64_splat_d node:$i),
232                                      node:$v, node:$v)>;
233
234class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
235                   SDNodeXForm xform = NOOP_SDNodeXForm>
236  : PatLeaf<frag, pred, xform> {
237  Operand OpClass = opclass;
238}
239
240class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
241                          list<SDNode> roots = [],
242                          list<SDNodeProperty> props = []> :
243  ComplexPattern<ty, numops, fn, roots, props> {
244  Operand OpClass = opclass;
245}
246
247def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
248                                         "selectVSplatUimm3",
249                                         [build_vector, bitconvert]>;
250
251def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
252                                         "selectVSplatUimm4",
253                                         [build_vector, bitconvert]>;
254
255def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
256                                         "selectVSplatUimm5",
257                                         [build_vector, bitconvert]>;
258
259def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
260                                         "selectVSplatUimm8",
261                                         [build_vector, bitconvert]>;
262
263def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
264                                         "selectVSplatSimm5",
265                                         [build_vector, bitconvert]>;
266
267def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
268                                          "selectVSplatUimm3",
269                                          [build_vector, bitconvert]>;
270
271def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
272                                          "selectVSplatUimm4",
273                                          [build_vector, bitconvert]>;
274
275def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
276                                          "selectVSplatUimm5",
277                                          [build_vector, bitconvert]>;
278
279def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
280                                          "selectVSplatSimm5",
281                                          [build_vector, bitconvert]>;
282
283def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
284                                          "selectVSplatUimm2",
285                                          [build_vector, bitconvert]>;
286
287def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
288                                          "selectVSplatUimm5",
289                                          [build_vector, bitconvert]>;
290
291def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
292                                          "selectVSplatSimm5",
293                                          [build_vector, bitconvert]>;
294
295def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
296                                          "selectVSplatUimm1",
297                                          [build_vector, bitconvert]>;
298
299def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
300                                          "selectVSplatUimm5",
301                                          [build_vector, bitconvert]>;
302
303def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
304                                          "selectVSplatUimm6",
305                                          [build_vector, bitconvert]>;
306
307def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
308                                          "selectVSplatSimm5",
309                                          [build_vector, bitconvert]>;
310
311// Any build_vector that is a constant splat with a value that is an exact
312// power of 2
313def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
314                                      [build_vector, bitconvert]>;
315
316// Any build_vector that is a constant splat with a value that is the bitwise
317// inverse of an exact power of 2
318def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
319                                          [build_vector, bitconvert]>;
320
321// Any build_vector that is a constant splat with only a consecutive sequence
322// of left-most bits set.
323def vsplat_maskl_bits_uimm3
324    : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL",
325                          [build_vector, bitconvert]>;
326def vsplat_maskl_bits_uimm4
327    : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL",
328                          [build_vector, bitconvert]>;
329def vsplat_maskl_bits_uimm5
330    : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL",
331                          [build_vector, bitconvert]>;
332def vsplat_maskl_bits_uimm6
333    : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL",
334                          [build_vector, bitconvert]>;
335
336// Any build_vector that is a constant splat with only a consecutive sequence
337// of right-most bits set.
338def vsplat_maskr_bits_uimm3
339    : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR",
340                          [build_vector, bitconvert]>;
341def vsplat_maskr_bits_uimm4
342    : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR",
343                          [build_vector, bitconvert]>;
344def vsplat_maskr_bits_uimm5
345    : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR",
346                          [build_vector, bitconvert]>;
347def vsplat_maskr_bits_uimm6
348    : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR",
349                          [build_vector, bitconvert]>;
350
351// Any build_vector that is a constant splat with a value that equals 1
352// FIXME: These should be a ComplexPattern but we can't use them because the
353//        ISel generator requires the uses to have a name, but providing a name
354//        causes other errors ("used in pattern but not operand list")
355def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
356  APInt Imm;
357  EVT EltTy = N->getValueType(0).getVectorElementType();
358
359  return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
360         Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
361}]>;
362
363def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
364                      (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
365                                          immAllOnesV))>;
366def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
367                      (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
368                                          immAllOnesV))>;
369def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
370                      (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
371                                          immAllOnesV))>;
372def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
373                      (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
374                                               node:$wt),
375                                          (bitconvert (v4i32 immAllOnesV))))>;
376
377def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
378                      (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
379def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
380                      (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
381def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
382                      (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
383def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
384                      (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
385                                          node:$wt))>;
386
387def vbset_b : PatFrag<(ops node:$ws, node:$wt),
388                      (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
389def vbset_h : PatFrag<(ops node:$ws, node:$wt),
390                      (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
391def vbset_w : PatFrag<(ops node:$ws, node:$wt),
392                      (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
393def vbset_d : PatFrag<(ops node:$ws, node:$wt),
394                      (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
395                                         node:$wt))>;
396
397def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
398                     (add node:$wd, (mul node:$ws, node:$wt))>;
399
400def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
401                     (sub node:$wd, (mul node:$ws, node:$wt))>;
402
403def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
404                        (fmul node:$ws, (fexp2 node:$wt))>;
405
406// Instruction encoding.
407class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
408class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
409class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
410class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
411
412class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
413class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
414class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
415class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
416
417class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
418class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
419class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
420class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
421
422class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
423class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
424class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
425class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
426
427class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
428class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
429class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
430class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
431
432class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
433class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
434class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
435class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
436
437class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
438
439class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
440
441class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
442class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
443class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
444class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
445
446class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
447class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
448class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
449class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
450
451class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
452class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
453class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
454class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
455
456class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
457class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
458class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
459class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
460
461class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
462class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
463class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
464class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
465
466class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
467class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
468class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
469class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
470
471class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
472class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
473class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
474class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
475
476class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
477class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
478class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
479class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
480
481class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
482class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
483class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
484class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
485
486class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
487class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
488class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
489class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
490
491class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
492class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
493class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
494class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
495
496class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
497class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
498class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
499class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
500
501class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
502
503class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
504
505class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
506
507class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
508
509class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
510class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
511class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
512class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
513
514class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
515class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
516class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
517class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
518
519class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
520class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
521class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
522class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
523
524class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
525
526class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
527
528class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
529
530class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
531class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
532class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
533class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
534
535class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
536class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
537class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
538class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
539
540class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
541class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
542class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
543class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
544
545class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
546
547class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
548class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
549class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
550class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
551
552class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
553class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
554class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
555class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
556
557class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
558
559class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
560class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
561class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
562class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
563
564class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
565class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
566class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
567class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
568
569class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
570class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
571class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
572class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
573
574class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
575class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
576class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
577class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
578
579class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
580class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
581class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
582class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
583
584class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
585class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
586class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
587class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
588
589class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
590class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
591class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
592class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
593
594class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
595class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
596class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
597class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
598
599class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
600class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
601class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
602class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
603
604class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
605class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
606class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
607
608class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
609
610class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
611class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
612class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
613class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
614
615class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
616class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
617class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
618class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
619
620class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
621class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
622class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
623
624class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
625class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
626class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
627
628class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
629class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
630class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
631
632class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
633class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
634class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
635
636class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
637class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
638class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
639
640class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
641class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
642class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
643
644class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
645class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
646
647class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
648class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
649
650class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
651class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
652
653class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
654class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
655
656class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
657class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
658
659class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
660class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
661
662class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
663class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
664
665class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
666class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
667
668class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
669class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
670
671class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
672class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
673
674class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
675class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
676
677class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
678class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
679
680class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
681class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
682
683class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
684class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
685
686class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
687class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
688
689class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
690class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
691
692class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
693class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
694
695class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
696class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
697
698class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
699class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
700
701class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
702class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
703
704class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
705class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
706
707class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
708class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
709
710class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
711class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
712class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
713class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
714
715class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
716class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
717
718class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
719class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
720
721class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
722class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
723
724class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
725class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
726
727class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
728class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
729
730class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
731class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
732
733class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
734class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
735
736class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
737class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
738
739class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
740class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
741
742class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
743class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
744
745class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
746class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
747
748class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
749class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
750
751class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
752class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
753
754class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
755class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
756
757class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
758class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
759
760class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
761class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
762
763class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
764class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
765
766class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
767class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
768
769class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
770class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
771
772class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
773class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
774
775class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
776class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
777
778class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
779class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
780
781class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
782class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
783
784class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
785class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
786
787class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
788class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
789
790class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
791class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
792
793class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
794class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
795
796class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
797class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
798
799class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
800class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
801
802class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
803class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
804class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
805
806class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
807class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
808class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
809
810class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
811class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
812class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
813
814class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
815class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
816class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
817
818class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
819class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
820class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
821class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
822
823class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
824class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
825class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
826class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
827
828class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
829class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
830class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
831class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
832
833class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
834class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
835class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
836class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
837
838class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
839class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
840class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
841class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
842
843class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
844class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
845class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
846class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
847
848class LD_B_ENC   : MSA_MI10_FMT<0b00, 0b1000>;
849class LD_H_ENC   : MSA_MI10_FMT<0b01, 0b1000>;
850class LD_W_ENC   : MSA_MI10_FMT<0b10, 0b1000>;
851class LD_D_ENC   : MSA_MI10_FMT<0b11, 0b1000>;
852
853class LDI_B_ENC  : MSA_I10_FMT<0b110, 0b00, 0b000111>;
854class LDI_H_ENC  : MSA_I10_FMT<0b110, 0b01, 0b000111>;
855class LDI_W_ENC  : MSA_I10_FMT<0b110, 0b10, 0b000111>;
856class LDI_D_ENC  : MSA_I10_FMT<0b110, 0b11, 0b000111>;
857
858class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
859class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
860
861class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
862class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
863
864class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
865class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
866
867class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
868class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
869class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
870class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
871
872class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
873class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
874class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
875class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
876
877class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
878class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
879class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
880class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
881
882class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
883class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
884class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
885class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
886
887class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
888class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
889class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
890class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
891
892class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
893class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
894class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
895class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
896
897class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
898class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
899class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
900class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
901
902class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
903class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
904class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
905class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
906
907class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
908class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
909class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
910class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
911
912class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
913class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
914class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
915class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
916
917class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
918class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
919class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
920class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
921
922class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
923class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
924class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
925class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
926
927class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
928class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
929class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
930class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
931
932class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
933
934class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
935class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
936
937class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
938class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
939
940class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
941class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
942class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
943class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
944
945class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
946class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
947
948class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
949class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
950
951class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
952class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
953class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
954class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
955
956class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
957class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
958class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
959class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
960
961class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
962class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
963class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
964class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
965
966class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
967
968class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
969
970class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
971
972class ORI_B_ENC  : MSA_I8_FMT<0b01, 0b000000>;
973
974class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
975class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
976class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
977class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
978
979class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
980class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
981class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
982class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
983
984class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
985class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
986class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
987class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
988
989class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
990class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
991class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
992class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
993
994class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
995class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
996class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
997class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
998
999class SHF_B_ENC  : MSA_I8_FMT<0b00, 0b000010>;
1000class SHF_H_ENC  : MSA_I8_FMT<0b01, 0b000010>;
1001class SHF_W_ENC  : MSA_I8_FMT<0b10, 0b000010>;
1002
1003class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1004class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1005class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1006class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1007
1008class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1009class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1010class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1011class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1012
1013class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1014class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1015class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1016class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1017
1018class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1019class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1020class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1021class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1022
1023class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1024class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1025class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1026class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1027
1028class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1029class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1030class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1031class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1032
1033class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1034class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1035class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1036class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1037
1038class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1039class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1040class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1041class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1042
1043class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1044class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1045class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1046class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1047
1048class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1049class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1050class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1051class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1052
1053class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1054class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1055class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1056class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1057
1058class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1059class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1060class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1061class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1062
1063class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1064class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1065class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1066class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1067
1068class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1069class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1070class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1071class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1072
1073class ST_B_ENC   : MSA_MI10_FMT<0b00, 0b1001>;
1074class ST_H_ENC   : MSA_MI10_FMT<0b01, 0b1001>;
1075class ST_W_ENC   : MSA_MI10_FMT<0b10, 0b1001>;
1076class ST_D_ENC   : MSA_MI10_FMT<0b11, 0b1001>;
1077
1078class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1079class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1080class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1081class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1082
1083class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1084class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1085class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1086class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1087
1088class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1089class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1090class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1091class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1092
1093class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1094class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1095class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1096class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1097
1098class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1099class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1100class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1101class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1102
1103class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1104class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1105class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1106class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1107
1108class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1109class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1110class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1111class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1112
1113class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1114
1115class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1116
1117// Instruction desc.
1118class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1119                          ComplexPattern Imm, RegisterOperand ROWD,
1120                          RegisterOperand ROWS = ROWD,
1121                          InstrItinClass itin = NoItinerary> {
1122  dag OutOperandList = (outs ROWD:$wd);
1123  dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1124  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1125  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1126  InstrItinClass Itinerary = itin;
1127}
1128
1129class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1130                          ComplexPattern Imm, RegisterOperand ROWD,
1131                          RegisterOperand ROWS = ROWD,
1132                          InstrItinClass itin = NoItinerary> {
1133  dag OutOperandList = (outs ROWD:$wd);
1134  dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1135  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1136  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1137  InstrItinClass Itinerary = itin;
1138}
1139
1140class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1141                          ComplexPattern Imm, RegisterOperand ROWD,
1142                          RegisterOperand ROWS = ROWD,
1143                          InstrItinClass itin = NoItinerary> {
1144  dag OutOperandList = (outs ROWD:$wd);
1145  dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1146  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1147  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1148  InstrItinClass Itinerary = itin;
1149}
1150
1151class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1152                          ComplexPattern Imm, RegisterOperand ROWD,
1153                          RegisterOperand ROWS = ROWD,
1154                          InstrItinClass itin = NoItinerary> {
1155  dag OutOperandList = (outs ROWD:$wd);
1156  dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1157  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1158  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1159  InstrItinClass Itinerary = itin;
1160}
1161
1162class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1163                          Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1164                          RegisterOperand ROWS = ROWD,
1165                          InstrItinClass itin = NoItinerary> {
1166  dag OutOperandList = (outs ROWD:$wd);
1167  dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
1168  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1169  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1170  InstrItinClass Itinerary = itin;
1171}
1172
1173class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1174                               SplatComplexPattern Mask, RegisterOperand ROWD,
1175                               RegisterOperand ROWS = ROWD,
1176                               InstrItinClass itin = NoItinerary> {
1177  dag OutOperandList = (outs ROWD:$wd);
1178  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m);
1179  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1180  // Note that binsxi and vselect treat the condition operand the opposite
1181  // way to each other.
1182  //   (vselect cond, if_set, if_clear)
1183  //   (BSEL_V cond, if_clear, if_set)
1184  list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1185                                               ROWS:$wd_in))];
1186  InstrItinClass Itinerary = itin;
1187  string Constraints = "$wd = $wd_in";
1188}
1189
1190class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1191                               SplatComplexPattern ImmOp, RegisterOperand ROWD,
1192                               RegisterOperand ROWS = ROWD,
1193                               InstrItinClass itin = NoItinerary> :
1194  MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1195
1196class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1197                               SplatComplexPattern ImmOp, RegisterOperand ROWD,
1198                               RegisterOperand ROWS = ROWD,
1199                               InstrItinClass itin = NoItinerary> :
1200  MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1201
1202class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1203                              SplatComplexPattern SplatImm,
1204                              RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1205                              InstrItinClass itin = NoItinerary> {
1206  dag OutOperandList = (outs ROWD:$wd);
1207  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1208  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1209  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1210  InstrItinClass Itinerary = itin;
1211}
1212
1213class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1214                         ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
1215                         RegisterOperand ROD, RegisterOperand ROWS,
1216                         InstrItinClass itin = NoItinerary> {
1217  dag OutOperandList = (outs ROD:$rd);
1218  dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
1219  string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1220  list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))];
1221  InstrItinClass Itinerary = itin;
1222}
1223
1224class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1225                            RegisterOperand ROWD, RegisterOperand ROWS,
1226                            Operand ImmOp, ImmLeaf Imm,
1227                            InstrItinClass itin = NoItinerary> {
1228  dag OutOperandList = (outs ROWD:$wd);
1229  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
1230  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1231  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1232                                              Imm:$n))];
1233  string Constraints = "$wd = $wd_in";
1234  InstrItinClass Itinerary = itin;
1235}
1236
1237class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1238                           Operand ImmOp, ImmLeaf Imm, RegisterClass RCD,
1239                           RegisterClass RCWS> :
1240      MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n),
1241                [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> {
1242  bit usesCustomInserter = 1;
1243}
1244
1245class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1246                       SplatComplexPattern SplatImm, RegisterOperand ROWD,
1247                       RegisterOperand ROWS = ROWD,
1248                       InstrItinClass itin = NoItinerary> {
1249  dag OutOperandList = (outs ROWD:$wd);
1250  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1251  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1252  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1253  InstrItinClass Itinerary = itin;
1254}
1255
1256class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1257                       SplatComplexPattern SplatImm, RegisterOperand ROWD,
1258                       RegisterOperand ROWS = ROWD,
1259                       InstrItinClass itin = NoItinerary> {
1260  dag OutOperandList = (outs ROWD:$wd);
1261  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1262  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1263  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1264  InstrItinClass Itinerary = itin;
1265}
1266
1267class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1268                           RegisterOperand ROWS = ROWD,
1269                           InstrItinClass itin = NoItinerary> {
1270  dag OutOperandList = (outs ROWD:$wd);
1271  dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1272  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1273  list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1274  InstrItinClass Itinerary = itin;
1275}
1276
1277class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1278                            InstrItinClass itin = NoItinerary> {
1279  dag OutOperandList = (outs ROWD:$wd);
1280  dag InOperandList = (ins vsplat_simm10:$s10);
1281  string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1282  // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1283  list<dag> Pattern = [];
1284  bit hasSideEffects = 0;
1285  InstrItinClass Itinerary = itin;
1286}
1287
1288class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1289                       RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1290                       InstrItinClass itin = NoItinerary> {
1291  dag OutOperandList = (outs ROWD:$wd);
1292  dag InOperandList = (ins ROWS:$ws);
1293  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1294  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1295  InstrItinClass Itinerary = itin;
1296}
1297
1298class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1299                            SDPatternOperator OpNode, RegisterOperand ROWD,
1300                            RegisterOperand ROS = ROWD,
1301                            InstrItinClass itin = NoItinerary> {
1302  dag OutOperandList = (outs ROWD:$wd);
1303  dag InOperandList = (ins ROS:$rs);
1304  string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1305  list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1306  InstrItinClass Itinerary = itin;
1307}
1308
1309class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1310                              RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1311      MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1312                [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1313  let usesCustomInserter = 1;
1314}
1315
1316class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1317                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1318                        InstrItinClass itin = NoItinerary> {
1319  dag OutOperandList = (outs ROWD:$wd);
1320  dag InOperandList = (ins ROWS:$ws);
1321  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1322  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1323  InstrItinClass Itinerary = itin;
1324}
1325
1326class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1327                       RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1328                       RegisterOperand ROWT = ROWD,
1329                       InstrItinClass itin = NoItinerary> {
1330  dag OutOperandList = (outs ROWD:$wd);
1331  dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1332  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1333  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1334  InstrItinClass Itinerary = itin;
1335}
1336
1337class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1338                             RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1339                             RegisterOperand ROWT = ROWD,
1340                             InstrItinClass itin = NoItinerary> {
1341  dag OutOperandList = (outs ROWD:$wd);
1342  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1343  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1344  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1345                                              ROWT:$wt))];
1346  string Constraints = "$wd = $wd_in";
1347  InstrItinClass Itinerary = itin;
1348}
1349
1350class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1351                             RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1352                             InstrItinClass itin = NoItinerary> {
1353  dag OutOperandList = (outs ROWD:$wd);
1354  dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1355  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1356  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1357  InstrItinClass Itinerary = itin;
1358}
1359
1360class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1361                            RegisterOperand ROWS = ROWD,
1362                            RegisterOperand ROWT = ROWD,
1363                            InstrItinClass itin = NoItinerary> {
1364  dag OutOperandList = (outs ROWD:$wd);
1365  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1366  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1367  list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1368                                                ROWT:$wt))];
1369  string Constraints = "$wd = $wd_in";
1370  InstrItinClass Itinerary = itin;
1371}
1372
1373class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1374                           RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1375                           InstrItinClass itin = NoItinerary> {
1376  dag OutOperandList = (outs ROWD:$wd);
1377  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1378  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1379  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1380                                              GPR32Opnd:$rt))];
1381  InstrItinClass Itinerary = itin;
1382  string Constraints = "$wd = $wd_in";
1383}
1384
1385class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1386                          RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1387                          RegisterOperand ROWT = ROWD,
1388                          InstrItinClass itin = NoItinerary> {
1389  dag OutOperandList = (outs ROWD:$wd);
1390  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1391  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1392  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1393                                              ROWT:$wt))];
1394  InstrItinClass Itinerary = itin;
1395  string Constraints = "$wd = $wd_in";
1396}
1397
1398class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1399                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1400                        RegisterOperand ROWT = ROWD,
1401                        InstrItinClass itin = NoItinerary> :
1402  MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1403
1404class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1405                            RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1406                            RegisterOperand ROWT = ROWD,
1407                            InstrItinClass itin = NoItinerary> :
1408  MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1409
1410class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1411  dag OutOperandList = (outs);
1412  dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1413  string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1414  list<dag> Pattern = [];
1415  InstrItinClass Itinerary = NoItinerary;
1416  bit isBranch = 1;
1417  bit isTerminator = 1;
1418  bit hasDelaySlot = 1;
1419  list<Register> Defs = [AT];
1420}
1421
1422class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1423                           Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1424                           RegisterOperand ROS,
1425                           InstrItinClass itin = NoItinerary> {
1426  dag OutOperandList = (outs ROWD:$wd);
1427  dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n);
1428  string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1429  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))];
1430  InstrItinClass Itinerary = itin;
1431  string Constraints = "$wd = $wd_in";
1432}
1433
1434class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1435                             Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1436                             RegisterOperand ROFS> :
1437      MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs),
1438                [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> {
1439  bit usesCustomInserter = 1;
1440  string Constraints = "$wd = $wd_in";
1441}
1442
1443class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1444                                  RegisterOperand ROWD, RegisterOperand ROFS,
1445                                  RegisterOperand ROIdx> :
1446      MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
1447                [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1448                                        ROIdx:$n))]> {
1449  bit usesCustomInserter = 1;
1450  string Constraints = "$wd = $wd_in";
1451}
1452
1453class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1454                          Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1455                          RegisterOperand ROWS = ROWD,
1456                          InstrItinClass itin = NoItinerary> {
1457  dag OutOperandList = (outs ROWD:$wd);
1458  dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
1459  string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1460  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1461                                              Imm:$n,
1462                                              ROWS:$ws,
1463                                              immz:$n2))];
1464  InstrItinClass Itinerary = itin;
1465  string Constraints = "$wd = $wd_in";
1466}
1467
1468class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1469                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1470                        RegisterOperand ROWT = ROWD,
1471                        InstrItinClass itin = NoItinerary> {
1472  dag OutOperandList = (outs ROWD:$wd);
1473  dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1474  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1475  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1476  InstrItinClass Itinerary = itin;
1477}
1478
1479class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1480                              RegisterOperand ROWD,
1481                              RegisterOperand ROWS = ROWD,
1482                              InstrItinClass itin = NoItinerary> {
1483  dag OutOperandList = (outs ROWD:$wd);
1484  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1485  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1486  list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1487                                                ROWS:$ws))];
1488  InstrItinClass Itinerary = itin;
1489}
1490
1491class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1492                          RegisterOperand ROWS = ROWD,
1493                          RegisterOperand ROWT = ROWD> :
1494      MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1495                [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1496
1497class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1498                     IsCommutable;
1499class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1500                     IsCommutable;
1501class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1502                     IsCommutable;
1503class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1504                     IsCommutable;
1505
1506class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1507                                       MSA128BOpnd>, IsCommutable;
1508class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1509                                       MSA128HOpnd>, IsCommutable;
1510class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1511                                       MSA128WOpnd>, IsCommutable;
1512class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1513                                       MSA128DOpnd>, IsCommutable;
1514
1515class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1516                                       MSA128BOpnd>, IsCommutable;
1517class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1518                                       MSA128HOpnd>, IsCommutable;
1519class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1520                                       MSA128WOpnd>, IsCommutable;
1521class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1522                                       MSA128DOpnd>, IsCommutable;
1523
1524class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1525                                       MSA128BOpnd>, IsCommutable;
1526class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1527                                       MSA128HOpnd>, IsCommutable;
1528class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1529                                       MSA128WOpnd>, IsCommutable;
1530class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1531                                       MSA128DOpnd>, IsCommutable;
1532
1533class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1534class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1535class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1536class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1537
1538class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1539                                      MSA128BOpnd>;
1540class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1541                                      MSA128HOpnd>;
1542class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1543                                      MSA128WOpnd>;
1544class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1545                                      MSA128DOpnd>;
1546
1547class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1548class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1549class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1550class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1551
1552class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1553                                     MSA128BOpnd>;
1554
1555class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1556                                       MSA128BOpnd>;
1557class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1558                                       MSA128HOpnd>;
1559class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1560                                       MSA128WOpnd>;
1561class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1562                                       MSA128DOpnd>;
1563
1564class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1565                                       MSA128BOpnd>;
1566class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1567                                       MSA128HOpnd>;
1568class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1569                                       MSA128WOpnd>;
1570class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1571                                       MSA128DOpnd>;
1572
1573class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1574                     IsCommutable;
1575class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1576                     IsCommutable;
1577class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1578                     IsCommutable;
1579class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1580                     IsCommutable;
1581
1582class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1583                     IsCommutable;
1584class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1585                     IsCommutable;
1586class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1587                     IsCommutable;
1588class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1589                     IsCommutable;
1590
1591class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1592                                       MSA128BOpnd>, IsCommutable;
1593class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1594                                       MSA128HOpnd>, IsCommutable;
1595class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1596                                       MSA128WOpnd>, IsCommutable;
1597class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1598                                       MSA128DOpnd>, IsCommutable;
1599
1600class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1601                                       MSA128BOpnd>, IsCommutable;
1602class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1603                                       MSA128HOpnd>, IsCommutable;
1604class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1605                                       MSA128WOpnd>, IsCommutable;
1606class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1607                                       MSA128DOpnd>, IsCommutable;
1608
1609class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1610class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1611class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1612class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1613
1614class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1615                                         MSA128BOpnd>;
1616class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1617                                         MSA128HOpnd>;
1618class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1619                                         MSA128WOpnd>;
1620class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1621                                         MSA128DOpnd>;
1622
1623class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1624                                            MSA128BOpnd>;
1625class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1626                                            MSA128HOpnd>;
1627class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1628                                            MSA128WOpnd>;
1629class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1630                                            MSA128DOpnd>;
1631
1632class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>;
1633class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>;
1634class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>;
1635class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>;
1636
1637class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1638                                            MSA128BOpnd>;
1639class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1640                                            MSA128HOpnd>;
1641class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1642                                            MSA128WOpnd>;
1643class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1644                                            MSA128DOpnd>;
1645
1646class BINSRI_B_DESC
1647    : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3,
1648                               MSA128BOpnd>;
1649class BINSRI_H_DESC
1650    : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4,
1651                               MSA128HOpnd>;
1652class BINSRI_W_DESC
1653    : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5,
1654                               MSA128WOpnd>;
1655class BINSRI_D_DESC
1656    : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6,
1657                               MSA128DOpnd>;
1658
1659class BMNZ_V_DESC {
1660  dag OutOperandList = (outs MSA128BOpnd:$wd);
1661  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1662                       MSA128BOpnd:$wt);
1663  string AsmString = "bmnz.v\t$wd, $ws, $wt";
1664  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1665                                                      MSA128BOpnd:$ws,
1666                                                      MSA128BOpnd:$wd_in))];
1667  InstrItinClass Itinerary = NoItinerary;
1668  string Constraints = "$wd = $wd_in";
1669}
1670
1671class BMNZI_B_DESC {
1672  dag OutOperandList = (outs MSA128BOpnd:$wd);
1673  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1674                           vsplat_uimm8:$u8);
1675  string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1676  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1677                                                      MSA128BOpnd:$ws,
1678                                                      MSA128BOpnd:$wd_in))];
1679  InstrItinClass Itinerary = NoItinerary;
1680  string Constraints = "$wd = $wd_in";
1681}
1682
1683class BMZ_V_DESC {
1684  dag OutOperandList = (outs MSA128BOpnd:$wd);
1685  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1686                       MSA128BOpnd:$wt);
1687  string AsmString = "bmz.v\t$wd, $ws, $wt";
1688  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1689                                                      MSA128BOpnd:$wd_in,
1690                                                      MSA128BOpnd:$ws))];
1691  InstrItinClass Itinerary = NoItinerary;
1692  string Constraints = "$wd = $wd_in";
1693}
1694
1695class BMZI_B_DESC {
1696  dag OutOperandList = (outs MSA128BOpnd:$wd);
1697  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1698                           vsplat_uimm8:$u8);
1699  string AsmString = "bmzi.b\t$wd, $ws, $u8";
1700  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1701                                                      MSA128BOpnd:$wd_in,
1702                                                      MSA128BOpnd:$ws))];
1703  InstrItinClass Itinerary = NoItinerary;
1704  string Constraints = "$wd = $wd_in";
1705}
1706
1707class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1708class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1709class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1710class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1711
1712class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1713                                         MSA128BOpnd>;
1714class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1715                                         MSA128HOpnd>;
1716class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1717                                         MSA128WOpnd>;
1718class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1719                                         MSA128DOpnd>;
1720
1721class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1722class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1723class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1724class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1725
1726class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1727
1728class BSEL_V_DESC {
1729  dag OutOperandList = (outs MSA128BOpnd:$wd);
1730  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1731                       MSA128BOpnd:$wt);
1732  string AsmString = "bsel.v\t$wd, $ws, $wt";
1733  // Note that vselect and BSEL_V treat the condition operand the opposite way
1734  // from each other.
1735  //   (vselect cond, if_set, if_clear)
1736  //   (BSEL_V cond, if_clear, if_set)
1737  list<dag> Pattern = [(set MSA128BOpnd:$wd,
1738                        (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1739                                                     MSA128BOpnd:$ws))];
1740  InstrItinClass Itinerary = NoItinerary;
1741  string Constraints = "$wd = $wd_in";
1742}
1743
1744class BSELI_B_DESC {
1745  dag OutOperandList = (outs MSA128BOpnd:$wd);
1746  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1747                           vsplat_uimm8:$u8);
1748  string AsmString = "bseli.b\t$wd, $ws, $u8";
1749  // Note that vselect and BSEL_V treat the condition operand the opposite way
1750  // from each other.
1751  //   (vselect cond, if_set, if_clear)
1752  //   (BSEL_V cond, if_clear, if_set)
1753  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1754                                                      vsplati8_uimm8:$u8,
1755                                                      MSA128BOpnd:$ws))];
1756  InstrItinClass Itinerary = NoItinerary;
1757  string Constraints = "$wd = $wd_in";
1758}
1759
1760class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1761class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1762class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1763class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1764
1765class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1766                                         MSA128BOpnd>;
1767class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1768                                         MSA128HOpnd>;
1769class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1770                                         MSA128WOpnd>;
1771class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1772                                         MSA128DOpnd>;
1773
1774class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1775class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1776class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1777class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1778
1779class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1780
1781class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1782                   IsCommutable;
1783class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1784                   IsCommutable;
1785class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1786                   IsCommutable;
1787class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1788                   IsCommutable;
1789
1790class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1791                                     MSA128BOpnd>;
1792class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1793                                     MSA128HOpnd>;
1794class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1795                                     MSA128WOpnd>;
1796class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1797                                     MSA128DOpnd>;
1798
1799class CFCMSA_DESC {
1800  dag OutOperandList = (outs GPR32Opnd:$rd);
1801  dag InOperandList = (ins MSA128CROpnd:$cs);
1802  string AsmString = "cfcmsa\t$rd, $cs";
1803  InstrItinClass Itinerary = NoItinerary;
1804  bit hasSideEffects = 1;
1805  bit isMoveReg = 1;
1806}
1807
1808class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1809class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1810class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1811class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1812
1813class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1814class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1815class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1816class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1817
1818class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1819                                       vsplati8_simm5,  MSA128BOpnd>;
1820class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1821                                       vsplati16_simm5, MSA128HOpnd>;
1822class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1823                                       vsplati32_simm5, MSA128WOpnd>;
1824class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1825                                       vsplati64_simm5, MSA128DOpnd>;
1826
1827class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1828                                       vsplati8_uimm5,  MSA128BOpnd>;
1829class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1830                                       vsplati16_uimm5, MSA128HOpnd>;
1831class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1832                                       vsplati32_uimm5, MSA128WOpnd>;
1833class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1834                                       vsplati64_uimm5, MSA128DOpnd>;
1835
1836class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1837class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1838class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1839class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1840
1841class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1842class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1843class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1844class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1845
1846class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1847                                       vsplati8_simm5, MSA128BOpnd>;
1848class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1849                                       vsplati16_simm5, MSA128HOpnd>;
1850class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1851                                       vsplati32_simm5, MSA128WOpnd>;
1852class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1853                                       vsplati64_simm5, MSA128DOpnd>;
1854
1855class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1856                                       vsplati8_uimm5, MSA128BOpnd>;
1857class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1858                                       vsplati16_uimm5, MSA128HOpnd>;
1859class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1860                                       vsplati32_uimm5, MSA128WOpnd>;
1861class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1862                                       vsplati64_uimm5, MSA128DOpnd>;
1863
1864class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8,  v16i8,
1865                                         uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1866                                         MSA128BOpnd>;
1867class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1868                                         uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1869                                         MSA128HOpnd>;
1870class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1871                                         uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1872                                         MSA128WOpnd>;
1873class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1874                                         uimm1_ptr, immZExt1Ptr, GPR64Opnd,
1875                                         MSA128DOpnd>;
1876
1877class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8,  v16i8,
1878                                         uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1879                                         MSA128BOpnd>;
1880class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1881                                         uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1882                                         MSA128HOpnd>;
1883class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1884                                         uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1885                                         MSA128WOpnd>;
1886
1887class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32,
1888                                                 uimm2_ptr, immZExt2Ptr, FGR32,
1889                                                 MSA128W>;
1890class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64,
1891                                                 uimm1_ptr, immZExt1Ptr, FGR64,
1892                                                 MSA128D>;
1893
1894class CTCMSA_DESC {
1895  dag OutOperandList = (outs);
1896  dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1897  string AsmString = "ctcmsa\t$cd, $rs";
1898  InstrItinClass Itinerary = NoItinerary;
1899  bit hasSideEffects = 1;
1900  bit isMoveReg = 1;
1901}
1902
1903class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1904class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1905class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1906class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1907
1908class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1909class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1910class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1911class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1912
1913class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1914                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1915                      IsCommutable;
1916class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1917                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1918                      IsCommutable;
1919class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1920                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1921                      IsCommutable;
1922
1923class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1924                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1925                      IsCommutable;
1926class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1927                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1928                      IsCommutable;
1929class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1930                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1931                      IsCommutable;
1932
1933class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1934                                           MSA128HOpnd, MSA128BOpnd,
1935                                           MSA128BOpnd>, IsCommutable;
1936class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1937                                           MSA128WOpnd, MSA128HOpnd,
1938                                           MSA128HOpnd>, IsCommutable;
1939class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1940                                           MSA128DOpnd, MSA128WOpnd,
1941                                           MSA128WOpnd>, IsCommutable;
1942
1943class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1944                                           MSA128HOpnd, MSA128BOpnd,
1945                                           MSA128BOpnd>, IsCommutable;
1946class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1947                                           MSA128WOpnd, MSA128HOpnd,
1948                                           MSA128HOpnd>, IsCommutable;
1949class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1950                                           MSA128DOpnd, MSA128WOpnd,
1951                                           MSA128WOpnd>, IsCommutable;
1952
1953class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1954                                           MSA128HOpnd, MSA128BOpnd,
1955                                           MSA128BOpnd>;
1956class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1957                                           MSA128WOpnd, MSA128HOpnd,
1958                                           MSA128HOpnd>;
1959class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1960                                           MSA128DOpnd, MSA128WOpnd,
1961                                           MSA128WOpnd>;
1962
1963class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1964                                           MSA128HOpnd, MSA128BOpnd,
1965                                           MSA128BOpnd>;
1966class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1967                                           MSA128WOpnd, MSA128HOpnd,
1968                                           MSA128HOpnd>;
1969class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1970                                           MSA128DOpnd, MSA128WOpnd,
1971                                           MSA128WOpnd>;
1972
1973class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1974                    IsCommutable;
1975class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1976                    IsCommutable;
1977
1978class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1979                    IsCommutable;
1980class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1981                    IsCommutable;
1982
1983class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1984                    IsCommutable;
1985class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1986                    IsCommutable;
1987
1988class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1989                                        MSA128WOpnd>;
1990class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1991                                        MSA128DOpnd>;
1992
1993class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1994class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1995
1996class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1997class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1998
1999class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
2000                    IsCommutable;
2001class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
2002                    IsCommutable;
2003
2004class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
2005                    IsCommutable;
2006class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
2007                    IsCommutable;
2008
2009class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
2010                     IsCommutable;
2011class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2012                     IsCommutable;
2013
2014class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2015                     IsCommutable;
2016class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2017                     IsCommutable;
2018
2019class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2020                     IsCommutable;
2021class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2022                     IsCommutable;
2023
2024class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2025                    IsCommutable;
2026class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2027                    IsCommutable;
2028
2029class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2030                     IsCommutable;
2031class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2032                     IsCommutable;
2033
2034class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2035class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2036
2037class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2038                                       MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2039class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2040                                       MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2041
2042// The fexp2.df instruction multiplies the first operand by 2 to the power of
2043// the second operand. We therefore need a pseudo-insn in order to invent the
2044// 1.0 when we only need to match ISD::FEXP2.
2045class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2046class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2047let usesCustomInserter = 1 in {
2048  class FEXP2_W_1_PSEUDO_DESC :
2049      MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2050                [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2051  class FEXP2_D_1_PSEUDO_DESC :
2052      MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2053                [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2054}
2055
2056class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2057                                        MSA128WOpnd, MSA128HOpnd>;
2058class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2059                                        MSA128DOpnd, MSA128WOpnd>;
2060
2061class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2062                                        MSA128WOpnd, MSA128HOpnd>;
2063class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2064                                        MSA128DOpnd, MSA128WOpnd>;
2065
2066class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2067class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2068
2069class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2070class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2071
2072class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2073                                      MSA128WOpnd, MSA128HOpnd>;
2074class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2075                                      MSA128DOpnd, MSA128WOpnd>;
2076
2077class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2078                                      MSA128WOpnd, MSA128HOpnd>;
2079class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2080                                      MSA128DOpnd, MSA128WOpnd>;
2081
2082class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2083                                          MSA128BOpnd, GPR32Opnd>;
2084class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2085                                          MSA128HOpnd, GPR32Opnd>;
2086class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2087                                          MSA128WOpnd, GPR32Opnd>;
2088class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2089                                          MSA128DOpnd, GPR64Opnd>;
2090
2091class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2092                                                    FGR32>;
2093class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2094                                                    FGR64>;
2095
2096class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2097class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2098
2099class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2100class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2101
2102class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2103class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2104
2105class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2106                                        MSA128WOpnd>;
2107class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2108                                        MSA128DOpnd>;
2109
2110class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2111class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2112
2113class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2114                                        MSA128WOpnd>;
2115class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2116                                        MSA128DOpnd>;
2117
2118class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>;
2119class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>;
2120
2121class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2122class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2123
2124class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2125class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2126
2127class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2128class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2129
2130class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2131                                        MSA128WOpnd>;
2132class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2133                                        MSA128DOpnd>;
2134
2135class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2136class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2137
2138class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2139class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2140
2141class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2142class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2143
2144class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2145class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2146
2147class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2148class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2149
2150class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2151class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2152
2153class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2154class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2155
2156class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2157class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2158
2159class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2160                                       MSA128WOpnd>;
2161class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2162                                       MSA128DOpnd>;
2163
2164class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2165                                       MSA128WOpnd>;
2166class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2167                                       MSA128DOpnd>;
2168
2169class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2170                                       MSA128WOpnd>;
2171class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2172                                       MSA128DOpnd>;
2173
2174class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2175                                      MSA128WOpnd>;
2176class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2177                                      MSA128DOpnd>;
2178
2179class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2180                                       MSA128WOpnd>;
2181class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2182                                       MSA128DOpnd>;
2183
2184class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2185                                         MSA128WOpnd>;
2186class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2187                                         MSA128DOpnd>;
2188
2189class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2190                                         MSA128WOpnd>;
2191class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2192                                         MSA128DOpnd>;
2193
2194class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2195                                     MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2196class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2197                                     MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2198
2199class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2200                                          MSA128WOpnd>;
2201class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2202                                          MSA128DOpnd>;
2203
2204class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2205                                          MSA128WOpnd>;
2206class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2207                                          MSA128DOpnd>;
2208
2209class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2210                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2211class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2212                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2213class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2214                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2215
2216class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2217                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2218class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2219                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2220class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2221                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2222
2223class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2224                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2225class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2226                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2227class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2228                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2229
2230class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2231                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2232class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2233                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2234class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2235                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2236
2237class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2238class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2239class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2240class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2241
2242class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2243class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2244class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2245class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2246
2247class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2248class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2249class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2250class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2251
2252class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2253class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2254class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2255class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2256
2257class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4,
2258                                           immZExt4Ptr, MSA128BOpnd, GPR32Opnd>;
2259class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3,
2260                                           immZExt3Ptr, MSA128HOpnd, GPR32Opnd>;
2261class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2,
2262                                           immZExt2Ptr, MSA128WOpnd, GPR32Opnd>;
2263class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1,
2264                                           immZExt1Ptr, MSA128DOpnd, GPR64Opnd>;
2265
2266class INSERT_B_VIDX_PSEUDO_DESC :
2267    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
2268class INSERT_H_VIDX_PSEUDO_DESC :
2269    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
2270class INSERT_W_VIDX_PSEUDO_DESC :
2271    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
2272class INSERT_D_VIDX_PSEUDO_DESC :
2273    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
2274
2275class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2276                                                     uimm2, immZExt2Ptr,
2277                                                     MSA128WOpnd, FGR32Opnd>;
2278class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2279                                                     uimm1, immZExt1Ptr,
2280                                                     MSA128DOpnd, FGR64Opnd>;
2281
2282class INSERT_FW_VIDX_PSEUDO_DESC :
2283    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
2284class INSERT_FD_VIDX_PSEUDO_DESC :
2285    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
2286
2287class INSERT_B_VIDX64_PSEUDO_DESC :
2288    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
2289class INSERT_H_VIDX64_PSEUDO_DESC :
2290    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
2291class INSERT_W_VIDX64_PSEUDO_DESC :
2292    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
2293class INSERT_D_VIDX64_PSEUDO_DESC :
2294    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
2295
2296class INSERT_FW_VIDX64_PSEUDO_DESC :
2297    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
2298class INSERT_FD_VIDX64_PSEUDO_DESC :
2299    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
2300
2301class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4,
2302                                         MSA128BOpnd>;
2303class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3,
2304                                         MSA128HOpnd>;
2305class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2,
2306                                         MSA128WOpnd>;
2307class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1,
2308                                         MSA128DOpnd>;
2309
2310class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2311                   ValueType TyNode, RegisterOperand ROWD,
2312                   Operand MemOpnd, ComplexPattern Addr = addrimm10,
2313                   InstrItinClass itin = NoItinerary> {
2314  dag OutOperandList = (outs ROWD:$wd);
2315  dag InOperandList = (ins MemOpnd:$addr);
2316  string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2317  list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2318  InstrItinClass Itinerary = itin;
2319  string DecoderMethod = "DecodeMSA128Mem";
2320}
2321
2322class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
2323class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd,
2324                               mem_simm10_lsl1, addrimm10lsl1>;
2325class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd,
2326                               mem_simm10_lsl2, addrimm10lsl2>;
2327class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd,
2328                               mem_simm10_lsl3, addrimm10lsl3>;
2329
2330class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2331class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2332class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2333class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2334
2335class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2336                    InstrItinClass itin = NoItinerary> {
2337  dag OutOperandList = (outs RORD:$rd);
2338  dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa);
2339  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2340  list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt,
2341                                                (shl RORD:$rs,
2342                                                     immZExt2Lsa:$sa)))];
2343  InstrItinClass Itinerary = itin;
2344}
2345
2346class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>;
2347class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
2348
2349class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2350                                            MSA128HOpnd>;
2351class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2352                                            MSA128WOpnd>;
2353
2354class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2355                                             MSA128HOpnd>;
2356class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2357                                             MSA128WOpnd>;
2358
2359class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2360class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2361class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2362class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2363
2364class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2365class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2366class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2367class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2368
2369class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>;
2370class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>;
2371class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>;
2372class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>;
2373
2374class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>;
2375class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>;
2376class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>;
2377class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>;
2378
2379class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5,
2380                                       MSA128BOpnd>;
2381class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5,
2382                                       MSA128HOpnd>;
2383class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5,
2384                                       MSA128WOpnd>;
2385class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5,
2386                                       MSA128DOpnd>;
2387
2388class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5,
2389                                       MSA128BOpnd>;
2390class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5,
2391                                       MSA128HOpnd>;
2392class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5,
2393                                       MSA128WOpnd>;
2394class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5,
2395                                       MSA128DOpnd>;
2396
2397class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2398class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2399class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2400class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2401
2402class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>;
2403class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>;
2404class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>;
2405class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>;
2406
2407class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>;
2408class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>;
2409class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>;
2410class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>;
2411
2412class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5,
2413                                       MSA128BOpnd>;
2414class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5,
2415                                       MSA128HOpnd>;
2416class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5,
2417                                       MSA128WOpnd>;
2418class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5,
2419                                       MSA128DOpnd>;
2420
2421class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5,
2422                                       MSA128BOpnd>;
2423class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5,
2424                                       MSA128HOpnd>;
2425class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5,
2426                                       MSA128WOpnd>;
2427class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5,
2428                                       MSA128DOpnd>;
2429
2430class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2431class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2432class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2433class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2434
2435class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2436class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2437class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2438class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2439
2440class MOVE_V_DESC {
2441  dag OutOperandList = (outs MSA128BOpnd:$wd);
2442  dag InOperandList = (ins MSA128BOpnd:$ws);
2443  string AsmString = "move.v\t$wd, $ws";
2444  list<dag> Pattern = [];
2445  InstrItinClass Itinerary = NoItinerary;
2446  bit isMoveReg = 1;
2447}
2448
2449class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2450                                            MSA128HOpnd>;
2451class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2452                                            MSA128WOpnd>;
2453
2454class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2455                                             MSA128HOpnd>;
2456class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2457                                             MSA128WOpnd>;
2458
2459class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2460class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2461class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2462class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2463
2464class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2465                                       MSA128HOpnd>;
2466class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2467                                       MSA128WOpnd>;
2468
2469class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2470                                        MSA128HOpnd>;
2471class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2472                                        MSA128WOpnd>;
2473
2474class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2475class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2476class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2477class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2478
2479class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2480class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2481class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2482class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2483
2484class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2485class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2486class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2487class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2488
2489class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2490class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2491class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2492class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2493
2494class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2495                                     MSA128BOpnd>;
2496
2497class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2498class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2499class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2500class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2501
2502class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2503
2504class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2505class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2506class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2507class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2508
2509class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2510class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2511class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2512class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2513
2514class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2515class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2516class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2517class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2518
2519class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3,
2520                                         immZExt3, MSA128BOpnd>;
2521class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4,
2522                                         immZExt4, MSA128HOpnd>;
2523class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5,
2524                                         immZExt5, MSA128WOpnd>;
2525class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6,
2526                                         immZExt6, MSA128DOpnd>;
2527
2528class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3,
2529                                         immZExt3, MSA128BOpnd>;
2530class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4,
2531                                         immZExt4, MSA128HOpnd>;
2532class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5,
2533                                         immZExt5, MSA128WOpnd>;
2534class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6,
2535                                         immZExt6, MSA128DOpnd>;
2536
2537class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2538class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2539class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2540
2541class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2542class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2543class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2544class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2545
2546class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2547                                          MSA128BOpnd, MSA128BOpnd, uimm4,
2548                                          immZExt4>;
2549class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2550                                          MSA128HOpnd, MSA128HOpnd, uimm3,
2551                                          immZExt3>;
2552class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2553                                          MSA128WOpnd, MSA128WOpnd, uimm2,
2554                                          immZExt2>;
2555class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2556                                          MSA128DOpnd, MSA128DOpnd, uimm1,
2557                                          immZExt1>;
2558
2559class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2560class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2561class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2562class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2563
2564class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2565                                            MSA128BOpnd>;
2566class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2567                                            MSA128HOpnd>;
2568class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2569                                            MSA128WOpnd>;
2570class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2571                                            MSA128DOpnd>;
2572
2573class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2574                                            MSA128BOpnd>;
2575class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2576                                            MSA128HOpnd>;
2577class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2578                                            MSA128WOpnd>;
2579class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2580                                            MSA128DOpnd>;
2581
2582class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2583                                              MSA128BOpnd>;
2584class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2585                                              MSA128HOpnd>;
2586class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2587                                              MSA128WOpnd>;
2588class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2589                                              MSA128DOpnd>;
2590
2591class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2592class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2593class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2594class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2595
2596class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2597                                            MSA128BOpnd>;
2598class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2599                                            MSA128HOpnd>;
2600class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2601                                            MSA128WOpnd>;
2602class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2603                                            MSA128DOpnd>;
2604
2605class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2606class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2607class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2608class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2609
2610class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3,
2611                                         immZExt3, MSA128BOpnd>;
2612class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4,
2613                                         immZExt4, MSA128HOpnd>;
2614class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5,
2615                                         immZExt5, MSA128WOpnd>;
2616class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6,
2617                                         immZExt6, MSA128DOpnd>;
2618
2619class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2620class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2621class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2622class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2623
2624class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2625                                            MSA128BOpnd>;
2626class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2627                                            MSA128HOpnd>;
2628class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2629                                            MSA128WOpnd>;
2630class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2631                                            MSA128DOpnd>;
2632
2633class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2634class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2635class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2636class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2637
2638class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3,
2639                                         immZExt3, MSA128BOpnd>;
2640class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4,
2641                                         immZExt4, MSA128HOpnd>;
2642class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5,
2643                                         immZExt5, MSA128WOpnd>;
2644class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
2645                                         immZExt6, MSA128DOpnd>;
2646
2647class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2648                   ValueType TyNode, RegisterOperand ROWD,
2649                   Operand MemOpnd, ComplexPattern Addr = addrimm10,
2650                   InstrItinClass itin = NoItinerary> {
2651  dag OutOperandList = (outs);
2652  dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2653  string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2654  list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2655  InstrItinClass Itinerary = itin;
2656  string DecoderMethod = "DecodeMSA128Mem";
2657}
2658
2659class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
2660class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd,
2661                               mem_simm10_lsl1, addrimm10lsl1>;
2662class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd,
2663                               mem_simm10_lsl2, addrimm10lsl2>;
2664class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd,
2665                               mem_simm10_lsl3, addrimm10lsl3>;
2666
2667class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2668                                       MSA128BOpnd>;
2669class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2670                                       MSA128HOpnd>;
2671class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2672                                       MSA128WOpnd>;
2673class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2674                                       MSA128DOpnd>;
2675
2676class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2677                                       MSA128BOpnd>;
2678class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2679                                       MSA128HOpnd>;
2680class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2681                                       MSA128WOpnd>;
2682class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2683                                       MSA128DOpnd>;
2684
2685class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2686                                         MSA128BOpnd>;
2687class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2688                                         MSA128HOpnd>;
2689class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2690                                         MSA128WOpnd>;
2691class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2692                                         MSA128DOpnd>;
2693
2694class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2695                                         MSA128BOpnd>;
2696class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2697                                         MSA128HOpnd>;
2698class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2699                                         MSA128WOpnd>;
2700class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2701                                         MSA128DOpnd>;
2702
2703class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2704class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2705class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2706class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2707
2708class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2709                                      MSA128BOpnd>;
2710class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2711                                      MSA128HOpnd>;
2712class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2713                                      MSA128WOpnd>;
2714class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2715                                      MSA128DOpnd>;
2716
2717class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2718class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2719class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2720class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2721
2722class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2723class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2724class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2725class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2726
2727class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2728                                     MSA128BOpnd>;
2729
2730// Instruction defs.
2731def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2732def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2733def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2734def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2735
2736def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2737def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2738def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2739def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2740
2741def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2742def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2743def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2744def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2745
2746def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2747def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2748def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2749def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2750
2751def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2752def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2753def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2754def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2755
2756def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2757def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2758def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2759def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2760
2761def AND_V : AND_V_ENC, AND_V_DESC;
2762def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2763                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2764                                                MSA128BOpnd:$ws,
2765                                                MSA128BOpnd:$wt)>;
2766def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2767                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2768                                                MSA128BOpnd:$ws,
2769                                                MSA128BOpnd:$wt)>;
2770def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2771                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2772                                                MSA128BOpnd:$ws,
2773                                                MSA128BOpnd:$wt)>;
2774
2775def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2776
2777def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2778def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2779def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2780def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2781
2782def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2783def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2784def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2785def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2786
2787def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2788def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2789def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2790def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2791
2792def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2793def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2794def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2795def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2796
2797def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2798def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2799def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2800def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2801
2802def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2803def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2804def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2805def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2806
2807def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2808def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2809def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2810def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2811
2812def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2813def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2814def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2815def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2816
2817def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2818def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2819def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2820def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2821
2822def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2823def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2824def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2825def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2826
2827def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2828def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2829def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2830def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2831
2832def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2833def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2834def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2835def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2836
2837def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2838
2839def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2840
2841def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2842
2843def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2844
2845def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2846def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2847def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2848def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2849
2850def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2851def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2852def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2853def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2854
2855def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2856def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2857def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2858def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2859
2860def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2861
2862def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2863
2864class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2865  MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2866            [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2867  // Note that vselect and BSEL_V treat the condition operand the opposite way
2868  // from each other.
2869  //   (vselect cond, if_set, if_clear)
2870  //   (BSEL_V cond, if_clear, if_set)
2871  PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2872                              MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2873  let Constraints = "$wd_in = $wd";
2874}
2875
2876def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2877def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2878def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2879def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2880def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2881
2882def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2883
2884def BSET_B : BSET_B_ENC, BSET_B_DESC;
2885def BSET_H : BSET_H_ENC, BSET_H_DESC;
2886def BSET_W : BSET_W_ENC, BSET_W_DESC;
2887def BSET_D : BSET_D_ENC, BSET_D_DESC;
2888
2889def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2890def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2891def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2892def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2893
2894def BZ_B : BZ_B_ENC, BZ_B_DESC;
2895def BZ_H : BZ_H_ENC, BZ_H_DESC;
2896def BZ_W : BZ_W_ENC, BZ_W_DESC;
2897def BZ_D : BZ_D_ENC, BZ_D_DESC;
2898
2899def BZ_V : BZ_V_ENC, BZ_V_DESC;
2900
2901def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2902def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2903def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2904def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2905
2906def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2907def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2908def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2909def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2910
2911def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2912
2913def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2914def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2915def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2916def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2917
2918def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2919def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2920def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2921def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2922
2923def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2924def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2925def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2926def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2927
2928def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2929def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2930def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2931def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2932
2933def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2934def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2935def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2936def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2937
2938def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2939def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2940def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2941def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2942
2943def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2944def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2945def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2946def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2947
2948def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2949def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2950def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2951def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2952
2953def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2954def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2955def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2956def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
2957
2958def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2959def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2960def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64;
2961
2962def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2963def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2964
2965def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2966
2967def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2968def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2969def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2970def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2971
2972def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2973def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2974def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2975def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2976
2977def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2978def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2979def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2980
2981def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2982def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2983def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2984
2985def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2986def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2987def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2988
2989def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2990def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2991def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2992
2993def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2994def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2995def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2996
2997def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2998def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2999def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
3000
3001def FADD_W : FADD_W_ENC, FADD_W_DESC;
3002def FADD_D : FADD_D_ENC, FADD_D_DESC;
3003
3004def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
3005def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
3006
3007def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
3008def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
3009
3010def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
3011def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
3012
3013def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
3014def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
3015
3016def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
3017def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
3018
3019def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
3020def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
3021
3022def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
3023def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
3024
3025def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
3026def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
3027
3028def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
3029def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
3030
3031def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
3032def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
3033
3034def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
3035def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
3036
3037def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
3038def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
3039
3040def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3041def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3042
3043def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3044def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3045
3046def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3047def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3048def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3049def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3050
3051def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3052def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3053
3054def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3055def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3056
3057def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3058def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3059
3060def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3061def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3062
3063def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3064def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3065
3066def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3067def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3068
3069def FILL_B : FILL_B_ENC, FILL_B_DESC;
3070def FILL_H : FILL_H_ENC, FILL_H_DESC;
3071def FILL_W : FILL_W_ENC, FILL_W_DESC;
3072def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
3073def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3074def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3075
3076def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3077def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3078
3079def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3080def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3081
3082def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3083def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3084
3085def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3086def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3087
3088def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3089def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3090
3091def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3092def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3093
3094def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3095def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3096
3097def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3098def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3099
3100def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3101def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3102
3103def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3104def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3105
3106def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3107def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3108
3109def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3110def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3111
3112def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3113def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3114
3115def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3116def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3117
3118def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3119def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3120
3121def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3122def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3123
3124def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3125def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3126
3127def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3128def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3129
3130def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3131def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3132
3133def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3134def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3135
3136def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3137def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3138
3139def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3140def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3141
3142def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3143def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3144
3145def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3146def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3147
3148def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3149def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3150
3151def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3152def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3153
3154def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3155def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3156
3157def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3158def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3159
3160def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3161def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3162
3163def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3164              (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3165              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3166def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3167              (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3168              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3169
3170def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3171              (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3172              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3173def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3174              (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3175              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3176
3177def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3178def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3179def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3180
3181def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3182def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3183def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3184
3185def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3186def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3187def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3188
3189def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3190def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3191def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3192
3193def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3194def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3195def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3196def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3197
3198def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3199def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3200def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3201def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3202
3203def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3204def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3205def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3206def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3207
3208def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3209def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3210def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3211def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3212
3213def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3214def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3215def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3216def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
3217
3218// INSERT_FW_PSEUDO defined after INSVE_W
3219// INSERT_FD_PSEUDO defined after INSVE_D
3220
3221// There is a fourth operand that is not present in the encoding. Use a
3222// custom decoder to get a chance to add it.
3223let DecoderMethod = "DecodeINSVE_DF" in {
3224  def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3225  def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3226  def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3227  def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3228}
3229
3230def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3231def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3232
3233def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3234def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3235def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3236def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3237def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3238def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3239
3240def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
3241def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
3242def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
3243def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
3244def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
3245def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
3246
3247def LD_B: LD_B_ENC, LD_B_DESC;
3248def LD_H: LD_H_ENC, LD_H_DESC;
3249def LD_W: LD_W_ENC, LD_W_DESC;
3250def LD_D: LD_D_ENC, LD_D_DESC;
3251
3252def LDI_B : LDI_B_ENC, LDI_B_DESC;
3253def LDI_H : LDI_H_ENC, LDI_H_DESC;
3254def LDI_W : LDI_W_ENC, LDI_W_DESC;
3255def LDI_D : LDI_D_ENC, LDI_D_DESC;
3256
3257def LSA : LSA_ENC, LSA_DESC;
3258def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
3259
3260def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3261def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3262
3263def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3264def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3265
3266def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3267def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3268def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3269def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3270
3271def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3272def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3273def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3274def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3275
3276def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3277def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3278def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3279def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3280
3281def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3282def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3283def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3284def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3285
3286def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3287def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3288def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3289def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3290
3291def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3292def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3293def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3294def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3295
3296def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3297def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3298def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3299def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3300
3301def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3302def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3303def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3304def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3305
3306def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3307def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3308def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3309def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3310
3311def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3312def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3313def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3314def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3315
3316def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3317def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3318def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3319def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3320
3321def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3322def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3323def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3324def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3325
3326def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3327def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3328def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3329def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3330
3331def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3332
3333def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3334def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3335
3336def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3337def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3338
3339def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3340def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3341def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3342def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3343
3344def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3345def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3346
3347def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3348def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3349
3350def MULV_B : MULV_B_ENC, MULV_B_DESC;
3351def MULV_H : MULV_H_ENC, MULV_H_DESC;
3352def MULV_W : MULV_W_ENC, MULV_W_DESC;
3353def MULV_D : MULV_D_ENC, MULV_D_DESC;
3354
3355def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3356def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3357def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3358def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3359
3360def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3361def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3362def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3363def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3364
3365def NOR_V : NOR_V_ENC, NOR_V_DESC;
3366def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3367                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3368                                                MSA128BOpnd:$ws,
3369                                                MSA128BOpnd:$wt)>;
3370def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3371                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3372                                                MSA128BOpnd:$ws,
3373                                                MSA128BOpnd:$wt)>;
3374def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3375                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3376                                                MSA128BOpnd:$ws,
3377                                                MSA128BOpnd:$wt)>;
3378
3379def NORI_B : NORI_B_ENC, NORI_B_DESC;
3380
3381def OR_V : OR_V_ENC, OR_V_DESC;
3382def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3383                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3384                                              MSA128BOpnd:$ws,
3385                                              MSA128BOpnd:$wt)>;
3386def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3387                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3388                                              MSA128BOpnd:$ws,
3389                                              MSA128BOpnd:$wt)>;
3390def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3391                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3392                                              MSA128BOpnd:$ws,
3393                                              MSA128BOpnd:$wt)>;
3394
3395def ORI_B : ORI_B_ENC, ORI_B_DESC;
3396
3397def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3398def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3399def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3400def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3401
3402def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3403def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3404def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3405def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3406
3407def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3408def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3409def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3410def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3411
3412def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3413def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3414def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3415def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3416
3417def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3418def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3419def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3420def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3421
3422def SHF_B : SHF_B_ENC, SHF_B_DESC;
3423def SHF_H : SHF_H_ENC, SHF_H_DESC;
3424def SHF_W : SHF_W_ENC, SHF_W_DESC;
3425
3426def SLD_B : SLD_B_ENC, SLD_B_DESC;
3427def SLD_H : SLD_H_ENC, SLD_H_DESC;
3428def SLD_W : SLD_W_ENC, SLD_W_DESC;
3429def SLD_D : SLD_D_ENC, SLD_D_DESC;
3430
3431def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3432def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3433def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3434def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3435
3436def SLL_B : SLL_B_ENC, SLL_B_DESC;
3437def SLL_H : SLL_H_ENC, SLL_H_DESC;
3438def SLL_W : SLL_W_ENC, SLL_W_DESC;
3439def SLL_D : SLL_D_ENC, SLL_D_DESC;
3440
3441def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3442def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3443def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3444def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3445
3446def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3447def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3448def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3449def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3450
3451def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3452def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3453def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3454def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3455
3456def SRA_B : SRA_B_ENC, SRA_B_DESC;
3457def SRA_H : SRA_H_ENC, SRA_H_DESC;
3458def SRA_W : SRA_W_ENC, SRA_W_DESC;
3459def SRA_D : SRA_D_ENC, SRA_D_DESC;
3460
3461def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3462def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3463def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3464def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3465
3466def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3467def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3468def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3469def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3470
3471def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3472def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3473def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3474def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3475
3476def SRL_B : SRL_B_ENC, SRL_B_DESC;
3477def SRL_H : SRL_H_ENC, SRL_H_DESC;
3478def SRL_W : SRL_W_ENC, SRL_W_DESC;
3479def SRL_D : SRL_D_ENC, SRL_D_DESC;
3480
3481def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3482def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3483def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3484def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3485
3486def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3487def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3488def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3489def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3490
3491def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3492def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3493def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3494def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3495
3496def ST_B: ST_B_ENC, ST_B_DESC;
3497def ST_H: ST_H_ENC, ST_H_DESC;
3498def ST_W: ST_W_ENC, ST_W_DESC;
3499def ST_D: ST_D_ENC, ST_D_DESC;
3500
3501def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3502def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3503def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3504def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3505
3506def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3507def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3508def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3509def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3510
3511def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3512def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3513def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3514def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3515
3516def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3517def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3518def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3519def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3520
3521def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3522def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3523def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3524def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3525
3526def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3527def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3528def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3529def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3530
3531def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3532def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3533def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3534def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3535
3536def XOR_V : XOR_V_ENC, XOR_V_DESC;
3537def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3538                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3539                                                MSA128BOpnd:$ws,
3540                                                MSA128BOpnd:$wt)>;
3541def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3542                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3543                                                MSA128BOpnd:$ws,
3544                                                MSA128BOpnd:$wt)>;
3545def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3546                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3547                                                MSA128BOpnd:$ws,
3548                                                MSA128BOpnd:$wt)>;
3549
3550def XORI_B : XORI_B_ENC, XORI_B_DESC;
3551
3552// Patterns.
3553class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3554  Pat<pattern, result>, Requires<pred>;
3555
3556def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3557             (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3558
3559def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>;
3560def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
3561def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>;
3562
3563def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr),
3564                   (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>;
3565def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr),
3566                   (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>;
3567def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr),
3568                   (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>;
3569
3570class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3571                                RegisterOperand ROWS = ROWD,
3572                                InstrItinClass itin = NoItinerary> :
3573  MSAPseudo<(outs ROWD:$wd),
3574            (ins ROWS:$ws),
3575            [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3576  InstrItinClass Itinerary = itin;
3577}
3578def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3579             PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3580                                           MSA128WOpnd:$ws)>;
3581def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3582             PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3583                                           MSA128DOpnd:$ws)>;
3584
3585class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3586                       RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3587   MSAPat<(DstVT (bitconvert SrcVT:$src)),
3588          (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3589
3590// These are endian-independent because the element size doesnt change
3591def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3592def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3593def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3594def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3595def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3596def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3597
3598// Little endian bitcasts are always no-ops
3599def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3600def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3601def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3602def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3603def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3604def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3605
3606def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3607def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3608def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3609def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3610def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3611
3612def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3613def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3614def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3615def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3616def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3617
3618def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3619def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3620def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3621def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3622def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3623
3624def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3625def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3626def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3627def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3628def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3629
3630def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3631def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3632def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3633def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3634def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3635
3636// Big endian bitcasts expand to shuffle instructions.
3637// This is because bitcast is defined to be a store/load sequence and the
3638// vector store/load instructions are mixed-endian with respect to the vector
3639// as a whole (little endian with respect to element order, but big endian
3640// elements).
3641
3642class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3643                                      RegisterClass DstRC, MSAInst Insn,
3644                                      RegisterClass ViaRC> :
3645  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3646         (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3647                           DstRC),
3648         [HasMSA, IsBE]>;
3649
3650class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3651                                    RegisterClass DstRC, MSAInst Insn,
3652                                    RegisterClass ViaRC> :
3653  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3654         (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3655                           DstRC),
3656         [HasMSA, IsBE]>;
3657
3658class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3659                                  RegisterClass DstRC> :
3660  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3661
3662class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3663                                  RegisterClass DstRC> :
3664  MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3665
3666class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3667                                  RegisterClass DstRC> :
3668  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3669         (COPY_TO_REGCLASS
3670           (SHF_W
3671             (COPY_TO_REGCLASS
3672               (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3673               MSA128W), 177),
3674           DstRC),
3675         [HasMSA, IsBE]>;
3676
3677class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3678                                  RegisterClass DstRC> :
3679  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3680
3681class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3682                                  RegisterClass DstRC> :
3683  MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3684
3685class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3686                                  RegisterClass DstRC> :
3687  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3688
3689def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3690def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3691def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3692def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3693def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3694def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3695
3696def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3697def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3698def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3699def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3700def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3701
3702def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3703def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3704def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3705def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3706def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3707
3708def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3709def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3710def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3711def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3712def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3713
3714def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3715def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3716def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3717def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3718def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3719
3720def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3721def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3722def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3723def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3724def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3725
3726def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3727def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3728def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3729def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3730def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3731
3732// Pseudos used to implement BNZ.df, and BZ.df
3733
3734class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3735                                   RegisterClass RCWS,
3736                                   InstrItinClass itin = NoItinerary> :
3737  MipsPseudo<(outs GPR32:$dst),
3738             (ins RCWS:$ws),
3739             [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3740  bit usesCustomInserter = 1;
3741}
3742
3743def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3744                                                MSA128B, NoItinerary>;
3745def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3746                                                MSA128H, NoItinerary>;
3747def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3748                                                MSA128W, NoItinerary>;
3749def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3750                                                MSA128D, NoItinerary>;
3751def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3752                                                MSA128B, NoItinerary>;
3753
3754def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3755                                               MSA128B, NoItinerary>;
3756def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3757                                               MSA128H, NoItinerary>;
3758def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3759                                               MSA128W, NoItinerary>;
3760def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3761                                               MSA128D, NoItinerary>;
3762def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3763                                               MSA128B, NoItinerary>;
3764
3765// Pseudoes used to implement transparent fp16 support.
3766
3767let ASEPredicate = [HasMSA] in {
3768 def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
3769                          [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> {
3770   let usesCustomInserter = 1;
3771 }
3772
3773 def LD_F16 : MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr),
3774                         [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]> {
3775   let usesCustomInserter = 1;
3776 }
3777
3778 def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd),
3779                                         (ins MSA128F16:$ws),
3780                              [(set FGR32Opnd:$fd,
3781                                    (f32 (fpextend MSA128F16:$ws)))]> {
3782  let usesCustomInserter = 1;
3783 }
3784
3785 def MSA_FP_ROUND_W_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
3786                                        (ins FGR32Opnd:$fs),
3787                              [(set MSA128F16:$wd,
3788                                    (f16 (fpround FGR32Opnd:$fs)))]> {
3789  let usesCustomInserter = 1;
3790 }
3791
3792 def MSA_FP_EXTEND_D_PSEUDO : MipsPseudo<(outs FGR64Opnd:$fd),
3793                                         (ins MSA128F16:$ws),
3794                              [(set FGR64Opnd:$fd,
3795                                    (f64 (fpextend MSA128F16:$ws)))]> {
3796  let usesCustomInserter = 1;
3797 }
3798
3799 def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
3800                                        (ins FGR64Opnd:$fs),
3801                              [(set MSA128F16:$wd,
3802                                    (f16 (fpround FGR64Opnd:$fs)))]> {
3803  let usesCustomInserter = 1;
3804 }
3805
3806 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
3807               (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>, ISA_MIPS1,
3808               ASE_MSA;
3809
3810 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
3811               (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
3812                         (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
3813       ISA_MIPS1_NOT_32R6_64R6, ASE_MSA;
3814}
3815
3816def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
3817  APInt Imm;
3818  SDNode *BV = N->getOperand(0).getNode();
3819  EVT EltTy = N->getValueType(0).getVectorElementType();
3820
3821  return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
3822         Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
3823}]>;
3824
3825def immi32Cst7  : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>;
3826def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>;
3827def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>;
3828
3829def vsplati8imm7 :   PatFrag<(ops node:$wt),
3830                             (and node:$wt, (vsplati8 immi32Cst7))>;
3831def vsplati16imm15 : PatFrag<(ops node:$wt),
3832                             (and node:$wt, (vsplati16 immi32Cst15))>;
3833def vsplati32imm31 : PatFrag<(ops node:$wt),
3834                             (and node:$wt, (vsplati32 immi32Cst31))>;
3835def vsplati64imm63 : PatFrag<(ops node:$wt),
3836                             (and node:$wt, vsplati64_imm_eq_63)>;
3837
3838class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> :
3839  MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))),
3840         (VT (Insn VT:$ws, VT:$wt))>;
3841
3842class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> :
3843  MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))),
3844         (VT (Insn VT:$ws, VT:$wt))>;
3845
3846multiclass MSAShiftPats<SDNode Node, string Insn> {
3847  def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B),
3848                    (vsplati8 immi32Cst7)>;
3849  def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H),
3850                    (vsplati16 immi32Cst15)>;
3851  def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W),
3852                    (vsplati32 immi32Cst31)>;
3853  def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt,
3854                                                   vsplati64_imm_eq_63)))),
3855               (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3856}
3857
3858multiclass MSABitPats<SDNode Node, string Insn> {
3859  def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>;
3860  def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>;
3861  def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>;
3862  def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1),
3863                                     (vsplati64imm63 v2i64:$wt))),
3864               (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3865}
3866
3867defm : MSAShiftPats<shl, "SLL">;
3868defm : MSAShiftPats<srl, "SRL">;
3869defm : MSAShiftPats<sra, "SRA">;
3870defm : MSABitPats<xor, "BNEG">;
3871defm : MSABitPats<or, "BSET">;
3872
3873def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1,
3874                                       (vsplati8imm7 v16i8:$wt)),
3875                                  immAllOnesV)),
3876             (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>;
3877def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1,
3878                                       (vsplati16imm15 v8i16:$wt)),
3879                             immAllOnesV)),
3880             (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>;
3881def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1,
3882                                       (vsplati32imm31 v4i32:$wt)),
3883                             immAllOnesV)),
3884             (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>;
3885def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
3886                                       (vsplati64imm63 v2i64:$wt)),
3887                                  (bitconvert (v4i32 immAllOnesV)))),
3888             (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>;
3889
3890// Vector extraction with fixed index.
3891//
3892// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
3893// COPY_U_W, even for the zero-extended case. This is because our forward
3894// compatibility strategy is to consider registers to be infinitely
3895// sign-extended so that a MIPS64 can execute MIPS32 code without getting
3896// different register values.
3897def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx),
3898             (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3899def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx),
3900             (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3901
3902// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than
3903// COPY_U_D, even for the zero-extended case. This is because our forward
3904// compatibility strategy is to consider registers to be infinitely
3905// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64
3906// code without getting different register values.
3907def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx),
3908             (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3909def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx),
3910             (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3911
3912// Vector extraction with variable index
3913def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3914             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3915                                                                  i32:$idx),
3916                                                         sub_lo)),
3917                                    GPR32), (i32 24))>;
3918def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3919             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3920                                                                  i32:$idx),
3921                                                         sub_lo)),
3922                                    GPR32), (i32 16))>;
3923def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3924             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3925                                                             i32:$idx),
3926                                                    sub_lo)),
3927                               GPR32)>;
3928def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3929             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3930                                                             i32:$idx),
3931                                                    sub_64)),
3932                               GPR64), [HasMSA, IsGP64bit]>;
3933
3934def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3935             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3936                                                                  i32:$idx),
3937                                                         sub_lo)),
3938                                    GPR32), (i32 24))>;
3939def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3940             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3941                                                                  i32:$idx),
3942                                                         sub_lo)),
3943                                    GPR32), (i32 16))>;
3944def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3945             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3946                                                             i32:$idx),
3947                                                    sub_lo)),
3948                               GPR32)>;
3949def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3950             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3951                                                             i32:$idx),
3952                                                    sub_64)),
3953                               GPR64), [HasMSA, IsGP64bit]>;
3954
3955def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3956             (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3957                                           i32:$idx),
3958                                  sub_lo))>;
3959def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3960             (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
3961                                           i32:$idx),
3962                                  sub_64))>;
3963
3964// Vector extraction with variable index (N64 ABI)
3965def : MSAPat<
3966  (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3967  (SRA (COPY_TO_REGCLASS
3968         (i32 (EXTRACT_SUBREG
3969                (SPLAT_B v16i8:$ws,
3970                  (COPY_TO_REGCLASS
3971                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3972                sub_lo)),
3973         GPR32),
3974       (i32 24))>;
3975def : MSAPat<
3976  (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
3977  (SRA (COPY_TO_REGCLASS
3978         (i32 (EXTRACT_SUBREG
3979                (SPLAT_H v8i16:$ws,
3980                  (COPY_TO_REGCLASS
3981                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3982                sub_lo)),
3983         GPR32),
3984       (i32 16))>;
3985def : MSAPat<
3986  (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
3987  (COPY_TO_REGCLASS
3988    (i32 (EXTRACT_SUBREG
3989           (SPLAT_W v4i32:$ws,
3990             (COPY_TO_REGCLASS
3991               (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3992           sub_lo)),
3993    GPR32)>;
3994def : MSAPat<
3995  (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
3996  (COPY_TO_REGCLASS
3997    (i64 (EXTRACT_SUBREG
3998           (SPLAT_D v2i64:$ws,
3999             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4000           sub_64)),
4001    GPR64), [HasMSA, IsGP64bit]>;
4002
4003def : MSAPat<
4004  (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
4005  (SRL (COPY_TO_REGCLASS
4006         (i32 (EXTRACT_SUBREG
4007                 (SPLAT_B v16i8:$ws,
4008                   (COPY_TO_REGCLASS
4009                     (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4010                 sub_lo)),
4011         GPR32),
4012       (i32 24))>;
4013def : MSAPat<
4014  (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
4015  (SRL (COPY_TO_REGCLASS
4016         (i32 (EXTRACT_SUBREG
4017                (SPLAT_H v8i16:$ws,
4018                  (COPY_TO_REGCLASS
4019                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4020                sub_lo)),
4021         GPR32),
4022       (i32 16))>;
4023def : MSAPat<
4024  (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
4025  (COPY_TO_REGCLASS
4026    (i32 (EXTRACT_SUBREG
4027           (SPLAT_W v4i32:$ws,
4028             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4029           sub_lo)),
4030    GPR32)>;
4031def : MSAPat<
4032  (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
4033  (COPY_TO_REGCLASS
4034    (i64 (EXTRACT_SUBREG
4035           (SPLAT_D v2i64:$ws,
4036             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4037           sub_64)),
4038    GPR64),
4039  [HasMSA, IsGP64bit]>;
4040
4041def : MSAPat<
4042  (f32 (vector_extract v4f32:$ws, i64:$idx)),
4043  (f32 (EXTRACT_SUBREG
4044         (SPLAT_W v4f32:$ws,
4045           (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4046         sub_lo))>;
4047def : MSAPat<
4048  (f64 (vector_extract v2f64:$ws, i64:$idx)),
4049  (f64 (EXTRACT_SUBREG
4050         (SPLAT_D v2f64:$ws,
4051           (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
4052         sub_64))>;
4053
4054def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4055             (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4056def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4057             (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4058def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4059             (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4060def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4061             (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4062def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4063             (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4064def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4065             (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4066def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
4067             (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
4068def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
4069             (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
4070