1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39class MMRel;
40
41def Std2MicroMips : InstrMapping {
42  let FilterClass = "MMRel";
43  // Instructions with the same BaseOpcode and isNVStore values form a row.
44  let RowFields = ["BaseOpcode"];
45  // Instructions with the same predicate sense form a column.
46  let ColFields = ["Arch"];
47  // The key column is the unpredicated instructions.
48  let KeyCol = ["se"];
49  // Value columns are PredSense=true and PredSense=false
50  let ValueCols = [["se"], ["micromips"]];
51}
52
53class StdMMR6Rel;
54
55def Std2MicroMipsR6 : InstrMapping {
56  let FilterClass = "StdMMR6Rel";
57  // Instructions with the same BaseOpcode and isNVStore values form a row.
58  let RowFields = ["BaseOpcode"];
59  // Instructions with the same predicate sense form a column.
60  let ColFields = ["Arch"];
61  // The key column is the unpredicated instructions.
62  let KeyCol = ["se"];
63  // Value columns are PredSense=true and PredSense=false
64  let ValueCols = [["se"], ["micromipsr6"]];
65}
66
67class StdArch {
68  string Arch = "se";
69}
70
71// Generic Mips Format
72class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
73               InstrItinClass itin, Format f>: Instruction, PredicateControl
74{
75  field bits<32> Inst;
76  Format Form = f;
77
78  let Namespace = "Mips";
79
80  let Size = 4;
81
82  bits<6> Opcode = 0;
83
84  // Top 6 bits are the 'opcode' field
85  let Inst{31-26} = Opcode;
86
87  let OutOperandList = outs;
88  let InOperandList  = ins;
89
90  let AsmString   = asmstr;
91  let Pattern     = pattern;
92  let Itinerary   = itin;
93
94  //
95  // Attributes specific to Mips instructions...
96  //
97  bits<4> FormBits     = Form.Value;
98  bit isCTI            = 0; // Any form of Control Transfer Instruction.
99                            // Required for MIPSR6
100  bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
101  bit IsPCRelativeLoad = 0; // Load instruction with implicit source register
102                            // ($pc) and with explicit offset and destination
103                            // register
104  bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
105                            // present in MIPS-I to MIPS-III.
106
107  // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h.
108  let TSFlags{3-0}   = FormBits;
109  let TSFlags{4}     = isCTI;
110  let TSFlags{5}     = hasForbiddenSlot;
111  let TSFlags{6}     = IsPCRelativeLoad;
112  let TSFlags{7}     = hasFCCRegOperand;
113
114  let DecoderNamespace = "Mips";
115
116  field bits<32> SoftFail = 0;
117}
118
119// Mips32/64 Instruction Format
120class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
121             InstrItinClass itin, Format f, string opstr = ""> :
122  MipsInst<outs, ins, asmstr, pattern, itin, f> {
123  let EncodingPredicates = [NotInMips16Mode];
124  string BaseOpcode = opstr;
125  string Arch;
126}
127
128// Mips Pseudo Instructions Format
129class MipsPseudo<dag outs, dag ins, list<dag> pattern,
130                 InstrItinClass itin = IIPseudo> :
131  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
132  let isCodeGenOnly = 1;
133  let isPseudo = 1;
134}
135
136// Mips32/64 Pseudo Instruction Format
137class PseudoSE<dag outs, dag ins, list<dag> pattern,
138               InstrItinClass itin = IIPseudo> :
139  MipsPseudo<outs, ins, pattern, itin> {
140  let EncodingPredicates = [NotInMips16Mode];
141}
142
143// Pseudo-instructions for alternate assembly syntax (never used by codegen).
144// These are aliases that require C++ handling to convert to the target
145// instruction, while InstAliases can be handled directly by tblgen.
146class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
147  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
148  let isPseudo = 1;
149  let Pattern = [];
150}
151//===----------------------------------------------------------------------===//
152// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
153//===----------------------------------------------------------------------===//
154
155class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
156         list<dag> pattern, InstrItinClass itin>:
157  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
158{
159  bits<5>  rd;
160  bits<5>  rs;
161  bits<5>  rt;
162  bits<5>  shamt;
163  bits<6>  funct;
164
165  let Opcode = op;
166  let funct  = _funct;
167
168  let Inst{25-21} = rs;
169  let Inst{20-16} = rt;
170  let Inst{15-11} = rd;
171  let Inst{10-6}  = shamt;
172  let Inst{5-0}   = funct;
173}
174
175//===----------------------------------------------------------------------===//
176// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
177//===----------------------------------------------------------------------===//
178
179class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
180         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
181{
182  bits<5>  rt;
183  bits<5>  rs;
184  bits<16> imm16;
185
186  let Opcode = op;
187
188  let Inst{25-21} = rs;
189  let Inst{20-16} = rt;
190  let Inst{15-0}  = imm16;
191}
192
193class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
194                  list<dag> pattern, InstrItinClass itin>:
195  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
196{
197  bits<5>  rs;
198  bits<5>  rt;
199  bits<16> imm16;
200
201  let Opcode = op;
202
203  let Inst{25-21} = rs;
204  let Inst{20-16} = rt;
205  let Inst{15-0}  = imm16;
206}
207
208//===----------------------------------------------------------------------===//
209// Format J instruction class in Mips : <|opcode|address|>
210//===----------------------------------------------------------------------===//
211
212class FJ<bits<6> op> : StdArch
213{
214  bits<26> target;
215
216  bits<32> Inst;
217
218  let Inst{31-26} = op;
219  let Inst{25-0}  = target;
220}
221
222//===----------------------------------------------------------------------===//
223// MFC instruction class in Mips : <|op|mf|rt|rd|gst|0000|sel|>
224//===----------------------------------------------------------------------===//
225class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
226  bits<5> rt;
227  bits<5> rd;
228  bits<3> sel;
229
230  bits<32> Inst;
231
232  let Inst{31-26} = op;
233  let Inst{25-21} = mfmt;
234  let Inst{20-16} = rt;
235  let Inst{15-11} = rd;
236  let Inst{10-8}  = guest;
237  let Inst{7-3}   = 0;
238  let Inst{2-0}   = sel;
239}
240
241class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
242  bits<5>  rt;
243  bits<16> imm16;
244
245  bits<32> Inst;
246
247  let Inst{31-26} = op;
248  let Inst{25-21} = mfmt;
249  let Inst{20-16} = rt;
250  let Inst{15-0}  = imm16;
251}
252
253class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
254  bits<5> rd;
255  bits<5> rs;
256  bits<5> rt;
257
258  bits<32> Inst;
259
260  let Inst{31-26} = op;
261  let Inst{25-21} = rs;
262  let Inst{20-16} = rt;
263  let Inst{15-11} = rd;
264  let Inst{10-6}  = 0;
265  let Inst{5-0}   = funct;
266}
267
268class ADDI_FM<bits<6> op> : StdArch {
269  bits<5>  rs;
270  bits<5>  rt;
271  bits<16> imm16;
272
273  bits<32> Inst;
274
275  let Inst{31-26} = op;
276  let Inst{25-21} = rs;
277  let Inst{20-16} = rt;
278  let Inst{15-0}  = imm16;
279}
280
281class SRA_FM<bits<6> funct, bit rotate> : StdArch {
282  bits<5> rd;
283  bits<5> rt;
284  bits<5> shamt;
285
286  bits<32> Inst;
287
288  let Inst{31-26} = 0;
289  let Inst{25-22} = 0;
290  let Inst{21}    = rotate;
291  let Inst{20-16} = rt;
292  let Inst{15-11} = rd;
293  let Inst{10-6}  = shamt;
294  let Inst{5-0}   = funct;
295}
296
297class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
298  bits<5> rd;
299  bits<5> rt;
300  bits<5> rs;
301
302  bits<32> Inst;
303
304  let Inst{31-26} = 0;
305  let Inst{25-21} = rs;
306  let Inst{20-16} = rt;
307  let Inst{15-11} = rd;
308  let Inst{10-7}  = 0;
309  let Inst{6}     = rotate;
310  let Inst{5-0}   = funct;
311}
312
313class BEQ_FM<bits<6> op> : StdArch {
314  bits<5>  rs;
315  bits<5>  rt;
316  bits<16> offset;
317
318  bits<32> Inst;
319
320  let Inst{31-26} = op;
321  let Inst{25-21} = rs;
322  let Inst{20-16} = rt;
323  let Inst{15-0}  = offset;
324}
325
326class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
327  bits<5>  rs;
328  bits<16> offset;
329
330  bits<32> Inst;
331
332  let Inst{31-26} = op;
333  let Inst{25-21} = rs;
334  let Inst{20-16} = funct;
335  let Inst{15-0}  = offset;
336}
337
338class BBIT_FM<bits<6> op> : StdArch {
339  bits<5>  rs;
340  bits<5>  p;
341  bits<16> offset;
342
343  bits<32> Inst;
344
345  let Inst{31-26} = op;
346  let Inst{25-21} = rs;
347  let Inst{20-16} = p;
348  let Inst{15-0}  = offset;
349}
350
351class SLTI_FM<bits<6> op> : StdArch {
352  bits<5> rt;
353  bits<5> rs;
354  bits<16> imm16;
355
356  bits<32> Inst;
357
358  let Inst{31-26} = op;
359  let Inst{25-21} = rs;
360  let Inst{20-16} = rt;
361  let Inst{15-0}  = imm16;
362}
363
364class MFLO_FM<bits<6> funct> : StdArch {
365  bits<5> rd;
366
367  bits<32> Inst;
368
369  let Inst{31-26} = 0;
370  let Inst{25-16} = 0;
371  let Inst{15-11} = rd;
372  let Inst{10-6}  = 0;
373  let Inst{5-0}   = funct;
374}
375
376class MTLO_FM<bits<6> funct> : StdArch {
377  bits<5> rs;
378
379  bits<32> Inst;
380
381  let Inst{31-26} = 0;
382  let Inst{25-21} = rs;
383  let Inst{20-6}  = 0;
384  let Inst{5-0}   = funct;
385}
386
387class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
388  bits<5> rd;
389  bits<5> rt;
390
391  bits<32> Inst;
392
393  let Inst{31-26} = 0x1f;
394  let Inst{25-21} = 0;
395  let Inst{20-16} = rt;
396  let Inst{15-11} = rd;
397  let Inst{10-6}  = funct;
398  let Inst{5-0}   = funct2;
399}
400
401class CLO_FM<bits<6> funct> : StdArch {
402  bits<5> rd;
403  bits<5> rs;
404  bits<5> rt;
405
406  bits<32> Inst;
407
408  let Inst{31-26} = 0x1c;
409  let Inst{25-21} = rs;
410  let Inst{20-16} = rt;
411  let Inst{15-11} = rd;
412  let Inst{10-6}  = 0;
413  let Inst{5-0}   = funct;
414  let rt = rd;
415}
416
417class LUI_FM : StdArch {
418  bits<5> rt;
419  bits<16> imm16;
420
421  bits<32> Inst;
422
423  let Inst{31-26} = 0xf;
424  let Inst{25-21} = 0;
425  let Inst{20-16} = rt;
426  let Inst{15-0}  = imm16;
427}
428
429class JALR_FM {
430  bits<5> rd;
431  bits<5> rs;
432
433  bits<32> Inst;
434
435  let Inst{31-26} = 0;
436  let Inst{25-21} = rs;
437  let Inst{20-16} = 0;
438  let Inst{15-11} = rd;
439  let Inst{10-6}  = 0;
440  let Inst{5-0}   = 9;
441}
442
443class BGEZAL_FM<bits<5> funct> : StdArch {
444  bits<5>  rs;
445  bits<16> offset;
446
447  bits<32> Inst;
448
449  let Inst{31-26} = 1;
450  let Inst{25-21} = rs;
451  let Inst{20-16} = funct;
452  let Inst{15-0}  = offset;
453}
454
455class SYNC_FM : StdArch {
456  bits<5> stype;
457
458  bits<32> Inst;
459
460  let Inst{31-26} = 0;
461  let Inst{10-6}  = stype;
462  let Inst{5-0}   = 0xf;
463}
464
465class SYNCI_FM : StdArch {
466  // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
467  bits<21> addr;
468  bits<5> rs = addr{20-16};
469  bits<16> offset = addr{15-0};
470
471  bits<32> Inst;
472
473  let Inst{31-26} = 0b000001;
474  let Inst{25-21} = rs;
475  let Inst{20-16} = 0b11111;
476  let Inst{15-0}  = offset;
477}
478
479class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
480  bits<5>  rs;
481  bits<5>  rt;
482
483  bits<32> Inst;
484
485  let Inst{31-26} = op;
486  let Inst{25-21} = rs;
487  let Inst{20-16} = rt;
488  let Inst{15-6}  = 0;
489  let Inst{5-0}   = funct;
490}
491
492class EXT_FM<bits<6> funct> : StdArch {
493  bits<5> rt;
494  bits<5> rs;
495  bits<5> pos;
496  bits<5> size;
497
498  bits<32> Inst;
499
500  let Inst{31-26} = 0x1f;
501  let Inst{25-21} = rs;
502  let Inst{20-16} = rt;
503  let Inst{15-11} = size;
504  let Inst{10-6}  = pos;
505  let Inst{5-0}   = funct;
506}
507
508class RDHWR_FM : StdArch {
509  bits<5> rt;
510  bits<5> rd;
511  bits<3> sel;
512
513  bits<32> Inst;
514
515  let Inst{31-26} = 0x1f;
516  let Inst{25-21} = 0;
517  let Inst{20-16} = rt;
518  let Inst{15-11} = rd;
519  let Inst{10-9}  = 0b00;
520  let Inst{8-6}   = sel;
521  let Inst{5-0}   = 0x3b;
522}
523
524class TEQ_FM<bits<6> funct> : StdArch {
525  bits<5> rs;
526  bits<5> rt;
527  bits<10> code_;
528
529  bits<32> Inst;
530
531  let Inst{31-26} = 0;
532  let Inst{25-21} = rs;
533  let Inst{20-16} = rt;
534  let Inst{15-6}  = code_;
535  let Inst{5-0}   = funct;
536}
537
538class TEQI_FM<bits<5> funct> : StdArch {
539  bits<5> rs;
540  bits<16> imm16;
541
542  bits<32> Inst;
543
544  let Inst{31-26} = 1;
545  let Inst{25-21} = rs;
546  let Inst{20-16}   = funct;
547  let Inst{15-0}  = imm16;
548}
549
550class WAIT_FM : StdArch {
551  bits<32> Inst;
552
553  let Inst{31-26} = 0x10;
554  let Inst{25}    = 1;
555  let Inst{24-6}  = 0;
556  let Inst{5-0}   = 0x20;
557}
558
559class EXTS_FM<bits<6> funct> : StdArch {
560  bits<5> rt;
561  bits<5> rs;
562  bits<5> pos;
563  bits<5> lenm1;
564
565  bits<32> Inst;
566
567  let Inst{31-26} = 0x1c;
568  let Inst{25-21} = rs;
569  let Inst{20-16} = rt;
570  let Inst{15-11} = lenm1;
571  let Inst{10-6}  = pos;
572  let Inst{5-0}   = funct;
573}
574
575class MTMR_FM<bits<6> funct> : StdArch {
576  bits<5> rs;
577
578  bits<32> Inst;
579
580  let Inst{31-26} = 0x1c;
581  let Inst{25-21} = rs;
582  let Inst{20-6}  = 0;
583  let Inst{5-0}   = funct;
584}
585
586class POP_FM<bits<6> funct> : StdArch {
587  bits<5> rd;
588  bits<5> rs;
589
590  bits<32> Inst;
591
592  let Inst{31-26} = 0x1c;
593  let Inst{25-21} = rs;
594  let Inst{20-16} = 0;
595  let Inst{15-11} = rd;
596  let Inst{10-6}  = 0;
597  let Inst{5-0}   = funct;
598}
599
600class SEQ_FM<bits<6> funct> : StdArch {
601  bits<5> rd;
602  bits<5> rs;
603  bits<5> rt;
604
605  bits<32> Inst;
606
607  let Inst{31-26} = 0x1c;
608  let Inst{25-21} = rs;
609  let Inst{20-16} = rt;
610  let Inst{15-11} = rd;
611  let Inst{10-6}  = 0;
612  let Inst{5-0}   = funct;
613}
614
615class SEQI_FM<bits<6> funct> : StdArch {
616  bits<5> rs;
617  bits<5> rt;
618  bits<10> imm10;
619
620  bits<32> Inst;
621
622  let Inst{31-26} = 0x1c;
623  let Inst{25-21} = rs;
624  let Inst{20-16} = rt;
625  let Inst{15-6}  = imm10;
626  let Inst{5-0}   = funct;
627}
628
629//===----------------------------------------------------------------------===//
630//  System calls format <op|code_|funct>
631//===----------------------------------------------------------------------===//
632
633class SYS_FM<bits<6> funct> : StdArch
634{
635  bits<20> code_;
636  bits<32> Inst;
637  let Inst{31-26} = 0x0;
638  let Inst{25-6} = code_;
639  let Inst{5-0}  = funct;
640}
641
642//===----------------------------------------------------------------------===//
643//  Break instruction format <op|code_1|funct>
644//===----------------------------------------------------------------------===//
645
646class BRK_FM<bits<6> funct> : StdArch
647{
648  bits<10> code_1;
649  bits<10> code_2;
650  bits<32> Inst;
651  let Inst{31-26} = 0x0;
652  let Inst{25-16} = code_1;
653  let Inst{15-6}  = code_2;
654  let Inst{5-0}   = funct;
655}
656
657//===----------------------------------------------------------------------===//
658//  Exception return format <Cop0|1|0|funct>
659//===----------------------------------------------------------------------===//
660
661class ER_FM<bits<6> funct, bit LLBit> : StdArch
662{
663  bits<32> Inst;
664  let Inst{31-26} = 0x10;
665  let Inst{25}    = 1;
666  let Inst{24-7}  = 0;
667  let Inst{6} = LLBit;
668  let Inst{5-0}   = funct;
669}
670
671//===----------------------------------------------------------------------===//
672//  Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
673//===----------------------------------------------------------------------===//
674
675class EI_FM<bits<1> sc> : StdArch
676{
677  bits<32> Inst;
678  bits<5> rt;
679  let Inst{31-26} = 0x10;
680  let Inst{25-21} = 0xb;
681  let Inst{20-16} = rt;
682  let Inst{15-11} = 0xc;
683  let Inst{10-6}  = 0;
684  let Inst{5}     = sc;
685  let Inst{4-0}   = 0;
686}
687
688//===----------------------------------------------------------------------===//
689//
690//  FLOATING POINT INSTRUCTION FORMATS
691//
692//  opcode  - operation code.
693//  fs      - src reg.
694//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
695//  fd      - dst reg, only used on 3 regs instr.
696//  fmt     - double or single precision.
697//  funct   - combined with opcode field give us an operation code.
698//
699//===----------------------------------------------------------------------===//
700
701//===----------------------------------------------------------------------===//
702// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
703//===----------------------------------------------------------------------===//
704
705class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
706  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
707{
708  bits<5>  ft;
709  bits<5>  base;
710  bits<16> imm16;
711
712  let Opcode = op;
713
714  let Inst{25-21} = base;
715  let Inst{20-16} = ft;
716  let Inst{15-0}  = imm16;
717}
718
719class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
720  bits<5> fd;
721  bits<5> fs;
722  bits<5> ft;
723
724  bits<32> Inst;
725
726  let Inst{31-26} = 0x11;
727  let Inst{25-21} = fmt;
728  let Inst{20-16} = ft;
729  let Inst{15-11} = fs;
730  let Inst{10-6}  = fd;
731  let Inst{5-0}   = funct;
732}
733
734class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
735  bits<5> fd;
736  bits<5> fs;
737
738  bits<32> Inst;
739
740  let Inst{31-26} = 0x11;
741  let Inst{25-21} = fmt;
742  let Inst{20-16} = 0;
743  let Inst{15-11} = fs;
744  let Inst{10-6}  = fd;
745  let Inst{5-0}   = funct;
746}
747
748class MFC1_FM<bits<5> funct> : StdArch {
749  bits<5> rt;
750  bits<5> fs;
751
752  bits<32> Inst;
753
754  let Inst{31-26} = 0x11;
755  let Inst{25-21} = funct;
756  let Inst{20-16} = rt;
757  let Inst{15-11} = fs;
758  let Inst{10-0}  = 0;
759}
760
761class LW_FM<bits<6> op> : StdArch {
762  bits<5> rt;
763  bits<21> addr;
764
765  bits<32> Inst;
766
767  let Inst{31-26} = op;
768  let Inst{25-21} = addr{20-16};
769  let Inst{20-16} = rt;
770  let Inst{15-0}  = addr{15-0};
771}
772
773class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
774  bits<5> fd;
775  bits<5> fr;
776  bits<5> fs;
777  bits<5> ft;
778
779  bits<32> Inst;
780
781  let Inst{31-26} = 0x13;
782  let Inst{25-21} = fr;
783  let Inst{20-16} = ft;
784  let Inst{15-11} = fs;
785  let Inst{10-6}  = fd;
786  let Inst{5-3}   = funct;
787  let Inst{2-0}   = fmt;
788}
789
790class LWXC1_FM<bits<6> funct> : StdArch {
791  bits<5> fd;
792  bits<5> base;
793  bits<5> index;
794
795  bits<32> Inst;
796
797  let Inst{31-26} = 0x13;
798  let Inst{25-21} = base;
799  let Inst{20-16} = index;
800  let Inst{15-11} = 0;
801  let Inst{10-6}  = fd;
802  let Inst{5-0}   = funct;
803}
804
805class SWXC1_FM<bits<6> funct> : StdArch {
806  bits<5> fs;
807  bits<5> base;
808  bits<5> index;
809
810  bits<32> Inst;
811
812  let Inst{31-26} = 0x13;
813  let Inst{25-21} = base;
814  let Inst{20-16} = index;
815  let Inst{15-11} = fs;
816  let Inst{10-6}  = 0;
817  let Inst{5-0}   = funct;
818}
819
820class BC1F_FM<bit nd, bit tf> : StdArch {
821  bits<3>  fcc;
822  bits<16> offset;
823
824  bits<32> Inst;
825
826  let Inst{31-26} = 0x11;
827  let Inst{25-21} = 0x8;
828  let Inst{20-18} = fcc;
829  let Inst{17} = nd;
830  let Inst{16} = tf;
831  let Inst{15-0} = offset;
832}
833
834class CEQS_FM<bits<5> fmt> : StdArch {
835  bits<5> fs;
836  bits<5> ft;
837  bits<3> fcc;
838  bits<4> cond;
839
840  bits<32> Inst;
841
842  let Inst{31-26} = 0x11;
843  let Inst{25-21} = fmt;
844  let Inst{20-16} = ft;
845  let Inst{15-11} = fs;
846  let Inst{10-8} = fcc;
847  let Inst{7-4} = 0x3;
848  let Inst{3-0} = cond;
849}
850
851class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
852  let cond = c;
853}
854
855class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
856  bits<5> fd;
857  bits<5> fs;
858  bits<5> rt;
859
860  bits<32> Inst;
861
862  let Inst{31-26} = 0x11;
863  let Inst{25-21} = fmt;
864  let Inst{20-16} = rt;
865  let Inst{15-11} = fs;
866  let Inst{10-6} = fd;
867  let Inst{5-0} = funct;
868}
869
870class CMov_F_I_FM<bit tf> : StdArch {
871  bits<5> rd;
872  bits<5> rs;
873  bits<3> fcc;
874
875  bits<32> Inst;
876
877  let Inst{31-26} = 0;
878  let Inst{25-21} = rs;
879  let Inst{20-18} = fcc;
880  let Inst{17} = 0;
881  let Inst{16} = tf;
882  let Inst{15-11} = rd;
883  let Inst{10-6} = 0;
884  let Inst{5-0} = 1;
885}
886
887class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
888  bits<5> fd;
889  bits<5> fs;
890  bits<3> fcc;
891
892  bits<32> Inst;
893
894  let Inst{31-26} = 0x11;
895  let Inst{25-21} = fmt;
896  let Inst{20-18} = fcc;
897  let Inst{17} = 0;
898  let Inst{16} = tf;
899  let Inst{15-11} = fs;
900  let Inst{10-6} = fd;
901  let Inst{5-0} = 0x11;
902}
903
904class BARRIER_FM<bits<5> op> : StdArch {
905  bits<32> Inst;
906
907  let Inst{31-26} = 0; // SPECIAL
908  let Inst{25-21} = 0;
909  let Inst{20-16} = 0; // rt = 0
910  let Inst{15-11} = 0; // rd = 0
911  let Inst{10-6} = op; // Operation
912  let Inst{5-0} = 0;   // SLL
913}
914
915class SDBBP_FM : StdArch {
916  bits<20> code_;
917
918  bits<32> Inst;
919
920  let Inst{31-26} = 0b011100; // SPECIAL2
921  let Inst{25-6} = code_;
922  let Inst{5-0} = 0b111111;   // SDBBP
923}
924
925class JR_HB_FM<bits<6> op> : StdArch{
926  bits<5> rs;
927
928  bits<32> Inst;
929
930  let Inst{31-26} = 0; // SPECIAL
931  let Inst{25-21} = rs;
932  let Inst{20-11} = 0;
933  let Inst{10} = 1;
934  let Inst{9-6} = 0;
935  let Inst{5-0} = op;
936}
937
938class JALR_HB_FM<bits<6> op> : StdArch {
939  bits<5> rd;
940  bits<5> rs;
941
942  bits<32> Inst;
943
944  let Inst{31-26} = 0; // SPECIAL
945  let Inst{25-21} = rs;
946  let Inst{20-16} = 0;
947  let Inst{15-11} = rd;
948  let Inst{10} = 1;
949  let Inst{9-6} = 0;
950  let Inst{5-0} = op;
951}
952
953class COP0_TLB_FM<bits<6> op> : StdArch {
954  bits<32> Inst;
955
956  let Inst{31-26} = 0x10; // COP0
957  let Inst{25} = 1;       // CO
958  let Inst{24-6} = 0;
959  let Inst{5-0} = op;     // Operation
960}
961
962class CACHEOP_FM<bits<6> op> : StdArch {
963  bits<21> addr;
964  bits<5> hint;
965  bits<5> base = addr{20-16};
966  bits<16> offset = addr{15-0};
967
968  bits<32> Inst;
969
970  let Inst{31-26} = op;
971  let Inst{25-21} = base;
972  let Inst{20-16} = hint;
973  let Inst{15-0}  = offset;
974}
975
976class HYPCALL_FM<bits<6> op> : StdArch {
977  bits<10> code_;
978
979  bits<32> Inst;
980
981  let Inst{31-26} = 0b010000;
982  let Inst{25}    = 1;
983  let Inst{20-11} = code_;
984  let Inst{5-0}   = op;
985}
986