1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an Mips MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstPrinter.h"
14 #include "MipsInstrInfo.h"
15 #include "MipsMCExpr.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "asm-printer"
26 
27 #define PRINT_ALIAS_INSTR
28 #include "MipsGenAsmWriter.inc"
29 
30 template<unsigned R>
isReg(const MCInst & MI,unsigned OpNo)31 static bool isReg(const MCInst &MI, unsigned OpNo) {
32   assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33   return MI.getOperand(OpNo).getReg() == R;
34 }
35 
MipsFCCToString(Mips::CondCode CC)36 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
37   switch (CC) {
38   case FCOND_F:
39   case FCOND_T:   return "f";
40   case FCOND_UN:
41   case FCOND_OR:  return "un";
42   case FCOND_OEQ:
43   case FCOND_UNE: return "eq";
44   case FCOND_UEQ:
45   case FCOND_ONE: return "ueq";
46   case FCOND_OLT:
47   case FCOND_UGE: return "olt";
48   case FCOND_ULT:
49   case FCOND_OGE: return "ult";
50   case FCOND_OLE:
51   case FCOND_UGT: return "ole";
52   case FCOND_ULE:
53   case FCOND_OGT: return "ule";
54   case FCOND_SF:
55   case FCOND_ST:  return "sf";
56   case FCOND_NGLE:
57   case FCOND_GLE: return "ngle";
58   case FCOND_SEQ:
59   case FCOND_SNE: return "seq";
60   case FCOND_NGL:
61   case FCOND_GL:  return "ngl";
62   case FCOND_LT:
63   case FCOND_NLT: return "lt";
64   case FCOND_NGE:
65   case FCOND_GE:  return "nge";
66   case FCOND_LE:
67   case FCOND_NLE: return "le";
68   case FCOND_NGT:
69   case FCOND_GT:  return "ngt";
70   }
71   llvm_unreachable("Impossible condition code!");
72 }
73 
printRegName(raw_ostream & OS,unsigned RegNo) const74 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
75   OS << '$' << StringRef(getRegisterName(RegNo)).lower();
76 }
77 
printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O)78 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
79                                 StringRef Annot, const MCSubtargetInfo &STI,
80                                 raw_ostream &O) {
81   switch (MI->getOpcode()) {
82   default:
83     break;
84   case Mips::RDHWR:
85   case Mips::RDHWR64:
86     O << "\t.set\tpush\n";
87     O << "\t.set\tmips32r2\n";
88     break;
89   case Mips::Save16:
90     O << "\tsave\t";
91     printSaveRestore(MI, STI, O);
92     O << " # 16 bit inst\n";
93     return;
94   case Mips::SaveX16:
95     O << "\tsave\t";
96     printSaveRestore(MI, STI, O);
97     O << "\n";
98     return;
99   case Mips::Restore16:
100     O << "\trestore\t";
101     printSaveRestore(MI, STI, O);
102     O << " # 16 bit inst\n";
103     return;
104   case Mips::RestoreX16:
105     O << "\trestore\t";
106     printSaveRestore(MI, STI, O);
107     O << "\n";
108     return;
109   }
110 
111   // Try to print any aliases first.
112   if (!printAliasInstr(MI, Address, STI, O) &&
113       !printAlias(*MI, Address, STI, O))
114     printInstruction(MI, Address, STI, O);
115   printAnnotation(O, Annot);
116 
117   switch (MI->getOpcode()) {
118   default:
119     break;
120   case Mips::RDHWR:
121   case Mips::RDHWR64:
122     O << "\n\t.set\tpop";
123   }
124 }
125 
printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)126 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
127                                    const MCSubtargetInfo &STI, raw_ostream &O) {
128   const MCOperand &Op = MI->getOperand(OpNo);
129   if (Op.isReg()) {
130     printRegName(O, Op.getReg());
131     return;
132   }
133 
134   if (Op.isImm()) {
135     O << formatImm(Op.getImm());
136     return;
137   }
138 
139   assert(Op.isExpr() && "unknown operand kind in printOperand");
140   Op.getExpr()->print(O, &MAI, true);
141 }
142 
printJumpOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)143 void MipsInstPrinter::printJumpOperand(const MCInst *MI, unsigned OpNo,
144                                        const MCSubtargetInfo &STI,
145                                        raw_ostream &O) {
146   const MCOperand &Op = MI->getOperand(OpNo);
147   if (!Op.isImm())
148     return printOperand(MI, OpNo, STI, O);
149 
150   if (PrintBranchImmAsAddress)
151     O << formatHex(Op.getImm());
152   else
153     O << formatImm(Op.getImm());
154 }
155 
printBranchOperand(const MCInst * MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)156 void MipsInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
157                                          unsigned OpNo,
158                                          const MCSubtargetInfo &STI,
159                                          raw_ostream &O) {
160   const MCOperand &Op = MI->getOperand(OpNo);
161   if (!Op.isImm())
162     return printOperand(MI, OpNo, STI, O);
163 
164   if (PrintBranchImmAsAddress) {
165     uint64_t Target = Address + Op.getImm();
166     if (STI.hasFeature(Mips::FeatureMips32))
167       Target &= 0xffffffff;
168     else if (STI.hasFeature(Mips::FeatureMips16))
169       Target &= 0xffff;
170     O << formatHex(Target);
171   } else {
172     O << formatImm(Op.getImm());
173   }
174 }
175 
176 template <unsigned Bits, unsigned Offset>
printUImm(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O)177 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum,
178                                 const MCSubtargetInfo &STI, raw_ostream &O) {
179   const MCOperand &MO = MI->getOperand(opNum);
180   if (MO.isImm()) {
181     uint64_t Imm = MO.getImm();
182     Imm -= Offset;
183     Imm &= (1 << Bits) - 1;
184     Imm += Offset;
185     O << formatImm(Imm);
186     return;
187   }
188 
189   printOperand(MI, opNum, STI, O);
190 }
191 
printMemOperand(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O)192 void MipsInstPrinter::printMemOperand(const MCInst *MI, int opNum,
193                                       const MCSubtargetInfo &STI,
194                                       raw_ostream &O) {
195   // Load/Store memory operands -- imm($reg)
196   // If PIC target the target is loaded as the
197   // pattern lw $25,%call16($28)
198 
199   // opNum can be invalid if instruction had reglist as operand.
200   // MemOperand is always last operand of instruction (base + offset).
201   switch (MI->getOpcode()) {
202   default:
203     break;
204   case Mips::SWM32_MM:
205   case Mips::LWM32_MM:
206   case Mips::SWM16_MM:
207   case Mips::SWM16_MMR6:
208   case Mips::LWM16_MM:
209   case Mips::LWM16_MMR6:
210     opNum = MI->getNumOperands() - 2;
211     break;
212   }
213 
214   printOperand(MI, opNum + 1, STI, O);
215   O << "(";
216   printOperand(MI, opNum, STI, O);
217   O << ")";
218 }
219 
printMemOperandEA(const MCInst * MI,int opNum,const MCSubtargetInfo & STI,raw_ostream & O)220 void MipsInstPrinter::printMemOperandEA(const MCInst *MI, int opNum,
221                                         const MCSubtargetInfo &STI,
222                                         raw_ostream &O) {
223   // when using stack locations for not load/store instructions
224   // print the same way as all normal 3 operand instructions.
225   printOperand(MI, opNum, STI, O);
226   O << ", ";
227   printOperand(MI, opNum + 1, STI, O);
228 }
229 
printFCCOperand(const MCInst * MI,int opNum,const MCSubtargetInfo &,raw_ostream & O)230 void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum,
231                                       const MCSubtargetInfo & /* STI */,
232                                       raw_ostream &O) {
233   const MCOperand &MO = MI->getOperand(opNum);
234   O << MipsFCCToString((Mips::CondCode)MO.getImm());
235 }
236 
237 void MipsInstPrinter::
printSHFMask(const MCInst * MI,int opNum,raw_ostream & O)238 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
239   llvm_unreachable("TODO");
240 }
241 
printAlias(const char * Str,const MCInst & MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & OS,bool IsBranch)242 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
243                                  uint64_t Address, unsigned OpNo,
244                                  const MCSubtargetInfo &STI, raw_ostream &OS,
245                                  bool IsBranch) {
246   OS << "\t" << Str << "\t";
247   if (IsBranch)
248     printBranchOperand(&MI, Address, OpNo, STI, OS);
249   else
250     printOperand(&MI, OpNo, STI, OS);
251   return true;
252 }
253 
printAlias(const char * Str,const MCInst & MI,uint64_t Address,unsigned OpNo0,unsigned OpNo1,const MCSubtargetInfo & STI,raw_ostream & OS,bool IsBranch)254 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
255                                  uint64_t Address, unsigned OpNo0,
256                                  unsigned OpNo1, const MCSubtargetInfo &STI,
257                                  raw_ostream &OS, bool IsBranch) {
258   printAlias(Str, MI, Address, OpNo0, STI, OS, IsBranch);
259   OS << ", ";
260   if (IsBranch)
261     printBranchOperand(&MI, Address, OpNo1, STI, OS);
262   else
263     printOperand(&MI, OpNo1, STI, OS);
264   return true;
265 }
266 
printAlias(const MCInst & MI,uint64_t Address,const MCSubtargetInfo & STI,raw_ostream & OS)267 bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address,
268                                  const MCSubtargetInfo &STI, raw_ostream &OS) {
269   switch (MI.getOpcode()) {
270   case Mips::BEQ:
271   case Mips::BEQ_MM:
272     // beq $zero, $zero, $L2 => b $L2
273     // beq $r0, $zero, $L2 => beqz $r0, $L2
274     return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
275             printAlias("b", MI, Address, 2, STI, OS, true)) ||
276            (isReg<Mips::ZERO>(MI, 1) &&
277             printAlias("beqz", MI, Address, 0, 2, STI, OS, true));
278   case Mips::BEQ64:
279     // beq $r0, $zero, $L2 => beqz $r0, $L2
280     return isReg<Mips::ZERO_64>(MI, 1) &&
281            printAlias("beqz", MI, Address, 0, 2, STI, OS, true);
282   case Mips::BNE:
283   case Mips::BNE_MM:
284     // bne $r0, $zero, $L2 => bnez $r0, $L2
285     return isReg<Mips::ZERO>(MI, 1) &&
286            printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
287   case Mips::BNE64:
288     // bne $r0, $zero, $L2 => bnez $r0, $L2
289     return isReg<Mips::ZERO_64>(MI, 1) &&
290            printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
291   case Mips::BGEZAL:
292     // bgezal $zero, $L1 => bal $L1
293     return isReg<Mips::ZERO>(MI, 0) &&
294            printAlias("bal", MI, Address, 1, STI, OS, true);
295   case Mips::BC1T:
296     // bc1t $fcc0, $L1 => bc1t $L1
297     return isReg<Mips::FCC0>(MI, 0) &&
298            printAlias("bc1t", MI, Address, 1, STI, OS, true);
299   case Mips::BC1F:
300     // bc1f $fcc0, $L1 => bc1f $L1
301     return isReg<Mips::FCC0>(MI, 0) &&
302            printAlias("bc1f", MI, Address, 1, STI, OS, true);
303   case Mips::JALR:
304     // jalr $zero, $r1 => jr $r1
305     // jalr $ra, $r1 => jalr $r1
306     return (isReg<Mips::ZERO>(MI, 0) &&
307             printAlias("jr", MI, Address, 1, STI, OS)) ||
308            (isReg<Mips::RA>(MI, 0) &&
309             printAlias("jalr", MI, Address, 1, STI, OS));
310   case Mips::JALR64:
311     // jalr $zero, $r1 => jr $r1
312     // jalr $ra, $r1 => jalr $r1
313     return (isReg<Mips::ZERO_64>(MI, 0) &&
314             printAlias("jr", MI, Address, 1, STI, OS)) ||
315            (isReg<Mips::RA_64>(MI, 0) &&
316             printAlias("jalr", MI, Address, 1, STI, OS));
317   case Mips::NOR:
318   case Mips::NOR_MM:
319   case Mips::NOR_MMR6:
320     // nor $r0, $r1, $zero => not $r0, $r1
321     return isReg<Mips::ZERO>(MI, 2) &&
322            printAlias("not", MI, Address, 0, 1, STI, OS);
323   case Mips::NOR64:
324     // nor $r0, $r1, $zero => not $r0, $r1
325     return isReg<Mips::ZERO_64>(MI, 2) &&
326            printAlias("not", MI, Address, 0, 1, STI, OS);
327   case Mips::OR:
328   case Mips::ADDu:
329     // or $r0, $r1, $zero => move $r0, $r1
330     // addu $r0, $r1, $zero => move $r0, $r1
331     return isReg<Mips::ZERO>(MI, 2) &&
332            printAlias("move", MI, Address, 0, 1, STI, OS);
333   default:
334     return false;
335   }
336 }
337 
printSaveRestore(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O)338 void MipsInstPrinter::printSaveRestore(const MCInst *MI,
339                                        const MCSubtargetInfo &STI,
340                                        raw_ostream &O) {
341   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
342     if (i != 0) O << ", ";
343     if (MI->getOperand(i).isReg())
344       printRegName(O, MI->getOperand(i).getReg());
345     else
346       printUImm<16>(MI, i, STI, O);
347   }
348 }
349 
printRegisterList(const MCInst * MI,int opNum,const MCSubtargetInfo &,raw_ostream & O)350 void MipsInstPrinter::printRegisterList(const MCInst *MI, int opNum,
351                                         const MCSubtargetInfo & /* STI */,
352                                         raw_ostream &O) {
353   // - 2 because register List is always first operand of instruction and it is
354   // always followed by memory operand (base + offset).
355   for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
356     if (i != opNum)
357       O << ", ";
358     printRegName(O, MI->getOperand(i).getReg());
359   }
360 }
361