1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/MipsMCTargetDesc.h"
15 #include "Mips.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Compiler.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include <cassert>
30 #include <cstdint>
31
32 using namespace llvm;
33
34 #define DEBUG_TYPE "mips-disassembler"
35
36 using DecodeStatus = MCDisassembler::DecodeStatus;
37
38 namespace {
39
40 class MipsDisassembler : public MCDisassembler {
41 bool IsMicroMips;
42 bool IsBigEndian;
43
44 public:
MipsDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx,bool IsBigEndian)45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
46 : MCDisassembler(STI, Ctx),
47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
48 IsBigEndian(IsBigEndian) {}
49
hasMips2() const50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
hasMips3() const51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
hasMips32() const52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
53
hasMips32r6() const54 bool hasMips32r6() const {
55 return STI.getFeatureBits()[Mips::FeatureMips32r6];
56 }
57
isFP64() const58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
59
isGP64() const60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
61
isPTR64() const62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
63
hasCnMips() const64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
65
hasCOP3() const66 bool hasCOP3() const {
67 // Only present in MIPS-I and MIPS-II
68 return !hasMips32() && !hasMips3();
69 }
70
71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
72 ArrayRef<uint8_t> Bytes, uint64_t Address,
73 raw_ostream &VStream,
74 raw_ostream &CStream) const override;
75 };
76
77 } // end anonymous namespace
78
79 // Forward declare these because the autogenerated code will reference them.
80 // Definitions are further down.
81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
82 unsigned RegNo,
83 uint64_t Address,
84 const void *Decoder);
85
86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
87 unsigned RegNo,
88 uint64_t Address,
89 const void *Decoder);
90
91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
92 unsigned RegNo,
93 uint64_t Address,
94 const void *Decoder);
95
96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
97 unsigned RegNo,
98 uint64_t Address,
99 const void *Decoder);
100
101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
102 unsigned RegNo,
103 uint64_t Address,
104 const void *Decoder);
105
106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
107 unsigned RegNo,
108 uint64_t Address,
109 const void *Decoder);
110
111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
112 unsigned Insn,
113 uint64_t Address,
114 const void *Decoder);
115
116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
117 unsigned RegNo,
118 uint64_t Address,
119 const void *Decoder);
120
121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
122 unsigned RegNo,
123 uint64_t Address,
124 const void *Decoder);
125
126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
127 unsigned RegNo,
128 uint64_t Address,
129 const void *Decoder);
130
131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
132 unsigned RegNo,
133 uint64_t Address,
134 const void *Decoder);
135
136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
137 unsigned RegNo,
138 uint64_t Address,
139 const void *Decoder);
140
141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address,
143 const void *Decoder);
144
145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
146 unsigned Insn,
147 uint64_t Address,
148 const void *Decoder);
149
150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
151 unsigned RegNo,
152 uint64_t Address,
153 const void *Decoder);
154
155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
156 unsigned RegNo,
157 uint64_t Address,
158 const void *Decoder);
159
160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
161 unsigned RegNo,
162 uint64_t Address,
163 const void *Decoder);
164
165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
166 unsigned RegNo,
167 uint64_t Address,
168 const void *Decoder);
169
170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
171 unsigned RegNo,
172 uint64_t Address,
173 const void *Decoder);
174
175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
176 unsigned RegNo,
177 uint64_t Address,
178 const void *Decoder);
179
180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
181 unsigned RegNo,
182 uint64_t Address,
183 const void *Decoder);
184
185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
186 unsigned RegNo,
187 uint64_t Address,
188 const void *Decoder);
189
190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
191 unsigned RegNo,
192 uint64_t Address,
193 const void *Decoder);
194
195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
196 unsigned RegNo,
197 uint64_t Address,
198 const void *Decoder);
199
200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
201 unsigned RegNo,
202 uint64_t Address,
203 const void *Decoder);
204
205 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
206 unsigned Offset,
207 uint64_t Address,
208 const void *Decoder);
209
210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
211 unsigned Offset,
212 uint64_t Address,
213 const void *Decoder);
214
215 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
216 unsigned Insn,
217 uint64_t Address,
218 const void *Decoder);
219
220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
221 unsigned Offset,
222 uint64_t Address,
223 const void *Decoder);
224
225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
226 unsigned Offset,
227 uint64_t Address,
228 const void *Decoder);
229
230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
231 unsigned Offset,
232 uint64_t Address,
233 const void *Decoder);
234
235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
236 // shifted left by 1 bit.
237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
238 unsigned Offset,
239 uint64_t Address,
240 const void *Decoder);
241
242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
243 // shifted left by 1 bit.
244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
245 unsigned Offset,
246 uint64_t Address,
247 const void *Decoder);
248
249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
250 // shifted left by 1 bit.
251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
252 unsigned Offset,
253 uint64_t Address,
254 const void *Decoder);
255
256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
257 // shifted left by 1 bit.
258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
259 unsigned Offset,
260 uint64_t Address,
261 const void *Decoder);
262
263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
264 // shifted left by 1 bit.
265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
266 unsigned Insn,
267 uint64_t Address,
268 const void *Decoder);
269
270 static DecodeStatus DecodeMem(MCInst &Inst,
271 unsigned Insn,
272 uint64_t Address,
273 const void *Decoder);
274
275 static DecodeStatus DecodeMemEVA(MCInst &Inst,
276 unsigned Insn,
277 uint64_t Address,
278 const void *Decoder);
279
280 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
281 unsigned Insn,
282 uint64_t Address,
283 const void *Decoder);
284
285 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
286 const void *Decoder);
287
288 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
289 unsigned Insn,
290 uint64_t Address,
291 const void *Decoder);
292
293 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
294 unsigned Insn,
295 uint64_t Address,
296 const void *Decoder);
297
298 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
299 unsigned Insn,
300 uint64_t Address,
301 const void *Decoder);
302
303 static DecodeStatus DecodeSyncI(MCInst &Inst,
304 unsigned Insn,
305 uint64_t Address,
306 const void *Decoder);
307
308 static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
309 unsigned Insn,
310 uint64_t Address,
311 const void *Decoder);
312
313 static DecodeStatus DecodeSynciR6(MCInst &Inst,
314 unsigned Insn,
315 uint64_t Address,
316 const void *Decoder);
317
318 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320
321 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
322 unsigned Insn,
323 uint64_t Address,
324 const void *Decoder);
325
326 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
327 unsigned Insn,
328 uint64_t Address,
329 const void *Decoder);
330
331 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
332 unsigned Insn,
333 uint64_t Address,
334 const void *Decoder);
335
336 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
337 unsigned Insn,
338 uint64_t Address,
339 const void *Decoder);
340
341 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
342 unsigned Insn,
343 uint64_t Address,
344 const void *Decoder);
345
346 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
347 unsigned Insn,
348 uint64_t Address,
349 const void *Decoder);
350
351 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
352 unsigned Insn,
353 uint64_t Address,
354 const void *Decoder);
355
356 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
357 uint64_t Address,
358 const void *Decoder);
359
360 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
361 uint64_t Address,
362 const void *Decoder);
363
364 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
365 const void *Decoder);
366
367 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
368 const void *Decoder);
369
370 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372
373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
374 uint64_t Address,
375 const void *Decoder);
376
377 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
378 unsigned Insn,
379 uint64_t Address,
380 const void *Decoder);
381
382 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
383 unsigned Value,
384 uint64_t Address,
385 const void *Decoder);
386
387 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
388 unsigned Value,
389 uint64_t Address,
390 const void *Decoder);
391
392 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
393 unsigned Value,
394 uint64_t Address,
395 const void *Decoder);
396
397 template <unsigned Bits, int Offset, int Scale>
398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
399 uint64_t Address,
400 const void *Decoder);
401
402 template <unsigned Bits, int Offset>
DecodeUImmWithOffset(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
404 uint64_t Address,
405 const void *Decoder) {
406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
407 Decoder);
408 }
409
410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
412 uint64_t Address,
413 const void *Decoder);
414
415 static DecodeStatus DecodeInsSize(MCInst &Inst,
416 unsigned Insn,
417 uint64_t Address,
418 const void *Decoder);
419
420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
421 uint64_t Address, const void *Decoder);
422
423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
424 uint64_t Address, const void *Decoder);
425
426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
427 uint64_t Address, const void *Decoder);
428
429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
430 uint64_t Address, const void *Decoder);
431
432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
433 uint64_t Address, const void *Decoder);
434
435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
436 /// handle.
437 template <typename InsnType>
438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
439 const void *Decoder);
440
441 template <typename InsnType>
442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
443 const void *Decoder);
444
445 template <typename InsnType>
446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
447 const void *Decoder);
448
449 template <typename InsnType>
450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
451 const void *Decoder);
452
453 template <typename InsnType>
454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
455 const void *Decoder);
456
457 template <typename InsnType>
458 static DecodeStatus
459 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
460 const void *Decoder);
461
462 template <typename InsnType>
463 static DecodeStatus
464 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
465 const void *Decoder);
466
467 template <typename InsnType>
468 static DecodeStatus
469 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
470 const void *Decoder);
471
472 template <typename InsnType>
473 static DecodeStatus
474 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
475 const void *Decoder);
476
477 template <typename InsnType>
478 static DecodeStatus
479 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
480 const void *Decoder);
481
482 template <typename InsnType>
483 static DecodeStatus
484 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
485 const void *Decoder);
486
487 template <typename InsnType>
488 static DecodeStatus
489 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
490 const void *Decoder);
491
492 template <typename InsnType>
493 static DecodeStatus
494 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
495 const void *Decoder);
496
497 template <typename InsnType>
498 static DecodeStatus
499 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
500 const void *Decoder);
501
502 template <typename InsnType>
503 static DecodeStatus
504 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
505 const void *Decoder);
506
507 template <typename InsnType>
508 static DecodeStatus
509 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
510 const void *Decoder);
511
512 template <typename InsnType>
513 static DecodeStatus
514 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
515 const void *Decoder);
516
517 template <typename InsnType>
518 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
519 const void *Decoder);
520
521 template <typename InsnType>
522 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
523 const void *Decoder);
524
525 template <typename InsnType>
526 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
527 const void *Decoder);
528
529 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
530 uint64_t Address,
531 const void *Decoder);
532
533 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
534 uint64_t Address,
535 const void *Decoder);
536
537 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
538 uint64_t Address,
539 const void *Decoder);
540
541 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
542 uint64_t Address, const void *Decoder);
543
544 namespace llvm {
545
546 Target &getTheMipselTarget();
547 Target &getTheMipsTarget();
548 Target &getTheMips64Target();
549 Target &getTheMips64elTarget();
550
551 } // end namespace llvm
552
createMipsDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)553 static MCDisassembler *createMipsDisassembler(
554 const Target &T,
555 const MCSubtargetInfo &STI,
556 MCContext &Ctx) {
557 return new MipsDisassembler(STI, Ctx, true);
558 }
559
createMipselDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)560 static MCDisassembler *createMipselDisassembler(
561 const Target &T,
562 const MCSubtargetInfo &STI,
563 MCContext &Ctx) {
564 return new MipsDisassembler(STI, Ctx, false);
565 }
566
LLVMInitializeMipsDisassembler()567 extern "C" void LLVMInitializeMipsDisassembler() {
568 // Register the disassembler.
569 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
570 createMipsDisassembler);
571 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
572 createMipselDisassembler);
573 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
574 createMipsDisassembler);
575 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
576 createMipselDisassembler);
577 }
578
579 #include "MipsGenDisassemblerTables.inc"
580
getReg(const void * D,unsigned RC,unsigned RegNo)581 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
582 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
583 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
584 return *(RegInfo->getRegClass(RC).begin() + RegNo);
585 }
586
587 template <typename InsnType>
DecodeINSVE_DF(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)588 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
589 const void *Decoder) {
590 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
591
592 // The size of the n field depends on the element size
593 // The register class also depends on this.
594 InsnType tmp = fieldFromInstruction(insn, 17, 5);
595 unsigned NSize = 0;
596 DecodeFN RegDecoder = nullptr;
597 if ((tmp & 0x18) == 0x00) { // INSVE_B
598 NSize = 4;
599 RegDecoder = DecodeMSA128BRegisterClass;
600 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
601 NSize = 3;
602 RegDecoder = DecodeMSA128HRegisterClass;
603 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
604 NSize = 2;
605 RegDecoder = DecodeMSA128WRegisterClass;
606 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
607 NSize = 1;
608 RegDecoder = DecodeMSA128DRegisterClass;
609 } else
610 llvm_unreachable("Invalid encoding");
611
612 assert(NSize != 0 && RegDecoder != nullptr);
613
614 // $wd
615 tmp = fieldFromInstruction(insn, 6, 5);
616 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
617 return MCDisassembler::Fail;
618 // $wd_in
619 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
620 return MCDisassembler::Fail;
621 // $n
622 tmp = fieldFromInstruction(insn, 16, NSize);
623 MI.addOperand(MCOperand::createImm(tmp));
624 // $ws
625 tmp = fieldFromInstruction(insn, 11, 5);
626 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
627 return MCDisassembler::Fail;
628 // $n2
629 MI.addOperand(MCOperand::createImm(0));
630
631 return MCDisassembler::Success;
632 }
633
634 template <typename InsnType>
DecodeDAHIDATIMMR6(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)635 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
636 const void *Decoder) {
637 InsnType Rs = fieldFromInstruction(insn, 16, 5);
638 InsnType Imm = fieldFromInstruction(insn, 0, 16);
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
640 Rs)));
641 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
642 Rs)));
643 MI.addOperand(MCOperand::createImm(Imm));
644
645 return MCDisassembler::Success;
646 }
647
648 template <typename InsnType>
DecodeDAHIDATI(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)649 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
650 const void *Decoder) {
651 InsnType Rs = fieldFromInstruction(insn, 21, 5);
652 InsnType Imm = fieldFromInstruction(insn, 0, 16);
653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
654 Rs)));
655 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
656 Rs)));
657 MI.addOperand(MCOperand::createImm(Imm));
658
659 return MCDisassembler::Success;
660 }
661
662 template <typename InsnType>
DecodeAddiGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)663 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
664 uint64_t Address,
665 const void *Decoder) {
666 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
667 // (otherwise we would have matched the ADDI instruction from the earlier
668 // ISA's instead).
669 //
670 // We have:
671 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
672 // BOVC if rs >= rt
673 // BEQZALC if rs == 0 && rt != 0
674 // BEQC if rs < rt && rs != 0
675
676 InsnType Rs = fieldFromInstruction(insn, 21, 5);
677 InsnType Rt = fieldFromInstruction(insn, 16, 5);
678 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
679 bool HasRs = false;
680
681 if (Rs >= Rt) {
682 MI.setOpcode(Mips::BOVC);
683 HasRs = true;
684 } else if (Rs != 0 && Rs < Rt) {
685 MI.setOpcode(Mips::BEQC);
686 HasRs = true;
687 } else
688 MI.setOpcode(Mips::BEQZALC);
689
690 if (HasRs)
691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
692 Rs)));
693
694 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
695 Rt)));
696 MI.addOperand(MCOperand::createImm(Imm));
697
698 return MCDisassembler::Success;
699 }
700
701 template <typename InsnType>
DecodePOP35GroupBranchMMR6(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)702 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
703 uint64_t Address,
704 const void *Decoder) {
705 InsnType Rt = fieldFromInstruction(insn, 21, 5);
706 InsnType Rs = fieldFromInstruction(insn, 16, 5);
707 int64_t Imm = 0;
708
709 if (Rs >= Rt) {
710 MI.setOpcode(Mips::BOVC_MMR6);
711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
712 Rt)));
713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
714 Rs)));
715 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
716 } else if (Rs != 0 && Rs < Rt) {
717 MI.setOpcode(Mips::BEQC_MMR6);
718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
719 Rs)));
720 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
721 Rt)));
722 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
723 } else {
724 MI.setOpcode(Mips::BEQZALC_MMR6);
725 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
726 Rt)));
727 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
728 }
729
730 MI.addOperand(MCOperand::createImm(Imm));
731
732 return MCDisassembler::Success;
733 }
734
735 template <typename InsnType>
DecodeDaddiGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)736 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
737 uint64_t Address,
738 const void *Decoder) {
739 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
740 // (otherwise we would have matched the ADDI instruction from the earlier
741 // ISA's instead).
742 //
743 // We have:
744 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
745 // BNVC if rs >= rt
746 // BNEZALC if rs == 0 && rt != 0
747 // BNEC if rs < rt && rs != 0
748
749 InsnType Rs = fieldFromInstruction(insn, 21, 5);
750 InsnType Rt = fieldFromInstruction(insn, 16, 5);
751 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
752 bool HasRs = false;
753
754 if (Rs >= Rt) {
755 MI.setOpcode(Mips::BNVC);
756 HasRs = true;
757 } else if (Rs != 0 && Rs < Rt) {
758 MI.setOpcode(Mips::BNEC);
759 HasRs = true;
760 } else
761 MI.setOpcode(Mips::BNEZALC);
762
763 if (HasRs)
764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
765 Rs)));
766
767 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
768 Rt)));
769 MI.addOperand(MCOperand::createImm(Imm));
770
771 return MCDisassembler::Success;
772 }
773
774 template <typename InsnType>
DecodePOP37GroupBranchMMR6(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)775 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
776 uint64_t Address,
777 const void *Decoder) {
778 InsnType Rt = fieldFromInstruction(insn, 21, 5);
779 InsnType Rs = fieldFromInstruction(insn, 16, 5);
780 int64_t Imm = 0;
781
782 if (Rs >= Rt) {
783 MI.setOpcode(Mips::BNVC_MMR6);
784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
785 Rt)));
786 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
787 Rs)));
788 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
789 } else if (Rs != 0 && Rs < Rt) {
790 MI.setOpcode(Mips::BNEC_MMR6);
791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
792 Rs)));
793 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
794 Rt)));
795 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
796 } else {
797 MI.setOpcode(Mips::BNEZALC_MMR6);
798 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
799 Rt)));
800 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
801 }
802
803 MI.addOperand(MCOperand::createImm(Imm));
804
805 return MCDisassembler::Success;
806 }
807
808 template <typename InsnType>
DecodePOP65GroupBranchMMR6(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)809 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
810 uint64_t Address,
811 const void *Decoder) {
812 // We have:
813 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
814 // Invalid if rt == 0
815 // BGTZC_MMR6 if rs == 0 && rt != 0
816 // BLTZC_MMR6 if rs == rt && rt != 0
817 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
818
819 InsnType Rt = fieldFromInstruction(insn, 21, 5);
820 InsnType Rs = fieldFromInstruction(insn, 16, 5);
821 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
822 bool HasRs = false;
823
824 if (Rt == 0)
825 return MCDisassembler::Fail;
826 else if (Rs == 0)
827 MI.setOpcode(Mips::BGTZC_MMR6);
828 else if (Rs == Rt)
829 MI.setOpcode(Mips::BLTZC_MMR6);
830 else {
831 MI.setOpcode(Mips::BLTC_MMR6);
832 HasRs = true;
833 }
834
835 if (HasRs)
836 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
837 Rs)));
838
839 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
840 Rt)));
841
842 MI.addOperand(MCOperand::createImm(Imm));
843
844 return MCDisassembler::Success;
845 }
846
847 template <typename InsnType>
DecodePOP75GroupBranchMMR6(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)848 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
849 uint64_t Address,
850 const void *Decoder) {
851 // We have:
852 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
853 // Invalid if rt == 0
854 // BLEZC_MMR6 if rs == 0 && rt != 0
855 // BGEZC_MMR6 if rs == rt && rt != 0
856 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
857
858 InsnType Rt = fieldFromInstruction(insn, 21, 5);
859 InsnType Rs = fieldFromInstruction(insn, 16, 5);
860 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
861 bool HasRs = false;
862
863 if (Rt == 0)
864 return MCDisassembler::Fail;
865 else if (Rs == 0)
866 MI.setOpcode(Mips::BLEZC_MMR6);
867 else if (Rs == Rt)
868 MI.setOpcode(Mips::BGEZC_MMR6);
869 else {
870 HasRs = true;
871 MI.setOpcode(Mips::BGEC_MMR6);
872 }
873
874 if (HasRs)
875 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
876 Rs)));
877
878 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
879 Rt)));
880
881 MI.addOperand(MCOperand::createImm(Imm));
882
883 return MCDisassembler::Success;
884 }
885
886 template <typename InsnType>
DecodeBlezlGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)887 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
888 uint64_t Address,
889 const void *Decoder) {
890 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
891 // (otherwise we would have matched the BLEZL instruction from the earlier
892 // ISA's instead).
893 //
894 // We have:
895 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
896 // Invalid if rs == 0
897 // BLEZC if rs == 0 && rt != 0
898 // BGEZC if rs == rt && rt != 0
899 // BGEC if rs != rt && rs != 0 && rt != 0
900
901 InsnType Rs = fieldFromInstruction(insn, 21, 5);
902 InsnType Rt = fieldFromInstruction(insn, 16, 5);
903 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
904 bool HasRs = false;
905
906 if (Rt == 0)
907 return MCDisassembler::Fail;
908 else if (Rs == 0)
909 MI.setOpcode(Mips::BLEZC);
910 else if (Rs == Rt)
911 MI.setOpcode(Mips::BGEZC);
912 else {
913 HasRs = true;
914 MI.setOpcode(Mips::BGEC);
915 }
916
917 if (HasRs)
918 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
919 Rs)));
920
921 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
922 Rt)));
923
924 MI.addOperand(MCOperand::createImm(Imm));
925
926 return MCDisassembler::Success;
927 }
928
929 template <typename InsnType>
DecodeBgtzlGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)930 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
931 uint64_t Address,
932 const void *Decoder) {
933 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
934 // (otherwise we would have matched the BGTZL instruction from the earlier
935 // ISA's instead).
936 //
937 // We have:
938 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
939 // Invalid if rs == 0
940 // BGTZC if rs == 0 && rt != 0
941 // BLTZC if rs == rt && rt != 0
942 // BLTC if rs != rt && rs != 0 && rt != 0
943
944 bool HasRs = false;
945
946 InsnType Rs = fieldFromInstruction(insn, 21, 5);
947 InsnType Rt = fieldFromInstruction(insn, 16, 5);
948 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
949
950 if (Rt == 0)
951 return MCDisassembler::Fail;
952 else if (Rs == 0)
953 MI.setOpcode(Mips::BGTZC);
954 else if (Rs == Rt)
955 MI.setOpcode(Mips::BLTZC);
956 else {
957 MI.setOpcode(Mips::BLTC);
958 HasRs = true;
959 }
960
961 if (HasRs)
962 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
963 Rs)));
964
965 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
966 Rt)));
967
968 MI.addOperand(MCOperand::createImm(Imm));
969
970 return MCDisassembler::Success;
971 }
972
973 template <typename InsnType>
DecodeBgtzGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)974 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
975 uint64_t Address,
976 const void *Decoder) {
977 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
978 // (otherwise we would have matched the BGTZ instruction from the earlier
979 // ISA's instead).
980 //
981 // We have:
982 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
983 // BGTZ if rt == 0
984 // BGTZALC if rs == 0 && rt != 0
985 // BLTZALC if rs != 0 && rs == rt
986 // BLTUC if rs != 0 && rs != rt
987
988 InsnType Rs = fieldFromInstruction(insn, 21, 5);
989 InsnType Rt = fieldFromInstruction(insn, 16, 5);
990 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
991 bool HasRs = false;
992 bool HasRt = false;
993
994 if (Rt == 0) {
995 MI.setOpcode(Mips::BGTZ);
996 HasRs = true;
997 } else if (Rs == 0) {
998 MI.setOpcode(Mips::BGTZALC);
999 HasRt = true;
1000 } else if (Rs == Rt) {
1001 MI.setOpcode(Mips::BLTZALC);
1002 HasRs = true;
1003 } else {
1004 MI.setOpcode(Mips::BLTUC);
1005 HasRs = true;
1006 HasRt = true;
1007 }
1008
1009 if (HasRs)
1010 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1011 Rs)));
1012
1013 if (HasRt)
1014 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1015 Rt)));
1016
1017 MI.addOperand(MCOperand::createImm(Imm));
1018
1019 return MCDisassembler::Success;
1020 }
1021
1022 template <typename InsnType>
DecodeBlezGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)1023 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
1024 uint64_t Address,
1025 const void *Decoder) {
1026 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
1027 // (otherwise we would have matched the BLEZL instruction from the earlier
1028 // ISA's instead).
1029 //
1030 // We have:
1031 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
1032 // Invalid if rs == 0
1033 // BLEZALC if rs == 0 && rt != 0
1034 // BGEZALC if rs == rt && rt != 0
1035 // BGEUC if rs != rt && rs != 0 && rt != 0
1036
1037 InsnType Rs = fieldFromInstruction(insn, 21, 5);
1038 InsnType Rt = fieldFromInstruction(insn, 16, 5);
1039 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1040 bool HasRs = false;
1041
1042 if (Rt == 0)
1043 return MCDisassembler::Fail;
1044 else if (Rs == 0)
1045 MI.setOpcode(Mips::BLEZALC);
1046 else if (Rs == Rt)
1047 MI.setOpcode(Mips::BGEZALC);
1048 else {
1049 HasRs = true;
1050 MI.setOpcode(Mips::BGEUC);
1051 }
1052
1053 if (HasRs)
1054 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1055 Rs)));
1056 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1057 Rt)));
1058
1059 MI.addOperand(MCOperand::createImm(Imm));
1060
1061 return MCDisassembler::Success;
1062 }
1063
1064 // Override the generated disassembler to produce DEXT all the time. This is
1065 // for feature / behaviour parity with binutils.
1066 template <typename InsnType>
DecodeDEXT(MCInst & MI,InsnType Insn,uint64_t Address,const void * Decoder)1067 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1068 const void *Decoder) {
1069 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1070 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1071 unsigned Size = 0;
1072 unsigned Pos = 0;
1073
1074 switch (MI.getOpcode()) {
1075 case Mips::DEXT:
1076 Pos = Lsb;
1077 Size = Msbd + 1;
1078 break;
1079 case Mips::DEXTM:
1080 Pos = Lsb;
1081 Size = Msbd + 1 + 32;
1082 break;
1083 case Mips::DEXTU:
1084 Pos = Lsb + 32;
1085 Size = Msbd + 1;
1086 break;
1087 default:
1088 llvm_unreachable("Unknown DEXT instruction!");
1089 }
1090
1091 MI.setOpcode(Mips::DEXT);
1092
1093 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1094 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1095
1096 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1097 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1098 MI.addOperand(MCOperand::createImm(Pos));
1099 MI.addOperand(MCOperand::createImm(Size));
1100
1101 return MCDisassembler::Success;
1102 }
1103
1104 // Override the generated disassembler to produce DINS all the time. This is
1105 // for feature / behaviour parity with binutils.
1106 template <typename InsnType>
DecodeDINS(MCInst & MI,InsnType Insn,uint64_t Address,const void * Decoder)1107 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1108 const void *Decoder) {
1109 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1110 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1111 unsigned Size = 0;
1112 unsigned Pos = 0;
1113
1114 switch (MI.getOpcode()) {
1115 case Mips::DINS:
1116 Pos = Lsb;
1117 Size = Msbd + 1 - Pos;
1118 break;
1119 case Mips::DINSM:
1120 Pos = Lsb;
1121 Size = Msbd + 33 - Pos;
1122 break;
1123 case Mips::DINSU:
1124 Pos = Lsb + 32;
1125 // mbsd = pos + size - 33
1126 // mbsd - pos + 33 = size
1127 Size = Msbd + 33 - Pos;
1128 break;
1129 default:
1130 llvm_unreachable("Unknown DINS instruction!");
1131 }
1132
1133 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1134 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1135
1136 MI.setOpcode(Mips::DINS);
1137 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1138 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1139 MI.addOperand(MCOperand::createImm(Pos));
1140 MI.addOperand(MCOperand::createImm(Size));
1141
1142 return MCDisassembler::Success;
1143 }
1144
1145 // Auto-generated decoder wouldn't add the third operand for CRC32*.
1146 template <typename InsnType>
DecodeCRC(MCInst & MI,InsnType Insn,uint64_t Address,const void * Decoder)1147 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1148 const void *Decoder) {
1149 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1150 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1151 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1152 Rt)));
1153 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1154 Rs)));
1155 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1156 Rt)));
1157 return MCDisassembler::Success;
1158 }
1159
1160 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1161 /// according to the given endianness.
readInstruction16(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn,bool IsBigEndian)1162 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1163 uint64_t &Size, uint32_t &Insn,
1164 bool IsBigEndian) {
1165 // We want to read exactly 2 Bytes of data.
1166 if (Bytes.size() < 2) {
1167 Size = 0;
1168 return MCDisassembler::Fail;
1169 }
1170
1171 if (IsBigEndian) {
1172 Insn = (Bytes[0] << 8) | Bytes[1];
1173 } else {
1174 Insn = (Bytes[1] << 8) | Bytes[0];
1175 }
1176
1177 return MCDisassembler::Success;
1178 }
1179
1180 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1181 /// according to the given endianness.
readInstruction32(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn,bool IsBigEndian,bool IsMicroMips)1182 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1183 uint64_t &Size, uint32_t &Insn,
1184 bool IsBigEndian, bool IsMicroMips) {
1185 // We want to read exactly 4 Bytes of data.
1186 if (Bytes.size() < 4) {
1187 Size = 0;
1188 return MCDisassembler::Fail;
1189 }
1190
1191 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1192 // always precede the low 16 bits in the instruction stream (that is, they
1193 // are placed at lower addresses in the instruction stream).
1194 //
1195 // microMIPS byte ordering:
1196 // Big-endian: 0 | 1 | 2 | 3
1197 // Little-endian: 1 | 0 | 3 | 2
1198
1199 if (IsBigEndian) {
1200 // Encoded as a big-endian 32-bit word in the stream.
1201 Insn =
1202 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1203 } else {
1204 if (IsMicroMips) {
1205 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1206 (Bytes[1] << 24);
1207 } else {
1208 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1209 (Bytes[3] << 24);
1210 }
1211 }
1212
1213 return MCDisassembler::Success;
1214 }
1215
getInstruction(MCInst & Instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & VStream,raw_ostream & CStream) const1216 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1217 ArrayRef<uint8_t> Bytes,
1218 uint64_t Address,
1219 raw_ostream &VStream,
1220 raw_ostream &CStream) const {
1221 uint32_t Insn;
1222 DecodeStatus Result;
1223 Size = 0;
1224
1225 if (IsMicroMips) {
1226 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1227 if (Result == MCDisassembler::Fail)
1228 return MCDisassembler::Fail;
1229
1230 if (hasMips32r6()) {
1231 LLVM_DEBUG(
1232 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1233 // Calling the auto-generated decoder function for microMIPS32R6
1234 // 16-bit instructions.
1235 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1236 Address, this, STI);
1237 if (Result != MCDisassembler::Fail) {
1238 Size = 2;
1239 return Result;
1240 }
1241 }
1242
1243 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1244 // Calling the auto-generated decoder function for microMIPS 16-bit
1245 // instructions.
1246 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1247 this, STI);
1248 if (Result != MCDisassembler::Fail) {
1249 Size = 2;
1250 return Result;
1251 }
1252
1253 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1254 if (Result == MCDisassembler::Fail)
1255 return MCDisassembler::Fail;
1256
1257 if (hasMips32r6()) {
1258 LLVM_DEBUG(
1259 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1260 // Calling the auto-generated decoder function.
1261 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
1262 this, STI);
1263 if (Result != MCDisassembler::Fail) {
1264 Size = 4;
1265 return Result;
1266 }
1267 }
1268
1269 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1270 // Calling the auto-generated decoder function.
1271 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1272 this, STI);
1273 if (Result != MCDisassembler::Fail) {
1274 Size = 4;
1275 return Result;
1276 }
1277
1278 if (isFP64()) {
1279 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1280 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1281 Address, this, STI);
1282 if (Result != MCDisassembler::Fail) {
1283 Size = 4;
1284 return Result;
1285 }
1286 }
1287
1288 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1289 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1290 // could form a valid instruction. The two bytes we rejected as an
1291 // instruction could have actually beeen an inline constant pool that is
1292 // unconditionally branched over.
1293 Size = 2;
1294 return MCDisassembler::Fail;
1295 }
1296
1297 // Attempt to read the instruction so that we can attempt to decode it. If
1298 // the buffer is not 4 bytes long, let the higher level logic figure out
1299 // what to do with a size of zero and MCDisassembler::Fail.
1300 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1301 if (Result == MCDisassembler::Fail)
1302 return MCDisassembler::Fail;
1303
1304 // The only instruction size for standard encoded MIPS.
1305 Size = 4;
1306
1307 if (hasCOP3()) {
1308 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1309 Result =
1310 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1311 if (Result != MCDisassembler::Fail)
1312 return Result;
1313 }
1314
1315 if (hasMips32r6() && isGP64()) {
1316 LLVM_DEBUG(
1317 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1318 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1319 Address, this, STI);
1320 if (Result != MCDisassembler::Fail)
1321 return Result;
1322 }
1323
1324 if (hasMips32r6() && isPTR64()) {
1325 LLVM_DEBUG(
1326 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1327 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1328 Address, this, STI);
1329 if (Result != MCDisassembler::Fail)
1330 return Result;
1331 }
1332
1333 if (hasMips32r6()) {
1334 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1335 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1336 Address, this, STI);
1337 if (Result != MCDisassembler::Fail)
1338 return Result;
1339 }
1340
1341 if (hasMips2() && isPTR64()) {
1342 LLVM_DEBUG(
1343 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1344 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1345 Address, this, STI);
1346 if (Result != MCDisassembler::Fail)
1347 return Result;
1348 }
1349
1350 if (hasCnMips()) {
1351 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1352 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1353 Address, this, STI);
1354 if (Result != MCDisassembler::Fail)
1355 return Result;
1356 }
1357
1358 if (isGP64()) {
1359 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1360 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1361 Address, this, STI);
1362 if (Result != MCDisassembler::Fail)
1363 return Result;
1364 }
1365
1366 if (isFP64()) {
1367 LLVM_DEBUG(
1368 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1369 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
1370 Address, this, STI);
1371 if (Result != MCDisassembler::Fail)
1372 return Result;
1373 }
1374
1375 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1376 // Calling the auto-generated decoder function.
1377 Result =
1378 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1379 if (Result != MCDisassembler::Fail)
1380 return Result;
1381
1382 return MCDisassembler::Fail;
1383 }
1384
DecodeCPU16RegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1385 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
1386 unsigned RegNo,
1387 uint64_t Address,
1388 const void *Decoder) {
1389 return MCDisassembler::Fail;
1390 }
1391
DecodeGPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1392 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
1393 unsigned RegNo,
1394 uint64_t Address,
1395 const void *Decoder) {
1396 if (RegNo > 31)
1397 return MCDisassembler::Fail;
1398
1399 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1400 Inst.addOperand(MCOperand::createReg(Reg));
1401 return MCDisassembler::Success;
1402 }
1403
DecodeGPRMM16RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1404 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1405 unsigned RegNo,
1406 uint64_t Address,
1407 const void *Decoder) {
1408 if (RegNo > 7)
1409 return MCDisassembler::Fail;
1410 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1411 Inst.addOperand(MCOperand::createReg(Reg));
1412 return MCDisassembler::Success;
1413 }
1414
DecodeGPRMM16ZeroRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1415 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1416 unsigned RegNo,
1417 uint64_t Address,
1418 const void *Decoder) {
1419 if (RegNo > 7)
1420 return MCDisassembler::Fail;
1421 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1422 Inst.addOperand(MCOperand::createReg(Reg));
1423 return MCDisassembler::Success;
1424 }
1425
DecodeGPRMM16MovePRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1426 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1427 unsigned RegNo,
1428 uint64_t Address,
1429 const void *Decoder) {
1430 if (RegNo > 7)
1431 return MCDisassembler::Fail;
1432 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1433 Inst.addOperand(MCOperand::createReg(Reg));
1434 return MCDisassembler::Success;
1435 }
1436
DecodeGPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1437 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1438 unsigned RegNo,
1439 uint64_t Address,
1440 const void *Decoder) {
1441 if (RegNo > 31)
1442 return MCDisassembler::Fail;
1443 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1444 Inst.addOperand(MCOperand::createReg(Reg));
1445 return MCDisassembler::Success;
1446 }
1447
DecodePtrRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1448 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1449 unsigned RegNo,
1450 uint64_t Address,
1451 const void *Decoder) {
1452 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1453 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1454
1455 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1456 }
1457
DecodeDSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1458 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1459 unsigned RegNo,
1460 uint64_t Address,
1461 const void *Decoder) {
1462 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1463 }
1464
DecodeFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1465 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1466 unsigned RegNo,
1467 uint64_t Address,
1468 const void *Decoder) {
1469 if (RegNo > 31)
1470 return MCDisassembler::Fail;
1471
1472 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1473 Inst.addOperand(MCOperand::createReg(Reg));
1474 return MCDisassembler::Success;
1475 }
1476
DecodeFGR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1477 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1478 unsigned RegNo,
1479 uint64_t Address,
1480 const void *Decoder) {
1481 if (RegNo > 31)
1482 return MCDisassembler::Fail;
1483
1484 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1485 Inst.addOperand(MCOperand::createReg(Reg));
1486 return MCDisassembler::Success;
1487 }
1488
DecodeCCRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1489 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1490 unsigned RegNo,
1491 uint64_t Address,
1492 const void *Decoder) {
1493 if (RegNo > 31)
1494 return MCDisassembler::Fail;
1495 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1496 Inst.addOperand(MCOperand::createReg(Reg));
1497 return MCDisassembler::Success;
1498 }
1499
DecodeFCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1500 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1501 unsigned RegNo,
1502 uint64_t Address,
1503 const void *Decoder) {
1504 if (RegNo > 7)
1505 return MCDisassembler::Fail;
1506 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1507 Inst.addOperand(MCOperand::createReg(Reg));
1508 return MCDisassembler::Success;
1509 }
1510
DecodeFGRCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1511 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1512 uint64_t Address,
1513 const void *Decoder) {
1514 if (RegNo > 31)
1515 return MCDisassembler::Fail;
1516
1517 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1518 Inst.addOperand(MCOperand::createReg(Reg));
1519 return MCDisassembler::Success;
1520 }
1521
DecodeMem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1522 static DecodeStatus DecodeMem(MCInst &Inst,
1523 unsigned Insn,
1524 uint64_t Address,
1525 const void *Decoder) {
1526 int Offset = SignExtend32<16>(Insn & 0xffff);
1527 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1528 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1529
1530 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1531 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1532
1533 if (Inst.getOpcode() == Mips::SC ||
1534 Inst.getOpcode() == Mips::SCD)
1535 Inst.addOperand(MCOperand::createReg(Reg));
1536
1537 Inst.addOperand(MCOperand::createReg(Reg));
1538 Inst.addOperand(MCOperand::createReg(Base));
1539 Inst.addOperand(MCOperand::createImm(Offset));
1540
1541 return MCDisassembler::Success;
1542 }
1543
DecodeMemEVA(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1544 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1545 unsigned Insn,
1546 uint64_t Address,
1547 const void *Decoder) {
1548 int Offset = SignExtend32<9>(Insn >> 7);
1549 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1550 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1551
1552 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1553 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1554
1555 if (Inst.getOpcode() == Mips::SCE)
1556 Inst.addOperand(MCOperand::createReg(Reg));
1557
1558 Inst.addOperand(MCOperand::createReg(Reg));
1559 Inst.addOperand(MCOperand::createReg(Base));
1560 Inst.addOperand(MCOperand::createImm(Offset));
1561
1562 return MCDisassembler::Success;
1563 }
1564
DecodeLoadByte15(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1565 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1566 unsigned Insn,
1567 uint64_t Address,
1568 const void *Decoder) {
1569 int Offset = SignExtend32<16>(Insn & 0xffff);
1570 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1571 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1572
1573 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1574 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1575
1576 Inst.addOperand(MCOperand::createReg(Reg));
1577 Inst.addOperand(MCOperand::createReg(Base));
1578 Inst.addOperand(MCOperand::createImm(Offset));
1579
1580 return MCDisassembler::Success;
1581 }
1582
DecodeCacheOp(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1583 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1584 unsigned Insn,
1585 uint64_t Address,
1586 const void *Decoder) {
1587 int Offset = SignExtend32<16>(Insn & 0xffff);
1588 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1589 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1590
1591 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1592
1593 Inst.addOperand(MCOperand::createReg(Base));
1594 Inst.addOperand(MCOperand::createImm(Offset));
1595 Inst.addOperand(MCOperand::createImm(Hint));
1596
1597 return MCDisassembler::Success;
1598 }
1599
DecodeCacheOpMM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1600 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1601 unsigned Insn,
1602 uint64_t Address,
1603 const void *Decoder) {
1604 int Offset = SignExtend32<12>(Insn & 0xfff);
1605 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1606 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1607
1608 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1609
1610 Inst.addOperand(MCOperand::createReg(Base));
1611 Inst.addOperand(MCOperand::createImm(Offset));
1612 Inst.addOperand(MCOperand::createImm(Hint));
1613
1614 return MCDisassembler::Success;
1615 }
1616
DecodePrefeOpMM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1617 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1618 unsigned Insn,
1619 uint64_t Address,
1620 const void *Decoder) {
1621 int Offset = SignExtend32<9>(Insn & 0x1ff);
1622 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1623 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1624
1625 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1626
1627 Inst.addOperand(MCOperand::createReg(Base));
1628 Inst.addOperand(MCOperand::createImm(Offset));
1629 Inst.addOperand(MCOperand::createImm(Hint));
1630
1631 return MCDisassembler::Success;
1632 }
1633
DecodeCacheeOp_CacheOpR6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1634 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1635 unsigned Insn,
1636 uint64_t Address,
1637 const void *Decoder) {
1638 int Offset = SignExtend32<9>(Insn >> 7);
1639 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1640 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1641
1642 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1643
1644 Inst.addOperand(MCOperand::createReg(Base));
1645 Inst.addOperand(MCOperand::createImm(Offset));
1646 Inst.addOperand(MCOperand::createImm(Hint));
1647
1648 return MCDisassembler::Success;
1649 }
1650
DecodeSyncI(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1651 static DecodeStatus DecodeSyncI(MCInst &Inst,
1652 unsigned Insn,
1653 uint64_t Address,
1654 const void *Decoder) {
1655 int Offset = SignExtend32<16>(Insn & 0xffff);
1656 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1657
1658 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1659
1660 Inst.addOperand(MCOperand::createReg(Base));
1661 Inst.addOperand(MCOperand::createImm(Offset));
1662
1663 return MCDisassembler::Success;
1664 }
1665
DecodeSyncI_MM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1666 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1667 uint64_t Address, const void *Decoder) {
1668 int Offset = SignExtend32<16>(Insn & 0xffff);
1669 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1670
1671 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1672
1673 Inst.addOperand(MCOperand::createReg(Base));
1674 Inst.addOperand(MCOperand::createImm(Offset));
1675
1676 return MCDisassembler::Success;
1677 }
1678
DecodeSynciR6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1679 static DecodeStatus DecodeSynciR6(MCInst &Inst,
1680 unsigned Insn,
1681 uint64_t Address,
1682 const void *Decoder) {
1683 int Immediate = SignExtend32<16>(Insn & 0xffff);
1684 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1685
1686 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1687
1688 Inst.addOperand(MCOperand::createReg(Base));
1689 Inst.addOperand(MCOperand::createImm(Immediate));
1690
1691 return MCDisassembler::Success;
1692 }
1693
DecodeMSA128Mem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1694 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1695 uint64_t Address, const void *Decoder) {
1696 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1697 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1698 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1699
1700 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1701 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1702
1703 Inst.addOperand(MCOperand::createReg(Reg));
1704 Inst.addOperand(MCOperand::createReg(Base));
1705
1706 // The immediate field of an LD/ST instruction is scaled which means it must
1707 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1708 // data format.
1709 // .b - 1 byte
1710 // .h - 2 bytes
1711 // .w - 4 bytes
1712 // .d - 8 bytes
1713 switch(Inst.getOpcode())
1714 {
1715 default:
1716 assert(false && "Unexpected instruction");
1717 return MCDisassembler::Fail;
1718 break;
1719 case Mips::LD_B:
1720 case Mips::ST_B:
1721 Inst.addOperand(MCOperand::createImm(Offset));
1722 break;
1723 case Mips::LD_H:
1724 case Mips::ST_H:
1725 Inst.addOperand(MCOperand::createImm(Offset * 2));
1726 break;
1727 case Mips::LD_W:
1728 case Mips::ST_W:
1729 Inst.addOperand(MCOperand::createImm(Offset * 4));
1730 break;
1731 case Mips::LD_D:
1732 case Mips::ST_D:
1733 Inst.addOperand(MCOperand::createImm(Offset * 8));
1734 break;
1735 }
1736
1737 return MCDisassembler::Success;
1738 }
1739
DecodeMemMMImm4(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1740 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1741 unsigned Insn,
1742 uint64_t Address,
1743 const void *Decoder) {
1744 unsigned Offset = Insn & 0xf;
1745 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1746 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1747
1748 switch (Inst.getOpcode()) {
1749 case Mips::LBU16_MM:
1750 case Mips::LHU16_MM:
1751 case Mips::LW16_MM:
1752 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1753 == MCDisassembler::Fail)
1754 return MCDisassembler::Fail;
1755 break;
1756 case Mips::SB16_MM:
1757 case Mips::SB16_MMR6:
1758 case Mips::SH16_MM:
1759 case Mips::SH16_MMR6:
1760 case Mips::SW16_MM:
1761 case Mips::SW16_MMR6:
1762 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1763 == MCDisassembler::Fail)
1764 return MCDisassembler::Fail;
1765 break;
1766 }
1767
1768 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1769 == MCDisassembler::Fail)
1770 return MCDisassembler::Fail;
1771
1772 switch (Inst.getOpcode()) {
1773 case Mips::LBU16_MM:
1774 if (Offset == 0xf)
1775 Inst.addOperand(MCOperand::createImm(-1));
1776 else
1777 Inst.addOperand(MCOperand::createImm(Offset));
1778 break;
1779 case Mips::SB16_MM:
1780 case Mips::SB16_MMR6:
1781 Inst.addOperand(MCOperand::createImm(Offset));
1782 break;
1783 case Mips::LHU16_MM:
1784 case Mips::SH16_MM:
1785 case Mips::SH16_MMR6:
1786 Inst.addOperand(MCOperand::createImm(Offset << 1));
1787 break;
1788 case Mips::LW16_MM:
1789 case Mips::SW16_MM:
1790 case Mips::SW16_MMR6:
1791 Inst.addOperand(MCOperand::createImm(Offset << 2));
1792 break;
1793 }
1794
1795 return MCDisassembler::Success;
1796 }
1797
DecodeMemMMSPImm5Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1798 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1799 unsigned Insn,
1800 uint64_t Address,
1801 const void *Decoder) {
1802 unsigned Offset = Insn & 0x1F;
1803 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1804
1805 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1806
1807 Inst.addOperand(MCOperand::createReg(Reg));
1808 Inst.addOperand(MCOperand::createReg(Mips::SP));
1809 Inst.addOperand(MCOperand::createImm(Offset << 2));
1810
1811 return MCDisassembler::Success;
1812 }
1813
DecodeMemMMGPImm7Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1814 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1815 unsigned Insn,
1816 uint64_t Address,
1817 const void *Decoder) {
1818 unsigned Offset = Insn & 0x7F;
1819 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1820
1821 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1822
1823 Inst.addOperand(MCOperand::createReg(Reg));
1824 Inst.addOperand(MCOperand::createReg(Mips::GP));
1825 Inst.addOperand(MCOperand::createImm(Offset << 2));
1826
1827 return MCDisassembler::Success;
1828 }
1829
DecodeMemMMReglistImm4Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1830 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1831 unsigned Insn,
1832 uint64_t Address,
1833 const void *Decoder) {
1834 int Offset;
1835 switch (Inst.getOpcode()) {
1836 case Mips::LWM16_MMR6:
1837 case Mips::SWM16_MMR6:
1838 Offset = fieldFromInstruction(Insn, 4, 4);
1839 break;
1840 default:
1841 Offset = SignExtend32<4>(Insn & 0xf);
1842 break;
1843 }
1844
1845 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1846 == MCDisassembler::Fail)
1847 return MCDisassembler::Fail;
1848
1849 Inst.addOperand(MCOperand::createReg(Mips::SP));
1850 Inst.addOperand(MCOperand::createImm(Offset << 2));
1851
1852 return MCDisassembler::Success;
1853 }
1854
DecodeMemMMImm9(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1855 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1856 unsigned Insn,
1857 uint64_t Address,
1858 const void *Decoder) {
1859 int Offset = SignExtend32<9>(Insn & 0x1ff);
1860 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1861 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1862
1863 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1864 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1865
1866 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1867 Inst.addOperand(MCOperand::createReg(Reg));
1868
1869 Inst.addOperand(MCOperand::createReg(Reg));
1870 Inst.addOperand(MCOperand::createReg(Base));
1871 Inst.addOperand(MCOperand::createImm(Offset));
1872
1873 return MCDisassembler::Success;
1874 }
1875
DecodeMemMMImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1876 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1877 unsigned Insn,
1878 uint64_t Address,
1879 const void *Decoder) {
1880 int Offset = SignExtend32<12>(Insn & 0x0fff);
1881 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1882 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1883
1884 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1885 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1886
1887 switch (Inst.getOpcode()) {
1888 case Mips::SWM32_MM:
1889 case Mips::LWM32_MM:
1890 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1891 == MCDisassembler::Fail)
1892 return MCDisassembler::Fail;
1893 Inst.addOperand(MCOperand::createReg(Base));
1894 Inst.addOperand(MCOperand::createImm(Offset));
1895 break;
1896 case Mips::SC_MM:
1897 Inst.addOperand(MCOperand::createReg(Reg));
1898 LLVM_FALLTHROUGH;
1899 default:
1900 Inst.addOperand(MCOperand::createReg(Reg));
1901 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1902 Inst.addOperand(MCOperand::createReg(Reg+1));
1903
1904 Inst.addOperand(MCOperand::createReg(Base));
1905 Inst.addOperand(MCOperand::createImm(Offset));
1906 }
1907
1908 return MCDisassembler::Success;
1909 }
1910
DecodeMemMMImm16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1911 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1912 unsigned Insn,
1913 uint64_t Address,
1914 const void *Decoder) {
1915 int Offset = SignExtend32<16>(Insn & 0xffff);
1916 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1917 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1918
1919 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1920 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1921
1922 Inst.addOperand(MCOperand::createReg(Reg));
1923 Inst.addOperand(MCOperand::createReg(Base));
1924 Inst.addOperand(MCOperand::createImm(Offset));
1925
1926 return MCDisassembler::Success;
1927 }
1928
DecodeFMem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1929 static DecodeStatus DecodeFMem(MCInst &Inst,
1930 unsigned Insn,
1931 uint64_t Address,
1932 const void *Decoder) {
1933 int Offset = SignExtend32<16>(Insn & 0xffff);
1934 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1935 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1936
1937 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1938 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1939
1940 Inst.addOperand(MCOperand::createReg(Reg));
1941 Inst.addOperand(MCOperand::createReg(Base));
1942 Inst.addOperand(MCOperand::createImm(Offset));
1943
1944 return MCDisassembler::Success;
1945 }
1946
DecodeFMemMMR2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1947 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1948 uint64_t Address, const void *Decoder) {
1949 // This function is the same as DecodeFMem but with the Reg and Base fields
1950 // swapped according to microMIPS spec.
1951 int Offset = SignExtend32<16>(Insn & 0xffff);
1952 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1953 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1954
1955 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1956 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1957
1958 Inst.addOperand(MCOperand::createReg(Reg));
1959 Inst.addOperand(MCOperand::createReg(Base));
1960 Inst.addOperand(MCOperand::createImm(Offset));
1961
1962 return MCDisassembler::Success;
1963 }
1964
DecodeFMem2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1965 static DecodeStatus DecodeFMem2(MCInst &Inst,
1966 unsigned Insn,
1967 uint64_t Address,
1968 const void *Decoder) {
1969 int Offset = SignExtend32<16>(Insn & 0xffff);
1970 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1971 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1972
1973 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1974 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1975
1976 Inst.addOperand(MCOperand::createReg(Reg));
1977 Inst.addOperand(MCOperand::createReg(Base));
1978 Inst.addOperand(MCOperand::createImm(Offset));
1979
1980 return MCDisassembler::Success;
1981 }
1982
DecodeFMem3(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1983 static DecodeStatus DecodeFMem3(MCInst &Inst,
1984 unsigned Insn,
1985 uint64_t Address,
1986 const void *Decoder) {
1987 int Offset = SignExtend32<16>(Insn & 0xffff);
1988 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1989 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1990
1991 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1992 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1993
1994 Inst.addOperand(MCOperand::createReg(Reg));
1995 Inst.addOperand(MCOperand::createReg(Base));
1996 Inst.addOperand(MCOperand::createImm(Offset));
1997
1998 return MCDisassembler::Success;
1999 }
2000
DecodeFMemCop2R6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2001 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
2002 unsigned Insn,
2003 uint64_t Address,
2004 const void *Decoder) {
2005 int Offset = SignExtend32<11>(Insn & 0x07ff);
2006 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
2007 unsigned Base = fieldFromInstruction(Insn, 11, 5);
2008
2009 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2010 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2011
2012 Inst.addOperand(MCOperand::createReg(Reg));
2013 Inst.addOperand(MCOperand::createReg(Base));
2014 Inst.addOperand(MCOperand::createImm(Offset));
2015
2016 return MCDisassembler::Success;
2017 }
2018
DecodeFMemCop2MMR6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2019 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
2020 uint64_t Address, const void *Decoder) {
2021 int Offset = SignExtend32<11>(Insn & 0x07ff);
2022 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
2023 unsigned Base = fieldFromInstruction(Insn, 16, 5);
2024
2025 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2026 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2027
2028 Inst.addOperand(MCOperand::createReg(Reg));
2029 Inst.addOperand(MCOperand::createReg(Base));
2030 Inst.addOperand(MCOperand::createImm(Offset));
2031
2032 return MCDisassembler::Success;
2033 }
2034
DecodeSpecial3LlSc(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2035 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
2036 unsigned Insn,
2037 uint64_t Address,
2038 const void *Decoder) {
2039 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
2040 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
2041 unsigned Base = fieldFromInstruction(Insn, 21, 5);
2042
2043 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
2044 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2045
2046 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2047 Inst.addOperand(MCOperand::createReg(Rt));
2048 }
2049
2050 Inst.addOperand(MCOperand::createReg(Rt));
2051 Inst.addOperand(MCOperand::createReg(Base));
2052 Inst.addOperand(MCOperand::createImm(Offset));
2053
2054 return MCDisassembler::Success;
2055 }
2056
DecodeHWRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2057 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
2058 unsigned RegNo,
2059 uint64_t Address,
2060 const void *Decoder) {
2061 // Currently only hardware register 29 is supported.
2062 if (RegNo != 29)
2063 return MCDisassembler::Fail;
2064 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
2065 return MCDisassembler::Success;
2066 }
2067
DecodeAFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2068 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
2069 unsigned RegNo,
2070 uint64_t Address,
2071 const void *Decoder) {
2072 if (RegNo > 30 || RegNo %2)
2073 return MCDisassembler::Fail;
2074
2075 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
2076 Inst.addOperand(MCOperand::createReg(Reg));
2077 return MCDisassembler::Success;
2078 }
2079
DecodeACC64DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2080 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
2081 unsigned RegNo,
2082 uint64_t Address,
2083 const void *Decoder) {
2084 if (RegNo >= 4)
2085 return MCDisassembler::Fail;
2086
2087 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2088 Inst.addOperand(MCOperand::createReg(Reg));
2089 return MCDisassembler::Success;
2090 }
2091
DecodeHI32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2092 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
2093 unsigned RegNo,
2094 uint64_t Address,
2095 const void *Decoder) {
2096 if (RegNo >= 4)
2097 return MCDisassembler::Fail;
2098
2099 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2100 Inst.addOperand(MCOperand::createReg(Reg));
2101 return MCDisassembler::Success;
2102 }
2103
DecodeLO32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2104 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
2105 unsigned RegNo,
2106 uint64_t Address,
2107 const void *Decoder) {
2108 if (RegNo >= 4)
2109 return MCDisassembler::Fail;
2110
2111 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2112 Inst.addOperand(MCOperand::createReg(Reg));
2113 return MCDisassembler::Success;
2114 }
2115
DecodeMSA128BRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2116 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
2117 unsigned RegNo,
2118 uint64_t Address,
2119 const void *Decoder) {
2120 if (RegNo > 31)
2121 return MCDisassembler::Fail;
2122
2123 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2124 Inst.addOperand(MCOperand::createReg(Reg));
2125 return MCDisassembler::Success;
2126 }
2127
DecodeMSA128HRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2128 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
2129 unsigned RegNo,
2130 uint64_t Address,
2131 const void *Decoder) {
2132 if (RegNo > 31)
2133 return MCDisassembler::Fail;
2134
2135 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2136 Inst.addOperand(MCOperand::createReg(Reg));
2137 return MCDisassembler::Success;
2138 }
2139
DecodeMSA128WRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2140 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
2141 unsigned RegNo,
2142 uint64_t Address,
2143 const void *Decoder) {
2144 if (RegNo > 31)
2145 return MCDisassembler::Fail;
2146
2147 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2148 Inst.addOperand(MCOperand::createReg(Reg));
2149 return MCDisassembler::Success;
2150 }
2151
DecodeMSA128DRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2152 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
2153 unsigned RegNo,
2154 uint64_t Address,
2155 const void *Decoder) {
2156 if (RegNo > 31)
2157 return MCDisassembler::Fail;
2158
2159 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2160 Inst.addOperand(MCOperand::createReg(Reg));
2161 return MCDisassembler::Success;
2162 }
2163
DecodeMSACtrlRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2164 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
2165 unsigned RegNo,
2166 uint64_t Address,
2167 const void *Decoder) {
2168 if (RegNo > 7)
2169 return MCDisassembler::Fail;
2170
2171 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2172 Inst.addOperand(MCOperand::createReg(Reg));
2173 return MCDisassembler::Success;
2174 }
2175
DecodeCOP0RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2176 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
2177 unsigned RegNo,
2178 uint64_t Address,
2179 const void *Decoder) {
2180 if (RegNo > 31)
2181 return MCDisassembler::Fail;
2182
2183 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2184 Inst.addOperand(MCOperand::createReg(Reg));
2185 return MCDisassembler::Success;
2186 }
2187
DecodeCOP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)2188 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
2189 unsigned RegNo,
2190 uint64_t Address,
2191 const void *Decoder) {
2192 if (RegNo > 31)
2193 return MCDisassembler::Fail;
2194
2195 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2196 Inst.addOperand(MCOperand::createReg(Reg));
2197 return MCDisassembler::Success;
2198 }
2199
DecodeBranchTarget(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2200 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
2201 unsigned Offset,
2202 uint64_t Address,
2203 const void *Decoder) {
2204 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2205 Inst.addOperand(MCOperand::createImm(BranchOffset));
2206 return MCDisassembler::Success;
2207 }
2208
DecodeBranchTarget1SImm16(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2209 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
2210 unsigned Offset,
2211 uint64_t Address,
2212 const void *Decoder) {
2213 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2214 Inst.addOperand(MCOperand::createImm(BranchOffset));
2215 return MCDisassembler::Success;
2216 }
2217
DecodeJumpTarget(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2218 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
2219 unsigned Insn,
2220 uint64_t Address,
2221 const void *Decoder) {
2222 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2223 Inst.addOperand(MCOperand::createImm(JumpOffset));
2224 return MCDisassembler::Success;
2225 }
2226
DecodeBranchTarget21(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2227 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
2228 unsigned Offset,
2229 uint64_t Address,
2230 const void *Decoder) {
2231 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2232
2233 Inst.addOperand(MCOperand::createImm(BranchOffset));
2234 return MCDisassembler::Success;
2235 }
2236
DecodeBranchTarget21MM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2237 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
2238 unsigned Offset,
2239 uint64_t Address,
2240 const void *Decoder) {
2241 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2242
2243 Inst.addOperand(MCOperand::createImm(BranchOffset));
2244 return MCDisassembler::Success;
2245 }
2246
DecodeBranchTarget26(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2247 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
2248 unsigned Offset,
2249 uint64_t Address,
2250 const void *Decoder) {
2251 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2252
2253 Inst.addOperand(MCOperand::createImm(BranchOffset));
2254 return MCDisassembler::Success;
2255 }
2256
DecodeBranchTarget7MM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2257 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
2258 unsigned Offset,
2259 uint64_t Address,
2260 const void *Decoder) {
2261 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2262 Inst.addOperand(MCOperand::createImm(BranchOffset));
2263 return MCDisassembler::Success;
2264 }
2265
DecodeBranchTarget10MM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2266 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
2267 unsigned Offset,
2268 uint64_t Address,
2269 const void *Decoder) {
2270 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2271 Inst.addOperand(MCOperand::createImm(BranchOffset));
2272 return MCDisassembler::Success;
2273 }
2274
DecodeBranchTargetMM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2275 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
2276 unsigned Offset,
2277 uint64_t Address,
2278 const void *Decoder) {
2279 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2280 Inst.addOperand(MCOperand::createImm(BranchOffset));
2281 return MCDisassembler::Success;
2282 }
2283
DecodeBranchTarget26MM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)2284 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
2285 unsigned Offset,
2286 uint64_t Address,
2287 const void *Decoder) {
2288 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2289
2290 Inst.addOperand(MCOperand::createImm(BranchOffset));
2291 return MCDisassembler::Success;
2292 }
2293
DecodeJumpTargetMM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2294 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
2295 unsigned Insn,
2296 uint64_t Address,
2297 const void *Decoder) {
2298 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2299 Inst.addOperand(MCOperand::createImm(JumpOffset));
2300 return MCDisassembler::Success;
2301 }
2302
DecodeAddiur2Simm7(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)2303 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
2304 unsigned Value,
2305 uint64_t Address,
2306 const void *Decoder) {
2307 if (Value == 0)
2308 Inst.addOperand(MCOperand::createImm(1));
2309 else if (Value == 0x7)
2310 Inst.addOperand(MCOperand::createImm(-1));
2311 else
2312 Inst.addOperand(MCOperand::createImm(Value << 2));
2313 return MCDisassembler::Success;
2314 }
2315
DecodeLi16Imm(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)2316 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
2317 unsigned Value,
2318 uint64_t Address,
2319 const void *Decoder) {
2320 if (Value == 0x7F)
2321 Inst.addOperand(MCOperand::createImm(-1));
2322 else
2323 Inst.addOperand(MCOperand::createImm(Value));
2324 return MCDisassembler::Success;
2325 }
2326
DecodePOOL16BEncodedField(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)2327 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
2328 unsigned Value,
2329 uint64_t Address,
2330 const void *Decoder) {
2331 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2332 return MCDisassembler::Success;
2333 }
2334
2335 template <unsigned Bits, int Offset, int Scale>
DecodeUImmWithOffsetAndScale(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)2336 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2337 uint64_t Address,
2338 const void *Decoder) {
2339 Value &= ((1 << Bits) - 1);
2340 Value *= Scale;
2341 Inst.addOperand(MCOperand::createImm(Value + Offset));
2342 return MCDisassembler::Success;
2343 }
2344
2345 template <unsigned Bits, int Offset, int ScaleBy>
DecodeSImmWithOffsetAndScale(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)2346 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2347 uint64_t Address,
2348 const void *Decoder) {
2349 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2350 Inst.addOperand(MCOperand::createImm(Imm + Offset));
2351 return MCDisassembler::Success;
2352 }
2353
DecodeInsSize(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2354 static DecodeStatus DecodeInsSize(MCInst &Inst,
2355 unsigned Insn,
2356 uint64_t Address,
2357 const void *Decoder) {
2358 // First we need to grab the pos(lsb) from MCInst.
2359 // This function only handles the 32 bit variants of ins, as dins
2360 // variants are handled differently.
2361 int Pos = Inst.getOperand(2).getImm();
2362 int Size = (int) Insn - Pos + 1;
2363 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2364 return MCDisassembler::Success;
2365 }
2366
DecodeSimm19Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2367 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2368 uint64_t Address, const void *Decoder) {
2369 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2370 return MCDisassembler::Success;
2371 }
2372
DecodeSimm18Lsl3(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2373 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2374 uint64_t Address, const void *Decoder) {
2375 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2376 return MCDisassembler::Success;
2377 }
2378
DecodeSimm9SP(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2379 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2380 uint64_t Address, const void *Decoder) {
2381 int32_t DecodedValue;
2382 switch (Insn) {
2383 case 0: DecodedValue = 256; break;
2384 case 1: DecodedValue = 257; break;
2385 case 510: DecodedValue = -258; break;
2386 case 511: DecodedValue = -257; break;
2387 default: DecodedValue = SignExtend32<9>(Insn); break;
2388 }
2389 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2390 return MCDisassembler::Success;
2391 }
2392
DecodeANDI16Imm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2393 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2394 uint64_t Address, const void *Decoder) {
2395 // Insn must be >= 0, since it is unsigned that condition is always true.
2396 assert(Insn < 16);
2397 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2398 255, 32768, 65535};
2399 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2400 return MCDisassembler::Success;
2401 }
2402
DecodeRegListOperand(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2403 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
2404 unsigned Insn,
2405 uint64_t Address,
2406 const void *Decoder) {
2407 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2408 Mips::S6, Mips::S7, Mips::FP};
2409 unsigned RegNum;
2410
2411 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2412
2413 // Empty register lists are not allowed.
2414 if (RegLst == 0)
2415 return MCDisassembler::Fail;
2416
2417 RegNum = RegLst & 0xf;
2418
2419 // RegLst values 10-15, and 26-31 are reserved.
2420 if (RegNum > 9)
2421 return MCDisassembler::Fail;
2422
2423 for (unsigned i = 0; i < RegNum; i++)
2424 Inst.addOperand(MCOperand::createReg(Regs[i]));
2425
2426 if (RegLst & 0x10)
2427 Inst.addOperand(MCOperand::createReg(Mips::RA));
2428
2429 return MCDisassembler::Success;
2430 }
2431
DecodeRegListOperand16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2432 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2433 uint64_t Address,
2434 const void *Decoder) {
2435 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2436 unsigned RegLst;
2437 switch(Inst.getOpcode()) {
2438 default:
2439 RegLst = fieldFromInstruction(Insn, 4, 2);
2440 break;
2441 case Mips::LWM16_MMR6:
2442 case Mips::SWM16_MMR6:
2443 RegLst = fieldFromInstruction(Insn, 8, 2);
2444 break;
2445 }
2446 unsigned RegNum = RegLst & 0x3;
2447
2448 for (unsigned i = 0; i <= RegNum; i++)
2449 Inst.addOperand(MCOperand::createReg(Regs[i]));
2450
2451 Inst.addOperand(MCOperand::createReg(Mips::RA));
2452
2453 return MCDisassembler::Success;
2454 }
2455
DecodeMovePOperands(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2456 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
2457 uint64_t Address,
2458 const void *Decoder) {
2459 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2460 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2461 MCDisassembler::Fail)
2462 return MCDisassembler::Fail;
2463
2464 unsigned RegRs;
2465 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
2466 RegRs = fieldFromInstruction(Insn, 0, 2) |
2467 (fieldFromInstruction(Insn, 3, 1) << 2);
2468 else
2469 RegRs = fieldFromInstruction(Insn, 1, 3);
2470 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2471 MCDisassembler::Fail)
2472 return MCDisassembler::Fail;
2473
2474 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
2475 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2476 MCDisassembler::Fail)
2477 return MCDisassembler::Fail;
2478
2479 return MCDisassembler::Success;
2480 }
2481
DecodeMovePRegPair(MCInst & Inst,unsigned RegPair,uint64_t Address,const void * Decoder)2482 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2483 uint64_t Address, const void *Decoder) {
2484 switch (RegPair) {
2485 default:
2486 return MCDisassembler::Fail;
2487 case 0:
2488 Inst.addOperand(MCOperand::createReg(Mips::A1));
2489 Inst.addOperand(MCOperand::createReg(Mips::A2));
2490 break;
2491 case 1:
2492 Inst.addOperand(MCOperand::createReg(Mips::A1));
2493 Inst.addOperand(MCOperand::createReg(Mips::A3));
2494 break;
2495 case 2:
2496 Inst.addOperand(MCOperand::createReg(Mips::A2));
2497 Inst.addOperand(MCOperand::createReg(Mips::A3));
2498 break;
2499 case 3:
2500 Inst.addOperand(MCOperand::createReg(Mips::A0));
2501 Inst.addOperand(MCOperand::createReg(Mips::S5));
2502 break;
2503 case 4:
2504 Inst.addOperand(MCOperand::createReg(Mips::A0));
2505 Inst.addOperand(MCOperand::createReg(Mips::S6));
2506 break;
2507 case 5:
2508 Inst.addOperand(MCOperand::createReg(Mips::A0));
2509 Inst.addOperand(MCOperand::createReg(Mips::A1));
2510 break;
2511 case 6:
2512 Inst.addOperand(MCOperand::createReg(Mips::A0));
2513 Inst.addOperand(MCOperand::createReg(Mips::A2));
2514 break;
2515 case 7:
2516 Inst.addOperand(MCOperand::createReg(Mips::A0));
2517 Inst.addOperand(MCOperand::createReg(Mips::A3));
2518 break;
2519 }
2520
2521 return MCDisassembler::Success;
2522 }
2523
DecodeSimm23Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2524 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2525 uint64_t Address, const void *Decoder) {
2526 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2527 return MCDisassembler::Success;
2528 }
2529
2530 template <typename InsnType>
DecodeBgtzGroupBranchMMR6(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)2531 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
2532 uint64_t Address,
2533 const void *Decoder) {
2534 // We have:
2535 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2536 // Invalid if rt == 0
2537 // BGTZALC_MMR6 if rs == 0 && rt != 0
2538 // BLTZALC_MMR6 if rs != 0 && rs == rt
2539 // BLTUC_MMR6 if rs != 0 && rs != rt
2540
2541 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2542 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2543 InsnType Imm = 0;
2544 bool HasRs = false;
2545 bool HasRt = false;
2546
2547 if (Rt == 0)
2548 return MCDisassembler::Fail;
2549 else if (Rs == 0) {
2550 MI.setOpcode(Mips::BGTZALC_MMR6);
2551 HasRt = true;
2552 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2553 }
2554 else if (Rs == Rt) {
2555 MI.setOpcode(Mips::BLTZALC_MMR6);
2556 HasRs = true;
2557 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2558 }
2559 else {
2560 MI.setOpcode(Mips::BLTUC_MMR6);
2561 HasRs = true;
2562 HasRt = true;
2563 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2564 }
2565
2566 if (HasRs)
2567 MI.addOperand(
2568 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2569
2570 if (HasRt)
2571 MI.addOperand(
2572 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2573
2574 MI.addOperand(MCOperand::createImm(Imm));
2575
2576 return MCDisassembler::Success;
2577 }
2578
2579 template <typename InsnType>
DecodeBlezGroupBranchMMR6(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)2580 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
2581 uint64_t Address,
2582 const void *Decoder) {
2583 // We have:
2584 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2585 // Invalid if rt == 0
2586 // BLEZALC_MMR6 if rs == 0 && rt != 0
2587 // BGEZALC_MMR6 if rs == rt && rt != 0
2588 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2589
2590 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2591 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2592 InsnType Imm = 0;
2593 bool HasRs = false;
2594
2595 if (Rt == 0)
2596 return MCDisassembler::Fail;
2597 else if (Rs == 0) {
2598 MI.setOpcode(Mips::BLEZALC_MMR6);
2599 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2600 }
2601 else if (Rs == Rt) {
2602 MI.setOpcode(Mips::BGEZALC_MMR6);
2603 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2604 }
2605 else {
2606 HasRs = true;
2607 MI.setOpcode(Mips::BGEUC_MMR6);
2608 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2609 }
2610
2611 if (HasRs)
2612 MI.addOperand(
2613 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2614 MI.addOperand(
2615 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2616
2617 MI.addOperand(MCOperand::createImm(Imm));
2618
2619 return MCDisassembler::Success;
2620 }
2621