1 //===-- MVEVPTBlockPass.cpp - Insert MVE VPT blocks -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "ARM.h"
10 #include "ARMMachineFunctionInfo.h"
11 #include "ARMSubtarget.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineInstrBundle.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/IR/DebugLoc.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/Support/Debug.h"
28 #include <cassert>
29 #include <new>
30
31 using namespace llvm;
32
33 #define DEBUG_TYPE "arm-mve-vpt"
34
35 namespace {
36 class MVEVPTBlock : public MachineFunctionPass {
37 public:
38 static char ID;
39 const Thumb2InstrInfo *TII;
40 const TargetRegisterInfo *TRI;
41
MVEVPTBlock()42 MVEVPTBlock() : MachineFunctionPass(ID) {}
43
44 bool runOnMachineFunction(MachineFunction &Fn) override;
45
getRequiredProperties() const46 MachineFunctionProperties getRequiredProperties() const override {
47 return MachineFunctionProperties().set(
48 MachineFunctionProperties::Property::NoVRegs);
49 }
50
getPassName() const51 StringRef getPassName() const override {
52 return "MVE VPT block insertion pass";
53 }
54
55 private:
56 bool InsertVPTBlocks(MachineBasicBlock &MBB);
57 };
58
59 char MVEVPTBlock::ID = 0;
60
61 } // end anonymous namespace
62
63 INITIALIZE_PASS(MVEVPTBlock, DEBUG_TYPE, "ARM MVE VPT block pass", false, false)
64
findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,const TargetRegisterInfo * TRI,unsigned & NewOpcode)65 static MachineInstr *findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,
66 const TargetRegisterInfo *TRI,
67 unsigned &NewOpcode) {
68 // Search backwards to the instruction that defines VPR. This may or not
69 // be a VCMP, we check that after this loop. If we find another instruction
70 // that reads cpsr, we return nullptr.
71 MachineBasicBlock::iterator CmpMI = MI;
72 while (CmpMI != MI->getParent()->begin()) {
73 --CmpMI;
74 if (CmpMI->modifiesRegister(ARM::VPR, TRI))
75 break;
76 if (CmpMI->readsRegister(ARM::VPR, TRI))
77 break;
78 }
79
80 if (CmpMI == MI)
81 return nullptr;
82 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode());
83 if (NewOpcode == 0)
84 return nullptr;
85
86 // Search forward from CmpMI to MI, checking if either register was def'd
87 if (registerDefinedBetween(CmpMI->getOperand(1).getReg(), std::next(CmpMI),
88 MI, TRI))
89 return nullptr;
90 if (registerDefinedBetween(CmpMI->getOperand(2).getReg(), std::next(CmpMI),
91 MI, TRI))
92 return nullptr;
93 return &*CmpMI;
94 }
95
96 // Advances Iter past a block of predicated instructions.
97 // Returns true if it successfully skipped the whole block of predicated
98 // instructions. Returns false when it stopped early (due to MaxSteps), or if
99 // Iter didn't point to a predicated instruction.
StepOverPredicatedInstrs(MachineBasicBlock::instr_iterator & Iter,MachineBasicBlock::instr_iterator EndIter,unsigned MaxSteps,unsigned & NumInstrsSteppedOver)100 static bool StepOverPredicatedInstrs(MachineBasicBlock::instr_iterator &Iter,
101 MachineBasicBlock::instr_iterator EndIter,
102 unsigned MaxSteps,
103 unsigned &NumInstrsSteppedOver) {
104 ARMVCC::VPTCodes NextPred = ARMVCC::None;
105 Register PredReg;
106 NumInstrsSteppedOver = 0;
107
108 while (Iter != EndIter) {
109 if (Iter->isDebugInstr()) {
110 // Skip debug instructions
111 ++Iter;
112 continue;
113 }
114
115 NextPred = getVPTInstrPredicate(*Iter, PredReg);
116 assert(NextPred != ARMVCC::Else &&
117 "VPT block pass does not expect Else preds");
118 if (NextPred == ARMVCC::None || MaxSteps == 0)
119 break;
120 --MaxSteps;
121 ++Iter;
122 ++NumInstrsSteppedOver;
123 };
124
125 return NumInstrsSteppedOver != 0 &&
126 (NextPred == ARMVCC::None || Iter == EndIter);
127 }
128
129 // Returns true if at least one instruction in the range [Iter, End) defines
130 // or kills VPR.
IsVPRDefinedOrKilledByBlock(MachineBasicBlock::iterator Iter,MachineBasicBlock::iterator End)131 static bool IsVPRDefinedOrKilledByBlock(MachineBasicBlock::iterator Iter,
132 MachineBasicBlock::iterator End) {
133 for (; Iter != End; ++Iter)
134 if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR))
135 return true;
136 return false;
137 }
138
139 // Creates a T, TT, TTT or TTTT BlockMask depending on BlockSize.
GetInitialBlockMask(unsigned BlockSize)140 static ARM::PredBlockMask GetInitialBlockMask(unsigned BlockSize) {
141 switch (BlockSize) {
142 case 1:
143 return ARM::PredBlockMask::T;
144 case 2:
145 return ARM::PredBlockMask::TT;
146 case 3:
147 return ARM::PredBlockMask::TTT;
148 case 4:
149 return ARM::PredBlockMask::TTTT;
150 default:
151 llvm_unreachable("Invalid BlockSize!");
152 }
153 }
154
155 // Given an iterator (Iter) that points at an instruction with a "Then"
156 // predicate, tries to create the largest block of continuous predicated
157 // instructions possible, and returns the VPT Block Mask of that block.
158 //
159 // This will try to perform some minor optimization in order to maximize the
160 // size of the block.
161 static ARM::PredBlockMask
CreateVPTBlock(MachineBasicBlock::instr_iterator & Iter,MachineBasicBlock::instr_iterator EndIter,SmallVectorImpl<MachineInstr * > & DeadInstructions)162 CreateVPTBlock(MachineBasicBlock::instr_iterator &Iter,
163 MachineBasicBlock::instr_iterator EndIter,
164 SmallVectorImpl<MachineInstr *> &DeadInstructions) {
165 MachineBasicBlock::instr_iterator BlockBeg = Iter;
166 (void)BlockBeg;
167 assert(getVPTInstrPredicate(*Iter) == ARMVCC::Then &&
168 "Expected a Predicated Instruction");
169
170 LLVM_DEBUG(dbgs() << "VPT block created for: "; Iter->dump());
171
172 unsigned BlockSize;
173 StepOverPredicatedInstrs(Iter, EndIter, 4, BlockSize);
174
175 LLVM_DEBUG(for (MachineBasicBlock::instr_iterator AddedInstIter =
176 std::next(BlockBeg);
177 AddedInstIter != Iter; ++AddedInstIter) {
178 if (AddedInstIter->isDebugInstr())
179 continue;
180 dbgs() << " adding: ";
181 AddedInstIter->dump();
182 });
183
184 // Generate the initial BlockMask
185 ARM::PredBlockMask BlockMask = GetInitialBlockMask(BlockSize);
186
187 // Remove VPNOTs while there's still room in the block, so we can make the
188 // largest block possible.
189 ARMVCC::VPTCodes CurrentPredicate = ARMVCC::Else;
190 while (BlockSize < 4 && Iter != EndIter &&
191 Iter->getOpcode() == ARM::MVE_VPNOT) {
192
193 // Try to skip all of the predicated instructions after the VPNOT, stopping
194 // after (4 - BlockSize). If we can't skip them all, stop.
195 unsigned ElseInstCnt = 0;
196 MachineBasicBlock::instr_iterator VPNOTBlockEndIter = std::next(Iter);
197 if (!StepOverPredicatedInstrs(VPNOTBlockEndIter, EndIter, (4 - BlockSize),
198 ElseInstCnt))
199 break;
200
201 // Check if this VPNOT can be removed or not: It can only be removed if at
202 // least one of the predicated instruction that follows it kills or sets
203 // VPR.
204 if (!IsVPRDefinedOrKilledByBlock(Iter, VPNOTBlockEndIter))
205 break;
206
207 LLVM_DEBUG(dbgs() << " removing VPNOT: "; Iter->dump());
208
209 // Record the new size of the block
210 BlockSize += ElseInstCnt;
211 assert(BlockSize <= 4 && "Block is too large!");
212
213 // Record the VPNot to remove it later.
214 DeadInstructions.push_back(&*Iter);
215 ++Iter;
216
217 // Replace the predicates of the instructions we're adding.
218 // Note that we are using "Iter" to iterate over the block so we can update
219 // it at the same time.
220 for (; Iter != VPNOTBlockEndIter; ++Iter) {
221 if (Iter->isDebugInstr())
222 continue;
223
224 // Find the register in which the predicate is
225 int OpIdx = findFirstVPTPredOperandIdx(*Iter);
226 assert(OpIdx != -1);
227
228 // Change the predicate and update the mask
229 Iter->getOperand(OpIdx).setImm(CurrentPredicate);
230 BlockMask = expandPredBlockMask(BlockMask, CurrentPredicate);
231
232 LLVM_DEBUG(dbgs() << " adding : "; Iter->dump());
233 }
234
235 CurrentPredicate =
236 (CurrentPredicate == ARMVCC::Then ? ARMVCC::Else : ARMVCC::Then);
237 }
238 return BlockMask;
239 }
240
InsertVPTBlocks(MachineBasicBlock & Block)241 bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
242 bool Modified = false;
243 MachineBasicBlock::instr_iterator MBIter = Block.instr_begin();
244 MachineBasicBlock::instr_iterator EndIter = Block.instr_end();
245
246 SmallVector<MachineInstr *, 4> DeadInstructions;
247
248 while (MBIter != EndIter) {
249 MachineInstr *MI = &*MBIter;
250 Register PredReg;
251 DebugLoc DL = MI->getDebugLoc();
252
253 ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg);
254
255 // The idea of the predicate is that None, Then and Else are for use when
256 // handling assembly language: they correspond to the three possible
257 // suffixes "", "t" and "e" on the mnemonic. So when instructions are read
258 // from assembly source or disassembled from object code, you expect to
259 // see a mixture whenever there's a long VPT block. But in code
260 // generation, we hope we'll never generate an Else as input to this pass.
261 assert(Pred != ARMVCC::Else && "VPT block pass does not expect Else preds");
262
263 if (Pred == ARMVCC::None) {
264 ++MBIter;
265 continue;
266 }
267
268 ARM::PredBlockMask BlockMask =
269 CreateVPTBlock(MBIter, EndIter, DeadInstructions);
270
271 // Search back for a VCMP that can be folded to create a VPT, or else
272 // create a VPST directly
273 MachineInstrBuilder MIBuilder;
274 unsigned NewOpcode;
275 LLVM_DEBUG(dbgs() << " final block mask: " << (unsigned)BlockMask << "\n");
276 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) {
277 LLVM_DEBUG(dbgs() << " folding VCMP into VPST: "; VCMP->dump());
278 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode));
279 MIBuilder.addImm((uint64_t)BlockMask);
280 MIBuilder.add(VCMP->getOperand(1));
281 MIBuilder.add(VCMP->getOperand(2));
282 MIBuilder.add(VCMP->getOperand(3));
283
284 // We need to remove any kill flags between the original VCMP and the new
285 // insertion point.
286 for (MachineInstr &MII :
287 make_range(VCMP->getIterator(), MI->getIterator())) {
288 MII.clearRegisterKills(VCMP->getOperand(1).getReg(), TRI);
289 MII.clearRegisterKills(VCMP->getOperand(2).getReg(), TRI);
290 }
291
292 VCMP->eraseFromParent();
293 } else {
294 MIBuilder = BuildMI(Block, MI, DL, TII->get(ARM::MVE_VPST));
295 MIBuilder.addImm((uint64_t)BlockMask);
296 }
297
298 // Erase all dead instructions (VPNOT's). Do that now so that they do not
299 // mess with the bundle creation.
300 for (MachineInstr *DeadMI : DeadInstructions)
301 DeadMI->eraseFromParent();
302 DeadInstructions.clear();
303
304 finalizeBundle(
305 Block, MachineBasicBlock::instr_iterator(MIBuilder.getInstr()), MBIter);
306
307 Modified = true;
308 }
309
310 return Modified;
311 }
312
runOnMachineFunction(MachineFunction & Fn)313 bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
314 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
315
316 if (!STI.isThumb2() || !STI.hasMVEIntegerOps())
317 return false;
318
319 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
320 TRI = STI.getRegisterInfo();
321
322 LLVM_DEBUG(dbgs() << "********** ARM MVE VPT BLOCKS **********\n"
323 << "********** Function: " << Fn.getName() << '\n');
324
325 bool Modified = false;
326 for (MachineBasicBlock &MBB : Fn)
327 Modified |= InsertVPTBlocks(MBB);
328
329 LLVM_DEBUG(dbgs() << "**************************************\n");
330 return Modified;
331 }
332
333 /// createMVEVPTBlock - Returns an instance of the MVE VPT block
334 /// insertion pass.
createMVEVPTBlockPass()335 FunctionPass *llvm::createMVEVPTBlockPass() { return new MVEVPTBlock(); }
336