1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "AVR.h"
11 #include "AVRRegisterInfo.h"
12 #include "MCTargetDesc/AVRMCELFStreamer.h"
13 #include "MCTargetDesc/AVRMCExpr.h"
14 #include "MCTargetDesc/AVRMCTargetDesc.h"
15
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstBuilder.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/MC/MCValue.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/TargetRegistry.h"
32
33 #include <sstream>
34
35 #define DEBUG_TYPE "avr-asm-parser"
36
37 using namespace llvm;
38
39 namespace {
40 /// Parses AVR assembly from a stream.
41 class AVRAsmParser : public MCTargetAsmParser {
42 const MCSubtargetInfo &STI;
43 MCAsmParser &Parser;
44 const MCRegisterInfo *MRI;
45 const std::string GENERATE_STUBS = "gs";
46
47 #define GET_ASSEMBLER_HEADER
48 #include "AVRGenAsmMatcher.inc"
49
50 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
51 OperandVector &Operands, MCStreamer &Out,
52 uint64_t &ErrorInfo,
53 bool MatchingInlineAsm) override;
54
55 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
56
57 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
58 SMLoc NameLoc, OperandVector &Operands) override;
59
60 bool ParseDirective(AsmToken DirectiveID) override;
61
62 OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
63
64 bool parseOperand(OperandVector &Operands);
65 int parseRegisterName(unsigned (*matchFn)(StringRef));
66 int parseRegisterName();
67 int parseRegister();
68 bool tryParseRegisterOperand(OperandVector &Operands);
69 bool tryParseExpression(OperandVector &Operands);
70 bool tryParseRelocExpression(OperandVector &Operands);
71 void eatComma();
72
73 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
74 unsigned Kind) override;
75
toDREG(unsigned Reg,unsigned From=AVR::sub_lo)76 unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
77 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
78 return MRI->getMatchingSuperReg(Reg, From, Class);
79 }
80
81 bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
82 bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
83 uint64_t const &ErrorInfo);
84 bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
85
86 bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
87
88 public:
AVRAsmParser(const MCSubtargetInfo & STI,MCAsmParser & Parser,const MCInstrInfo & MII,const MCTargetOptions & Options)89 AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
90 const MCInstrInfo &MII, const MCTargetOptions &Options)
91 : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
92 MCAsmParserExtension::Initialize(Parser);
93 MRI = getContext().getRegisterInfo();
94
95 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
96 }
97
getParser() const98 MCAsmParser &getParser() const { return Parser; }
getLexer() const99 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
100 };
101
102 /// An parsed AVR assembly operand.
103 class AVROperand : public MCParsedAsmOperand {
104 typedef MCParsedAsmOperand Base;
105 enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
106
107 public:
AVROperand(StringRef Tok,SMLoc const & S)108 AVROperand(StringRef Tok, SMLoc const &S)
109 : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
AVROperand(unsigned Reg,SMLoc const & S,SMLoc const & E)110 AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
111 : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
AVROperand(MCExpr const * Imm,SMLoc const & S,SMLoc const & E)112 AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
113 : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
AVROperand(unsigned Reg,MCExpr const * Imm,SMLoc const & S,SMLoc const & E)114 AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
115 : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
116
117 struct RegisterImmediate {
118 unsigned Reg;
119 MCExpr const *Imm;
120 };
121 union {
122 StringRef Tok;
123 RegisterImmediate RegImm;
124 };
125
126 SMLoc Start, End;
127
128 public:
addRegOperands(MCInst & Inst,unsigned N) const129 void addRegOperands(MCInst &Inst, unsigned N) const {
130 assert(Kind == k_Register && "Unexpected operand kind");
131 assert(N == 1 && "Invalid number of operands!");
132
133 Inst.addOperand(MCOperand::createReg(getReg()));
134 }
135
addExpr(MCInst & Inst,const MCExpr * Expr) const136 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
137 // Add as immediate when possible
138 if (!Expr)
139 Inst.addOperand(MCOperand::createImm(0));
140 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
141 Inst.addOperand(MCOperand::createImm(CE->getValue()));
142 else
143 Inst.addOperand(MCOperand::createExpr(Expr));
144 }
145
addImmOperands(MCInst & Inst,unsigned N) const146 void addImmOperands(MCInst &Inst, unsigned N) const {
147 assert(Kind == k_Immediate && "Unexpected operand kind");
148 assert(N == 1 && "Invalid number of operands!");
149
150 const MCExpr *Expr = getImm();
151 addExpr(Inst, Expr);
152 }
153
154 /// Adds the contained reg+imm operand to an instruction.
addMemriOperands(MCInst & Inst,unsigned N) const155 void addMemriOperands(MCInst &Inst, unsigned N) const {
156 assert(Kind == k_Memri && "Unexpected operand kind");
157 assert(N == 2 && "Invalid number of operands");
158
159 Inst.addOperand(MCOperand::createReg(getReg()));
160 addExpr(Inst, getImm());
161 }
162
isReg() const163 bool isReg() const { return Kind == k_Register; }
isImm() const164 bool isImm() const { return Kind == k_Immediate; }
isToken() const165 bool isToken() const { return Kind == k_Token; }
isMem() const166 bool isMem() const { return Kind == k_Memri; }
isMemri() const167 bool isMemri() const { return Kind == k_Memri; }
168
getToken() const169 StringRef getToken() const {
170 assert(Kind == k_Token && "Invalid access!");
171 return Tok;
172 }
173
getReg() const174 unsigned getReg() const {
175 assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
176
177 return RegImm.Reg;
178 }
179
getImm() const180 const MCExpr *getImm() const {
181 assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
182 return RegImm.Imm;
183 }
184
CreateToken(StringRef Str,SMLoc S)185 static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
186 return make_unique<AVROperand>(Str, S);
187 }
188
CreateReg(unsigned RegNum,SMLoc S,SMLoc E)189 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
190 SMLoc E) {
191 return make_unique<AVROperand>(RegNum, S, E);
192 }
193
CreateImm(const MCExpr * Val,SMLoc S,SMLoc E)194 static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
195 SMLoc E) {
196 return make_unique<AVROperand>(Val, S, E);
197 }
198
199 static std::unique_ptr<AVROperand>
CreateMemri(unsigned RegNum,const MCExpr * Val,SMLoc S,SMLoc E)200 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
201 return make_unique<AVROperand>(RegNum, Val, S, E);
202 }
203
makeToken(StringRef Token)204 void makeToken(StringRef Token) {
205 Kind = k_Token;
206 Tok = Token;
207 }
208
makeReg(unsigned RegNo)209 void makeReg(unsigned RegNo) {
210 Kind = k_Register;
211 RegImm = {RegNo, nullptr};
212 }
213
makeImm(MCExpr const * Ex)214 void makeImm(MCExpr const *Ex) {
215 Kind = k_Immediate;
216 RegImm = {0, Ex};
217 }
218
makeMemri(unsigned RegNo,MCExpr const * Imm)219 void makeMemri(unsigned RegNo, MCExpr const *Imm) {
220 Kind = k_Memri;
221 RegImm = {RegNo, Imm};
222 }
223
getStartLoc() const224 SMLoc getStartLoc() const { return Start; }
getEndLoc() const225 SMLoc getEndLoc() const { return End; }
226
print(raw_ostream & O) const227 virtual void print(raw_ostream &O) const {
228 switch (Kind) {
229 case k_Token:
230 O << "Token: \"" << getToken() << "\"";
231 break;
232 case k_Register:
233 O << "Register: " << getReg();
234 break;
235 case k_Immediate:
236 O << "Immediate: \"" << *getImm() << "\"";
237 break;
238 case k_Memri: {
239 // only manually print the size for non-negative values,
240 // as the sign is inserted automatically.
241 O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
242 break;
243 }
244 }
245 O << "\n";
246 }
247 };
248
249 } // end anonymous namespace.
250
251 // Auto-generated Match Functions
252
253 /// Maps from the set of all register names to a register number.
254 /// \note Generated by TableGen.
255 static unsigned MatchRegisterName(StringRef Name);
256
257 /// Maps from the set of all alternative registernames to a register number.
258 /// \note Generated by TableGen.
259 static unsigned MatchRegisterAltName(StringRef Name);
260
invalidOperand(SMLoc const & Loc,OperandVector const & Operands,uint64_t const & ErrorInfo)261 bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
262 OperandVector const &Operands,
263 uint64_t const &ErrorInfo) {
264 SMLoc ErrorLoc = Loc;
265 char const *Diag = 0;
266
267 if (ErrorInfo != ~0U) {
268 if (ErrorInfo >= Operands.size()) {
269 Diag = "too few operands for instruction.";
270 } else {
271 AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
272
273 // TODO: See if we can do a better error than just "invalid ...".
274 if (Op.getStartLoc() != SMLoc()) {
275 ErrorLoc = Op.getStartLoc();
276 }
277 }
278 }
279
280 if (!Diag) {
281 Diag = "invalid operand for instruction";
282 }
283
284 return Error(ErrorLoc, Diag);
285 }
286
missingFeature(llvm::SMLoc const & Loc,uint64_t const & ErrorInfo)287 bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
288 uint64_t const &ErrorInfo) {
289 return Error(Loc, "instruction requires a CPU feature not currently enabled");
290 }
291
emit(MCInst & Inst,SMLoc const & Loc,MCStreamer & Out) const292 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
293 Inst.setLoc(Loc);
294 Out.EmitInstruction(Inst, STI);
295
296 return false;
297 }
298
MatchAndEmitInstruction(SMLoc Loc,unsigned & Opcode,OperandVector & Operands,MCStreamer & Out,uint64_t & ErrorInfo,bool MatchingInlineAsm)299 bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
300 OperandVector &Operands,
301 MCStreamer &Out, uint64_t &ErrorInfo,
302 bool MatchingInlineAsm) {
303 MCInst Inst;
304 unsigned MatchResult =
305 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
306
307 switch (MatchResult) {
308 case Match_Success: return emit(Inst, Loc, Out);
309 case Match_MissingFeature: return missingFeature(Loc, ErrorInfo);
310 case Match_InvalidOperand: return invalidOperand(Loc, Operands, ErrorInfo);
311 case Match_MnemonicFail: return Error(Loc, "invalid instruction");
312 default: return true;
313 }
314 }
315
316 /// Parses a register name using a given matching function.
317 /// Checks for lowercase or uppercase if necessary.
parseRegisterName(unsigned (* matchFn)(StringRef))318 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
319 StringRef Name = Parser.getTok().getString();
320
321 int RegNum = matchFn(Name);
322
323 // GCC supports case insensitive register names. Some of the AVR registers
324 // are all lower case, some are all upper case but non are mixed. We prefer
325 // to use the original names in the register definitions. That is why we
326 // have to test both upper and lower case here.
327 if (RegNum == AVR::NoRegister) {
328 RegNum = matchFn(Name.lower());
329 }
330 if (RegNum == AVR::NoRegister) {
331 RegNum = matchFn(Name.upper());
332 }
333
334 return RegNum;
335 }
336
parseRegisterName()337 int AVRAsmParser::parseRegisterName() {
338 int RegNum = parseRegisterName(&MatchRegisterName);
339
340 if (RegNum == AVR::NoRegister)
341 RegNum = parseRegisterName(&MatchRegisterAltName);
342
343 return RegNum;
344 }
345
parseRegister()346 int AVRAsmParser::parseRegister() {
347 int RegNum = AVR::NoRegister;
348
349 if (Parser.getTok().is(AsmToken::Identifier)) {
350 // Check for register pair syntax
351 if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
352 Parser.Lex();
353 Parser.Lex(); // Eat high (odd) register and colon
354
355 if (Parser.getTok().is(AsmToken::Identifier)) {
356 // Convert lower (even) register to DREG
357 RegNum = toDREG(parseRegisterName());
358 }
359 } else {
360 RegNum = parseRegisterName();
361 }
362 }
363 return RegNum;
364 }
365
tryParseRegisterOperand(OperandVector & Operands)366 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
367 int RegNo = parseRegister();
368
369 if (RegNo == AVR::NoRegister)
370 return true;
371
372 AsmToken const &T = Parser.getTok();
373 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
374 Parser.Lex(); // Eat register token.
375
376 return false;
377 }
378
tryParseExpression(OperandVector & Operands)379 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
380 SMLoc S = Parser.getTok().getLoc();
381
382 if (!tryParseRelocExpression(Operands))
383 return false;
384
385 if ((Parser.getTok().getKind() == AsmToken::Plus ||
386 Parser.getTok().getKind() == AsmToken::Minus) &&
387 Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
388 // Don't handle this case - it should be split into two
389 // separate tokens.
390 return true;
391 }
392
393 // Parse (potentially inner) expression
394 MCExpr const *Expression;
395 if (getParser().parseExpression(Expression))
396 return true;
397
398 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
399 Operands.push_back(AVROperand::CreateImm(Expression, S, E));
400 return false;
401 }
402
tryParseRelocExpression(OperandVector & Operands)403 bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
404 bool isNegated = false;
405 AVRMCExpr::VariantKind ModifierKind = AVRMCExpr::VK_AVR_None;
406
407 SMLoc S = Parser.getTok().getLoc();
408
409 // Check for sign
410 AsmToken tokens[2];
411 size_t ReadCount = Parser.getLexer().peekTokens(tokens);
412
413 if (ReadCount == 2) {
414 if ((tokens[0].getKind() == AsmToken::Identifier &&
415 tokens[1].getKind() == AsmToken::LParen) ||
416 (tokens[0].getKind() == AsmToken::LParen &&
417 tokens[1].getKind() == AsmToken::Minus)) {
418
419 AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
420 if (CurTok == AsmToken::Minus ||
421 tokens[1].getKind() == AsmToken::Minus) {
422 isNegated = true;
423 } else {
424 assert(CurTok == AsmToken::Plus);
425 isNegated = false;
426 }
427
428 // Eat the sign
429 if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
430 Parser.Lex();
431 }
432 }
433
434 // Check if we have a target specific modifier (lo8, hi8, &c)
435 if (Parser.getTok().getKind() != AsmToken::Identifier ||
436 Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
437 // Not a reloc expr
438 return true;
439 }
440 StringRef ModifierName = Parser.getTok().getString();
441 ModifierKind = AVRMCExpr::getKindByName(ModifierName.str().c_str());
442
443 if (ModifierKind != AVRMCExpr::VK_AVR_None) {
444 Parser.Lex();
445 Parser.Lex(); // Eat modifier name and parenthesis
446 if (Parser.getTok().getString() == GENERATE_STUBS &&
447 Parser.getTok().getKind() == AsmToken::Identifier) {
448 std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
449 ModifierKind = AVRMCExpr::getKindByName(GSModName.c_str());
450 if (ModifierKind != AVRMCExpr::VK_AVR_None)
451 Parser.Lex(); // Eat gs modifier name
452 }
453 } else {
454 return Error(Parser.getTok().getLoc(), "unknown modifier");
455 }
456
457 if (tokens[1].getKind() == AsmToken::Minus ||
458 tokens[1].getKind() == AsmToken::Plus) {
459 Parser.Lex();
460 assert(Parser.getTok().getKind() == AsmToken::LParen);
461 Parser.Lex(); // Eat the sign and parenthesis
462 }
463
464 MCExpr const *InnerExpression;
465 if (getParser().parseExpression(InnerExpression))
466 return true;
467
468 if (tokens[1].getKind() == AsmToken::Minus ||
469 tokens[1].getKind() == AsmToken::Plus) {
470 assert(Parser.getTok().getKind() == AsmToken::RParen);
471 Parser.Lex(); // Eat closing parenthesis
472 }
473
474 // If we have a modifier wrap the inner expression
475 assert(Parser.getTok().getKind() == AsmToken::RParen);
476 Parser.Lex(); // Eat closing parenthesis
477
478 MCExpr const *Expression = AVRMCExpr::create(ModifierKind, InnerExpression,
479 isNegated, getContext());
480
481 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
482 Operands.push_back(AVROperand::CreateImm(Expression, S, E));
483
484 return false;
485 }
486
parseOperand(OperandVector & Operands)487 bool AVRAsmParser::parseOperand(OperandVector &Operands) {
488 LLVM_DEBUG(dbgs() << "parseOperand\n");
489
490 switch (getLexer().getKind()) {
491 default:
492 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
493
494 case AsmToken::Identifier:
495 // Try to parse a register, if it fails,
496 // fall through to the next case.
497 if (!tryParseRegisterOperand(Operands)) {
498 return false;
499 }
500 LLVM_FALLTHROUGH;
501 case AsmToken::LParen:
502 case AsmToken::Integer:
503 case AsmToken::Dot:
504 return tryParseExpression(Operands);
505 case AsmToken::Plus:
506 case AsmToken::Minus: {
507 // If the sign preceeds a number, parse the number,
508 // otherwise treat the sign a an independent token.
509 switch (getLexer().peekTok().getKind()) {
510 case AsmToken::Integer:
511 case AsmToken::BigNum:
512 case AsmToken::Identifier:
513 case AsmToken::Real:
514 if (!tryParseExpression(Operands))
515 return false;
516 break;
517 default:
518 break;
519 }
520 // Treat the token as an independent token.
521 Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
522 Parser.getTok().getLoc()));
523 Parser.Lex(); // Eat the token.
524 return false;
525 }
526 }
527
528 // Could not parse operand
529 return true;
530 }
531
532 OperandMatchResultTy
parseMemriOperand(OperandVector & Operands)533 AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
534 LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
535
536 SMLoc E, S;
537 MCExpr const *Expression;
538 int RegNo;
539
540 // Parse register.
541 {
542 RegNo = parseRegister();
543
544 if (RegNo == AVR::NoRegister)
545 return MatchOperand_ParseFail;
546
547 S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
548 Parser.Lex(); // Eat register token.
549 }
550
551 // Parse immediate;
552 {
553 if (getParser().parseExpression(Expression))
554 return MatchOperand_ParseFail;
555
556 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
557 }
558
559 Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
560
561 return MatchOperand_Success;
562 }
563
ParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc)564 bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
565 SMLoc &EndLoc) {
566 StartLoc = Parser.getTok().getLoc();
567 RegNo = parseRegister();
568 EndLoc = Parser.getTok().getLoc();
569
570 return (RegNo == AVR::NoRegister);
571 }
572
eatComma()573 void AVRAsmParser::eatComma() {
574 if (getLexer().is(AsmToken::Comma)) {
575 Parser.Lex();
576 } else {
577 // GCC allows commas to be omitted.
578 }
579 }
580
ParseInstruction(ParseInstructionInfo & Info,StringRef Mnemonic,SMLoc NameLoc,OperandVector & Operands)581 bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
582 StringRef Mnemonic, SMLoc NameLoc,
583 OperandVector &Operands) {
584 Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
585
586 bool first = true;
587 while (getLexer().isNot(AsmToken::EndOfStatement)) {
588 if (!first) eatComma();
589
590 first = false;
591
592 auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
593
594 if (MatchResult == MatchOperand_Success) {
595 continue;
596 }
597
598 if (MatchResult == MatchOperand_ParseFail) {
599 SMLoc Loc = getLexer().getLoc();
600 Parser.eatToEndOfStatement();
601
602 return Error(Loc, "failed to parse register and immediate pair");
603 }
604
605 if (parseOperand(Operands)) {
606 SMLoc Loc = getLexer().getLoc();
607 Parser.eatToEndOfStatement();
608 return Error(Loc, "unexpected token in argument list");
609 }
610 }
611 Parser.Lex(); // Consume the EndOfStatement
612 return false;
613 }
614
ParseDirective(llvm::AsmToken DirectiveID)615 bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
616 StringRef IDVal = DirectiveID.getIdentifier();
617 if (IDVal.lower() == ".long") {
618 parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
619 } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
620 parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
621 } else if (IDVal.lower() == ".byte") {
622 parseLiteralValues(1, DirectiveID.getLoc());
623 }
624 return true;
625 }
626
parseLiteralValues(unsigned SizeInBytes,SMLoc L)627 bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
628 MCAsmParser &Parser = getParser();
629 AVRMCELFStreamer &AVRStreamer =
630 static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
631 AsmToken Tokens[2];
632 size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
633 if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
634 Tokens[0].getKind() == AsmToken::Minus &&
635 Tokens[1].getKind() == AsmToken::Identifier) {
636 MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
637 AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L,
638 AVRMCExpr::VK_AVR_None);
639 return false;
640 }
641
642 if (Parser.getTok().getKind() == AsmToken::Identifier &&
643 Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
644 StringRef ModifierName = Parser.getTok().getString();
645 AVRMCExpr::VariantKind ModifierKind =
646 AVRMCExpr::getKindByName(ModifierName.str().c_str());
647 if (ModifierKind != AVRMCExpr::VK_AVR_None) {
648 Parser.Lex();
649 Parser.Lex(); // Eat the modifier and parenthesis
650 } else {
651 return Error(Parser.getTok().getLoc(), "unknown modifier");
652 }
653 MCSymbol *Symbol =
654 getContext().getOrCreateSymbol(Parser.getTok().getString());
655 AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
656 return false;
657 }
658
659 auto parseOne = [&]() -> bool {
660 const MCExpr *Value;
661 if (Parser.parseExpression(Value))
662 return true;
663 Parser.getStreamer().EmitValue(Value, SizeInBytes, L);
664 return false;
665 };
666 return (parseMany(parseOne));
667 }
668
LLVMInitializeAVRAsmParser()669 extern "C" void LLVMInitializeAVRAsmParser() {
670 RegisterMCAsmParser<AVRAsmParser> X(getTheAVRTarget());
671 }
672
673 #define GET_REGISTER_MATCHER
674 #define GET_MATCHER_IMPLEMENTATION
675 #include "AVRGenAsmMatcher.inc"
676
677 // Uses enums defined in AVRGenAsmMatcher.inc
validateTargetOperandClass(MCParsedAsmOperand & AsmOp,unsigned ExpectedKind)678 unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
679 unsigned ExpectedKind) {
680 AVROperand &Op = static_cast<AVROperand &>(AsmOp);
681 MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
682
683 // If need be, GCC converts bare numbers to register names
684 // It's ugly, but GCC supports it.
685 if (Op.isImm()) {
686 if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
687 int64_t RegNum = Const->getValue();
688 std::ostringstream RegName;
689 RegName << "r" << RegNum;
690 RegNum = MatchRegisterName(RegName.str().c_str());
691 if (RegNum != AVR::NoRegister) {
692 Op.makeReg(RegNum);
693 if (validateOperandClass(Op, Expected) == Match_Success) {
694 return Match_Success;
695 }
696 }
697 // Let the other quirks try their magic.
698 }
699 }
700
701 if (Op.isReg()) {
702 // If the instruction uses a register pair but we got a single, lower
703 // register we perform a "class cast".
704 if (isSubclass(Expected, MCK_DREGS)) {
705 unsigned correspondingDREG = toDREG(Op.getReg());
706
707 if (correspondingDREG != AVR::NoRegister) {
708 Op.makeReg(correspondingDREG);
709 return validateOperandClass(Op, Expected);
710 }
711 }
712 }
713 return Match_InvalidOperand;
714 }
715