1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains DAG node defintions for the AMDGPU target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// AMDGPU DAG Profiles
16//===----------------------------------------------------------------------===//
17
18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
20]>;
21
22def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
24>;
25
26def AMDGPULdExpOp : SDTypeProfile<1, 2,
27  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
28>;
29
30def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
32>;
33
34def AMDGPUFPPackOp : SDTypeProfile<1, 2,
35  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
36>;
37
38def AMDGPUIntPackOp : SDTypeProfile<1, 2,
39  [SDTCisInt<1>, SDTCisSameAs<1, 2>]
40>;
41
42def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
43  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
44>;
45
46// float, float, float, vcc
47def AMDGPUFmasOp : SDTypeProfile<1, 4,
48  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
49>;
50
51def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
52
53def AMDGPUIfOp : SDTypeProfile<1, 2,
54  [SDTCisVT<0, i64>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
55>;
56
57def AMDGPUElseOp : SDTypeProfile<1, 2,
58  [SDTCisVT<0, i64>, SDTCisVT<1, i64>, SDTCisVT<2, OtherVT>]
59>;
60
61def AMDGPULoopOp : SDTypeProfile<0, 2,
62  [SDTCisVT<0, i64>, SDTCisVT<1, OtherVT>]
63>;
64
65def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
66  [SDTCisVT<0, i64>, SDTCisVT<1, i1>, SDTCisVT<2, i64>]
67>;
68
69def AMDGPUAddeSubeOp : SDTypeProfile<2, 3,
70  [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, i32>, SDTCisVT<1, i1>, SDTCisVT<4, i1>]
71>;
72
73def SDT_AMDGPUTCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
74
75//===----------------------------------------------------------------------===//
76// AMDGPU DAG Nodes
77//
78
79def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
80def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
81def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
82
83def callseq_start : SDNode<"ISD::CALLSEQ_START",
84  SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
85  [SDNPHasChain, SDNPOutGlue]
86>;
87
88def callseq_end : SDNode<"ISD::CALLSEQ_END",
89 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
90  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
91>;
92
93def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
94  SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
95  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
96  SDNPVariadic]
97>;
98
99def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN", SDT_AMDGPUTCRET,
100  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
101>;
102
103def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
104  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
105    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
106>;
107
108def AMDGPUconstdata_ptr : SDNode<
109  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
110                                                     SDTCisVT<0, iPTR>]>
111>;
112
113// This argument to this node is a dword address.
114def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
115
116// Force dependencies for vector trunc stores
117def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
118
119def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
120def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
121
122// out = a - floor(a)
123def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
124
125// out = 1.0 / a
126def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
127
128// out = 1.0 / sqrt(a)
129def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
130
131// out = 1.0 / sqrt(a)
132def AMDGPUrcp_legacy : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
133def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
134
135def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
136
137// out = 1.0 / sqrt(a) result clamped to +/- max_float.
138def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
139
140def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
141
142def AMDGPUpkrtz_f16_f32 : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
143def AMDGPUpknorm_i16_f32 : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
144def AMDGPUpknorm_u16_f32 : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
145def AMDGPUpk_i16_i32 : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
146def AMDGPUpk_u16_u32 : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
147def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
148def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
149
150
151def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
152
153// out = max(a, b) a and b are floats, where a nan comparison fails.
154// This is not commutative because this gives the second operand:
155//   x < nan ? x : nan -> nan
156//   nan < x ? nan : x -> x
157def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
158  []
159>;
160
161def AMDGPUfmul_legacy : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
162  [SDNPCommutative, SDNPAssociative]
163>;
164
165// out = min(a, b) a and b are floats, where a nan comparison fails.
166def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
167  []
168>;
169
170// FIXME: TableGen doesn't like commutative instructions with more
171// than 2 operands.
172// out = max(a, b, c) a, b and c are floats
173def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
174  [/*SDNPCommutative, SDNPAssociative*/]
175>;
176
177// out = max(a, b, c) a, b, and c are signed ints
178def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
179  [/*SDNPCommutative, SDNPAssociative*/]
180>;
181
182// out = max(a, b, c) a, b and c are unsigned ints
183def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
184  [/*SDNPCommutative, SDNPAssociative*/]
185>;
186
187// out = min(a, b, c) a, b and c are floats
188def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
189  [/*SDNPCommutative, SDNPAssociative*/]
190>;
191
192// out = min(a, b, c) a, b and c are signed ints
193def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
194  [/*SDNPCommutative, SDNPAssociative*/]
195>;
196
197// out = min(a, b) a and b are unsigned ints
198def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
199  [/*SDNPCommutative, SDNPAssociative*/]
200>;
201
202// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
203def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
204
205// out = (src1 > src0) ? 1 : 0
206def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
207
208// TODO: remove AMDGPUadde/AMDGPUsube when ADDCARRY/SUBCARRY get their own
209// nodes in TargetSelectionDAG.td.
210def AMDGPUadde : SDNode<"ISD::ADDCARRY", AMDGPUAddeSubeOp, []>;
211
212def AMDGPUsube : SDNode<"ISD::SUBCARRY", AMDGPUAddeSubeOp, []>;
213
214def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
215  SDTCisVT<0, i64>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
216]>;
217
218def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
219
220def AMDGPUSetRegOp :  SDTypeProfile<0, 2, [
221  SDTCisInt<0>, SDTCisInt<1>
222]>;
223
224def AMDGPUsetreg : SDNode<"AMDGPUISD::SETREG", AMDGPUSetRegOp, [
225  SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>;
226
227def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
228   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
229
230def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
231  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
232
233def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
234  SDTIntToFPOp, []>;
235def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
236  SDTIntToFPOp, []>;
237def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
238  SDTIntToFPOp, []>;
239def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
240  SDTIntToFPOp, []>;
241
242
243// urecip - This operation is a helper for integer division, it returns the
244// result of 1 / a as a fractional unsigned integer.
245// out = (2^32 / a) + e
246// e is rounding error
247def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
248
249// Special case divide preop and flags.
250def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
251
252//  Special case divide FMA with scale and flags (src0 = Quotient,
253//  src1 = Denominator, src2 = Numerator).
254def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
255
256// Single or double precision division fixup.
257// Special case divide fixup and flags(src0 = Quotient, src1 =
258// Denominator, src2 = Numerator).
259def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
260
261def AMDGPUfmad_ftz : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
262
263// Look Up 2.0 / pi src0 with segment select src1[4:0]
264def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
265
266def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
267                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
268                          [SDNPHasChain, SDNPMayLoad]>;
269
270def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
271                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
272                           [SDNPHasChain, SDNPMayStore]>;
273
274// MSKOR instructions are atomic memory instructions used mainly for storing
275// 8-bit and 16-bit values.  The definition is:
276//
277// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
278//
279// src0: vec4(src, 0, 0, mask)
280// src1: dst - rat offset (aka pointer) in dwords
281def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
282                        SDTypeProfile<0, 2, []>,
283                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
284
285def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
286                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
287                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
288                             SDNPMemOperand]>;
289
290def AMDGPUround : SDNode<"ISD::FROUND",
291                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
292
293def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
294def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
295def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
296def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
297
298def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
299def AMDGPUffbh_i32 : SDNode<"AMDGPUISD::FFBH_I32", SDTIntUnaryOp>;
300
301def AMDGPUffbl_b32 : SDNode<"AMDGPUISD::FFBL_B32", SDTIntUnaryOp>;
302
303// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
304// when performing the mulitply. The result is a 32-bit value.
305def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
306  [SDNPCommutative, SDNPAssociative]
307>;
308def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
309  [SDNPCommutative, SDNPAssociative]
310>;
311
312def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
313  [SDNPCommutative, SDNPAssociative]
314>;
315def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
316  [SDNPCommutative, SDNPAssociative]
317>;
318
319def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
320  []
321>;
322def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
323  []
324>;
325
326def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
327  []
328>;
329
330def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
331  []
332>;
333
334def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
335
336def AMDGPUfdot2 : SDNode<"AMDGPUISD::FDOT2",
337                  SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
338                                       SDTCisFP<0>, SDTCisVec<1>,
339                                       SDTCisInt<4>]>,
340                  []>;
341
342def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
343
344def AMDGPUinit_exec : SDNode<"AMDGPUISD::INIT_EXEC",
345                      SDTypeProfile<0, 1, [SDTCisInt<0>]>,
346                      [SDNPHasChain, SDNPInGlue]>;
347
348def AMDGPUinit_exec_from_input : SDNode<"AMDGPUISD::INIT_EXEC_FROM_INPUT",
349                                 SDTypeProfile<0, 2,
350                                 [SDTCisInt<0>, SDTCisInt<1>]>,
351                                 [SDNPHasChain, SDNPInGlue]>;
352
353def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
354                    SDTypeProfile<0, 1, [SDTCisInt<0>]>,
355                    [SDNPHasChain, SDNPInGlue]>;
356
357def AMDGPUsendmsghalt : SDNode<"AMDGPUISD::SENDMSGHALT",
358                    SDTypeProfile<0, 1, [SDTCisInt<0>]>,
359                    [SDNPHasChain, SDNPInGlue]>;
360
361def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
362                        SDTypeProfile<1, 3, [SDTCisFP<0>]>,
363                        [SDNPInGlue]>;
364
365def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
366                      SDTypeProfile<1, 3, [SDTCisFP<0>]>,
367                      [SDNPInGlue, SDNPOutGlue]>;
368
369def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
370                      SDTypeProfile<1, 4, [SDTCisFP<0>]>,
371                      [SDNPInGlue]>;
372
373
374def AMDGPUkill : SDNode<"AMDGPUISD::KILL", AMDGPUKillSDT,
375  [SDNPHasChain, SDNPSideEffect]>;
376
377// SI+ export
378def AMDGPUExportOp : SDTypeProfile<0, 8, [
379  SDTCisInt<0>,       // i8 tgt
380  SDTCisInt<1>,       // i8 en
381                      // i32 or f32 src0
382  SDTCisSameAs<3, 2>, // f32 src1
383  SDTCisSameAs<4, 2>, // f32 src2
384  SDTCisSameAs<5, 2>, // f32 src3
385  SDTCisInt<6>,       // i1 compr
386  // skip done
387  SDTCisInt<1>        // i1 vm
388
389]>;
390
391def AMDGPUexport: SDNode<"AMDGPUISD::EXPORT", AMDGPUExportOp,
392  [SDNPHasChain, SDNPMayStore]>;
393
394def AMDGPUexport_done: SDNode<"AMDGPUISD::EXPORT_DONE", AMDGPUExportOp,
395  [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
396
397
398def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
399
400def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
401  [SDNPHasChain, SDNPSideEffect]>;
402
403//===----------------------------------------------------------------------===//
404// Flow Control Profile Types
405//===----------------------------------------------------------------------===//
406// Branch instruction where second and third are basic blocks
407def SDTIL_BRCond : SDTypeProfile<0, 2, [
408    SDTCisVT<0, OtherVT>
409    ]>;
410
411//===----------------------------------------------------------------------===//
412// Flow Control DAG Nodes
413//===----------------------------------------------------------------------===//
414def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
415
416//===----------------------------------------------------------------------===//
417// Call/Return DAG Nodes
418//===----------------------------------------------------------------------===//
419def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
420    [SDNPHasChain, SDNPOptInGlue]>;
421
422def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
423    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
424
425def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
426  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
427>;
428