1//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file defines all the static objects used by AMDGPURegisterBankInfo.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14namespace llvm {
15namespace AMDGPU {
16
17enum PartialMappingIdx {
18  None = - 1,
19  PM_SGPR1  = 2,
20  PM_SGPR16 = 6,
21  PM_SGPR32 = 7,
22  PM_SGPR64 = 8,
23  PM_SGPR128 = 9,
24  PM_SGPR256 = 10,
25  PM_SGPR512 = 11,
26  PM_VGPR1  = 12,
27  PM_VGPR16 = 16,
28  PM_VGPR32 = 17,
29  PM_VGPR64 = 18,
30  PM_VGPR128 = 19,
31  PM_VGPR256 = 20,
32  PM_VGPR512 = 21,
33  PM_SGPR96 = 22,
34  PM_VGPR96 = 23
35};
36
37const RegisterBankInfo::PartialMapping PartMappings[] {
38  // StartIdx, Length, RegBank
39  {0, 1,  SCCRegBank},
40  {0, 1,  VCCRegBank},
41
42  {0, 1,  SGPRRegBank}, // SGPR begin
43  {0, 16, SGPRRegBank},
44  {0, 32, SGPRRegBank},
45  {0, 64, SGPRRegBank},
46  {0, 128, SGPRRegBank},
47  {0, 256, SGPRRegBank},
48  {0, 512, SGPRRegBank},
49
50  {0, 1,  VGPRRegBank}, // VGPR begin
51  {0, 16, VGPRRegBank},
52  {0, 32, VGPRRegBank},
53  {0, 64, VGPRRegBank},
54  {0, 128, VGPRRegBank},
55  {0, 256, VGPRRegBank},
56  {0, 512, VGPRRegBank},
57  {0, 96, SGPRRegBank},
58  {0, 96, VGPRRegBank},
59};
60
61const RegisterBankInfo::ValueMapping ValMappings[] {
62  // SCC
63  {&PartMappings[0], 1},
64
65  // VCC
66  {&PartMappings[1], 1},
67
68  // SGPRs
69  {&PartMappings[2], 1},
70  {nullptr, 0}, // Illegal power of 2 sizes
71  {nullptr, 0},
72  {nullptr, 0},
73  {&PartMappings[3], 1},
74  {&PartMappings[4], 1},
75  {&PartMappings[5], 1},
76  {&PartMappings[6], 1},
77  {&PartMappings[7], 1},
78  {&PartMappings[8], 1},
79
80    // VGPRs
81  {&PartMappings[9], 1},
82  {nullptr, 0},
83  {nullptr, 0},
84  {nullptr, 0},
85  {&PartMappings[10], 1},
86  {&PartMappings[11], 1},
87  {&PartMappings[12], 1},
88  {&PartMappings[13], 1},
89  {&PartMappings[14], 1},
90  {&PartMappings[15], 1},
91  {&PartMappings[16], 1},
92  {&PartMappings[17], 1}
93};
94
95enum ValueMappingIdx {
96  SCCStartIdx = 0,
97  SGPRStartIdx = 2,
98  VGPRStartIdx = 12
99};
100
101const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
102                                                      unsigned Size) {
103  unsigned Idx;
104  switch (Size) {
105  case 1:
106    if (BankID == AMDGPU::SCCRegBankID)
107      return &ValMappings[0];
108    if (BankID == AMDGPU::VCCRegBankID)
109      return &ValMappings[1];
110
111    // 1-bit values not from a compare etc.
112    Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
113    break;
114  case 96:
115    assert(BankID != AMDGPU::VCCRegBankID);
116    Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
117    break;
118  default:
119    assert(BankID != AMDGPU::VCCRegBankID);
120    Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
121    Idx += Log2_32_Ceil(Size);
122    break;
123  }
124
125  assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
126  assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
127
128  return &ValMappings[Idx];
129}
130
131} // End AMDGPU namespace.
132} // End llvm namespace.
133