1 /*-
2 * Copyright (c) 2017 Andriy Gapon
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/conf.h>
34 #include <sys/malloc.h>
35 #include <sys/module.h>
36 #include <sys/sysctl.h>
37 #include <sys/types.h>
38
39 #include <dev/pci/pcivar.h>
40
41 #include <vm/vm.h>
42 #include <vm/vm_extern.h>
43 #include <vm/vm_kern.h>
44
45 #include <machine/cputypes.h>
46 #include <machine/md_var.h>
47
48
49 /*
50 * See BKDG for AMD Family 15h Models 00h-0Fh Processors
51 * (publication 42301 Rev 3.08 - March 12, 2012):
52 * - 2.13.3.1 DRAM Error Injection
53 * - D18F3xB8 NB Array Address
54 * - D18F3xBC NB Array Data Port
55 * - D18F3xBC_x8 DRAM ECC
56 */
57 #define NB_MCA_CFG 0x44
58 #define DRAM_ECC_EN (1 << 22)
59 #define NB_MCA_EXTCFG 0x180
60 #define ECC_SYMB_SZ (1 << 25)
61 #define NB_ARRAY_ADDR 0xb8
62 #define DRAM_ECC_SEL (0x8 << 28)
63 #define QUADRANT_SHIFT 1
64 #define QUADRANT_MASK 0x3
65 #define NB_ARRAY_PORT 0xbc
66 #define INJ_WORD_SHIFT 20
67 #define INJ_WORD_MASK 0x1ff
68 #define DRAM_ERR_EN (1 << 18)
69 #define DRAM_WR_REQ (1 << 17)
70 #define DRAM_RD_REQ (1 << 16)
71 #define INJ_VECTOR_MASK 0xffff
72
73 static void ecc_ei_inject(int);
74
75 static device_t nbdev;
76 static int delay_ms = 0;
77 static int quadrant = 0; /* 0 - 3 */
78 static int word_mask = 0x001; /* 9 bits: 8 + 1 for ECC */
79 static int bit_mask = 0x0001; /* 16 bits */
80
81 static int
sysctl_int_with_max(SYSCTL_HANDLER_ARGS)82 sysctl_int_with_max(SYSCTL_HANDLER_ARGS)
83 {
84 u_int value;
85 int error;
86
87 value = *(u_int *)arg1;
88 error = sysctl_handle_int(oidp, &value, 0, req);
89 if (error || req->newptr == NULL)
90 return (error);
91 if (value > arg2)
92 return (EINVAL);
93 *(u_int *)arg1 = value;
94 return (0);
95 }
96
97 static int
sysctl_nonzero_int_with_max(SYSCTL_HANDLER_ARGS)98 sysctl_nonzero_int_with_max(SYSCTL_HANDLER_ARGS)
99 {
100 u_int value;
101 int error;
102
103 value = *(u_int *)arg1;
104 error = sysctl_int_with_max(oidp, &value, arg2, req);
105 if (error || req->newptr == NULL)
106 return (error);
107 if (value == 0)
108 return (EINVAL);
109 *(u_int *)arg1 = value;
110 return (0);
111 }
112
113 static int
sysctl_proc_inject(SYSCTL_HANDLER_ARGS)114 sysctl_proc_inject(SYSCTL_HANDLER_ARGS)
115 {
116 int error;
117 int i;
118
119 i = 0;
120 error = sysctl_handle_int(oidp, &i, 0, req);
121 if (error)
122 return (error);
123 if (i != 0)
124 ecc_ei_inject(i);
125 return (0);
126 }
127
128 static SYSCTL_NODE(_hw, OID_AUTO, error_injection, CTLFLAG_RD, NULL,
129 "Hardware error injection");
130 static SYSCTL_NODE(_hw_error_injection, OID_AUTO, dram_ecc, CTLFLAG_RD, NULL,
131 "DRAM ECC error injection");
132 SYSCTL_UINT(_hw_error_injection_dram_ecc, OID_AUTO, delay,
133 CTLTYPE_UINT | CTLFLAG_RW, &delay_ms, 0,
134 "Delay in milliseconds between error injections");
135 SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, quadrant,
136 CTLTYPE_UINT | CTLFLAG_RW, &quadrant, QUADRANT_MASK,
137 sysctl_int_with_max, "IU",
138 "Index of 16-byte quadrant within 64-byte line where errors "
139 "should be injected");
140 SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, word_mask,
141 CTLTYPE_UINT | CTLFLAG_RW, &word_mask, INJ_WORD_MASK,
142 sysctl_nonzero_int_with_max, "IU",
143 "9-bit mask of words where errors should be injected (8 data + 1 ECC)");
144 SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, bit_mask,
145 CTLTYPE_UINT | CTLFLAG_RW, &bit_mask, INJ_VECTOR_MASK,
146 sysctl_nonzero_int_with_max, "IU",
147 "16-bit mask of bits within each selected word where errors "
148 "should be injected");
149 SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, inject,
150 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0, sysctl_proc_inject, "I",
151 "Inject a number of errors according to configured parameters");
152
153 static void
ecc_ei_inject_one(void * arg,size_t size)154 ecc_ei_inject_one(void *arg, size_t size)
155 {
156 volatile uint64_t *memory = arg;
157 uint32_t val;
158 int i;
159
160 val = DRAM_ECC_SEL | (quadrant << QUADRANT_SHIFT);
161 pci_write_config(nbdev, NB_ARRAY_ADDR, val, 4);
162
163 val = (word_mask << INJ_WORD_SHIFT) | DRAM_WR_REQ | bit_mask;
164 pci_write_config(nbdev, NB_ARRAY_PORT, val, 4);
165
166 for (i = 0; i < size / sizeof(uint64_t); i++) {
167 memory[i] = 0;
168 val = pci_read_config(nbdev, NB_ARRAY_PORT, 4);
169 if ((val & DRAM_WR_REQ) == 0)
170 break;
171 }
172 for (i = 0; i < size / sizeof(uint64_t); i++)
173 memory[0] = memory[i];
174 }
175
176 static void
ecc_ei_inject(int count)177 ecc_ei_inject(int count)
178 {
179 vm_offset_t memory;
180 int injected;
181
182 KASSERT((quadrant & ~QUADRANT_MASK) == 0,
183 ("quadrant value is outside of range: %u", quadrant));
184 KASSERT(word_mask != 0 && (word_mask & ~INJ_WORD_MASK) == 0,
185 ("word mask value is outside of range: 0x%x", word_mask));
186 KASSERT(bit_mask != 0 && (bit_mask & ~INJ_VECTOR_MASK) == 0,
187 ("bit mask value is outside of range: 0x%x", bit_mask));
188
189 memory = kmem_alloc_attr(PAGE_SIZE, M_WAITOK, 0, ~0,
190 VM_MEMATTR_UNCACHEABLE);
191
192 for (injected = 0; injected < count; injected++) {
193 ecc_ei_inject_one((void*)memory, PAGE_SIZE);
194 if (delay_ms != 0 && injected != count - 1)
195 pause_sbt("ecc_ei_inject", delay_ms * SBT_1MS, 0, 0);
196 }
197
198 kmem_free(memory, PAGE_SIZE);
199 }
200
201 static int
ecc_ei_load(void)202 ecc_ei_load(void)
203 {
204 uint32_t val;
205
206 if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) {
207 printf("DRAM ECC error injection is not supported\n");
208 return (ENXIO);
209 }
210 nbdev = pci_find_bsf(0, 24, 3);
211 if (nbdev == NULL) {
212 printf("Couldn't find NB PCI device\n");
213 return (ENXIO);
214 }
215 val = pci_read_config(nbdev, NB_MCA_CFG, 4);
216 if ((val & DRAM_ECC_EN) == 0) {
217 printf("DRAM ECC is not supported or disabled\n");
218 return (ENXIO);
219 }
220 printf("DRAM ECC error injection support loaded\n");
221 return (0);
222 }
223
224 static int
tsc_modevent(module_t mod __unused,int type,void * data __unused)225 tsc_modevent(module_t mod __unused, int type, void *data __unused)
226 {
227 int error;
228
229 error = 0;
230 switch (type) {
231 case MOD_LOAD:
232 error = ecc_ei_load();
233 break;
234 case MOD_UNLOAD:
235 case MOD_SHUTDOWN:
236 break;
237 default:
238 return (EOPNOTSUPP);
239 }
240 return (0);
241 }
242
243 DEV_MODULE(tsc, tsc_modevent, NULL);
244