xref: /dpdk/drivers/common/cnxk/hw/nix.h (revision 4968b362) 
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #ifndef __NIX_HW_H__
6 #define __NIX_HW_H__
7 
8 /* Register offsets */
9 
10 #define NIX_AF_CFG			(0x0ull)
11 #define NIX_AF_STATUS			(0x10ull)
12 #define NIX_AF_NDC_CFG			(0x18ull)
13 #define NIX_AF_CONST			(0x20ull)
14 #define NIX_AF_CONST1			(0x28ull)
15 #define NIX_AF_CONST2			(0x30ull)
16 #define NIX_AF_CONST3			(0x38ull)
17 #define NIX_AF_SQ_CONST			(0x40ull)
18 #define NIX_AF_CQ_CONST			(0x48ull)
19 #define NIX_AF_RQ_CONST			(0x50ull)
20 #define NIX_AF_PL_CONST			(0x58ull) /* [CN10K, .) */
21 #define NIX_AF_PSE_CONST		(0x60ull)
22 #define NIX_AF_TL1_CONST		(0x70ull)
23 #define NIX_AF_TL2_CONST		(0x78ull)
24 #define NIX_AF_TL3_CONST		(0x80ull)
25 #define NIX_AF_TL4_CONST		(0x88ull)
26 #define NIX_AF_MDQ_CONST		(0x90ull)
27 #define NIX_AF_MC_MIRROR_CONST		(0x98ull)
28 #define NIX_AF_LSO_CFG			(0xa8ull)
29 #define NIX_AF_BLK_RST			(0xb0ull)
30 #define NIX_AF_TX_TSTMP_CFG		(0xc0ull)
31 #define NIX_AF_PL_TS			(0xc8ull) /* [CN10K, .) */
32 #define NIX_AF_RX_CFG			(0xd0ull)
33 #define NIX_AF_AVG_DELAY		(0xe0ull)
34 #define NIX_AF_CINT_DELAY		(0xf0ull)
35 #define NIX_AF_VWQE_TIMER		(0xf8ull) /* [CN10K, .) */
36 #define NIX_AF_RX_MCAST_BASE		(0x100ull)
37 #define NIX_AF_RX_MCAST_CFG		(0x110ull)
38 #define NIX_AF_RX_MCAST_BUF_BASE	(0x120ull)
39 #define NIX_AF_RX_MCAST_BUF_CFG		(0x130ull)
40 #define NIX_AF_RX_MIRROR_BUF_BASE	(0x140ull)
41 #define NIX_AF_RX_MIRROR_BUF_CFG	(0x148ull)
42 #define NIX_AF_LF_RST			(0x150ull)
43 #define NIX_AF_GEN_INT			(0x160ull)
44 #define NIX_AF_GEN_INT_W1S		(0x168ull)
45 #define NIX_AF_GEN_INT_ENA_W1S		(0x170ull)
46 #define NIX_AF_GEN_INT_ENA_W1C		(0x178ull)
47 #define NIX_AF_ERR_INT			(0x180ull)
48 #define NIX_AF_ERR_INT_W1S		(0x188ull)
49 #define NIX_AF_ERR_INT_ENA_W1S		(0x190ull)
50 #define NIX_AF_ERR_INT_ENA_W1C		(0x198ull)
51 #define NIX_AF_RAS			(0x1a0ull)
52 #define NIX_AF_RAS_W1S			(0x1a8ull)
53 #define NIX_AF_RAS_ENA_W1S		(0x1b0ull)
54 #define NIX_AF_RAS_ENA_W1C		(0x1b8ull)
55 #define NIX_AF_RVU_INT			(0x1c0ull)
56 #define NIX_AF_RVU_INT_W1S		(0x1c8ull)
57 #define NIX_AF_RVU_INT_ENA_W1S		(0x1d0ull)
58 #define NIX_AF_RVU_INT_ENA_W1C		(0x1d8ull)
59 #define NIX_AF_TCP_TIMER		(0x1e0ull)
60 /* [CN10k, .) */
61 #define NIX_AF_RX_DEF_ETX(a)		(0x1f0ull | (uint64_t)(a) << 3)
62 #define NIX_AF_RX_DEF_OL2		(0x200ull)
63 #define NIX_AF_RX_DEF_GEN0_COLOR	(0x208ull) /* [CN10K, .) */
64 #define NIX_AF_RX_DEF_OIP4		(0x210ull)
65 #define NIX_AF_RX_DEF_GEN1_COLOR	(0x218ull) /* [CN10K, .) */
66 #define NIX_AF_RX_DEF_IIP4		(0x220ull)
67 #define NIX_AF_RX_DEF_VLAN0_PCP_DEI	(0x228ull) /* [CN10K, .) */
68 #define NIX_AF_RX_DEF_OIP6		(0x230ull)
69 #define NIX_AF_RX_DEF_VLAN1_PCP_DEI	(0x238ull) /* [CN10K, .) */
70 #define NIX_AF_RX_DEF_IIP6		(0x240ull)
71 #define NIX_AF_RX_DEF_OTCP		(0x250ull)
72 #define NIX_AF_RX_DEF_ITCP		(0x260ull)
73 #define NIX_AF_RX_DEF_OUDP		(0x270ull)
74 #define NIX_AF_RX_DEF_IUDP		(0x280ull)
75 #define NIX_AF_RX_DEF_OSCTP		(0x290ull)
76 #define NIX_AF_RX_DEF_CST_APAD_0	(0x298ull) /* [CN10K, .) */
77 #define NIX_AF_RX_DEF_ISCTP		(0x2a0ull)
78 #define NIX_AF_RX_DEF_CST_APAD_1	(0x2a8ull) /* [CN10K, .) */
79 #define NIX_AF_RX_DEF_IPSECX(a)		(0x2b0ull | (uint64_t)(a) << 3)
80 #define NIX_AF_RX_DEF_IIP4_DSCP		(0x2e0ull) /* [CN10K, .) */
81 #define NIX_AF_RX_DEF_OIP4_DSCP		(0x2e8ull) /* [CN10K, .) */
82 #define NIX_AF_RX_DEF_IIP6_DSCP		(0x2f0ull) /* [CN10K, .) */
83 #define NIX_AF_RX_DEF_OIP6_DSCP		(0x2f8ull) /* [CN10K, .) */
84 #define NIX_AF_RX_IPSEC_GEN_CFG		(0x300ull)
85 #define NIX_AF_RX_IPSEC_VWQE_GEN_CFG	(0x310ull) /* [CN10K, .) */
86 #define NIX_AF_RX_CPTX_INST_QSEL(a)	(0x320ull | (uint64_t)(a) << 3)
87 #define NIX_AF_RX_CPTX_CREDIT(a)	(0x360ull | (uint64_t)(a) << 3)
88 #define NIX_AF_NDC_RX_SYNC		(0x3e0ull)
89 #define NIX_AF_NDC_TX_SYNC		(0x3f0ull)
90 #define NIX_AF_AQ_CFG			(0x400ull)
91 #define NIX_AF_AQ_BASE			(0x410ull)
92 #define NIX_AF_AQ_STATUS		(0x420ull)
93 #define NIX_AF_AQ_DOOR			(0x430ull)
94 #define NIX_AF_AQ_DONE_WAIT		(0x440ull)
95 #define NIX_AF_AQ_DONE			(0x450ull)
96 #define NIX_AF_AQ_DONE_ACK		(0x460ull)
97 #define NIX_AF_AQ_DONE_TIMER		(0x470ull)
98 #define NIX_AF_AQ_DONE_ENA_W1S		(0x490ull)
99 #define NIX_AF_AQ_DONE_ENA_W1C		(0x498ull)
100 #define NIX_AF_RX_LINKX_CFG(a)		(0x540ull | (uint64_t)(a) << 16)
101 #define NIX_AF_RX_SW_SYNC		(0x550ull)
102 #define NIX_AF_RX_LINKX_WRR_CFG(a)	(0x560ull | (uint64_t)(a) << 16)
103 #define NIX_AF_SEB_CFG			(0x5f0ull) /* [CN10K, .) */
104 #define NIX_AF_EXPR_TX_FIFO_STATUS	(0x640ull) /* [CN9K, CN10K) */
105 #define NIX_AF_NORM_TX_FIFO_STATUS	(0x648ull)
106 #define NIX_AF_SDP_TX_FIFO_STATUS	(0x650ull)
107 #define NIX_AF_TX_NPC_CAPTURE_CONFIG	(0x660ull)
108 #define NIX_AF_TX_NPC_CAPTURE_INFO	(0x668ull)
109 #define NIX_AF_TX_NPC_CAPTURE_RESPX(a)	(0x680ull | (uint64_t)(a) << 3)
110 #define NIX_AF_SEB_ACTIVE_CYCLES_PCX(a) (0x6c0ull | (uint64_t)(a) << 3)
111 #define NIX_AF_SMQX_CFG(a)		(0x700ull | (uint64_t)(a) << 16)
112 #define NIX_AF_SMQX_HEAD(a)		(0x710ull | (uint64_t)(a) << 16)
113 #define NIX_AF_SMQX_TAIL(a)		(0x720ull | (uint64_t)(a) << 16)
114 #define NIX_AF_SMQX_STATUS(a)		(0x730ull | (uint64_t)(a) << 16)
115 #define NIX_AF_SMQX_NXT_HEAD(a)		(0x740ull | (uint64_t)(a) << 16)
116 #define NIX_AF_SQM_ACTIVE_CYCLES_PC	(0x770ull)
117 #define NIX_AF_SQM_SCLK_CNT		(0x780ull) /* [CN10K, .) */
118 #define NIX_AF_DWRR_SDP_MTU		(0x790ull) /* [CN10K, .) */
119 #define NIX_AF_DWRR_RPM_MTU		(0x7a0ull) /* [CN10K, .) */
120 #define NIX_AF_PSE_CHANNEL_LEVEL	(0x800ull)
121 #define NIX_AF_PSE_SHAPER_CFG		(0x810ull)
122 #define NIX_AF_PSE_ACTIVE_CYCLES_PC	(0x8c0ull)
123 #define NIX_AF_MARK_FORMATX_CTL(a)	(0x900ull | (uint64_t)(a) << 18)
124 #define NIX_AF_TX_LINKX_NORM_CREDIT(a)	(0xa00ull | (uint64_t)(a) << 16)
125 /* [CN9K, CN10K) */
126 #define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xa10ull | (uint64_t)(a) << 16)
127 /* [CN9K, CN10K) */
128 #define NIX_AF_TX_LINKX_SW_XOFF(a) (0xa20ull | (uint64_t)(a) << 16)
129 /* [CN10K, .) */
130 #define NIX_AF_TX_LINKX_NORM_CDT_ADJ(a) (0xa20ull | (uint64_t)(a) << 16)
131 #define NIX_AF_TX_LINKX_HW_XOFF(a)	(0xa30ull | (uint64_t)(a) << 16)
132 #define NIX_AF_SDP_LINK_CREDIT		(0xa40ull)
133 #define NIX_AF_SDP_LINK_CDT_ADJ		(0xa50ull) /* [CN10K, .) */
134 /* [CN9K, CN10K) */
135 #define NIX_AF_SDP_SW_XOFFX(a)	    (0xa60ull | (uint64_t)(a) << 3)
136 #define NIX_AF_SDP_HW_XOFFX(a)	    (0xac0ull | (uint64_t)(a) << 3)
137 #define NIX_AF_TL4X_BP_STATUS(a)    (0xb00ull | (uint64_t)(a) << 16)
138 #define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xb10ull | (uint64_t)(a) << 16)
139 #define NIX_AF_TL1_TW_ARB_CTL_DEBUG (0xbc0ull) /* [CN10K, .) */
140 #define NIX_AF_TL1_TW_ARB_REQ_DEBUG (0xbc8ull) /* [CN10K, .) */
141 #define NIX_AF_TL1X_SCHEDULE(a)	    (0xc00ull | (uint64_t)(a) << 16)
142 #define NIX_AF_TL1X_SHAPE(a)	    (0xc10ull | (uint64_t)(a) << 16)
143 #define NIX_AF_TL1X_CIR(a)	    (0xc20ull | (uint64_t)(a) << 16)
144 /* [CN9K, CN10K) */
145 #define NIX_AF_TL1X_SHAPE_STATE(a) (0xc50ull | (uint64_t)(a) << 16)
146 /* [CN10K, .) */
147 #define NIX_AF_TL1X_SHAPE_STATE_CIR(a) (0xc50ull | (uint64_t)(a) << 16)
148 #define NIX_AF_TL1X_SW_XOFF(a)	       (0xc70ull | (uint64_t)(a) << 16)
149 #define NIX_AF_TL1X_TOPOLOGY(a)	       (0xc80ull | (uint64_t)(a) << 16)
150 #define NIX_AF_TL1X_MD_DEBUG0(a)       (0xcc0ull | (uint64_t)(a) << 16)
151 #define NIX_AF_TL1X_MD_DEBUG1(a)       (0xcc8ull | (uint64_t)(a) << 16)
152 /* [CN9K, CN10K) */
153 #define NIX_AF_TL1X_MD_DEBUG2(a) (0xcd0ull | (uint64_t)(a) << 16)
154 /* [CN10K, .) */
155 #define NIX_AF_TL2X_SHAPE_STATE_CIR(a) (0xcd0ull | (uint64_t)(a) << 16)
156 /* [CN9K, CN10K) */
157 #define NIX_AF_TL1X_MD_DEBUG3(a)       (0xcd8ull | (uint64_t)(a) << 16)
158 #define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xd20ull | (uint64_t)(a) << 16)
159 #define NIX_AF_TL1X_DROPPED_BYTES(a)   (0xd30ull | (uint64_t)(a) << 16)
160 #define NIX_AF_TL1X_RED_PACKETS(a)     (0xd40ull | (uint64_t)(a) << 16)
161 #define NIX_AF_TL1X_RED_BYTES(a)       (0xd50ull | (uint64_t)(a) << 16)
162 #define NIX_AF_TL1X_YELLOW_PACKETS(a)  (0xd60ull | (uint64_t)(a) << 16)
163 #define NIX_AF_TL1X_YELLOW_BYTES(a)    (0xd70ull | (uint64_t)(a) << 16)
164 #define NIX_AF_TL1X_GREEN_PACKETS(a)   (0xd80ull | (uint64_t)(a) << 16)
165 #define NIX_AF_TL1X_GREEN_BYTES(a)     (0xd90ull | (uint64_t)(a) << 16)
166 #define NIX_AF_MDQ_MD_COUNT	       (0xda0ull) /* [CN10K, .) */
167 /* [CN10K, .) */
168 #define NIX_AF_MDQX_OUT_MD_COUNT(a) (0xdb0ull | (uint64_t)(a) << 16)
169 #define NIX_AF_TL2_TW_ARB_CTL_DEBUG (0xdc0ull) /* [CN10K, .) */
170 /* [CN10K, .) */
171 #define NIX_AF_TL2_TWX_ARB_REQ_DEBUG0(a) (0xdc8ull | (uint64_t)(a) << 16)
172 /* [CN10K, .) */
173 #define NIX_AF_TL2_TWX_ARB_REQ_DEBUG1(a) (0xdd0ull | (uint64_t)(a) << 16)
174 #define NIX_AF_TL2X_SCHEDULE(a)		 (0xe00ull | (uint64_t)(a) << 16)
175 #define NIX_AF_TL2X_SHAPE(a)		 (0xe10ull | (uint64_t)(a) << 16)
176 #define NIX_AF_TL2X_CIR(a)		 (0xe20ull | (uint64_t)(a) << 16)
177 #define NIX_AF_TL2X_PIR(a)		 (0xe30ull | (uint64_t)(a) << 16)
178 #define NIX_AF_TL2X_SCHED_STATE(a)	 (0xe40ull | (uint64_t)(a) << 16)
179 /* [CN9K, CN10K) */
180 #define NIX_AF_TL2X_SHAPE_STATE(a) (0xe50ull | (uint64_t)(a) << 16)
181 /* [CN10K, .) */
182 #define NIX_AF_TL2X_SHAPE_STATE_PIR(a) (0xe50ull | (uint64_t)(a) << 16)
183 #define NIX_AF_TL2X_SW_XOFF(a)	       (0xe70ull | (uint64_t)(a) << 16)
184 #define NIX_AF_TL2X_TOPOLOGY(a)	       (0xe80ull | (uint64_t)(a) << 16)
185 #define NIX_AF_TL2X_PARENT(a)	       (0xe88ull | (uint64_t)(a) << 16)
186 #define NIX_AF_TL2X_MD_DEBUG0(a)       (0xec0ull | (uint64_t)(a) << 16)
187 #define NIX_AF_TL2X_MD_DEBUG1(a)       (0xec8ull | (uint64_t)(a) << 16)
188 /* [CN9K, CN10K) */
189 #define NIX_AF_TL2X_MD_DEBUG2(a) (0xed0ull | (uint64_t)(a) << 16)
190 /* [CN10K, .) */
191 #define NIX_AF_TL3X_SHAPE_STATE_CIR(a) (0xed0ull | (uint64_t)(a) << 16)
192 /* [CN9K, CN10K) */
193 #define NIX_AF_TL2X_MD_DEBUG3(a)    (0xed8ull | (uint64_t)(a) << 16)
194 #define NIX_AF_TL3_TW_ARB_CTL_DEBUG (0xfc0ull) /* [CN10K, .) */
195 /* [CN10k, .) */
196 #define NIX_AF_TL3_TWX_ARB_REQ_DEBUG0(a) (0xfc8ull | (uint64_t)(a) << 16)
197 /* [CN10K, .) */
198 #define NIX_AF_TL3_TWX_ARB_REQ_DEBUG1(a) (0xfd0ull | (uint64_t)(a) << 16)
199 #define NIX_AF_TL3X_SCHEDULE(a)		 (0x1000ull | (uint64_t)(a) << 16)
200 #define NIX_AF_TL3X_SHAPE(a)		 (0x1010ull | (uint64_t)(a) << 16)
201 #define NIX_AF_TL3X_CIR(a)		 (0x1020ull | (uint64_t)(a) << 16)
202 #define NIX_AF_TL3X_PIR(a)		 (0x1030ull | (uint64_t)(a) << 16)
203 #define NIX_AF_TL3X_SCHED_STATE(a)	 (0x1040ull | (uint64_t)(a) << 16)
204 /* [CN9K, CN10K) */
205 #define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050ull | (uint64_t)(a) << 16)
206 /* [CN10K, .) */
207 #define NIX_AF_TL3X_SHAPE_STATE_PIR(a) (0x1050ull | (uint64_t)(a) << 16)
208 #define NIX_AF_TL3X_SW_XOFF(a)	       (0x1070ull | (uint64_t)(a) << 16)
209 #define NIX_AF_TL3X_TOPOLOGY(a)	       (0x1080ull | (uint64_t)(a) << 16)
210 #define NIX_AF_TL3X_PARENT(a)	       (0x1088ull | (uint64_t)(a) << 16)
211 #define NIX_AF_TL3X_MD_DEBUG0(a)       (0x10c0ull | (uint64_t)(a) << 16)
212 #define NIX_AF_TL3X_MD_DEBUG1(a)       (0x10c8ull | (uint64_t)(a) << 16)
213 /* [CN9K, CN10K) */
214 #define NIX_AF_TL3X_MD_DEBUG2(a) (0x10d0ull | (uint64_t)(a) << 16)
215 /* [CN10K, .) */
216 #define NIX_AF_TL4X_SHAPE_STATE_CIR(a) (0x10d0ull | (uint64_t)(a) << 16)
217 /* [CN9K, CN10K) */
218 #define NIX_AF_TL3X_MD_DEBUG3(a)    (0x10d8ull | (uint64_t)(a) << 16)
219 #define NIX_AF_TL4_TW_ARB_CTL_DEBUG (0x11c0ull) /* [CN10K, .) */
220 /* [CN10K, .) */
221 #define NIX_AF_TL4_TWX_ARB_REQ_DEBUG0(a) (0x11c8ull | (uint64_t)(a) << 16)
222 /* [CN10K, .) */
223 #define NIX_AF_TL4_TWX_ARB_REQ_DEBUG1(a) (0x11d0ull | (uint64_t)(a) << 16)
224 #define NIX_AF_TL4X_SCHEDULE(a)		 (0x1200ull | (uint64_t)(a) << 16)
225 #define NIX_AF_TL4X_SHAPE(a)		 (0x1210ull | (uint64_t)(a) << 16)
226 #define NIX_AF_TL4X_CIR(a)		 (0x1220ull | (uint64_t)(a) << 16)
227 #define NIX_AF_TL4X_PIR(a)		 (0x1230ull | (uint64_t)(a) << 16)
228 #define NIX_AF_TL4X_SCHED_STATE(a)	 (0x1240ull | (uint64_t)(a) << 16)
229 #define NIX_AF_TL4X_SHAPE_STATE(a)	 (0x1250ull | (uint64_t)(a) << 16)
230 #define NIX_AF_TL4X_SW_XOFF(a)		 (0x1270ull | (uint64_t)(a) << 16)
231 #define NIX_AF_TL4X_TOPOLOGY(a)		 (0x1280ull | (uint64_t)(a) << 16)
232 #define NIX_AF_TL4X_PARENT(a)		 (0x1288ull | (uint64_t)(a) << 16)
233 #define NIX_AF_TL4X_MD_DEBUG0(a)	 (0x12c0ull | (uint64_t)(a) << 16)
234 #define NIX_AF_TL4X_MD_DEBUG1(a)	 (0x12c8ull | (uint64_t)(a) << 16)
235 /* [CN9K, CN10K) */
236 #define NIX_AF_TL4X_MD_DEBUG2(a) (0x12d0ull | (uint64_t)(a) << 16)
237 /* [CN10K, .) */
238 #define NIX_AF_MDQX_SHAPE_STATE_CIR(a) (0x12d0ull | (uint64_t)(a) << 16)
239 /* [CN9K, CN10K) */
240 #define NIX_AF_TL4X_MD_DEBUG3(a)    (0x12d8ull | (uint64_t)(a) << 16)
241 #define NIX_AF_MDQ_TW_ARB_CTL_DEBUG (0x13c0ull) /* [CN10K, .) */
242 /* [CN10K, .) */
243 #define NIX_AF_MDQ_TWX_ARB_REQ_DEBUG0(a) (0x13c8ull | (uint64_t)(a) << 16)
244 /* [CN10K, .) */
245 #define NIX_AF_MDQ_TWX_ARB_REQ_DEBUG1(a) (0x13d0ull | (uint64_t)(a) << 16)
246 #define NIX_AF_MDQX_SCHEDULE(a)		 (0x1400ull | (uint64_t)(a) << 16)
247 #define NIX_AF_MDQX_SHAPE(a)		 (0x1410ull | (uint64_t)(a) << 16)
248 #define NIX_AF_MDQX_CIR(a)		 (0x1420ull | (uint64_t)(a) << 16)
249 #define NIX_AF_MDQX_PIR(a)		 (0x1430ull | (uint64_t)(a) << 16)
250 #define NIX_AF_MDQX_SCHED_STATE(a)	 (0x1440ull | (uint64_t)(a) << 16)
251 /* [CN9K, CN10K) */
252 #define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450ull | (uint64_t)(a) << 16)
253 /* [CN10K, .) */
254 #define NIX_AF_MDQX_SHAPE_STATE_PIR(a) (0x1450ull | (uint64_t)(a) << 16)
255 #define NIX_AF_MDQX_SW_XOFF(a)	       (0x1470ull | (uint64_t)(a) << 16)
256 #define NIX_AF_MDQX_PARENT(a)	       (0x1480ull | (uint64_t)(a) << 16)
257 #define NIX_AF_MDQX_MD_DEBUG(a)	       (0x14c0ull | (uint64_t)(a) << 16)
258 /* [CN10K, .) */
259 #define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0ull | (uint64_t)(a) << 16)
260 /* [CN9K, CN10K) */
261 #define NIX_AF_TL3_TL2X_CFG(a)	     (0x1600ull | (uint64_t)(a) << 16)
262 #define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610ull | (uint64_t)(a) << 16)
263 #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b)                                        \
264 	(0x1700ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)
265 #define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b)                                   \
266 	(0x1800ull | (uint64_t)(a) << 18 | (uint64_t)(b) << 3)
267 #define NIX_AF_TX_MCASTX(a)	    (0x1900ull | (uint64_t)(a) << 15)
268 #define NIX_AF_TX_VTAG_DEFX_CTL(a)  (0x1a00ull | (uint64_t)(a) << 16)
269 #define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1a10ull | (uint64_t)(a) << 16)
270 #define NIX_AF_RX_BPIDX_STATUS(a)   (0x1a20ull | (uint64_t)(a) << 17)
271 #define NIX_AF_RX_CHANX_CFG(a)	    (0x1a30ull | (uint64_t)(a) << 15)
272 #define NIX_AF_CINT_TIMERX(a)	    (0x1a40ull | (uint64_t)(a) << 18)
273 #define NIX_AF_LSO_FORMATX_FIELDX(a, b)                                        \
274 	(0x1b00ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)
275 #define NIX_AF_LFX_CFG(a) (0x4000ull | (uint64_t)(a) << 17)
276 /* [CN10K, .) */
277 #define NIX_AF_LINKX_CFG(a)		 (0x4010ull | (uint64_t)(a) << 17)
278 #define NIX_AF_LFX_SQS_CFG(a)		 (0x4020ull | (uint64_t)(a) << 17)
279 #define NIX_AF_LFX_TX_CFG2(a)		 (0x4028ull | (uint64_t)(a) << 17)
280 #define NIX_AF_LFX_SQS_BASE(a)		 (0x4030ull | (uint64_t)(a) << 17)
281 #define NIX_AF_LFX_RQS_CFG(a)		 (0x4040ull | (uint64_t)(a) << 17)
282 #define NIX_AF_LFX_RQS_BASE(a)		 (0x4050ull | (uint64_t)(a) << 17)
283 #define NIX_AF_LFX_CQS_CFG(a)		 (0x4060ull | (uint64_t)(a) << 17)
284 #define NIX_AF_LFX_CQS_BASE(a)		 (0x4070ull | (uint64_t)(a) << 17)
285 #define NIX_AF_LFX_TX_CFG(a)		 (0x4080ull | (uint64_t)(a) << 17)
286 #define NIX_AF_LFX_TX_PARSE_CFG(a)	 (0x4090ull | (uint64_t)(a) << 17)
287 #define NIX_AF_LFX_RX_CFG(a)		 (0x40a0ull | (uint64_t)(a) << 17)
288 #define NIX_AF_LFX_RSS_CFG(a)		 (0x40c0ull | (uint64_t)(a) << 17)
289 #define NIX_AF_LFX_RSS_BASE(a)		 (0x40d0ull | (uint64_t)(a) << 17)
290 #define NIX_AF_LFX_QINTS_CFG(a)		 (0x4100ull | (uint64_t)(a) << 17)
291 #define NIX_AF_LFX_QINTS_BASE(a)	 (0x4110ull | (uint64_t)(a) << 17)
292 #define NIX_AF_LFX_CINTS_CFG(a)		 (0x4120ull | (uint64_t)(a) << 17)
293 #define NIX_AF_LFX_CINTS_BASE(a)	 (0x4130ull | (uint64_t)(a) << 17)
294 #define NIX_AF_LFX_RX_IPSEC_CFG0(a)	 (0x4140ull | (uint64_t)(a) << 17)
295 #define NIX_AF_LFX_RX_IPSEC_CFG1(a)	 (0x4148ull | (uint64_t)(a) << 17)
296 #define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a)	 (0x4150ull | (uint64_t)(a) << 17)
297 #define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158ull | (uint64_t)(a) << 17)
298 #define NIX_AF_LFX_RX_IPSEC_SA_BASE(a)	 (0x4170ull | (uint64_t)(a) << 17)
299 #define NIX_AF_LFX_TX_STATUS(a)		 (0x4180ull | (uint64_t)(a) << 17)
300 #define NIX_AF_LFX_RX_VTAG_TYPEX(a, b)                                         \
301 	(0x4200ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
302 #define NIX_AF_LFX_LOCKX(a, b)                                                 \
303 	(0x4300ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
304 #define NIX_AF_LFX_TX_STATX(a, b)                                              \
305 	(0x4400ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
306 #define NIX_AF_LFX_RX_STATX(a, b)                                              \
307 	(0x4500ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
308 #define NIX_AF_LFX_RSS_GRPX(a, b)                                              \
309 	(0x4600ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
310 #define NIX_AF_RX_NPC_MC_RCV	  (0x4700ull)
311 #define NIX_AF_RX_NPC_MC_DROP	  (0x4710ull)
312 #define NIX_AF_RX_NPC_MIRROR_RCV  (0x4720ull)
313 #define NIX_AF_RX_NPC_MIRROR_DROP (0x4730ull)
314 /* [CN10K, .) */
315 #define NIX_AF_LFX_VWQE_NORM_COMPL(a) (0x4740ull | (uint64_t)(a) << 17)
316 /* [CN10K, .) */
317 #define NIX_AF_LFX_VWQE_RLS_TIMEOUT(a) (0x4750ull | (uint64_t)(a) << 17)
318 /* [CN10K, .) */
319 #define NIX_AF_LFX_VWQE_HASH_FULL(a) (0x4760ull | (uint64_t)(a) << 17)
320 /* [CN10K, .) */
321 #define NIX_AF_LFX_VWQE_SA_FULL(a)     (0x4770ull | (uint64_t)(a) << 17)
322 #define NIX_AF_VWQE_HASH_FUNC_MASK     (0x47a0ull) /* [CN10K, .) */
323 #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800ull | (uint64_t)(a) << 16)
324 /* [CN10K, .) */
325 #define NIX_AF_RX_LINKX_WRR_OUT_CFG(a) (0x4a00ull | (uint64_t)(a) << 16)
326 #define NIX_PRIV_AF_INT_CFG	       (0x8000000ull)
327 #define NIX_PRIV_LFX_CFG(a)	       (0x8000010ull | (uint64_t)(a) << 8)
328 #define NIX_PRIV_LFX_INT_CFG(a)	       (0x8000020ull | (uint64_t)(a) << 8)
329 #define NIX_AF_RVU_LF_CFG_DEBUG	       (0x8000030ull)
330 
331 #define NIX_LF_RX_SECRETX(a)	 (0x0ull | (uint64_t)(a) << 3)
332 #define NIX_LF_CFG		 (0x100ull)
333 #define NIX_LF_GINT		 (0x200ull)
334 #define NIX_LF_GINT_W1S		 (0x208ull)
335 #define NIX_LF_GINT_ENA_W1C	 (0x210ull)
336 #define NIX_LF_GINT_ENA_W1S	 (0x218ull)
337 #define NIX_LF_ERR_INT		 (0x220ull)
338 #define NIX_LF_ERR_INT_W1S	 (0x228ull)
339 #define NIX_LF_ERR_INT_ENA_W1C	 (0x230ull)
340 #define NIX_LF_ERR_INT_ENA_W1S	 (0x238ull)
341 #define NIX_LF_RAS		 (0x240ull)
342 #define NIX_LF_RAS_W1S		 (0x248ull)
343 #define NIX_LF_RAS_ENA_W1C	 (0x250ull)
344 #define NIX_LF_RAS_ENA_W1S	 (0x258ull)
345 #define NIX_LF_SQ_OP_ERR_DBG	 (0x260ull)
346 #define NIX_LF_MNQ_ERR_DBG	 (0x270ull)
347 #define NIX_LF_SEND_ERR_DBG	 (0x280ull)
348 #define NIX_LF_TX_STATX(a)	 (0x300ull | (uint64_t)(a) << 3)
349 #define NIX_LF_RX_STATX(a)	 (0x400ull | (uint64_t)(a) << 3)
350 #define NIX_LF_OP_SENDX(a)	 (0x800ull | (uint64_t)(a) << 3)
351 #define NIX_LF_RQ_OP_INT	 (0x900ull)
352 #define NIX_LF_RQ_OP_OCTS	 (0x910ull)
353 #define NIX_LF_RQ_OP_PKTS	 (0x920ull)
354 #define NIX_LF_RQ_OP_DROP_OCTS	 (0x930ull)
355 #define NIX_LF_RQ_OP_DROP_PKTS	 (0x940ull)
356 #define NIX_LF_RQ_OP_RE_PKTS	 (0x950ull)
357 #define NIX_LF_OP_IPSEC_DYNO_CNT (0x980ull)
358 #define NIX_LF_OP_VWQE_FLUSH	 (0x9a0ull) /* [CN10K, .) */
359 #define NIX_LF_PL_OP_BAND_PROF	 (0x9c0ull) /* [CN10K, .) */
360 #define NIX_LF_SQ_OP_INT	 (0xa00ull)
361 #define NIX_LF_SQ_OP_OCTS	 (0xa10ull)
362 #define NIX_LF_SQ_OP_PKTS	 (0xa20ull)
363 #define NIX_LF_SQ_OP_STATUS	 (0xa30ull)
364 #define NIX_LF_SQ_OP_DROP_OCTS	 (0xa40ull)
365 #define NIX_LF_SQ_OP_DROP_PKTS	 (0xa50ull)
366 #define NIX_LF_CQ_OP_INT	 (0xb00ull)
367 #define NIX_LF_CQ_OP_DOOR	 (0xb30ull)
368 #define NIX_LF_CQ_OP_STATUS	 (0xb40ull)
369 #define NIX_LF_QINTX_CNT(a)	 (0xc00ull | (uint64_t)(a) << 12)
370 #define NIX_LF_QINTX_INT(a)	 (0xc10ull | (uint64_t)(a) << 12)
371 #define NIX_LF_QINTX_ENA_W1S(a)	 (0xc20ull | (uint64_t)(a) << 12)
372 #define NIX_LF_QINTX_ENA_W1C(a)	 (0xc30ull | (uint64_t)(a) << 12)
373 #define NIX_LF_CINTX_CNT(a)	 (0xd00ull | (uint64_t)(a) << 12)
374 #define NIX_LF_CINTX_WAIT(a)	 (0xd10ull | (uint64_t)(a) << 12)
375 #define NIX_LF_CINTX_INT(a)	 (0xd20ull | (uint64_t)(a) << 12)
376 #define NIX_LF_CINTX_INT_W1S(a)	 (0xd30ull | (uint64_t)(a) << 12)
377 #define NIX_LF_CINTX_ENA_W1S(a)	 (0xd40ull | (uint64_t)(a) << 12)
378 #define NIX_LF_CINTX_ENA_W1C(a)	 (0xd50ull | (uint64_t)(a) << 12)
379 /* [CN10K, .) */
380 #define NIX_LF_RX_GEN_COLOR_CONVX(a) (0x4740ull | (uint64_t)(a) << 3)
381 #define NIX_LF_RX_VLAN0_COLOR_CONV   (0x4760ull) /* [CN10K, .) */
382 #define NIX_LF_RX_VLAN1_COLOR_CONV   (0x4768ull) /* [CN10K, .) */
383 #define NIX_LF_RX_IIP_COLOR_CONV_LO  (0x4770ull) /* [CN10K, .) */
384 #define NIX_LF_RX_IIP_COLOR_CONV_HI  (0x4778ull) /* [CN10K, .) */
385 #define NIX_LF_RX_OIP_COLOR_CONV_LO  (0x4780ull) /* [CN10K, .) */
386 #define NIX_LF_RX_OIP_COLOR_CONV_HI  (0x4788ull) /* [CN10K, .) */
387 
388 /* Enum offsets */
389 
390 #define NIX_STAT_LF_TX_TX_UCAST (0x0ull)
391 #define NIX_STAT_LF_TX_TX_BCAST (0x1ull)
392 #define NIX_STAT_LF_TX_TX_MCAST (0x2ull)
393 #define NIX_STAT_LF_TX_TX_DROP	(0x3ull)
394 #define NIX_STAT_LF_TX_TX_OCTS	(0x4ull)
395 
396 #define NIX_STAT_LF_RX_RX_OCTS	      (0x0ull)
397 #define NIX_STAT_LF_RX_RX_UCAST	      (0x1ull)
398 #define NIX_STAT_LF_RX_RX_BCAST	      (0x2ull)
399 #define NIX_STAT_LF_RX_RX_MCAST	      (0x3ull)
400 #define NIX_STAT_LF_RX_RX_DROP	      (0x4ull)
401 #define NIX_STAT_LF_RX_RX_DROP_OCTS   (0x5ull)
402 #define NIX_STAT_LF_RX_RX_FCS	      (0x6ull)
403 #define NIX_STAT_LF_RX_RX_ERR	      (0x7ull)
404 #define NIX_STAT_LF_RX_RX_DRP_BCAST   (0x8ull)
405 #define NIX_STAT_LF_RX_RX_DRP_MCAST   (0x9ull)
406 #define NIX_STAT_LF_RX_RX_DRP_L3BCAST (0xaull)
407 #define NIX_STAT_LF_RX_RX_DRP_L3MCAST (0xbull)
408 
409 #define NIX_STAT_LF_RX_RX_GC_OCTS_PASSED (0xcull)  /* [CN10K, .) */
410 #define NIX_STAT_LF_RX_RX_GC_PKTS_PASSED (0xdull)  /* [CN10K, .) */
411 #define NIX_STAT_LF_RX_RX_YC_OCTS_PASSED (0xeull)  /* [CN10K, .) */
412 #define NIX_STAT_LF_RX_RX_YC_PKTS_PASSED (0xfull)  /* [CN10K, .) */
413 #define NIX_STAT_LF_RX_RX_RC_OCTS_PASSED (0x10ull) /* [CN10K, .) */
414 #define NIX_STAT_LF_RX_RX_RC_PKTS_PASSED (0x11ull) /* [CN10K, .) */
415 #define NIX_STAT_LF_RX_RX_GC_OCTS_DROP	 (0x12ull) /* [CN10K, .) */
416 #define NIX_STAT_LF_RX_RX_GC_PKTS_DROP	 (0x13ull) /* [CN10K, .) */
417 #define NIX_STAT_LF_RX_RX_YC_OCTS_DROP	 (0x14ull) /* [CN10K, .) */
418 #define NIX_STAT_LF_RX_RX_YC_PKTS_DROP	 (0x15ull) /* [CN10K, .) */
419 #define NIX_STAT_LF_RX_RX_RC_OCTS_DROP	 (0x16ull) /* [CN10K, .) */
420 #define NIX_STAT_LF_RX_RX_RC_PKTS_DROP	 (0x17ull) /* [CN10K, .) */
421 #define NIX_STAT_LF_RX_RX_CPT_DROP_PKTS	 (0x18ull) /* [CN10K, .) */
422 #define NIX_STAT_LF_RX_RX_IPSECD_DROP_PKTS (0x19ull) /* [CN10K, .) */
423 
424 #define CGX_RX_PKT_CNT		 (0x0ull) /* [CN9K, CN10K) */
425 #define CGX_RX_OCT_CNT		 (0x1ull) /* [CN9K, CN10K) */
426 #define CGX_RX_PAUSE_PKT_CNT	 (0x2ull) /* [CN9K, CN10K) */
427 #define CGX_RX_PAUSE_OCT_CNT	 (0x3ull) /* [CN9K, CN10K) */
428 #define CGX_RX_DMAC_FILT_PKT_CNT (0x4ull) /* [CN9K, CN10K) */
429 #define CGX_RX_DMAC_FILT_OCT_CNT (0x5ull) /* [CN9K, CN10K) */
430 #define CGX_RX_FIFO_DROP_PKT_CNT (0x6ull) /* [CN9K, CN10K) */
431 #define CGX_RX_FIFO_DROP_OCT_CNT (0x7ull) /* [CN9K, CN10K) */
432 #define CGX_RX_ERR_CNT		 (0x8ull) /* [CN9K, CN10K) */
433 
434 #define CGX_TX_COLLISION_DROP	  (0x0ull)  /* [CN9K, CN10K) */
435 #define CGX_TX_FRAME_DEFER_CNT	  (0x1ull)  /* [CN9K, CN10K) */
436 #define CGX_TX_MULTIPLE_COLLISION (0x2ull)  /* [CN9K, CN10K) */
437 #define CGX_TX_SINGLE_COLLISION	  (0x3ull)  /* [CN9K, CN10K) */
438 #define CGX_TX_OCT_CNT		  (0x4ull)  /* [CN9K, CN10K) */
439 #define CGX_TX_PKT_CNT		  (0x5ull)  /* [CN9K, CN10K) */
440 #define CGX_TX_1_63_PKT_CNT	  (0x6ull)  /* [CN9K, CN10K) */
441 #define CGX_TX_64_PKT_CNT	  (0x7ull)  /* [CN9K, CN10K) */
442 #define CGX_TX_65_127_PKT_CNT	  (0x8ull)  /* [CN9K, CN10K) */
443 #define CGX_TX_128_255_PKT_CNT	  (0x9ull)  /* [CN9K, CN10K) */
444 #define CGX_TX_256_511_PKT_CNT	  (0xaull)  /* [CN9K, CN10K) */
445 #define CGX_TX_512_1023_PKT_CNT	  (0xbull)  /* [CN9K, CN10K) */
446 #define CGX_TX_1024_1518_PKT_CNT  (0xcull)  /* [CN9K, CN10K) */
447 #define CGX_TX_1519_MAX_PKT_CNT	  (0xdull)  /* [CN9K, CN10K) */
448 #define CGX_TX_BCAST_PKTS	  (0xeull)  /* [CN9K, CN10K) */
449 #define CGX_TX_MCAST_PKTS	  (0xfull)  /* [CN9K, CN10K) */
450 #define CGX_TX_UFLOW_PKTS	  (0x10ull) /* [CN9K, CN10K) */
451 #define CGX_TX_PAUSE_PKTS	  (0x11ull) /* [CN9K, CN10K) */
452 
453 #define RPM_MTI_STAT_RX_OCT_CNT		  (0x0ull)  /* [CN10K, .) */
454 #define RPM_MTI_STAT_RX_OCT_RECV_OK	  (0x1ull)  /* [CN10K, .) */
455 #define RPM_MTI_STAT_RX_ALIG_ERR	  (0x2ull)  /* [CN10K, .) */
456 #define RPM_MTI_STAT_RX_CTRL_FRM_RECV	  (0x3ull)  /* [CN10K, .) */
457 #define RPM_MTI_STAT_RX_FRM_LONG	  (0x4ull)  /* [CN10K, .) */
458 #define RPM_MTI_STAT_RX_LEN_ERR		  (0x5ull)  /* [CN10K, .) */
459 #define RPM_MTI_STAT_RX_FRM_RECV	  (0x6ull)  /* [CN10K, .) */
460 #define RPM_MTI_STAT_RX_FRM_SEQ_ERR	  (0x7ull)  /* [CN10K, .) */
461 #define RPM_MTI_STAT_RX_VLAN_OK		  (0x8ull)  /* [CN10K, .) */
462 #define RPM_MTI_STAT_RX_IN_ERR		  (0x9ull)  /* [CN10K, .) */
463 #define RPM_MTI_STAT_RX_IN_UCAST_PKT	  (0xaull)  /* [CN10K, .) */
464 #define RPM_MTI_STAT_RX_IN_MCAST_PKT	  (0xbull)  /* [CN10K, .) */
465 #define RPM_MTI_STAT_RX_IN_BCAST_PKT	  (0xcull)  /* [CN10K, .) */
466 #define RPM_MTI_STAT_RX_DRP_EVENTS	  (0xdull)  /* [CN10K, .) */
467 #define RPM_MTI_STAT_RX_PKT		  (0xeull)  /* [CN10K, .) */
468 #define RPM_MTI_STAT_RX_UNDER_SIZE	  (0xfull)  /* [CN10K, .) */
469 #define RPM_MTI_STAT_RX_1_64_PKT_CNT	  (0x10ull) /* [CN10K, .) */
470 #define RPM_MTI_STAT_RX_65_127_PKT_CNT	  (0x11ull) /* [CN10K, .) */
471 #define RPM_MTI_STAT_RX_128_255_PKT_CNT	  (0x12ull) /* [CN10K, .) */
472 #define RPM_MTI_STAT_RX_256_511_PKT_CNT	  (0x13ull) /* [CN10K, .) */
473 #define RPM_MTI_STAT_RX_512_1023_PKT_CNT  (0x14ull) /* [CN10K, .) */
474 #define RPM_MTI_STAT_RX_1024_1518_PKT_CNT (0x15ull) /* [CN10K, .) */
475 #define RPM_MTI_STAT_RX_1519_MAX_PKT_CNT  (0x16ull) /* [CN10K, .) */
476 #define RPM_MTI_STAT_RX_OVER_SIZE	  (0x17ull) /* [CN10K, .) */
477 #define RPM_MTI_STAT_RX_JABBER		  (0x18ull) /* [CN10K, .) */
478 #define RPM_MTI_STAT_RX_ETH_FRAGS	  (0x19ull) /* [CN10K, .) */
479 #define RPM_MTI_STAT_RX_CBFC_CLASS_0	  (0x1aull) /* [CN10K, .) */
480 #define RPM_MTI_STAT_RX_CBFC_CLASS_1	  (0x1bull) /* [CN10K, .) */
481 #define RPM_MTI_STAT_RX_CBFC_CLASS_2	  (0x1cull) /* [CN10K, .) */
482 #define RPM_MTI_STAT_RX_CBFC_CLASS_3	  (0x1dull) /* [CN10K, .) */
483 #define RPM_MTI_STAT_RX_CBFC_CLASS_4	  (0x1eull) /* [CN10K, .) */
484 #define RPM_MTI_STAT_RX_CBFC_CLASS_5	  (0x1full) /* [CN10K, .) */
485 #define RPM_MTI_STAT_RX_CBFC_CLASS_6	  (0x20ull) /* [CN10K, .) */
486 #define RPM_MTI_STAT_RX_CBFC_CLASS_7	  (0x21ull) /* [CN10K, .) */
487 #define RPM_MTI_STAT_RX_CBFC_CLASS_8	  (0x22ull) /* [CN10K, .) */
488 #define RPM_MTI_STAT_RX_CBFC_CLASS_9	  (0x23ull) /* [CN10K, .) */
489 #define RPM_MTI_STAT_RX_CBFC_CLASS_10	  (0x24ull) /* [CN10K, .) */
490 #define RPM_MTI_STAT_RX_CBFC_CLASS_11	  (0x25ull) /* [CN10K, .) */
491 #define RPM_MTI_STAT_RX_CBFC_CLASS_12	  (0x26ull) /* [CN10K, .) */
492 #define RPM_MTI_STAT_RX_CBFC_CLASS_13	  (0x27ull) /* [CN10K, .) */
493 #define RPM_MTI_STAT_RX_CBFC_CLASS_14	  (0x28ull) /* [CN10K, .) */
494 #define RPM_MTI_STAT_RX_CBFC_CLASS_15	  (0x29ull) /* [CN10K, .) */
495 #define RPM_MTI_STAT_RX_MAC_CONTROL	  (0x2aull) /* [CN10K, .) */
496 
497 #define RPM_MTI_STAT_TX_OCT_CNT		   (0x0ull)  /* [CN10K, .) */
498 #define RPM_MTI_STAT_TX_OCT_TX_OK	   (0x1ull)  /* [CN10K, .) */
499 #define RPM_MTI_STAT_TX_PAUSE_MAC_CTRL	   (0x2ull)  /* [CN10K, .) */
500 #define RPM_MTI_STAT_TX_FRAMES_OK	   (0x3ull)  /* [CN10K, .) */
501 #define RPM_MTI_STAT_TX_VLAN_OK		   (0x4ull)  /* [CN10K, .) */
502 #define RPM_MTI_STAT_TX_OUT_ERR		   (0x5ull)  /* [CN10K, .) */
503 #define RPM_MTI_STAT_TX_UCAST_PKT_CNT	   (0x6ull)  /* [CN10K, .) */
504 #define RPM_MTI_STAT_TX_MCAST_PKT_CNT	   (0x7ull)  /* [CN10K, .) */
505 #define RPM_MTI_STAT_TX_BCAST_PKT_CNT	   (0x8ull)  /* [CN10K, .) */
506 #define RPM_MTI_STAT_TX_1_64_PKT_CNT	   (0x9ull)  /* [CN10K, .) */
507 #define RPM_MTI_STAT_TX_65_127_PKT_CNT	   (0xaull)  /* [CN10K, .) */
508 #define RPM_MTI_STAT_TX_128_255_PKT_CNT	   (0xbull)  /* [CN10K, .) */
509 #define RPM_MTI_STAT_TX_256_511_PKT_CNT	   (0xcull)  /* [CN10K, .) */
510 #define RPM_MTI_STAT_TX_512_1023_PKT_CNT   (0xdull)  /* [CN10K, .) */
511 #define RPM_MTI_STAT_TX_1024_1518_PKT_CNT  (0xeull)  /* [CN10K, .) */
512 #define RPM_MTI_STAT_TX_1519_MAX_PKT_CNT   (0xfull)  /* [CN10K, .) */
513 #define RPM_MTI_STAT_TX_CBFC_CLASS_0	   (0x10ull) /* [CN10K, .) */
514 #define RPM_MTI_STAT_TX_CBFC_CLASS_1	   (0x11ull) /* [CN10K, .) */
515 #define RPM_MTI_STAT_TX_CBFC_CLASS_2	   (0x12ull) /* [CN10K, .) */
516 #define RPM_MTI_STAT_TX_CBFC_CLASS_3	   (0x13ull) /* [CN10K, .) */
517 #define RPM_MTI_STAT_TX_CBFC_CLASS_4	   (0x14ull) /* [CN10K, .) */
518 #define RPM_MTI_STAT_TX_CBFC_CLASS_5	   (0x15ull) /* [CN10K, .) */
519 #define RPM_MTI_STAT_TX_CBFC_CLASS_6	   (0x16ull) /* [CN10K, .) */
520 #define RPM_MTI_STAT_TX_CBFC_CLASS_7	   (0x17ull) /* [CN10K, .) */
521 #define RPM_MTI_STAT_TX_CBFC_CLASS_8	   (0x18ull) /* [CN10K, .) */
522 #define RPM_MTI_STAT_TX_CBFC_CLASS_9	   (0x19ull) /* [CN10K, .) */
523 #define RPM_MTI_STAT_TX_CBFC_CLASS_10	   (0x1aull) /* [CN10K, .) */
524 #define RPM_MTI_STAT_TX_CBFC_CLASS_11	   (0x1bull) /* [CN10K, .) */
525 #define RPM_MTI_STAT_TX_CBFC_CLASS_12	   (0x1cull) /* [CN10K, .) */
526 #define RPM_MTI_STAT_TX_CBFC_CLASS_13	   (0x1dull) /* [CN10K, .) */
527 #define RPM_MTI_STAT_TX_CBFC_CLASS_14	   (0x1eull) /* [CN10K, .) */
528 #define RPM_MTI_STAT_TX_CBFC_CLASS_15	   (0x1full) /* [CN10K, .) */
529 #define RPM_MTI_STAT_TX_MAC_CONTROL_FRAMES (0x20ull) /* [CN10K, .) */
530 #define RPM_MTI_STAT_TX_PKT_CNT		   (0x21ull) /* [CN10K, .) */
531 
532 #define NIX_SQOPERR_SQ_OOR	     (0x0ull)
533 #define NIX_SQOPERR_SQ_CTX_FAULT     (0x1ull)
534 #define NIX_SQOPERR_SQ_CTX_POISON    (0x2ull)
535 #define NIX_SQOPERR_SQ_DISABLED	     (0x3ull)
536 #define NIX_SQOPERR_MAX_SQE_SIZE_ERR (0x4ull)
537 #define NIX_SQOPERR_SQE_OFLOW	     (0x5ull)
538 #define NIX_SQOPERR_SQB_NULL	     (0x6ull)
539 #define NIX_SQOPERR_SQB_FAULT	     (0x7ull)
540 #define NIX_SQOPERR_SQE_SIZEM1_ZERO  (0x8ull) /* [CN10K, .) */
541 
542 #define NIX_SQINT_LMT_ERR	 (0x0ull)
543 #define NIX_SQINT_MNQ_ERR	 (0x1ull)
544 #define NIX_SQINT_SEND_ERR	 (0x2ull)
545 #define NIX_SQINT_SQB_ALLOC_FAIL (0x3ull)
546 
547 #define NIX_SEND_STATUS_GOOD		   (0x0ull)
548 #define NIX_SEND_STATUS_SQ_CTX_FAULT	   (0x1ull)
549 #define NIX_SEND_STATUS_SQ_CTX_POISON	   (0x2ull)
550 #define NIX_SEND_STATUS_SQB_FAULT	   (0x3ull)
551 #define NIX_SEND_STATUS_SQB_POISON	   (0x4ull)
552 #define NIX_SEND_STATUS_SEND_HDR_ERR	   (0x5ull)
553 #define NIX_SEND_STATUS_SEND_EXT_ERR	   (0x6ull)
554 #define NIX_SEND_STATUS_JUMP_FAULT	   (0x7ull)
555 #define NIX_SEND_STATUS_JUMP_POISON	   (0x8ull)
556 #define NIX_SEND_STATUS_SEND_CRC_ERR	   (0x10ull)
557 #define NIX_SEND_STATUS_SEND_IMM_ERR	   (0x11ull)
558 #define NIX_SEND_STATUS_SEND_SG_ERR	   (0x12ull)
559 #define NIX_SEND_STATUS_SEND_MEM_ERR	   (0x13ull)
560 #define NIX_SEND_STATUS_INVALID_SUBDC	   (0x14ull)
561 #define NIX_SEND_STATUS_SUBDC_ORDER_ERR	   (0x15ull)
562 #define NIX_SEND_STATUS_DATA_FAULT	   (0x16ull)
563 #define NIX_SEND_STATUS_DATA_POISON	   (0x17ull)
564 #define NIX_SEND_STATUS_NPC_DROP_ACTION	   (0x20ull)
565 #define NIX_SEND_STATUS_LOCK_VIOL	   (0x21ull)
566 #define NIX_SEND_STATUS_NPC_UCAST_CHAN_ERR (0x22ull)
567 #define NIX_SEND_STATUS_NPC_MCAST_CHAN_ERR (0x23ull)
568 #define NIX_SEND_STATUS_NPC_MCAST_ABORT	   (0x24ull)
569 #define NIX_SEND_STATUS_NPC_VTAG_PTR_ERR   (0x25ull)
570 #define NIX_SEND_STATUS_NPC_VTAG_SIZE_ERR  (0x26ull)
571 #define NIX_SEND_STATUS_SEND_MEM_FAULT	   (0x27ull)
572 #define NIX_SEND_STATUS_SEND_STATS_ERR	   (0x28ull)
573 
574 #define NIX_SENDSTATSALG_NOP			     (0x0ull)
575 #define NIX_SENDSTATSALG_ADD_PKT_CNT		     (0x1ull)
576 #define NIX_SENDSTATSALG_ADD_BYTE_CNT		     (0x2ull)
577 #define NIX_SENDSTATSALG_ADD_PKT_BYTE_CNT	     (0x3ull)
578 #define NIX_SENDSTATSALG_UPDATE_PKT_CNT_ON_DROP	     (0x4ull)
579 #define NIX_SENDSTATSALG_UPDATE_BYTE_CNT_ON_DROP     (0x5ull)
580 #define NIX_SENDSTATSALG_UPDATE_PKT_BYTE_CNT_ON_DROP (0x6ull)
581 
582 #define NIX_SENDMEMDSZ_B64 (0x0ull)
583 #define NIX_SENDMEMDSZ_B32 (0x1ull)
584 #define NIX_SENDMEMDSZ_B16 (0x2ull)
585 #define NIX_SENDMEMDSZ_B8  (0x3ull)
586 
587 #define NIX_SENDMEMALG_SET	(0x0ull)
588 #define NIX_SENDMEMALG_SETTSTMP (0x1ull)
589 #define NIX_SENDMEMALG_SETRSLT	(0x2ull)
590 #define NIX_SENDMEMALG_ADD	(0x8ull)
591 #define NIX_SENDMEMALG_SUB	(0x9ull)
592 #define NIX_SENDMEMALG_ADDLEN	(0xaull)
593 #define NIX_SENDMEMALG_SUBLEN	(0xbull)
594 #define NIX_SENDMEMALG_ADDMBUF	(0xcull)
595 #define NIX_SENDMEMALG_SUBMBUF	(0xdull)
596 
597 #define NIX_SUBDC_NOP		(0x0ull)
598 #define NIX_SUBDC_EXT		(0x1ull)
599 #define NIX_SUBDC_CRC		(0x2ull)
600 #define NIX_SUBDC_IMM		(0x3ull)
601 #define NIX_SUBDC_SG		(0x4ull)
602 #define NIX_SUBDC_MEM		(0x5ull)
603 #define NIX_SUBDC_JUMP		(0x6ull)
604 #define NIX_SUBDC_WORK		(0x7ull)
605 #define NIX_SUBDC_SG2		(0x8ull) /* [CN10K, .) */
606 #define NIX_SUBDC_AGE_AND_STATS (0x9ull) /* [CN10K, .) */
607 #define NIX_SUBDC_SOD		(0xfull)
608 
609 #define NIX_STYPE_STF (0x0ull)
610 #define NIX_STYPE_STT (0x1ull)
611 #define NIX_STYPE_STP (0x2ull)
612 
613 #define NIX_RX_ACTIONOP_DROP	     (0x0ull)
614 #define NIX_RX_ACTIONOP_UCAST	     (0x1ull)
615 #define NIX_RX_ACTIONOP_UCAST_IPSEC  (0x2ull)
616 #define NIX_RX_ACTIONOP_MCAST	     (0x3ull)
617 #define NIX_RX_ACTIONOP_RSS	     (0x4ull)
618 #define NIX_RX_ACTIONOP_PF_FUNC_DROP (0x5ull)
619 #define NIX_RX_ACTIONOP_MIRROR	     (0x6ull)
620 
621 #define NIX_RX_VTAGACTION_VTAG0_RELPTR (0x0ull)
622 #define NIX_RX_VTAGACTION_VTAG1_RELPTR (0x4ull)
623 #define NIX_RX_VTAGACTION_VTAG_VALID   (0x1ull)
624 #define NIX_TX_VTAGACTION_VTAG0_RELPTR (sizeof(struct nix_inst_hdr_s) + 2 * 6)
625 #define NIX_TX_VTAGACTION_VTAG1_RELPTR                                         \
626 	(sizeof(struct nix_inst_hdr_s) + 2 * 6 + 4)
627 #define NIX_RQINT_DROP (0x0ull)
628 #define NIX_RQINT_RED  (0x1ull)
629 #define NIX_RQINT_R2   (0x2ull)
630 #define NIX_RQINT_R3   (0x3ull)
631 #define NIX_RQINT_R4   (0x4ull)
632 #define NIX_RQINT_R5   (0x5ull)
633 #define NIX_RQINT_R6   (0x6ull)
634 #define NIX_RQINT_R7   (0x7ull)
635 
636 #define NIX_MAXSQESZ_W16 (0x0ull)
637 #define NIX_MAXSQESZ_W8	 (0x1ull)
638 
639 #define NIX_LSOALG_NOP	      (0x0ull)
640 #define NIX_LSOALG_ADD_SEGNUM (0x1ull)
641 #define NIX_LSOALG_ADD_PAYLEN (0x2ull)
642 #define NIX_LSOALG_ADD_OFFSET (0x3ull)
643 #define NIX_LSOALG_TCP_FLAGS  (0x4ull)
644 
645 #define NIX_MNQERR_SQ_CTX_FAULT	    (0x0ull)
646 #define NIX_MNQERR_SQ_CTX_POISON    (0x1ull)
647 #define NIX_MNQERR_SQB_FAULT	    (0x2ull)
648 #define NIX_MNQERR_SQB_POISON	    (0x3ull)
649 #define NIX_MNQERR_TOTAL_ERR	    (0x4ull)
650 #define NIX_MNQERR_LSO_ERR	    (0x5ull)
651 #define NIX_MNQERR_CQ_QUERY_ERR	    (0x6ull)
652 #define NIX_MNQERR_MAX_SQE_SIZE_ERR (0x7ull)
653 #define NIX_MNQERR_MAXLEN_ERR	    (0x8ull)
654 #define NIX_MNQERR_SQE_SIZEM1_ZERO  (0x9ull)
655 
656 #define NIX_MDTYPE_RSVD	 (0x0ull)
657 #define NIX_MDTYPE_FLUSH (0x1ull)
658 #define NIX_MDTYPE_PMD	 (0x2ull)
659 
660 #define NIX_NDC_TX_PORT_LMT (0x0ull)
661 #define NIX_NDC_TX_PORT_ENQ (0x1ull)
662 #define NIX_NDC_TX_PORT_MNQ (0x2ull)
663 #define NIX_NDC_TX_PORT_DEQ (0x3ull)
664 #define NIX_NDC_TX_PORT_DMA (0x4ull)
665 #define NIX_NDC_TX_PORT_XQE (0x5ull)
666 
667 #define NIX_NDC_RX_PORT_AQ   (0x0ull)
668 #define NIX_NDC_RX_PORT_CQ   (0x1ull)
669 #define NIX_NDC_RX_PORT_CINT (0x2ull)
670 #define NIX_NDC_RX_PORT_MC   (0x3ull)
671 #define NIX_NDC_RX_PORT_PKT  (0x4ull)
672 #define NIX_NDC_RX_PORT_RQ   (0x5ull)
673 
674 #define NIX_RE_OPCODE_RE_NONE	   (0x0ull)
675 #define NIX_RE_OPCODE_RE_PARTIAL   (0x1ull)
676 #define NIX_RE_OPCODE_RE_JABBER	   (0x2ull)
677 #define NIX_RE_OPCODE_RE_FCS	   (0x7ull)
678 #define NIX_RE_OPCODE_RE_FCS_RCV   (0x8ull)
679 #define NIX_RE_OPCODE_RE_TERMINATE (0x9ull)
680 #define NIX_RE_OPCODE_RE_RX_CTL	   (0xbull)
681 #define NIX_RE_OPCODE_RE_SKIP	   (0xcull)
682 #define NIX_RE_OPCODE_RE_DMAPKT	   (0xfull)
683 #define NIX_RE_OPCODE_UNDERSIZE	   (0x10ull)
684 #define NIX_RE_OPCODE_OVERSIZE	   (0x11ull)
685 #define NIX_RE_OPCODE_OL2_LENMISM  (0x12ull)
686 
687 #define NIX_REDALG_STD	   (0x0ull)
688 #define NIX_REDALG_SEND	   (0x1ull)
689 #define NIX_REDALG_STALL   (0x2ull)
690 #define NIX_REDALG_DISCARD (0x3ull)
691 
692 #define NIX_RX_BAND_PROF_ACTIONRESULT_PASS (0x0ull) /* [CN10K, .) */
693 #define NIX_RX_BAND_PROF_ACTIONRESULT_DROP (0x1ull) /* [CN10K, .) */
694 #define NIX_RX_BAND_PROF_ACTIONRESULT_RED  (0x2ull) /* [CN10K, .) */
695 
696 #define NIX_RX_BAND_PROF_LAYER_LEAF    (0x0ull) /* [CN10K, .) */
697 #define NIX_RX_BAND_PROF_LAYER_INVALID (0x1ull) /* [CN10K, .) */
698 #define NIX_RX_BAND_PROF_LAYER_MIDDLE  (0x2ull) /* [CN10K, .) */
699 #define NIX_RX_BAND_PROF_LAYER_TOP     (0x3ull) /* [CN10K, .) */
700 #define NIX_RX_BAND_PROF_LAYER_MAX     (0x4ull) /* [CN10K, .) */
701 
702 #define NIX_RX_BAND_PROF_PC_MODE_VLAN (0x0ull) /* [CN10K, .) */
703 #define NIX_RX_BAND_PROF_PC_MODE_DSCP (0x1ull) /* [CN10K, .) */
704 #define NIX_RX_BAND_PROF_PC_MODE_GEN  (0x2ull) /* [CN10K, .) */
705 #define NIX_RX_BAND_PROF_PC_MODE_RSVD (0x3ull) /* [CN10K, .) */
706 
707 #define NIX_RX_COLORRESULT_GREEN  (0x0ull) /* [CN10K, .) */
708 #define NIX_RX_COLORRESULT_YELLOW (0x1ull) /* [CN10K, .) */
709 #define NIX_RX_COLORRESULT_RED	  (0x2ull) /* [CN10K, .) */
710 
711 #define NIX_RX_MCOP_RQ	(0x0ull)
712 #define NIX_RX_MCOP_RSS (0x1ull)
713 
714 #define NIX_RX_PERRCODE_NPC_RESULT_ERR (0x2ull)
715 #define NIX_RX_PERRCODE_MCAST_FAULT    (0x4ull)
716 #define NIX_RX_PERRCODE_MIRROR_FAULT   (0x5ull)
717 #define NIX_RX_PERRCODE_MCAST_POISON   (0x6ull)
718 #define NIX_RX_PERRCODE_MIRROR_POISON  (0x7ull)
719 #define NIX_RX_PERRCODE_DATA_FAULT     (0x8ull)
720 #define NIX_RX_PERRCODE_MEMOUT	       (0x9ull)
721 #define NIX_RX_PERRCODE_BUFS_OFLOW     (0xaull)
722 #define NIX_RX_PERRCODE_OL3_LEN	       (0x10ull)
723 #define NIX_RX_PERRCODE_OL4_LEN	       (0x11ull)
724 #define NIX_RX_PERRCODE_OL4_CHK	       (0x12ull)
725 #define NIX_RX_PERRCODE_OL4_PORT       (0x13ull)
726 #define NIX_RX_PERRCODE_IL3_LEN	       (0x20ull)
727 #define NIX_RX_PERRCODE_IL4_LEN	       (0x21ull)
728 #define NIX_RX_PERRCODE_IL4_CHK	       (0x22ull)
729 #define NIX_RX_PERRCODE_IL4_PORT       (0x23ull)
730 
731 #define NIX_SA_ALG_NON_MS     (0x0ull) /* [CN10K, .) */
732 #define NIX_SA_ALG_MS_CISCO   (0x1ull) /* [CN10K, .) */
733 #define NIX_SA_ALG_MS_VIPTELA (0x2ull) /* [CN10K, .) */
734 
735 #define NIX_SENDCRCALG_CRC32  (0x0ull)
736 #define NIX_SENDCRCALG_CRC32C (0x1ull)
737 #define NIX_SENDCRCALG_ONES16 (0x2ull)
738 
739 #define NIX_SENDL3TYPE_NONE	 (0x0ull)
740 #define NIX_SENDL3TYPE_IP4	 (0x2ull)
741 #define NIX_SENDL3TYPE_IP4_CKSUM (0x3ull)
742 #define NIX_SENDL3TYPE_IP6	 (0x4ull)
743 
744 #define NIX_SENDL4TYPE_NONE	  (0x0ull)
745 #define NIX_SENDL4TYPE_TCP_CKSUM  (0x1ull)
746 #define NIX_SENDL4TYPE_SCTP_CKSUM (0x2ull)
747 #define NIX_SENDL4TYPE_UDP_CKSUM  (0x3ull)
748 
749 #define NIX_SENDLDTYPE_LDD  (0x0ull)
750 #define NIX_SENDLDTYPE_LDT  (0x1ull)
751 #define NIX_SENDLDTYPE_LDWB (0x2ull)
752 
753 #define NIX_XQESZ_W64 (0x0ull)
754 #define NIX_XQESZ_W16 (0x1ull)
755 
756 #define NIX_XQE_TYPE_INVALID   (0x0ull)
757 #define NIX_XQE_TYPE_RX	       (0x1ull)
758 #define NIX_XQE_TYPE_RX_IPSECS (0x2ull)
759 #define NIX_XQE_TYPE_RX_IPSECH (0x3ull)
760 #define NIX_XQE_TYPE_RX_IPSECD (0x4ull)
761 #define NIX_XQE_TYPE_RX_VWQE   (0x5ull) /* [CN10K, .) */
762 #define NIX_XQE_TYPE_RES_6     (0x6ull)
763 #define NIX_XQE_TYPE_RES_7     (0x7ull)
764 #define NIX_XQE_TYPE_SEND      (0x8ull)
765 #define NIX_XQE_TYPE_RES_9     (0x9ull)
766 #define NIX_XQE_TYPE_RES_A     (0xAull)
767 #define NIX_XQE_TYPE_RES_B     (0xBull)
768 #define NIX_XQE_TYPE_RES_C     (0xCull)
769 #define NIX_XQE_TYPE_RES_D     (0xDull)
770 #define NIX_XQE_TYPE_RES_E     (0xEull)
771 #define NIX_XQE_TYPE_RES_F     (0xFull)
772 
773 #define NIX_TX_VTAGOP_NOP     (0x0ull)
774 #define NIX_TX_VTAGOP_INSERT  (0x1ull)
775 #define NIX_TX_VTAGOP_REPLACE (0x2ull)
776 
777 #define NIX_VTAGSIZE_T4 (0x0ull)
778 #define NIX_VTAGSIZE_T8 (0x1ull)
779 
780 #define NIX_TXLAYER_OL3 (0x0ull)
781 #define NIX_TXLAYER_OL4 (0x1ull)
782 #define NIX_TXLAYER_IL3 (0x2ull)
783 #define NIX_TXLAYER_IL4 (0x3ull)
784 
785 #define NIX_TX_ACTIONOP_DROP	      (0x0ull)
786 #define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
787 #define NIX_TX_ACTIONOP_UCAST_CHAN    (0x2ull)
788 #define NIX_TX_ACTIONOP_MCAST	      (0x3ull)
789 #define NIX_TX_ACTIONOP_DROP_VIOL     (0x5ull)
790 
791 #define NIX_AQ_COMP_NOTDONE	   (0x0ull)
792 #define NIX_AQ_COMP_GOOD	   (0x1ull)
793 #define NIX_AQ_COMP_SWERR	   (0x2ull)
794 #define NIX_AQ_COMP_CTX_POISON	   (0x3ull)
795 #define NIX_AQ_COMP_CTX_FAULT	   (0x4ull)
796 #define NIX_AQ_COMP_LOCKERR	   (0x5ull)
797 #define NIX_AQ_COMP_SQB_ALLOC_FAIL (0x6ull)
798 
799 #define NIX_AF_INT_VEC_RVU     (0x0ull)
800 #define NIX_AF_INT_VEC_GEN     (0x1ull)
801 #define NIX_AF_INT_VEC_AQ_DONE (0x2ull)
802 #define NIX_AF_INT_VEC_AF_ERR  (0x3ull)
803 #define NIX_AF_INT_VEC_POISON  (0x4ull)
804 
805 #define NIX_AQINT_GEN_RX_MCAST_DROP  (0x0ull)
806 #define NIX_AQINT_GEN_RX_MIRROR_DROP (0x1ull)
807 #define NIX_AQINT_GEN_TL1_DRAIN	     (0x3ull)
808 #define NIX_AQINT_GEN_SMQ_FLUSH_DONE (0x4ull)
809 
810 #define NIX_AQ_INSTOP_NOP    (0x0ull)
811 #define NIX_AQ_INSTOP_INIT   (0x1ull)
812 #define NIX_AQ_INSTOP_WRITE  (0x2ull)
813 #define NIX_AQ_INSTOP_READ   (0x3ull)
814 #define NIX_AQ_INSTOP_LOCK   (0x4ull)
815 #define NIX_AQ_INSTOP_UNLOCK (0x5ull)
816 
817 #define NIX_AQ_CTYPE_RQ	       (0x0ull)
818 #define NIX_AQ_CTYPE_SQ	       (0x1ull)
819 #define NIX_AQ_CTYPE_CQ	       (0x2ull)
820 #define NIX_AQ_CTYPE_MCE       (0x3ull)
821 #define NIX_AQ_CTYPE_RSS       (0x4ull)
822 #define NIX_AQ_CTYPE_DYNO      (0x5ull)
823 #define NIX_AQ_CTYPE_BAND_PROF (0x6ull) /* [CN10K, .) */
824 
825 #define NIX_COLORRESULT_GREEN	 (0x0ull)
826 #define NIX_COLORRESULT_YELLOW	 (0x1ull)
827 #define NIX_COLORRESULT_RED_SEND (0x2ull)
828 #define NIX_COLORRESULT_RED_DROP (0x3ull)
829 
830 #define NIX_CHAN_LBKX_CHX(a, b)                                                \
831 	(0x000ull | ((uint64_t)(a) << 8) | (uint64_t)(b))
832 #define NIX_CHAN_CPT_CH_END   (0x4ffull) /* [CN10K, .) */
833 #define NIX_CHAN_CPT_CH_START (0x800ull) /* [CN10K, .) */
834 #define NIX_CHAN_R4	      (0x400ull) /* [CN9K, CN10K) */
835 #define NIX_CHAN_R5	      (0x500ull)
836 #define NIX_CHAN_R6	      (0x600ull)
837 #define NIX_CHAN_SDP_CH_END   (0x7ffull)
838 #define NIX_CHAN_SDP_CH_START (0x700ull)
839 /* [CN9K, CN10K) */
840 #define NIX_CHAN_CGXX_LMACX_CHX(a, b, c)                                       \
841 	(0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c))
842 /* [CN10K, .) */
843 #define NIX_CHAN_RPMX_LMACX_CHX(a, b, c)                                       \
844 	(0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c))
845 
846 /* The mask is to extract lower 10-bits of channel number
847  * which CPT will pass to X2P.
848  */
849 #define NIX_CHAN_CPT_X2P_MASK (0x3ffull)
850 
851 #define NIX_INTF_SDP  (0x4ull)
852 #define NIX_INTF_CGX0 (0x0ull) /* [CN9K, CN10K) */
853 #define NIX_INTF_CGX1 (0x1ull) /* [CN9K, CN10K) */
854 #define NIX_INTF_CGX2 (0x2ull) /* [CN9K, CN10K) */
855 #define NIX_INTF_RPM0 (0x0ull) /* [CN10K, .) */
856 #define NIX_INTF_RPM1 (0x1ull) /* [CN10K, .) */
857 #define NIX_INTF_RPM2 (0x2ull) /* [CN10K, .) */
858 #define NIX_INTF_LBK0 (0x3ull)
859 #define NIX_INTF_CPT0 (0x5ull) /* [CN10K, .) */
860 
861 #define NIX_CQERRINT_DOOR_ERR  (0x0ull)
862 #define NIX_CQERRINT_WR_FULL   (0x1ull)
863 #define NIX_CQERRINT_CQE_FAULT (0x2ull)
864 
865 #define NIX_LINK_SDP (0xdull) /* [CN10K, .) */
866 #define NIX_LINK_CPT (0xeull) /* [CN10K, .) */
867 #define NIX_LINK_MC  (0xfull) /* [CN10K, .) */
868 /* [CN10K, .) */
869 #define NIX_LINK_RPMX_LMACX(a, b)                                              \
870 	(0x00ull | ((uint64_t)(a) << 2) | (uint64_t)(b))
871 #define NIX_LINK_LBK0 (0xcull)
872 
873 #define NIX_LF_INT_VEC_GINT	  (0x80ull)
874 #define NIX_LF_INT_VEC_ERR_INT	  (0x81ull)
875 #define NIX_LF_INT_VEC_POISON	  (0x82ull)
876 #define NIX_LF_INT_VEC_QINT_END	  (0x3full)
877 #define NIX_LF_INT_VEC_QINT_START (0x0ull)
878 #define NIX_LF_INT_VEC_CINT_END	  (0x7full)
879 #define NIX_LF_INT_VEC_CINT_START (0x40ull)
880 
881 #define NIX_INTF_RX (0x0ull)
882 #define NIX_INTF_TX (0x1ull)
883 
884 /* Enums definitions */
885 
886 /* Structures definitions */
887 
888 /* NIX aging and send stats subdescriptor structure */
889 struct nix_age_and_send_stats_s {
890 	uint64_t threshold : 29;
891 	uint64_t latency_drop : 1;
892 	uint64_t aging : 1;
893 	uint64_t wmem : 1;
894 	uint64_t ooffset : 12;
895 	uint64_t ioffset : 12;
896 	uint64_t sel : 1;
897 	uint64_t alg : 3;
898 	uint64_t subdc : 4;
899 	uint64_t addr : 64; /* W1 */
900 };
901 
902 /* NIX admin queue instruction structure */
903 struct nix_aq_inst_s {
904 	uint64_t op : 4;
905 	uint64_t ctype : 4;
906 	uint64_t lf : 7;
907 	uint64_t rsvd_23_15 : 9;
908 	uint64_t cindex : 20;
909 	uint64_t rsvd_62_44 : 19;
910 	uint64_t doneint : 1;
911 	uint64_t res_addr : 64; /* W1 */
912 };
913 
914 /* NIX admin queue result structure */
915 struct nix_aq_res_s {
916 	uint64_t op : 4;
917 	uint64_t ctype : 4;
918 	uint64_t compcode : 8;
919 	uint64_t doneint : 1;
920 	uint64_t rsvd_63_17 : 47;
921 	uint64_t rsvd_127_64 : 64; /* W1 */
922 };
923 
924 /* NIX bandwidth profile structure */
925 struct nix_band_prof_s {
926 	uint64_t pc_mode : 2;
927 	uint64_t icolor : 2;
928 	uint64_t tnl_ena : 1;
929 	uint64_t rsvd_7_5 : 3;
930 	uint64_t peir_exponent : 5;
931 	uint64_t rsvd_15_13 : 3;
932 	uint64_t pebs_exponent : 5;
933 	uint64_t rsvd_23_21 : 3;
934 	uint64_t cir_exponent : 5;
935 	uint64_t rsvd_31_29 : 3;
936 	uint64_t cbs_exponent : 5;
937 	uint64_t rsvd_39_37 : 3;
938 	uint64_t peir_mantissa : 8;
939 	uint64_t pebs_mantissa : 8;
940 	uint64_t cir_mantissa : 8;
941 	uint64_t cbs_mantissa : 8;
942 	uint64_t lmode : 1;
943 	uint64_t l_sellect : 3;
944 	uint64_t rdiv : 4;
945 	uint64_t adjust_exponent : 5;
946 	uint64_t rsvd_86_85 : 2;
947 	uint64_t adjust_mantissa : 9;
948 	uint64_t gc_action : 2;
949 	uint64_t yc_action : 2;
950 	uint64_t rc_action : 2;
951 	uint64_t meter_algo : 2;
952 	uint64_t band_prof_id : 7;
953 	uint64_t rsvd_118_111 : 8;
954 	uint64_t hl_en : 1;
955 	uint64_t rsvd_127_120 : 8;
956 	uint64_t ts : 48;
957 	uint64_t rsvd_191_176 : 16;
958 	uint64_t pe_accum : 32;
959 	uint64_t c_accum : 32;
960 	uint64_t green_pkt_pass : 48;
961 	uint64_t rsvd_319_304 : 16;
962 	uint64_t yellow_pkt_pass : 48;
963 	uint64_t rsvd_383_368 : 16;
964 	uint64_t red_pkt_pass : 48;
965 	uint64_t rsvd_447_432 : 16;
966 	uint64_t green_octs_pass : 48;
967 	uint64_t rsvd_511_496 : 16;
968 	uint64_t yellow_octs_pass : 48;
969 	uint64_t rsvd_575_560 : 16;
970 	uint64_t red_octs_pass : 48;
971 	uint64_t rsvd_639_624 : 16;
972 	uint64_t green_pkt_drop : 48;
973 	uint64_t rsvd_703_688 : 16;
974 	uint64_t yellow_pkt_drop : 48;
975 	uint64_t rsvd_767_752 : 16;
976 	uint64_t red_pkt_drop : 48;
977 	uint64_t rsvd_831_816 : 16;
978 	uint64_t green_octs_drop : 48;
979 	uint64_t rsvd_895_880 : 16;
980 	uint64_t yellow_octs_drop : 48;
981 	uint64_t rsvd_959_944 : 16;
982 	uint64_t red_octs_drop : 48;
983 	uint64_t rsvd_1023_1008 : 16;
984 };
985 
986 /* NIX completion interrupt context hardware structure */
987 struct nix_cint_hw_s {
988 	uint64_t ecount : 32;
989 	uint64_t qcount : 16;
990 	uint64_t intr : 1;
991 	uint64_t ena : 1;
992 	uint64_t timer_idx : 8;
993 	uint64_t rsvd_63_58 : 6;
994 	uint64_t ecount_wait : 32;
995 	uint64_t qcount_wait : 16;
996 	uint64_t time_wait : 8;
997 	uint64_t rsvd_127_120 : 8;
998 };
999 
1000 /* NIX completion queue entry header structure */
1001 struct nix_cqe_hdr_s {
1002 	uint64_t tag : 32;
1003 	uint64_t q : 20;
1004 	uint64_t rsvd_57_52 : 6;
1005 	uint64_t node : 2;
1006 	uint64_t cqe_type : 4;
1007 };
1008 
1009 /* NIX completion queue context structure */
1010 struct nix_cq_ctx_s {
1011 	uint64_t base : 64; /* W0 */
1012 	uint64_t rsvd_67_64 : 4;
1013 	uint64_t bp_ena : 1;
1014 	uint64_t rsvd_71_69 : 3;
1015 	uint64_t bpid : 9;
1016 	uint64_t rsvd_83_81 : 3;
1017 	uint64_t qint_idx : 7;
1018 	uint64_t cq_err : 1;
1019 	uint64_t cint_idx : 7;
1020 	uint64_t avg_con : 9;
1021 	uint64_t wrptr : 20;
1022 	uint64_t tail : 20;
1023 	uint64_t head : 20;
1024 	uint64_t avg_level : 8;
1025 	uint64_t update_time : 16;
1026 	uint64_t bp : 8;
1027 	uint64_t drop : 8;
1028 	uint64_t drop_ena : 1;
1029 	uint64_t ena : 1;
1030 	uint64_t rsvd_211_210 : 2;
1031 	uint64_t substream : 20;
1032 	uint64_t caching : 1;
1033 	uint64_t rsvd_235_233 : 3;
1034 	uint64_t qsize : 4;
1035 	uint64_t cq_err_int : 8;
1036 	uint64_t cq_err_int_ena : 8;
1037 };
1038 
1039 /* NIX instruction header structure */
1040 struct nix_inst_hdr_s {
1041 	uint64_t pf_func : 16;
1042 	uint64_t sq : 20;
1043 	uint64_t rsvd_63_36 : 28;
1044 };
1045 
1046 /* NIX i/o virtual address structure */
1047 struct nix_iova_s {
1048 	uint64_t addr : 64; /* W0 */
1049 };
1050 
1051 /* NIX IPsec dynamic ordering counter structure */
1052 struct nix_ipsec_dyno_s {
1053 	uint32_t count : 32; /* W0 */
1054 };
1055 
1056 /* NIX memory value structure */
1057 struct nix_mem_result_s {
1058 	uint64_t v : 1;
1059 	uint64_t color : 2;
1060 	uint64_t rsvd_63_3 : 61;
1061 };
1062 
1063 /* NIX statistics operation write data structure */
1064 struct nix_op_q_wdata_s {
1065 	uint64_t rsvd_31_0 : 32;
1066 	uint64_t q : 20;
1067 	uint64_t rsvd_63_52 : 12;
1068 };
1069 
1070 /* NIX queue interrupt context hardware structure */
1071 struct nix_qint_hw_s {
1072 	uint32_t count : 22;
1073 	uint32_t rsvd_30_22 : 9;
1074 	uint32_t ena : 1;
1075 };
1076 
1077 /* [CN10K, .) NIX receive queue context structure */
1078 struct nix_cn10k_rq_ctx_hw_s {
1079 	uint64_t ena : 1;
1080 	uint64_t sso_ena : 1;
1081 	uint64_t ipsech_ena : 1;
1082 	uint64_t ena_wqwd : 1;
1083 	uint64_t cq : 20;
1084 	uint64_t rsvd_36_24 : 13;
1085 	uint64_t lenerr_dis : 1;
1086 	uint64_t csum_il4_dis : 1;
1087 	uint64_t csum_ol4_dis : 1;
1088 	uint64_t len_il4_dis : 1;
1089 	uint64_t len_il3_dis : 1;
1090 	uint64_t len_ol4_dis : 1;
1091 	uint64_t len_ol3_dis : 1;
1092 	uint64_t wqe_aura : 20;
1093 	uint64_t spb_aura : 20;
1094 	uint64_t lpb_aura : 20;
1095 	uint64_t sso_grp : 10;
1096 	uint64_t sso_tt : 2;
1097 	uint64_t pb_caching : 2;
1098 	uint64_t wqe_caching : 1;
1099 	uint64_t xqe_drop_ena : 1;
1100 	uint64_t spb_drop_ena : 1;
1101 	uint64_t lpb_drop_ena : 1;
1102 	uint64_t pb_stashing : 1;
1103 	uint64_t ipsecd_drop_en : 1;
1104 	uint64_t chi_ena : 1;
1105 	uint64_t rsvd_127_125 : 3;
1106 	uint64_t band_prof_id : 10;
1107 	uint64_t rsvd_138 : 1;
1108 	uint64_t policer_ena : 1;
1109 	uint64_t spb_sizem1 : 6;
1110 	uint64_t wqe_skip : 2;
1111 	uint64_t spb_high_sizem1 : 3;
1112 	uint64_t spb_ena : 1;
1113 	uint64_t lpb_sizem1 : 12;
1114 	uint64_t first_skip : 7;
1115 	uint64_t rsvd_171 : 1;
1116 	uint64_t later_skip : 6;
1117 	uint64_t xqe_imm_size : 6;
1118 	uint64_t rsvd_189_184 : 6;
1119 	uint64_t xqe_imm_copy : 1;
1120 	uint64_t xqe_hdr_split : 1;
1121 	uint64_t xqe_drop : 8;
1122 	uint64_t xqe_pass : 8;
1123 	uint64_t wqe_pool_drop : 8;
1124 	uint64_t wqe_pool_pass : 8;
1125 	uint64_t spb_aura_drop : 8;
1126 	uint64_t spb_aura_pass : 8;
1127 	uint64_t spb_pool_drop : 8;
1128 	uint64_t spb_pool_pass : 8;
1129 	uint64_t lpb_aura_drop : 8;
1130 	uint64_t lpb_aura_pass : 8;
1131 	uint64_t lpb_pool_drop : 8;
1132 	uint64_t lpb_pool_pass : 8;
1133 	uint64_t rsvd_319_288 : 32;
1134 	uint64_t ltag : 24;
1135 	uint64_t good_utag : 8;
1136 	uint64_t bad_utag : 8;
1137 	uint64_t flow_tagw : 6;
1138 	uint64_t ipsec_vwqe : 1;
1139 	uint64_t vwqe_ena : 1;
1140 	uint64_t vtime_wait : 8;
1141 	uint64_t max_vsize_exp : 4;
1142 	uint64_t vwqe_skip : 2;
1143 	uint64_t rsvd_383_382 : 2;
1144 	uint64_t octs : 48;
1145 	uint64_t rsvd_447_432 : 16;
1146 	uint64_t pkts : 48;
1147 	uint64_t rsvd_511_496 : 16;
1148 	uint64_t drop_octs : 48;
1149 	uint64_t rsvd_575_560 : 16;
1150 	uint64_t drop_pkts : 48;
1151 	uint64_t rsvd_639_624 : 16;
1152 	uint64_t re_pkts : 48;
1153 	uint64_t rsvd_702_688 : 15;
1154 	uint64_t ena_copy : 1;
1155 	uint64_t rsvd_739_704 : 36;
1156 	uint64_t rq_int : 8;
1157 	uint64_t rq_int_ena : 8;
1158 	uint64_t qint_idx : 7;
1159 	uint64_t rsvd_767_763 : 5;
1160 	uint64_t rsvd_831_768 : 64;  /* W12 */
1161 	uint64_t rsvd_895_832 : 64;  /* W13 */
1162 	uint64_t rsvd_959_896 : 64;  /* W14 */
1163 	uint64_t rsvd_1023_960 : 64; /* W15 */
1164 };
1165 
1166 /* NIX receive queue context structure */
1167 struct nix_rq_ctx_hw_s {
1168 	uint64_t ena : 1;
1169 	uint64_t sso_ena : 1;
1170 	uint64_t ipsech_ena : 1;
1171 	uint64_t ena_wqwd : 1;
1172 	uint64_t cq : 20;
1173 	uint64_t substream : 20;
1174 	uint64_t wqe_aura : 20;
1175 	uint64_t spb_aura : 20;
1176 	uint64_t lpb_aura : 20;
1177 	uint64_t sso_grp : 10;
1178 	uint64_t sso_tt : 2;
1179 	uint64_t pb_caching : 2;
1180 	uint64_t wqe_caching : 1;
1181 	uint64_t xqe_drop_ena : 1;
1182 	uint64_t spb_drop_ena : 1;
1183 	uint64_t lpb_drop_ena : 1;
1184 	uint64_t wqe_skip : 2;
1185 	uint64_t rsvd_127_124 : 4;
1186 	uint64_t rsvd_139_128 : 12;
1187 	uint64_t spb_sizem1 : 6;
1188 	uint64_t rsvd_150_146 : 5;
1189 	uint64_t spb_ena : 1;
1190 	uint64_t lpb_sizem1 : 12;
1191 	uint64_t first_skip : 7;
1192 	uint64_t rsvd_171 : 1;
1193 	uint64_t later_skip : 6;
1194 	uint64_t xqe_imm_size : 6;
1195 	uint64_t rsvd_189_184 : 6;
1196 	uint64_t xqe_imm_copy : 1;
1197 	uint64_t xqe_hdr_split : 1;
1198 	uint64_t xqe_drop : 8;
1199 	uint64_t xqe_pass : 8;
1200 	uint64_t wqe_pool_drop : 8;
1201 	uint64_t wqe_pool_pass : 8;
1202 	uint64_t spb_aura_drop : 8;
1203 	uint64_t spb_aura_pass : 8;
1204 	uint64_t spb_pool_drop : 8;
1205 	uint64_t spb_pool_pass : 8;
1206 	uint64_t lpb_aura_drop : 8;
1207 	uint64_t lpb_aura_pass : 8;
1208 	uint64_t lpb_pool_drop : 8;
1209 	uint64_t lpb_pool_pass : 8;
1210 	uint64_t rsvd_319_288 : 32;
1211 	uint64_t ltag : 24;
1212 	uint64_t good_utag : 8;
1213 	uint64_t bad_utag : 8;
1214 	uint64_t flow_tagw : 6;
1215 	uint64_t rsvd_383_366 : 18;
1216 	uint64_t octs : 48;
1217 	uint64_t rsvd_447_432 : 16;
1218 	uint64_t pkts : 48;
1219 	uint64_t rsvd_511_496 : 16;
1220 	uint64_t drop_octs : 48;
1221 	uint64_t rsvd_575_560 : 16;
1222 	uint64_t drop_pkts : 48;
1223 	uint64_t rsvd_639_624 : 16;
1224 	uint64_t re_pkts : 48;
1225 	uint64_t rsvd_702_688 : 15;
1226 	uint64_t ena_copy : 1;
1227 	uint64_t rsvd_739_704 : 36;
1228 	uint64_t rq_int : 8;
1229 	uint64_t rq_int_ena : 8;
1230 	uint64_t qint_idx : 7;
1231 	uint64_t rsvd_767_763 : 5;
1232 	uint64_t rsvd_831_768 : 64;  /* W12 */
1233 	uint64_t rsvd_895_832 : 64;  /* W13 */
1234 	uint64_t rsvd_959_896 : 64;  /* W14 */
1235 	uint64_t rsvd_1023_960 : 64; /* W15 */
1236 };
1237 
1238 /* [CN10K, .) NIX Receive queue context structure */
1239 struct nix_cn10k_rq_ctx_s {
1240 	uint64_t ena : 1;
1241 	uint64_t sso_ena : 1;
1242 	uint64_t ipsech_ena : 1;
1243 	uint64_t ena_wqwd : 1;
1244 	uint64_t cq : 20;
1245 	uint64_t rsvd_36_24 : 13;
1246 	uint64_t lenerr_dis : 1;
1247 	uint64_t csum_il4_dis : 1;
1248 	uint64_t csum_ol4_dis : 1;
1249 	uint64_t len_il4_dis : 1;
1250 	uint64_t len_il3_dis : 1;
1251 	uint64_t len_ol4_dis : 1;
1252 	uint64_t len_ol3_dis : 1;
1253 	uint64_t wqe_aura : 20;
1254 	uint64_t spb_aura : 20;
1255 	uint64_t lpb_aura : 20;
1256 	uint64_t sso_grp : 10;
1257 	uint64_t sso_tt : 2;
1258 	uint64_t pb_caching : 2;
1259 	uint64_t wqe_caching : 1;
1260 	uint64_t xqe_drop_ena : 1;
1261 	uint64_t spb_drop_ena : 1;
1262 	uint64_t lpb_drop_ena : 1;
1263 	uint64_t pb_stashing : 1;
1264 	uint64_t ipsecd_drop_en : 1;
1265 	uint64_t chi_ena : 1;
1266 	uint64_t rsvd_127_125 : 3;
1267 	uint64_t band_prof_id : 10;
1268 	uint64_t rsvd_138 : 1;
1269 	uint64_t policer_ena : 1;
1270 	uint64_t spb_sizem1 : 6;
1271 	uint64_t wqe_skip : 2;
1272 	uint64_t spb_high_sizem1 : 3;
1273 	uint64_t spb_ena : 1;
1274 	uint64_t lpb_sizem1 : 12;
1275 	uint64_t first_skip : 7;
1276 	uint64_t rsvd_171 : 1;
1277 	uint64_t later_skip : 6;
1278 	uint64_t xqe_imm_size : 6;
1279 	uint64_t rsvd_189_184 : 6;
1280 	uint64_t xqe_imm_copy : 1;
1281 	uint64_t xqe_hdr_split : 1;
1282 	uint64_t xqe_drop : 8;
1283 	uint64_t xqe_pass : 8;
1284 	uint64_t wqe_pool_drop : 8;
1285 	uint64_t wqe_pool_pass : 8;
1286 	uint64_t spb_aura_drop : 8;
1287 	uint64_t spb_aura_pass : 8;
1288 	uint64_t spb_pool_drop : 8;
1289 	uint64_t spb_pool_pass : 8;
1290 	uint64_t lpb_aura_drop : 8;
1291 	uint64_t lpb_aura_pass : 8;
1292 	uint64_t lpb_pool_drop : 8;
1293 	uint64_t lpb_pool_pass : 8;
1294 	uint64_t rsvd_291_288 : 4;
1295 	uint64_t rq_int : 8;
1296 	uint64_t rq_int_ena : 8;
1297 	uint64_t qint_idx : 7;
1298 	uint64_t rsvd_319_315 : 5;
1299 	uint64_t ltag : 24;
1300 	uint64_t good_utag : 8;
1301 	uint64_t bad_utag : 8;
1302 	uint64_t flow_tagw : 6;
1303 	uint64_t ipsec_vwqe : 1;
1304 	uint64_t vwqe_ena : 1;
1305 	uint64_t vtime_wait : 8;
1306 	uint64_t max_vsize_exp : 4;
1307 	uint64_t vwqe_skip : 2;
1308 	uint64_t rsvd_383_382 : 2;
1309 	uint64_t octs : 48;
1310 	uint64_t rsvd_447_432 : 16;
1311 	uint64_t pkts : 48;
1312 	uint64_t rsvd_511_496 : 16;
1313 	uint64_t drop_octs : 48;
1314 	uint64_t rsvd_575_560 : 16;
1315 	uint64_t drop_pkts : 48;
1316 	uint64_t rsvd_639_624 : 16;
1317 	uint64_t re_pkts : 48;
1318 	uint64_t rsvd_703_688 : 16;
1319 	uint64_t rsvd_767_704 : 64;  /* W11 */
1320 	uint64_t rsvd_831_768 : 64;  /* W12 */
1321 	uint64_t rsvd_895_832 : 64;  /* W13 */
1322 	uint64_t rsvd_959_896 : 64;  /* W14 */
1323 	uint64_t rsvd_1023_960 : 64; /* W15 */
1324 };
1325 
1326 /* NIX receive queue context structure */
1327 struct nix_rq_ctx_s {
1328 	uint64_t ena : 1;
1329 	uint64_t sso_ena : 1;
1330 	uint64_t ipsech_ena : 1;
1331 	uint64_t ena_wqwd : 1;
1332 	uint64_t cq : 20;
1333 	uint64_t substream : 20;
1334 	uint64_t wqe_aura : 20;
1335 	uint64_t spb_aura : 20;
1336 	uint64_t lpb_aura : 20;
1337 	uint64_t sso_grp : 10;
1338 	uint64_t sso_tt : 2;
1339 	uint64_t pb_caching : 2;
1340 	uint64_t wqe_caching : 1;
1341 	uint64_t xqe_drop_ena : 1;
1342 	uint64_t spb_drop_ena : 1;
1343 	uint64_t lpb_drop_ena : 1;
1344 	uint64_t rsvd_127_122 : 6;
1345 	uint64_t rsvd_139_128 : 12;
1346 	uint64_t spb_sizem1 : 6;
1347 	uint64_t wqe_skip : 2;
1348 	uint64_t rsvd_150_148 : 3;
1349 	uint64_t spb_ena : 1;
1350 	uint64_t lpb_sizem1 : 12;
1351 	uint64_t first_skip : 7;
1352 	uint64_t rsvd_171 : 1;
1353 	uint64_t later_skip : 6;
1354 	uint64_t xqe_imm_size : 6;
1355 	uint64_t rsvd_189_184 : 6;
1356 	uint64_t xqe_imm_copy : 1;
1357 	uint64_t xqe_hdr_split : 1;
1358 	uint64_t xqe_drop : 8;
1359 	uint64_t xqe_pass : 8;
1360 	uint64_t wqe_pool_drop : 8;
1361 	uint64_t wqe_pool_pass : 8;
1362 	uint64_t spb_aura_drop : 8;
1363 	uint64_t spb_aura_pass : 8;
1364 	uint64_t spb_pool_drop : 8;
1365 	uint64_t spb_pool_pass : 8;
1366 	uint64_t lpb_aura_drop : 8;
1367 	uint64_t lpb_aura_pass : 8;
1368 	uint64_t lpb_pool_drop : 8;
1369 	uint64_t lpb_pool_pass : 8;
1370 	uint64_t rsvd_291_288 : 4;
1371 	uint64_t rq_int : 8;
1372 	uint64_t rq_int_ena : 8;
1373 	uint64_t qint_idx : 7;
1374 	uint64_t rsvd_319_315 : 5;
1375 	uint64_t ltag : 24;
1376 	uint64_t good_utag : 8;
1377 	uint64_t bad_utag : 8;
1378 	uint64_t flow_tagw : 6;
1379 	uint64_t rsvd_383_366 : 18;
1380 	uint64_t octs : 48;
1381 	uint64_t rsvd_447_432 : 16;
1382 	uint64_t pkts : 48;
1383 	uint64_t rsvd_511_496 : 16;
1384 	uint64_t drop_octs : 48;
1385 	uint64_t rsvd_575_560 : 16;
1386 	uint64_t drop_pkts : 48;
1387 	uint64_t rsvd_639_624 : 16;
1388 	uint64_t re_pkts : 48;
1389 	uint64_t rsvd_703_688 : 16;
1390 	uint64_t rsvd_767_704 : 64;  /* W11 */
1391 	uint64_t rsvd_831_768 : 64;  /* W12 */
1392 	uint64_t rsvd_895_832 : 64;  /* W13 */
1393 	uint64_t rsvd_959_896 : 64;  /* W14 */
1394 	uint64_t rsvd_1023_960 : 64; /* W15 */
1395 };
1396 
1397 /* NIX receive side scaling entry structure */
1398 struct nix_rsse_s {
1399 	uint32_t rq : 20;
1400 	uint32_t rsvd_31_20 : 12;
1401 };
1402 
1403 /* NIX receive action structure */
1404 struct nix_rx_action_s {
1405 	uint64_t op : 4;
1406 	uint64_t pf_func : 16;
1407 	uint64_t index : 20;
1408 	uint64_t match_id : 16;
1409 	uint64_t flow_key_alg : 5;
1410 	uint64_t rsvd_63_61 : 3;
1411 };
1412 
1413 /* NIX receive immediate sub descriptor structure */
1414 struct nix_rx_imm_s {
1415 	uint64_t size : 16;
1416 	uint64_t apad : 3;
1417 	uint64_t rsvd_59_19 : 41;
1418 	uint64_t subdc : 4;
1419 };
1420 
1421 /* NIX receive multicast/mirror entry structure */
1422 struct nix_rx_mce_s {
1423 	uint64_t op : 2;
1424 	uint64_t rsvd_2 : 1;
1425 	uint64_t eol : 1;
1426 	uint64_t index : 20;
1427 	uint64_t rsvd_31_24 : 8;
1428 	uint64_t pf_func : 16;
1429 	uint64_t next : 16;
1430 };
1431 
1432 /* NIX receive parse structure */
1433 union nix_rx_parse_u {
1434 	struct {
1435 		uint64_t chan : 12;
1436 		uint64_t desc_sizem1 : 5;
1437 		uint64_t imm_copy : 1;
1438 		uint64_t express : 1;
1439 		uint64_t wqwd : 1;
1440 		uint64_t errlev : 4;
1441 		uint64_t errcode : 8;
1442 		uint64_t latype : 4;
1443 		uint64_t lbtype : 4;
1444 		uint64_t lctype : 4;
1445 		uint64_t ldtype : 4;
1446 		uint64_t letype : 4;
1447 		uint64_t lftype : 4;
1448 		uint64_t lgtype : 4;
1449 		uint64_t lhtype : 4;
1450 		uint64_t pkt_lenm1 : 16;
1451 		uint64_t l2m : 1;
1452 		uint64_t l2b : 1;
1453 		uint64_t l3m : 1;
1454 		uint64_t l3b : 1;
1455 		uint64_t vtag0_valid : 1;
1456 		uint64_t vtag0_gone : 1;
1457 		uint64_t vtag1_valid : 1;
1458 		uint64_t vtag1_gone : 1;
1459 		uint64_t pkind : 6;
1460 		uint64_t nix_idx : 2;
1461 		uint64_t vtag0_tci : 16;
1462 		uint64_t vtag1_tci : 16;
1463 		uint64_t laflags : 8;
1464 		uint64_t lbflags : 8;
1465 		uint64_t lcflags : 8;
1466 		uint64_t ldflags : 8;
1467 		uint64_t leflags : 8;
1468 		uint64_t lfflags : 8;
1469 		uint64_t lgflags : 8;
1470 		uint64_t lhflags : 8;
1471 		uint64_t eoh_ptr : 8;
1472 		uint64_t wqe_aura : 20;
1473 		uint64_t pb_aura : 20;
1474 		uint64_t match_id : 16;
1475 		uint64_t laptr : 8;
1476 		uint64_t lbptr : 8;
1477 		uint64_t lcptr : 8;
1478 		uint64_t ldptr : 8;
1479 		uint64_t leptr : 8;
1480 		uint64_t lfptr : 8;
1481 		uint64_t lgptr : 8;
1482 		uint64_t lhptr : 8;
1483 		uint64_t vtag0_ptr : 8;
1484 		uint64_t vtag1_ptr : 8;
1485 		uint64_t flow_key_alg : 5;
1486 		uint64_t rsvd_341 : 1;
1487 		uint64_t rsvd_349_342 : 8;
1488 		uint64_t rsvd_353_350 : 4;
1489 		uint64_t rsvd_359_354 : 6;
1490 		uint64_t color : 2;
1491 		uint64_t rsvd_381_362 : 20;
1492 		uint64_t rsvd_382 : 1;
1493 		uint64_t rsvd_383 : 1;
1494 		uint64_t rsvd_447_384 : 64; /* W6 */
1495 	};
1496 	struct {
1497 		uint64_t chan : 12;
1498 		uint64_t desc_sizem1 : 5;
1499 		uint64_t imm_copy : 1;
1500 		uint64_t express : 1;
1501 		uint64_t wqwd : 1;
1502 		uint64_t errlev : 4;
1503 		uint64_t errcode : 8;
1504 		uint64_t latype : 4;
1505 		uint64_t lbtype : 4;
1506 		uint64_t lctype : 4;
1507 		uint64_t ldtype : 4;
1508 		uint64_t letype : 4;
1509 		uint64_t lftype : 4;
1510 		uint64_t lgtype : 4;
1511 		uint64_t lhtype : 4;
1512 		uint64_t pkt_lenm1 : 16;
1513 		uint64_t l2m : 1;
1514 		uint64_t l2b : 1;
1515 		uint64_t l3m : 1;
1516 		uint64_t l3b : 1;
1517 		uint64_t vtag0_valid : 1;
1518 		uint64_t vtag0_gone : 1;
1519 		uint64_t vtag1_valid : 1;
1520 		uint64_t vtag1_gone : 1;
1521 		uint64_t pkind : 6;
1522 		uint64_t rsvd_95_94 : 2;
1523 		uint64_t vtag0_tci : 16;
1524 		uint64_t vtag1_tci : 16;
1525 		uint64_t laflags : 8;
1526 		uint64_t lbflags : 8;
1527 		uint64_t lcflags : 8;
1528 		uint64_t ldflags : 8;
1529 		uint64_t leflags : 8;
1530 		uint64_t lfflags : 8;
1531 		uint64_t lgflags : 8;
1532 		uint64_t lhflags : 8;
1533 		uint64_t eoh_ptr : 8;
1534 		uint64_t wqe_aura : 20;
1535 		uint64_t pb_aura : 20;
1536 		uint64_t match_id : 16;
1537 		uint64_t laptr : 8;
1538 		uint64_t lbptr : 8;
1539 		uint64_t lcptr : 8;
1540 		uint64_t ldptr : 8;
1541 		uint64_t leptr : 8;
1542 		uint64_t lfptr : 8;
1543 		uint64_t lgptr : 8;
1544 		uint64_t lhptr : 8;
1545 		uint64_t vtag0_ptr : 8;
1546 		uint64_t vtag1_ptr : 8;
1547 		uint64_t flow_key_alg : 5;
1548 		uint64_t rsvd_383_341 : 43;
1549 		uint64_t rsvd_447_384 : 64; /* W6 */
1550 	} cn9k;
1551 };
1552 
1553 /* NIX receive scatter/gather sub descriptor structure */
1554 struct nix_rx_sg_s {
1555 	uint64_t seg1_size : 16;
1556 	uint64_t seg2_size : 16;
1557 	uint64_t seg3_size : 16;
1558 	uint64_t segs : 2;
1559 	uint64_t rsvd_59_50 : 10;
1560 	uint64_t subdc : 4;
1561 };
1562 
1563 /* NIX receive vtag action structure */
1564 union nix_rx_vtag_action_u {
1565 	struct {
1566 		uint64_t vtag0_relptr : 8;
1567 		uint64_t vtag0_lid : 3;
1568 		uint64_t sa_xor : 1;
1569 		uint64_t vtag0_type : 3;
1570 		uint64_t vtag0_valid : 1;
1571 		uint64_t sa_lo : 16;
1572 		uint64_t vtag1_relptr : 8;
1573 		uint64_t vtag1_lid : 3;
1574 		uint64_t rsvd_43 : 1;
1575 		uint64_t vtag1_type : 3;
1576 		uint64_t vtag1_valid : 1;
1577 		uint64_t sa_hi : 16;
1578 	};
1579 	struct {
1580 		uint64_t vtag0_relptr : 8;
1581 		uint64_t vtag0_lid : 3;
1582 		uint64_t rsvd_11 : 1;
1583 		uint64_t vtag0_type : 3;
1584 		uint64_t vtag0_valid : 1;
1585 		uint64_t rsvd_31_16 : 16;
1586 		uint64_t vtag1_relptr : 8;
1587 		uint64_t vtag1_lid : 3;
1588 		uint64_t rsvd_43 : 1;
1589 		uint64_t vtag1_type : 3;
1590 		uint64_t vtag1_valid : 1;
1591 		uint64_t rsvd_63_48 : 16;
1592 	} cn9k;
1593 };
1594 
1595 /* NIX send completion structure */
1596 struct nix_send_comp_s {
1597 	uint64_t status : 8;
1598 	uint64_t sqe_id : 16;
1599 	uint64_t rsvd_63_24 : 40;
1600 };
1601 
1602 /* NIX send CRC sub descriptor structure */
1603 struct nix_send_crc_s {
1604 	uint64_t size : 16;
1605 	uint64_t start : 16;
1606 	uint64_t insert : 16;
1607 	uint64_t rsvd_57_48 : 10;
1608 	uint64_t alg : 2;
1609 	uint64_t subdc : 4;
1610 	uint64_t iv : 32;
1611 	uint64_t rsvd_127_96 : 32;
1612 };
1613 
1614 /* NIX send extended header sub descriptor structure */
1615 PLT_STD_C11
1616 union nix_send_ext_w0_u {
1617 	uint64_t u;
1618 	struct {
1619 		uint64_t lso_mps : 14;
1620 		uint64_t lso : 1;
1621 		uint64_t tstmp : 1;
1622 		uint64_t lso_sb : 8;
1623 		uint64_t lso_format : 5;
1624 		uint64_t rsvd_31_29 : 3;
1625 		uint64_t shp_chg : 9;
1626 		uint64_t shp_dis : 1;
1627 		uint64_t shp_ra : 2;
1628 		uint64_t markptr : 8;
1629 		uint64_t markform : 7;
1630 		uint64_t mark_en : 1;
1631 		uint64_t subdc : 4;
1632 	};
1633 };
1634 
1635 PLT_STD_C11
1636 union nix_send_ext_w1_u {
1637 	uint64_t u;
1638 	struct {
1639 		uint64_t vlan0_ins_ptr : 8;
1640 		uint64_t vlan0_ins_tci : 16;
1641 		uint64_t vlan1_ins_ptr : 8;
1642 		uint64_t vlan1_ins_tci : 16;
1643 		uint64_t vlan0_ins_ena : 1;
1644 		uint64_t vlan1_ins_ena : 1;
1645 		uint64_t init_color : 2;
1646 		uint64_t rsvd_127_116 : 12;
1647 	};
1648 	struct {
1649 		uint64_t vlan0_ins_ptr : 8;
1650 		uint64_t vlan0_ins_tci : 16;
1651 		uint64_t vlan1_ins_ptr : 8;
1652 		uint64_t vlan1_ins_tci : 16;
1653 		uint64_t vlan0_ins_ena : 1;
1654 		uint64_t vlan1_ins_ena : 1;
1655 		uint64_t rsvd_127_114 : 14;
1656 	} cn9k;
1657 };
1658 
1659 struct nix_send_ext_s {
1660 	union nix_send_ext_w0_u w0;
1661 	union nix_send_ext_w1_u w1;
1662 };
1663 
1664 /* NIX send header sub descriptor structure */
1665 PLT_STD_C11
1666 union nix_send_hdr_w0_u {
1667 	uint64_t u;
1668 	struct {
1669 		uint64_t total : 18;
1670 		uint64_t rsvd_18 : 1;
1671 		uint64_t df : 1;
1672 		uint64_t aura : 20;
1673 		uint64_t sizem1 : 3;
1674 		uint64_t pnc : 1;
1675 		uint64_t sq : 20;
1676 	};
1677 };
1678 
1679 PLT_STD_C11
1680 union nix_send_hdr_w1_u {
1681 	uint64_t u;
1682 	struct {
1683 		uint64_t ol3ptr : 8;
1684 		uint64_t ol4ptr : 8;
1685 		uint64_t il3ptr : 8;
1686 		uint64_t il4ptr : 8;
1687 		uint64_t ol3type : 4;
1688 		uint64_t ol4type : 4;
1689 		uint64_t il3type : 4;
1690 		uint64_t il4type : 4;
1691 		uint64_t sqe_id : 16;
1692 	};
1693 };
1694 
1695 struct nix_send_hdr_s {
1696 	union nix_send_hdr_w0_u w0;
1697 	union nix_send_hdr_w1_u w1;
1698 };
1699 
1700 /* NIX send immediate sub descriptor structure */
1701 struct nix_send_imm_s {
1702 	uint64_t size : 16;
1703 	uint64_t apad : 3;
1704 	uint64_t rsvd_59_19 : 41;
1705 	uint64_t subdc : 4;
1706 };
1707 
1708 /* NIX send jump sub descriptor structure */
1709 struct nix_send_jump_s {
1710 	uint64_t sizem1 : 7;
1711 	uint64_t rsvd_13_7 : 7;
1712 	uint64_t ld_type : 2;
1713 	uint64_t aura : 20;
1714 	uint64_t rsvd_58_36 : 23;
1715 	uint64_t f : 1;
1716 	uint64_t subdc : 4;
1717 	uint64_t addr : 64; /* W1 */
1718 };
1719 
1720 /* NIX send memory sub descriptor structure */
1721 PLT_STD_C11
1722 union nix_send_mem_w0_u {
1723 	uint64_t u;
1724 	struct {
1725 		uint64_t offset : 16;
1726 		uint64_t rsvd_51_16 : 36;
1727 		uint64_t per_lso_seg : 1;
1728 		uint64_t wmem : 1;
1729 		uint64_t dsz : 2;
1730 		uint64_t alg : 4;
1731 		uint64_t subdc : 4;
1732 	};
1733 	struct {
1734 		uint64_t offset : 16;
1735 		uint64_t rsvd_52_16 : 37;
1736 		uint64_t wmem : 1;
1737 		uint64_t dsz : 2;
1738 		uint64_t alg : 4;
1739 		uint64_t subdc : 4;
1740 	} cn9k;
1741 };
1742 
1743 struct nix_send_mem_s {
1744 	union nix_send_mem_w0_u w0;
1745 	uint64_t addr : 64; /* W1 */
1746 };
1747 
1748 /* NIX send scatter/gather sub descriptor structure */
1749 PLT_STD_C11
1750 union nix_send_sg2_s {
1751 	uint64_t u;
1752 	struct {
1753 		uint64_t seg1_size : 16;
1754 		uint64_t aura : 20;
1755 		uint64_t i1 : 1;
1756 		uint64_t fabs : 1;
1757 		uint64_t foff : 8;
1758 		uint64_t rsvd_57_46 : 12;
1759 		uint64_t ld_type : 2;
1760 		uint64_t subdc : 4;
1761 	};
1762 };
1763 
1764 PLT_STD_C11
1765 union nix_send_sg_s {
1766 	uint64_t u;
1767 	struct {
1768 		uint64_t seg1_size : 16;
1769 		uint64_t seg2_size : 16;
1770 		uint64_t seg3_size : 16;
1771 		uint64_t segs : 2;
1772 		uint64_t rsvd_54_50 : 5;
1773 		uint64_t i1 : 1;
1774 		uint64_t i2 : 1;
1775 		uint64_t i3 : 1;
1776 		uint64_t ld_type : 2;
1777 		uint64_t subdc : 4;
1778 	};
1779 };
1780 
1781 /* NIX send work sub descriptor structure */
1782 struct nix_send_work_s {
1783 	uint64_t tag : 32;
1784 	uint64_t tt : 2;
1785 	uint64_t grp : 10;
1786 	uint64_t rsvd_59_44 : 16;
1787 	uint64_t subdc : 4;
1788 	uint64_t addr : 64; /* W1 */
1789 };
1790 
1791 /* [CN10K, .) NIX sq context hardware structure */
1792 struct nix_cn10k_sq_ctx_hw_s {
1793 	uint64_t ena : 1;
1794 	uint64_t substream : 20;
1795 	uint64_t max_sqe_size : 2;
1796 	uint64_t sqe_way_mask : 16;
1797 	uint64_t sqb_aura : 20;
1798 	uint64_t gbl_rsvd1 : 5;
1799 	uint64_t cq_id : 20;
1800 	uint64_t cq_ena : 1;
1801 	uint64_t qint_idx : 6;
1802 	uint64_t gbl_rsvd2 : 1;
1803 	uint64_t sq_int : 8;
1804 	uint64_t sq_int_ena : 8;
1805 	uint64_t xoff : 1;
1806 	uint64_t sqe_stype : 2;
1807 	uint64_t gbl_rsvd : 17;
1808 	uint64_t head_sqb : 64; /* W2 */
1809 	uint64_t head_offset : 6;
1810 	uint64_t sqb_dequeue_count : 16;
1811 	uint64_t default_chan : 12;
1812 	uint64_t sdp_mcast : 1;
1813 	uint64_t sso_ena : 1;
1814 	uint64_t dse_rsvd1 : 28;
1815 	uint64_t sqb_enqueue_count : 16;
1816 	uint64_t tail_offset : 6;
1817 	uint64_t lmt_dis : 1;
1818 	uint64_t smq_rr_weight : 14;
1819 	uint64_t dnq_rsvd1 : 27;
1820 	uint64_t tail_sqb : 64; /* W5 */
1821 	uint64_t next_sqb : 64; /* W6 */
1822 	uint64_t smq : 10;
1823 	uint64_t smq_pend : 1;
1824 	uint64_t smq_next_sq : 20;
1825 	uint64_t smq_next_sq_vld : 1;
1826 	uint64_t mnq_dis : 1;
1827 	uint64_t scm1_rsvd2 : 31;
1828 	uint64_t smenq_sqb : 64; /* W8 */
1829 	uint64_t smenq_offset : 6;
1830 	uint64_t cq_limit : 8;
1831 	uint64_t smq_rr_count : 32;
1832 	uint64_t scm_lso_rem : 18;
1833 	uint64_t smq_lso_segnum : 8;
1834 	uint64_t vfi_lso_total : 18;
1835 	uint64_t vfi_lso_sizem1 : 3;
1836 	uint64_t vfi_lso_sb : 8;
1837 	uint64_t vfi_lso_mps : 14;
1838 	uint64_t vfi_lso_vlan0_ins_ena : 1;
1839 	uint64_t vfi_lso_vlan1_ins_ena : 1;
1840 	uint64_t vfi_lso_vld : 1;
1841 	uint64_t smenq_next_sqb_vld : 1;
1842 	uint64_t scm_dq_rsvd1 : 9;
1843 	uint64_t smenq_next_sqb : 64; /* W11 */
1844 	uint64_t age_drop_octs : 32;
1845 	uint64_t age_drop_pkts : 32;
1846 	uint64_t drop_pkts : 48;
1847 	uint64_t drop_octs_lsw : 16;
1848 	uint64_t drop_octs_msw : 32;
1849 	uint64_t pkts_lsw : 32;
1850 	uint64_t pkts_msw : 16;
1851 	uint64_t octs : 48;
1852 };
1853 
1854 /* NIX sq context hardware structure */
1855 struct nix_sq_ctx_hw_s {
1856 	uint64_t ena : 1;
1857 	uint64_t substream : 20;
1858 	uint64_t max_sqe_size : 2;
1859 	uint64_t sqe_way_mask : 16;
1860 	uint64_t sqb_aura : 20;
1861 	uint64_t gbl_rsvd1 : 5;
1862 	uint64_t cq_id : 20;
1863 	uint64_t cq_ena : 1;
1864 	uint64_t qint_idx : 6;
1865 	uint64_t gbl_rsvd2 : 1;
1866 	uint64_t sq_int : 8;
1867 	uint64_t sq_int_ena : 8;
1868 	uint64_t xoff : 1;
1869 	uint64_t sqe_stype : 2;
1870 	uint64_t gbl_rsvd : 17;
1871 	uint64_t head_sqb : 64; /* W2 */
1872 	uint64_t head_offset : 6;
1873 	uint64_t sqb_dequeue_count : 16;
1874 	uint64_t default_chan : 12;
1875 	uint64_t sdp_mcast : 1;
1876 	uint64_t sso_ena : 1;
1877 	uint64_t dse_rsvd1 : 28;
1878 	uint64_t sqb_enqueue_count : 16;
1879 	uint64_t tail_offset : 6;
1880 	uint64_t lmt_dis : 1;
1881 	uint64_t smq_rr_quantum : 24;
1882 	uint64_t dnq_rsvd1 : 17;
1883 	uint64_t tail_sqb : 64; /* W5 */
1884 	uint64_t next_sqb : 64; /* W6 */
1885 	uint64_t mnq_dis : 1;
1886 	uint64_t smq : 9;
1887 	uint64_t smq_pend : 1;
1888 	uint64_t smq_next_sq : 20;
1889 	uint64_t smq_next_sq_vld : 1;
1890 	uint64_t scm1_rsvd2 : 32;
1891 	uint64_t smenq_sqb : 64; /* W8 */
1892 	uint64_t smenq_offset : 6;
1893 	uint64_t cq_limit : 8;
1894 	uint64_t smq_rr_count : 25;
1895 	uint64_t scm_lso_rem : 18;
1896 	uint64_t scm_dq_rsvd0 : 7;
1897 	uint64_t smq_lso_segnum : 8;
1898 	uint64_t vfi_lso_total : 18;
1899 	uint64_t vfi_lso_sizem1 : 3;
1900 	uint64_t vfi_lso_sb : 8;
1901 	uint64_t vfi_lso_mps : 14;
1902 	uint64_t vfi_lso_vlan0_ins_ena : 1;
1903 	uint64_t vfi_lso_vlan1_ins_ena : 1;
1904 	uint64_t vfi_lso_vld : 1;
1905 	uint64_t smenq_next_sqb_vld : 1;
1906 	uint64_t scm_dq_rsvd1 : 9;
1907 	uint64_t smenq_next_sqb : 64; /* W11 */
1908 	uint64_t seb_rsvd1 : 64;      /* W12 */
1909 	uint64_t drop_pkts : 48;
1910 	uint64_t drop_octs_lsw : 16;
1911 	uint64_t drop_octs_msw : 32;
1912 	uint64_t pkts_lsw : 32;
1913 	uint64_t pkts_msw : 16;
1914 	uint64_t octs : 48;
1915 };
1916 
1917 /* [CN10K, .) NIX Send queue context structure */
1918 struct nix_cn10k_sq_ctx_s {
1919 	uint64_t ena : 1;
1920 	uint64_t qint_idx : 6;
1921 	uint64_t substream : 20;
1922 	uint64_t sdp_mcast : 1;
1923 	uint64_t cq : 20;
1924 	uint64_t sqe_way_mask : 16;
1925 	uint64_t smq : 10;
1926 	uint64_t cq_ena : 1;
1927 	uint64_t xoff : 1;
1928 	uint64_t sso_ena : 1;
1929 	uint64_t smq_rr_weight : 14;
1930 	uint64_t default_chan : 12;
1931 	uint64_t sqb_count : 16;
1932 	uint64_t rsvd_120_119 : 2;
1933 	uint64_t smq_rr_count_lb : 7;
1934 	uint64_t smq_rr_count_ub : 25;
1935 	uint64_t sqb_aura : 20;
1936 	uint64_t sq_int : 8;
1937 	uint64_t sq_int_ena : 8;
1938 	uint64_t sqe_stype : 2;
1939 	uint64_t rsvd_191 : 1;
1940 	uint64_t max_sqe_size : 2;
1941 	uint64_t cq_limit : 8;
1942 	uint64_t lmt_dis : 1;
1943 	uint64_t mnq_dis : 1;
1944 	uint64_t smq_next_sq : 20;
1945 	uint64_t smq_lso_segnum : 8;
1946 	uint64_t tail_offset : 6;
1947 	uint64_t smenq_offset : 6;
1948 	uint64_t head_offset : 6;
1949 	uint64_t smenq_next_sqb_vld : 1;
1950 	uint64_t smq_pend : 1;
1951 	uint64_t smq_next_sq_vld : 1;
1952 	uint64_t rsvd_255_253 : 3;
1953 	uint64_t next_sqb : 64;	      /* W4 */
1954 	uint64_t tail_sqb : 64;	      /* W5 */
1955 	uint64_t smenq_sqb : 64;      /* W6 */
1956 	uint64_t smenq_next_sqb : 64; /* W7 */
1957 	uint64_t head_sqb : 64;	      /* W8 */
1958 	uint64_t rsvd_583_576 : 8;
1959 	uint64_t vfi_lso_total : 18;
1960 	uint64_t vfi_lso_sizem1 : 3;
1961 	uint64_t vfi_lso_sb : 8;
1962 	uint64_t vfi_lso_mps : 14;
1963 	uint64_t vfi_lso_vlan0_ins_ena : 1;
1964 	uint64_t vfi_lso_vlan1_ins_ena : 1;
1965 	uint64_t vfi_lso_vld : 1;
1966 	uint64_t rsvd_639_630 : 10;
1967 	uint64_t scm_lso_rem : 18;
1968 	uint64_t rsvd_703_658 : 46;
1969 	uint64_t octs : 48;
1970 	uint64_t rsvd_767_752 : 16;
1971 	uint64_t pkts : 48;
1972 	uint64_t rsvd_831_816 : 16;
1973 	uint64_t aged_drop_octs : 32;
1974 	uint64_t aged_drop_pkts : 32;
1975 	uint64_t drop_octs : 48;
1976 	uint64_t rsvd_959_944 : 16;
1977 	uint64_t drop_pkts : 48;
1978 	uint64_t rsvd_1023_1008 : 16;
1979 };
1980 
1981 /* NIX send queue context structure */
1982 struct nix_sq_ctx_s {
1983 	uint64_t ena : 1;
1984 	uint64_t qint_idx : 6;
1985 	uint64_t substream : 20;
1986 	uint64_t sdp_mcast : 1;
1987 	uint64_t cq : 20;
1988 	uint64_t sqe_way_mask : 16;
1989 	uint64_t smq : 9;
1990 	uint64_t cq_ena : 1;
1991 	uint64_t xoff : 1;
1992 	uint64_t sso_ena : 1;
1993 	uint64_t smq_rr_quantum : 24;
1994 	uint64_t default_chan : 12;
1995 	uint64_t sqb_count : 16;
1996 	uint64_t smq_rr_count : 25;
1997 	uint64_t sqb_aura : 20;
1998 	uint64_t sq_int : 8;
1999 	uint64_t sq_int_ena : 8;
2000 	uint64_t sqe_stype : 2;
2001 	uint64_t rsvd_191 : 1;
2002 	uint64_t max_sqe_size : 2;
2003 	uint64_t cq_limit : 8;
2004 	uint64_t lmt_dis : 1;
2005 	uint64_t mnq_dis : 1;
2006 	uint64_t smq_next_sq : 20;
2007 	uint64_t smq_lso_segnum : 8;
2008 	uint64_t tail_offset : 6;
2009 	uint64_t smenq_offset : 6;
2010 	uint64_t head_offset : 6;
2011 	uint64_t smenq_next_sqb_vld : 1;
2012 	uint64_t smq_pend : 1;
2013 	uint64_t smq_next_sq_vld : 1;
2014 	uint64_t rsvd_255_253 : 3;
2015 	uint64_t next_sqb : 64;	      /* W4 */
2016 	uint64_t tail_sqb : 64;	      /* W5 */
2017 	uint64_t smenq_sqb : 64;      /* W6 */
2018 	uint64_t smenq_next_sqb : 64; /* W7 */
2019 	uint64_t head_sqb : 64;	      /* W8 */
2020 	uint64_t rsvd_583_576 : 8;
2021 	uint64_t vfi_lso_total : 18;
2022 	uint64_t vfi_lso_sizem1 : 3;
2023 	uint64_t vfi_lso_sb : 8;
2024 	uint64_t vfi_lso_mps : 14;
2025 	uint64_t vfi_lso_vlan0_ins_ena : 1;
2026 	uint64_t vfi_lso_vlan1_ins_ena : 1;
2027 	uint64_t vfi_lso_vld : 1;
2028 	uint64_t rsvd_639_630 : 10;
2029 	uint64_t scm_lso_rem : 18;
2030 	uint64_t rsvd_703_658 : 46;
2031 	uint64_t octs : 48;
2032 	uint64_t rsvd_767_752 : 16;
2033 	uint64_t pkts : 48;
2034 	uint64_t rsvd_831_816 : 16;
2035 	uint64_t rsvd_895_832 : 64; /* W13 */
2036 	uint64_t drop_octs : 48;
2037 	uint64_t rsvd_959_944 : 16;
2038 	uint64_t drop_pkts : 48;
2039 	uint64_t rsvd_1023_1008 : 16;
2040 };
2041 
2042 /* NIX transmit action structure */
2043 struct nix_tx_action_s {
2044 	uint64_t op : 4;
2045 	uint64_t rsvd_11_4 : 8;
2046 	uint64_t index : 20;
2047 	uint64_t match_id : 16;
2048 	uint64_t rsvd_63_48 : 16;
2049 };
2050 
2051 /* NIX transmit vtag action structure */
2052 struct nix_tx_vtag_action_s {
2053 	uint64_t vtag0_relptr : 8;
2054 	uint64_t vtag0_lid : 3;
2055 	uint64_t rsvd_11 : 1;
2056 	uint64_t vtag0_op : 2;
2057 	uint64_t rsvd_15_14 : 2;
2058 	uint64_t vtag0_def : 10;
2059 	uint64_t rsvd_31_26 : 6;
2060 	uint64_t vtag1_relptr : 8;
2061 	uint64_t vtag1_lid : 3;
2062 	uint64_t rsvd_43 : 1;
2063 	uint64_t vtag1_op : 2;
2064 	uint64_t rsvd_47_46 : 2;
2065 	uint64_t vtag1_def : 10;
2066 	uint64_t rsvd_63_58 : 6;
2067 };
2068 
2069 /* NIX work queue entry header structure */
2070 struct nix_wqe_hdr_s {
2071 	uint64_t tag : 32;
2072 	uint64_t tt : 2;
2073 	uint64_t grp : 10;
2074 	uint64_t node : 2;
2075 	uint64_t q : 14;
2076 	uint64_t wqe_type : 4;
2077 };
2078 
2079 /* NIX Rx flow key algorithm field structure */
2080 struct nix_rx_flowkey_alg {
2081 	uint64_t key_offset : 6;
2082 	uint64_t ln_mask : 1;
2083 	uint64_t fn_mask : 1;
2084 	uint64_t hdr_offset : 8;
2085 	uint64_t bytesm1 : 5;
2086 	uint64_t lid : 3;
2087 	uint64_t reserved_24_24 : 1;
2088 	uint64_t ena : 1;
2089 	uint64_t sel_chan : 1;
2090 	uint64_t ltype_mask : 4;
2091 	uint64_t ltype_match : 4;
2092 	uint64_t reserved_35_63 : 29;
2093 };
2094 
2095 /* NIX LSO format field structure */
2096 struct nix_lso_format {
2097 	uint64_t offset : 8;
2098 	uint64_t layer : 2;
2099 	uint64_t rsvd_10_11 : 2;
2100 	uint64_t sizem1 : 2;
2101 	uint64_t rsvd_14_15 : 2;
2102 	uint64_t alg : 3;
2103 	uint64_t rsvd_19_63 : 45;
2104 };
2105 
2106 #define NIX_LSO_FIELD_MAX      (8)
2107 #define NIX_LSO_FIELD_ALG_MASK GENMASK(18, 16)
2108 #define NIX_LSO_FIELD_SZ_MASK  GENMASK(13, 12)
2109 #define NIX_LSO_FIELD_LY_MASK  GENMASK(9, 8)
2110 #define NIX_LSO_FIELD_OFF_MASK GENMASK(7, 0)
2111 
2112 #define NIX_LSO_FIELD_MASK                                                     \
2113 	(NIX_LSO_FIELD_OFF_MASK | NIX_LSO_FIELD_LY_MASK |                      \
2114 	 NIX_LSO_FIELD_SZ_MASK | NIX_LSO_FIELD_ALG_MASK)
2115 
2116 #define NIX_CN9K_MAX_HW_FRS 9212UL
2117 #define NIX_LBK_MAX_HW_FRS  65535UL
2118 #define NIX_SDP_MAX_HW_FRS  65535UL
2119 #define NIX_RPM_MAX_HW_FRS  16380UL
2120 #define NIX_MIN_HW_FRS	    60UL
2121 
2122 /** NIX policer rate limits */
2123 #define NIX_BPF_MAX_RATE_DIV_EXP  12
2124 #define NIX_BPF_MAX_RATE_EXPONENT 0x16
2125 #define NIX_BPF_MAX_RATE_MANTISSA 0xff
2126 
2127 #define NIX_BPF_RATE_CONST 8000000000ULL
2128 
2129 /* NIX rate calculation in Bits/Sec
2130  *	PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])
2131  *		<< NIX_*_PIR[RATE_EXPONENT]) / 256
2132  *	PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))
2133  *
2134  *	CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])
2135  *		<< NIX_*_CIR[RATE_EXPONENT]) / 256
2136  *	CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))
2137  */
2138 #define NIX_BPF_RATE(policer_timeunit, exponent, mantissa, div_exp)            \
2139 	((NIX_BPF_RATE_CONST * ((256 + (mantissa)) << (exponent))) /           \
2140 	 (((1ull << (div_exp)) * 256 * policer_timeunit)))
2141 
2142 #define NIX_BPF_DEFAULT_ADJUST_MANTISSA 511
2143 #define NIX_BPF_DEFAULT_ADJUST_EXPONENT 0
2144 
2145 /** NIX burst limits */
2146 #define NIX_BPF_MAX_BURST_EXPONENT 0xf
2147 #define NIX_BPF_MAX_BURST_MANTISSA 0xff
2148 
2149 /* NIX burst calculation
2150  *	PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])
2151  *		<< (NIX_*_PIR[BURST_EXPONENT] + 1))
2152  *			/ 256
2153  *
2154  *	CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])
2155  *		<< (NIX_*_CIR[BURST_EXPONENT] + 1))
2156  *			/ 256
2157  */
2158 #define NIX_BPF_BURST(exponent, mantissa)                                      \
2159 	(((256 + (mantissa)) << ((exponent) + 1)) / 256)
2160 
2161 /** Meter burst limits */
2162 #define NIX_BPF_BURST_MIN NIX_BPF_BURST(0, 0)
2163 #define NIX_BPF_BURST_MAX                                                      \
2164 	NIX_BPF_BURST(NIX_BPF_MAX_BURST_EXPONENT, NIX_BPF_MAX_BURST_MANTISSA)
2165 
2166 /* NIX rate limits */
2167 #define NIX_TM_MAX_RATE_DIV_EXP	 12
2168 #define NIX_TM_MAX_RATE_EXPONENT 0xf
2169 #define NIX_TM_MAX_RATE_MANTISSA 0xff
2170 
2171 #define NIX_TM_SHAPER_RATE_CONST ((uint64_t)2E6)
2172 
2173 /* NIX rate calculation in Bits/Sec
2174  *	PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])
2175  *		<< NIX_*_PIR[RATE_EXPONENT]) / 256
2176  *	PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))
2177  *
2178  *	CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])
2179  *		<< NIX_*_CIR[RATE_EXPONENT]) / 256
2180  *	CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))
2181  */
2182 #define NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp)                        \
2183 	((NIX_TM_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent))) /     \
2184 	 (((1ull << (div_exp)) * 256)))
2185 
2186 /* Rate limit in Bits/Sec */
2187 #define NIX_TM_MIN_SHAPER_RATE NIX_TM_SHAPER_RATE(0, 0, NIX_TM_MAX_RATE_DIV_EXP)
2188 
2189 #define NIX_TM_MAX_SHAPER_RATE                                                 \
2190 	NIX_TM_SHAPER_RATE(NIX_TM_MAX_RATE_EXPONENT, NIX_TM_MAX_RATE_MANTISSA, \
2191 			   0)
2192 
2193 #define NIX_TM_MIN_SHAPER_PPS_RATE 25
2194 #define NIX_TM_MAX_SHAPER_PPS_RATE (100ul << 20)
2195 
2196 /* NIX burst limits */
2197 #define NIX_TM_MAX_BURST_EXPONENT      0xful
2198 #define NIX_TM_MAX_BURST_MANTISSA      0x7ffful
2199 #define NIX_CN9K_TM_MAX_BURST_MANTISSA 0xfful
2200 
2201 /* NIX burst calculation
2202  *	PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])
2203  *		<< (NIX_*_PIR[BURST_EXPONENT] + 1))
2204  *			/ 256
2205  *
2206  *	CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])
2207  *		<< (NIX_*_CIR[BURST_EXPONENT] + 1))
2208  *			/ 256
2209  */
2210 #define NIX_TM_SHAPER_BURST(exponent, mantissa)                                \
2211 	(((256ul + (mantissa)) << ((exponent) + 1)) / 256ul)
2212 
2213 /* Burst limit in Bytes */
2214 #define NIX_TM_MIN_SHAPER_BURST NIX_TM_SHAPER_BURST(0, 0)
2215 
2216 #define NIX_TM_MAX_SHAPER_BURST                                                \
2217 	NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT,                         \
2218 			    NIX_TM_MAX_BURST_MANTISSA)
2219 
2220 #define NIX_CN9K_TM_MAX_SHAPER_BURST                                           \
2221 	NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT,                         \
2222 			    NIX_CN9K_TM_MAX_BURST_MANTISSA)
2223 
2224 /* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */
2225 #define NIX_TM_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1)
2226 #define NIX_TM_LENGTH_ADJUST_MAX 255
2227 
2228 #define NIX_TM_TLX_SP_PRIO_MAX	   10
2229 #define NIX_CN9K_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)
2230 #define NIX_TM_RR_WEIGHT_MAX	   (BIT_ULL(14) - 1)
2231 
2232 /* [CN9K, CN10K) */
2233 #define NIX_CN9K_TXSCH_LVL_SMQ_MAX 512
2234 
2235 /* [CN10K, .) */
2236 #define NIX_TXSCH_LVL_SMQ_MAX 832
2237 
2238 /* [CN9K, .) */
2239 #define NIX_TXSCH_LVL_TL4_MAX 512
2240 #define NIX_TXSCH_LVL_TL3_MAX 256
2241 #define NIX_TXSCH_LVL_TL2_MAX 256
2242 #define NIX_TXSCH_LVL_TL1_MAX 28
2243 
2244 #define NIX_CQ_OP_STAT_OP_ERR 63
2245 #define NIX_CQ_OP_STAT_CQ_ERR 46
2246 
2247 #define NIX_RQ_CN10K_SPB_MAX_SIZE 4096
2248 
2249 /* [CN9K, .) */
2250 #define NIX_LSO_SEG_MAX 256
2251 #define NIX_LSO_MPS_MAX (BIT_ULL(14) - 1)
2252 
2253 /* Software defined LSO base format IDX */
2254 #define NIX_LSO_FORMAT_IDX_TSOV4 0
2255 #define NIX_LSO_FORMAT_IDX_TSOV6 1
2256 
2257 /* [CN10K, .) */
2258 #define NIX_SENDSTATALG_MASK	  0x7
2259 #define NIX_SENDSTATALG_SEL_MASK  0x8
2260 #define NIX_SENDSTAT_IOFFSET_MASK 0xFFF
2261 #define NIX_SENDSTAT_OOFFSET_MASK 0xFFF
2262 
2263 #endif /* __NIX_HW_H__ */
2264