1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015 Cavium, Inc
3 */
4
5 #ifndef _RTE_VECT_ARM_H_
6 #define _RTE_VECT_ARM_H_
7
8 #include <stdint.h>
9 #include "generic/rte_vect.h"
10 #include "rte_debug.h"
11 #include "arm_neon.h"
12
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16
17 #define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_MAX
18
19 typedef int32x4_t xmm_t;
20
21 #define XMM_SIZE (sizeof(xmm_t))
22 #define XMM_MASK (XMM_SIZE - 1)
23
24 typedef union rte_xmm {
25 xmm_t x;
26 uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
27 uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
28 uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
29 uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
30 double pd[XMM_SIZE / sizeof(double)];
31 } __rte_aligned(16) rte_xmm_t;
32
33 #if defined(RTE_ARCH_ARM) && defined(RTE_ARCH_32)
34 /* NEON intrinsic vqtbl1q_u8() is not supported in ARMv7-A(AArch32) */
35 static __inline uint8x16_t
vqtbl1q_u8(uint8x16_t a,uint8x16_t b)36 vqtbl1q_u8(uint8x16_t a, uint8x16_t b)
37 {
38 uint8_t i, pos;
39 rte_xmm_t rte_a, rte_b, rte_ret;
40
41 vst1q_u8(rte_a.u8, a);
42 vst1q_u8(rte_b.u8, b);
43
44 for (i = 0; i < 16; i++) {
45 pos = rte_b.u8[i];
46 if (pos < 16)
47 rte_ret.u8[i] = rte_a.u8[pos];
48 else
49 rte_ret.u8[i] = 0;
50 }
51
52 return vld1q_u8(rte_ret.u8);
53 }
54
55 static inline uint16_t
vaddvq_u16(uint16x8_t a)56 vaddvq_u16(uint16x8_t a)
57 {
58 uint32x4_t m = vpaddlq_u16(a);
59 uint64x2_t n = vpaddlq_u32(m);
60 uint64x1_t o = vget_low_u64(n) + vget_high_u64(n);
61
62 return vget_lane_u32((uint32x2_t)o, 0);
63 }
64
65 #endif
66
67 #if (defined(RTE_ARCH_ARM) && defined(RTE_ARCH_32)) || \
68 (defined(RTE_ARCH_ARM64) && RTE_CC_IS_GNU && (GCC_VERSION < 70000))
69 /* NEON intrinsic vcopyq_laneq_u32() is not supported in ARMv7-A(AArch32)
70 * On AArch64, this intrinsic is supported since GCC version 7.
71 */
72 static inline uint32x4_t
vcopyq_laneq_u32(uint32x4_t a,const int lane_a,uint32x4_t b,const int lane_b)73 vcopyq_laneq_u32(uint32x4_t a, const int lane_a,
74 uint32x4_t b, const int lane_b)
75 {
76 return vsetq_lane_u32(vgetq_lane_u32(b, lane_b), a, lane_a);
77 }
78 #endif
79
80 #if defined(RTE_ARCH_ARM64)
81 #if RTE_CC_IS_GNU && (GCC_VERSION < 70000)
82
83 #if (GCC_VERSION < 40900)
84 typedef uint64_t poly64_t;
85 typedef uint64x2_t poly64x2_t;
86 typedef uint8_t poly128_t __attribute__((vector_size(16), aligned(16)));
87
88 static inline uint32x4_t
vceqzq_u32(uint32x4_t a)89 vceqzq_u32(uint32x4_t a)
90 {
91 return (a == 0);
92 }
93 #endif
94
95 /* NEON intrinsic vreinterpretq_u64_p128() is supported since GCC version 7 */
96 static inline uint64x2_t
vreinterpretq_u64_p128(poly128_t x)97 vreinterpretq_u64_p128(poly128_t x)
98 {
99 return (uint64x2_t)x;
100 }
101
102 /* NEON intrinsic vreinterpretq_p64_u64() is supported since GCC version 7 */
103 static inline poly64x2_t
vreinterpretq_p64_u64(uint64x2_t x)104 vreinterpretq_p64_u64(uint64x2_t x)
105 {
106 return (poly64x2_t)x;
107 }
108
109 /* NEON intrinsic vgetq_lane_p64() is supported since GCC version 7 */
110 static inline poly64_t
vgetq_lane_p64(poly64x2_t x,const int lane)111 vgetq_lane_p64(poly64x2_t x, const int lane)
112 {
113 RTE_ASSERT(lane >= 0 && lane <= 1);
114
115 poly64_t *p = (poly64_t *)&x;
116
117 return p[lane];
118 }
119 #endif
120 #endif
121
122 /*
123 * If (0 <= index <= 15), then call the ASIMD ext instruction on the
124 * 128 bit regs v0 and v1 with the appropriate index.
125 *
126 * Else returns a zero vector.
127 */
128 static inline uint8x16_t
vextract(uint8x16_t v0,uint8x16_t v1,const int index)129 vextract(uint8x16_t v0, uint8x16_t v1, const int index)
130 {
131 switch (index) {
132 case 0: return vextq_u8(v0, v1, 0);
133 case 1: return vextq_u8(v0, v1, 1);
134 case 2: return vextq_u8(v0, v1, 2);
135 case 3: return vextq_u8(v0, v1, 3);
136 case 4: return vextq_u8(v0, v1, 4);
137 case 5: return vextq_u8(v0, v1, 5);
138 case 6: return vextq_u8(v0, v1, 6);
139 case 7: return vextq_u8(v0, v1, 7);
140 case 8: return vextq_u8(v0, v1, 8);
141 case 9: return vextq_u8(v0, v1, 9);
142 case 10: return vextq_u8(v0, v1, 10);
143 case 11: return vextq_u8(v0, v1, 11);
144 case 12: return vextq_u8(v0, v1, 12);
145 case 13: return vextq_u8(v0, v1, 13);
146 case 14: return vextq_u8(v0, v1, 14);
147 case 15: return vextq_u8(v0, v1, 15);
148 }
149 return vdupq_n_u8(0);
150 }
151
152 /**
153 * Shifts right 128 bit register by specified number of bytes
154 *
155 * Value of shift parameter must be in range 0 - 16
156 */
157 static inline uint64x2_t
vshift_bytes_right(uint64x2_t reg,const unsigned int shift)158 vshift_bytes_right(uint64x2_t reg, const unsigned int shift)
159 {
160 return vreinterpretq_u64_u8(vextract(
161 vreinterpretq_u8_u64(reg),
162 vdupq_n_u8(0),
163 shift));
164 }
165
166 /**
167 * Shifts left 128 bit register by specified number of bytes
168 *
169 * Value of shift parameter must be in range 0 - 16
170 */
171 static inline uint64x2_t
vshift_bytes_left(uint64x2_t reg,const unsigned int shift)172 vshift_bytes_left(uint64x2_t reg, const unsigned int shift)
173 {
174 return vreinterpretq_u64_u8(vextract(
175 vdupq_n_u8(0),
176 vreinterpretq_u8_u64(reg),
177 16 - shift));
178 }
179
180 #ifdef __cplusplus
181 }
182 #endif
183
184 #endif
185