1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2022 NXP
5 *
6 */
7 #include <unistd.h>
8 #include <stdio.h>
9 #include <string.h>
10 #include <stdlib.h>
11 #include <fcntl.h>
12 #include <errno.h>
13 #include <stdarg.h>
14 #include <inttypes.h>
15 #include <signal.h>
16 #include <pthread.h>
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
20 #include <sys/stat.h>
21 #include <sys/mman.h>
22 #include <sys/epoll.h>
23 #include <sys/eventfd.h>
24 #include <sys/syscall.h>
25
26 #include <rte_mbuf.h>
27 #include <ethdev_driver.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
33 #include <rte_dev.h>
34
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
40
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
42
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
45
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
47
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
52
53 /* Variable to store DPAA2 platform type */
54 uint32_t dpaa2_svr_family;
55
56 /* Variable to store DPAA2 DQRR size */
57 uint8_t dpaa2_dqrr_size;
58 /* Variable to store DPAA2 EQCR size */
59 uint8_t dpaa2_eqcr_size;
60
61 /* Variable to hold the portal_key, once created.*/
62 static pthread_key_t dpaa2_portal_key;
63
64 /*Stashing Macros default for LS208x*/
65 static int dpaa2_core_cluster_base = 0x04;
66 static int dpaa2_cluster_sz = 2;
67
68 /* For LS208X platform There are four clusters with following mapping:
69 * Cluster 1 (ID = x04) : CPU0, CPU1;
70 * Cluster 2 (ID = x05) : CPU2, CPU3;
71 * Cluster 3 (ID = x06) : CPU4, CPU5;
72 * Cluster 4 (ID = x07) : CPU6, CPU7;
73 */
74 /* For LS108X platform There are two clusters with following mapping:
75 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
76 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
77 */
78 /* For LX2160 platform There are four clusters with following mapping:
79 * Cluster 1 (ID = x00) : CPU0, CPU1;
80 * Cluster 2 (ID = x01) : CPU2, CPU3;
81 * Cluster 3 (ID = x02) : CPU4, CPU5;
82 * Cluster 4 (ID = x03) : CPU6, CPU7;
83 * Cluster 1 (ID = x04) : CPU8, CPU9;
84 * Cluster 2 (ID = x05) : CPU10, CP11;
85 * Cluster 3 (ID = x06) : CPU12, CPU13;
86 * Cluster 4 (ID = x07) : CPU14, CPU15;
87 */
88
89 static int
dpaa2_get_core_id(void)90 dpaa2_get_core_id(void)
91 {
92 rte_cpuset_t cpuset;
93 int i, ret, cpu_id = -1;
94
95 ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),
96 &cpuset);
97 if (ret) {
98 DPAA2_BUS_ERR("pthread_getaffinity_np() failed");
99 return ret;
100 }
101
102 for (i = 0; i < RTE_MAX_LCORE; i++) {
103 if (CPU_ISSET(i, &cpuset)) {
104 if (cpu_id == -1)
105 cpu_id = i;
106 else
107 /* Multiple cpus are affined */
108 return -1;
109 }
110 }
111
112 return cpu_id;
113 }
114
115 static int
dpaa2_core_cluster_sdest(int cpu_id)116 dpaa2_core_cluster_sdest(int cpu_id)
117 {
118 int x = cpu_id / dpaa2_cluster_sz;
119
120 return dpaa2_core_cluster_base + x;
121 }
122
123 #ifdef RTE_EVENT_DPAA2
124 static void
dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id,int cpu_id)125 dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int cpu_id)
126 {
127 #define STRING_LEN 28
128 #define COMMAND_LEN 50
129 uint32_t cpu_mask = 1;
130 int ret;
131 size_t len = 0;
132 char *temp = NULL, *token = NULL;
133 char string[STRING_LEN], command[COMMAND_LEN];
134 FILE *file;
135
136 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
137 file = fopen("/proc/interrupts", "r");
138 if (!file) {
139 DPAA2_BUS_WARN("Failed to open /proc/interrupts file");
140 return;
141 }
142 while (getline(&temp, &len, file) != -1) {
143 if ((strstr(temp, string)) != NULL) {
144 token = strtok(temp, ":");
145 break;
146 }
147 }
148
149 if (!token) {
150 DPAA2_BUS_WARN("Failed to get interrupt id for dpio.%d",
151 dpio_id);
152 free(temp);
153 fclose(file);
154 return;
155 }
156
157 cpu_mask = cpu_mask << cpu_id;
158 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
159 cpu_mask, token);
160 ret = system(command);
161 if (ret < 0)
162 DPAA2_BUS_DEBUG(
163 "Failed to affine interrupts on respective core");
164 else
165 DPAA2_BUS_DEBUG(" %s command is executed", command);
166
167 free(temp);
168 fclose(file);
169 }
170
dpaa2_dpio_intr_init(struct dpaa2_dpio_dev * dpio_dev)171 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
172 {
173 struct epoll_event epoll_ev;
174 int eventfd, dpio_epoll_fd, ret;
175 int threshold = 0x3, timeout = 0xFF;
176
177 dpio_epoll_fd = epoll_create(1);
178 ret = rte_dpaa2_intr_enable(dpio_dev->intr_handle, 0);
179 if (ret) {
180 DPAA2_BUS_ERR("Interrupt registration failed");
181 return -1;
182 }
183
184 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
185 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
186
187 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
188 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
189
190 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
191 QBMAN_SWP_INTERRUPT_DQRI);
192 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
193 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
194 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
195 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
196
197 eventfd = rte_intr_fd_get(dpio_dev->intr_handle);
198 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
199 epoll_ev.data.fd = eventfd;
200
201 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
202 if (ret < 0) {
203 DPAA2_BUS_ERR("epoll_ctl failed");
204 return -1;
205 }
206 dpio_dev->epoll_fd = dpio_epoll_fd;
207
208 return 0;
209 }
210
dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev * dpio_dev)211 static void dpaa2_dpio_intr_deinit(struct dpaa2_dpio_dev *dpio_dev)
212 {
213 int ret;
214
215 ret = rte_dpaa2_intr_disable(dpio_dev->intr_handle, 0);
216 if (ret)
217 DPAA2_BUS_ERR("DPIO interrupt disable failed");
218
219 close(dpio_dev->epoll_fd);
220 }
221 #endif
222
223 static int
dpaa2_configure_stashing(struct dpaa2_dpio_dev * dpio_dev,int cpu_id)224 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
225 {
226 int sdest, ret;
227
228 /* Set the STASH Destination depending on Current CPU ID.
229 * Valid values of SDEST are 4,5,6,7. Where,
230 */
231 sdest = dpaa2_core_cluster_sdest(cpu_id);
232 DPAA2_BUS_DEBUG("Portal= %d CPU= %u SDEST= %d",
233 dpio_dev->index, cpu_id, sdest);
234
235 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
236 dpio_dev->token, sdest);
237 if (ret) {
238 DPAA2_BUS_ERR("%d ERROR in SDEST", ret);
239 return -1;
240 }
241
242 #ifdef RTE_EVENT_DPAA2
243 if (dpaa2_dpio_intr_init(dpio_dev)) {
244 DPAA2_BUS_ERR("Interrupt registration failed for dpio");
245 return -1;
246 }
247 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, cpu_id);
248 #endif
249
250 return 0;
251 }
252
dpaa2_put_qbman_swp(struct dpaa2_dpio_dev * dpio_dev)253 static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
254 {
255 if (dpio_dev) {
256 #ifdef RTE_EVENT_DPAA2
257 dpaa2_dpio_intr_deinit(dpio_dev);
258 #endif
259 rte_atomic16_clear(&dpio_dev->ref_count);
260 }
261 }
262
dpaa2_get_qbman_swp(void)263 static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
264 {
265 struct dpaa2_dpio_dev *dpio_dev = NULL;
266 int cpu_id;
267 int ret;
268
269 /* Get DPIO dev handle from list using index */
270 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
271 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
272 break;
273 }
274 if (!dpio_dev) {
275 DPAA2_BUS_ERR("No software portal resource left");
276 return NULL;
277 }
278
279 DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %u",
280 dpio_dev, dpio_dev->index, rte_gettid());
281
282 /* Set the Stashing Destination */
283 cpu_id = dpaa2_get_core_id();
284 if (cpu_id < 0) {
285 DPAA2_BUS_WARN("Thread not affined to a single core");
286 if (dpaa2_svr_family != SVR_LX2160A)
287 qbman_swp_update(dpio_dev->sw_portal, 1);
288 } else {
289 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
290 if (ret) {
291 DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
292 rte_atomic16_clear(&dpio_dev->ref_count);
293 return NULL;
294 }
295 }
296
297 ret = pthread_setspecific(dpaa2_portal_key, (void *)dpio_dev);
298 if (ret) {
299 DPAA2_BUS_ERR("pthread_setspecific failed with ret: %d", ret);
300 dpaa2_put_qbman_swp(dpio_dev);
301 return NULL;
302 }
303
304 return dpio_dev;
305 }
306
307 int
dpaa2_affine_qbman_swp(void)308 dpaa2_affine_qbman_swp(void)
309 {
310 struct dpaa2_dpio_dev *dpio_dev;
311 uint64_t tid = rte_gettid();
312
313 /* Populate the dpaa2_io_portal structure */
314 if (!RTE_PER_LCORE(_dpaa2_io).dpio_dev) {
315 dpio_dev = dpaa2_get_qbman_swp();
316 if (!dpio_dev) {
317 DPAA2_BUS_ERR("Error in software portal allocation");
318 return -1;
319 }
320 RTE_PER_LCORE(_dpaa2_io).dpio_dev = dpio_dev;
321
322 DPAA2_BUS_INFO(
323 "DPAA Portal=%p (%d) is affined to thread %" PRIu64,
324 dpio_dev, dpio_dev->index, tid);
325 }
326 return 0;
327 }
328
329 int
dpaa2_affine_qbman_ethrx_swp(void)330 dpaa2_affine_qbman_ethrx_swp(void)
331 {
332 struct dpaa2_dpio_dev *dpio_dev;
333 uint64_t tid = rte_gettid();
334
335 /* Populate the dpaa2_io_portal structure */
336 if (!RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev) {
337 dpio_dev = dpaa2_get_qbman_swp();
338 if (!dpio_dev) {
339 DPAA2_BUS_ERR("Error in software portal allocation");
340 return -1;
341 }
342 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev = dpio_dev;
343
344 DPAA2_BUS_INFO(
345 "DPAA Portal=%p (%d) is affined for eth rx to thread %"
346 PRIu64, dpio_dev, dpio_dev->index, tid);
347 }
348 return 0;
349 }
350
dpaa2_portal_finish(void * arg)351 static void dpaa2_portal_finish(void *arg)
352 {
353 RTE_SET_USED(arg);
354
355 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).dpio_dev);
356 dpaa2_put_qbman_swp(RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev);
357
358 pthread_setspecific(dpaa2_portal_key, NULL);
359 }
360
361 static int
dpaa2_create_dpio_device(int vdev_fd,struct vfio_device_info * obj_info,int object_id)362 dpaa2_create_dpio_device(int vdev_fd,
363 struct vfio_device_info *obj_info,
364 int object_id)
365 {
366 struct dpaa2_dpio_dev *dpio_dev = NULL;
367 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
368 struct qbman_swp_desc p_des;
369 struct dpio_attr attr;
370 int ret;
371
372 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
373 DPAA2_BUS_ERR("Not sufficient number of DPIO regions");
374 return -1;
375 }
376
377 dpio_dev = rte_zmalloc(NULL, sizeof(struct dpaa2_dpio_dev),
378 RTE_CACHE_LINE_SIZE);
379 if (!dpio_dev) {
380 DPAA2_BUS_ERR("Memory allocation failed for DPIO Device");
381 return -1;
382 }
383
384 dpio_dev->dpio = NULL;
385 dpio_dev->hw_id = object_id;
386 rte_atomic16_init(&dpio_dev->ref_count);
387 /* Using single portal for all devices */
388 dpio_dev->mc_portal = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
389
390 /* Allocate interrupt instance */
391 dpio_dev->intr_handle =
392 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
393 if (!dpio_dev->intr_handle) {
394 DPAA2_BUS_ERR("Failed to allocate intr handle");
395 goto err;
396 }
397
398 dpio_dev->dpio = rte_zmalloc(NULL, sizeof(struct fsl_mc_io),
399 RTE_CACHE_LINE_SIZE);
400 if (!dpio_dev->dpio) {
401 DPAA2_BUS_ERR("Memory allocation failure");
402 goto err;
403 }
404
405 dpio_dev->dpio->regs = dpio_dev->mc_portal;
406 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
407 &dpio_dev->token)) {
408 DPAA2_BUS_ERR("Failed to allocate IO space");
409 goto err;
410 }
411
412 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
413 DPAA2_BUS_ERR("Failed to reset dpio");
414 goto err;
415 }
416
417 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
418 DPAA2_BUS_ERR("Failed to Enable dpio");
419 goto err;
420 }
421
422 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
423 dpio_dev->token, &attr)) {
424 DPAA2_BUS_ERR("DPIO Get attribute failed");
425 goto err;
426 }
427
428 /* find the SoC type for the first time */
429 if (!dpaa2_svr_family) {
430 struct mc_soc_version mc_plat_info = {0};
431
432 if (mc_get_soc_version(dpio_dev->dpio,
433 CMD_PRI_LOW, &mc_plat_info)) {
434 DPAA2_BUS_ERR("Unable to get SoC version information");
435 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
436 dpaa2_core_cluster_base = 0x02;
437 dpaa2_cluster_sz = 4;
438 DPAA2_BUS_DEBUG("LS108x (A53) Platform Detected");
439 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
440 dpaa2_core_cluster_base = 0x00;
441 dpaa2_cluster_sz = 2;
442 DPAA2_BUS_DEBUG("LX2160 Platform Detected");
443 }
444 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
445
446 if (dpaa2_svr_family == SVR_LX2160A) {
447 dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;
448 dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;
449 } else {
450 dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;
451 dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;
452 }
453 }
454
455 if (dpaa2_svr_family == SVR_LX2160A)
456 reg_info.index = DPAA2_SWP_CENA_MEM_REGION;
457 else
458 reg_info.index = DPAA2_SWP_CENA_REGION;
459
460 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
461 DPAA2_BUS_ERR("vfio: error getting region info");
462 goto err;
463 }
464
465 dpio_dev->ce_size = reg_info.size;
466 dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
467 PROT_WRITE | PROT_READ, MAP_SHARED,
468 vdev_fd, reg_info.offset);
469
470 reg_info.index = DPAA2_SWP_CINH_REGION;
471 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
472 DPAA2_BUS_ERR("vfio: error getting region info");
473 goto err;
474 }
475
476 dpio_dev->ci_size = reg_info.size;
477 dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
478 PROT_WRITE | PROT_READ, MAP_SHARED,
479 vdev_fd, reg_info.offset);
480
481 /* Configure & setup SW portal */
482 p_des.block = NULL;
483 p_des.idx = attr.qbman_portal_id;
484 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
485 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
486 p_des.irq = -1;
487 p_des.qman_version = attr.qbman_version;
488 p_des.eqcr_mode = qman_eqcr_vb_ring;
489 p_des.cena_access_mode = qman_cena_fastest_access;
490
491 dpio_dev->sw_portal = qbman_swp_init(&p_des);
492 if (dpio_dev->sw_portal == NULL) {
493 DPAA2_BUS_ERR("QBMan SW Portal Init failed");
494 goto err;
495 }
496
497 io_space_count++;
498 dpio_dev->index = io_space_count;
499
500 if (rte_dpaa2_vfio_setup_intr(dpio_dev->intr_handle, vdev_fd, 1)) {
501 DPAA2_BUS_ERR("Fail to setup interrupt for %d",
502 dpio_dev->hw_id);
503 goto err;
504 }
505
506 dpio_dev->eqresp = rte_zmalloc(NULL, MAX_EQ_RESP_ENTRIES *
507 (sizeof(struct qbman_result) +
508 sizeof(struct eqresp_metadata)),
509 RTE_CACHE_LINE_SIZE);
510 if (!dpio_dev->eqresp) {
511 DPAA2_BUS_ERR("Memory allocation failed for eqresp");
512 goto err;
513 }
514 dpio_dev->eqresp_meta = (struct eqresp_metadata *)(dpio_dev->eqresp +
515 MAX_EQ_RESP_ENTRIES);
516
517
518 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
519
520 if (!dpaa2_portal_key) {
521 /* create the key, supplying a function that'll be invoked
522 * when a portal affined thread will be deleted.
523 */
524 ret = pthread_key_create(&dpaa2_portal_key,
525 dpaa2_portal_finish);
526 if (ret) {
527 DPAA2_BUS_DEBUG("Unable to create pthread key (%d)",
528 ret);
529 goto err;
530 }
531 }
532
533 return 0;
534
535 err:
536 if (dpio_dev->dpio) {
537 if (dpio_dev->token) {
538 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
539 dpio_dev->token);
540 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
541 dpio_dev->token);
542 }
543
544 rte_free(dpio_dev->eqresp);
545 rte_free(dpio_dev->dpio);
546 }
547
548 rte_intr_instance_free(dpio_dev->intr_handle);
549 rte_free(dpio_dev);
550
551 /* For each element in the list, cleanup */
552 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
553 if (dpio_dev->dpio) {
554 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
555 dpio_dev->token);
556 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
557 dpio_dev->token);
558 rte_free(dpio_dev->dpio);
559 }
560 rte_intr_instance_free(dpio_dev->intr_handle);
561 rte_free(dpio_dev);
562 }
563
564 /* Preventing re-use of the list with old entries */
565 TAILQ_INIT(&dpio_dev_list);
566
567 return -1;
568 }
569
570 void
dpaa2_free_dq_storage(struct queue_storage_info_t * q_storage)571 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
572 {
573 int i = 0;
574
575 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
576 rte_free(q_storage->dq_storage[i]);
577 }
578 }
579
580 int
dpaa2_alloc_dq_storage(struct queue_storage_info_t * q_storage)581 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
582 {
583 int i = 0;
584
585 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
586 q_storage->dq_storage[i] = rte_malloc(NULL,
587 dpaa2_dqrr_size * sizeof(struct qbman_result),
588 RTE_CACHE_LINE_SIZE);
589 if (!q_storage->dq_storage[i])
590 goto fail;
591 }
592 return 0;
593 fail:
594 while (--i >= 0)
595 rte_free(q_storage->dq_storage[i]);
596
597 return -1;
598 }
599
600 uint32_t
dpaa2_free_eq_descriptors(void)601 dpaa2_free_eq_descriptors(void)
602 {
603 struct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;
604 struct qbman_result *eqresp;
605 struct eqresp_metadata *eqresp_meta;
606 struct dpaa2_queue *txq;
607
608 while (dpio_dev->eqresp_ci != dpio_dev->eqresp_pi) {
609 eqresp = &dpio_dev->eqresp[dpio_dev->eqresp_ci];
610 eqresp_meta = &dpio_dev->eqresp_meta[dpio_dev->eqresp_ci];
611
612 if (!qbman_result_eqresp_rspid(eqresp))
613 break;
614
615 if (qbman_result_eqresp_rc(eqresp)) {
616 txq = eqresp_meta->dpaa2_q;
617 txq->cb_eqresp_free(dpio_dev->eqresp_ci, txq);
618 }
619 qbman_result_eqresp_set_rspid(eqresp, 0);
620
621 dpio_dev->eqresp_ci + 1 < MAX_EQ_RESP_ENTRIES ?
622 dpio_dev->eqresp_ci++ : (dpio_dev->eqresp_ci = 0);
623 }
624
625 /* Return 1 less entry so that PI and CI are never same in a
626 * case there all the EQ responses are in use.
627 */
628 if (dpio_dev->eqresp_ci > dpio_dev->eqresp_pi)
629 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi - 1;
630 else
631 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi +
632 MAX_EQ_RESP_ENTRIES - 1;
633 }
634
635 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
636 .dev_type = DPAA2_IO,
637 .create = dpaa2_create_dpio_device,
638 };
639
640 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);
641