1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 /* date: Wed Aug 25 14:37:06 2021 */ 7 8 #include "ulp_template_db_enum.h" 9 #include "ulp_template_db_field.h" 10 #include "ulp_template_struct.h" 11 #include "ulp_template_db_tbl.h" 12 13 /* 14 * Action signature table: 15 * maps hash id to ulp_act_match_list[] index 16 */ 17 uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { 18 [BNXT_ULP_ACT_HID_0000] = 1, 19 [BNXT_ULP_ACT_HID_0001] = 2, 20 [BNXT_ULP_ACT_HID_0400] = 3, 21 [BNXT_ULP_ACT_HID_01ab] = 4, 22 [BNXT_ULP_ACT_HID_0010] = 5, 23 [BNXT_ULP_ACT_HID_05ab] = 6, 24 [BNXT_ULP_ACT_HID_01bb] = 7, 25 [BNXT_ULP_ACT_HID_0002] = 8, 26 [BNXT_ULP_ACT_HID_0003] = 9, 27 [BNXT_ULP_ACT_HID_0402] = 10, 28 [BNXT_ULP_ACT_HID_01ad] = 11, 29 [BNXT_ULP_ACT_HID_0012] = 12, 30 [BNXT_ULP_ACT_HID_05ad] = 13, 31 [BNXT_ULP_ACT_HID_01bd] = 14, 32 [BNXT_ULP_ACT_HID_0613] = 15, 33 [BNXT_ULP_ACT_HID_02a9] = 16, 34 [BNXT_ULP_ACT_HID_0054] = 17, 35 [BNXT_ULP_ACT_HID_0622] = 18, 36 [BNXT_ULP_ACT_HID_0454] = 19, 37 [BNXT_ULP_ACT_HID_0064] = 20, 38 [BNXT_ULP_ACT_HID_0614] = 21, 39 [BNXT_ULP_ACT_HID_0615] = 22, 40 [BNXT_ULP_ACT_HID_02ab] = 23, 41 [BNXT_ULP_ACT_HID_0056] = 24, 42 [BNXT_ULP_ACT_HID_0624] = 25, 43 [BNXT_ULP_ACT_HID_0456] = 26, 44 [BNXT_ULP_ACT_HID_0066] = 27, 45 [BNXT_ULP_ACT_HID_048d] = 28, 46 [BNXT_ULP_ACT_HID_048f] = 29, 47 [BNXT_ULP_ACT_HID_04bc] = 30, 48 [BNXT_ULP_ACT_HID_00a9] = 31, 49 [BNXT_ULP_ACT_HID_020f] = 32, 50 [BNXT_ULP_ACT_HID_0153] = 33, 51 [BNXT_ULP_ACT_HID_04a9] = 34, 52 [BNXT_ULP_ACT_HID_01fc] = 35, 53 [BNXT_ULP_ACT_HID_04be] = 36, 54 [BNXT_ULP_ACT_HID_00ab] = 37, 55 [BNXT_ULP_ACT_HID_0211] = 38, 56 [BNXT_ULP_ACT_HID_0155] = 39, 57 [BNXT_ULP_ACT_HID_04ab] = 40, 58 [BNXT_ULP_ACT_HID_01fe] = 41, 59 [BNXT_ULP_ACT_HID_0667] = 42, 60 [BNXT_ULP_ACT_HID_0254] = 43, 61 [BNXT_ULP_ACT_HID_03ba] = 44, 62 [BNXT_ULP_ACT_HID_02fe] = 45, 63 [BNXT_ULP_ACT_HID_0654] = 46, 64 [BNXT_ULP_ACT_HID_03a7] = 47, 65 [BNXT_ULP_ACT_HID_0669] = 48, 66 [BNXT_ULP_ACT_HID_0256] = 49, 67 [BNXT_ULP_ACT_HID_03bc] = 50, 68 [BNXT_ULP_ACT_HID_0300] = 51, 69 [BNXT_ULP_ACT_HID_0656] = 52, 70 [BNXT_ULP_ACT_HID_03a9] = 53, 71 [BNXT_ULP_ACT_HID_021b] = 54, 72 [BNXT_ULP_ACT_HID_021c] = 55, 73 [BNXT_ULP_ACT_HID_021e] = 56, 74 [BNXT_ULP_ACT_HID_063f] = 57, 75 [BNXT_ULP_ACT_HID_0510] = 58, 76 [BNXT_ULP_ACT_HID_03c6] = 59, 77 [BNXT_ULP_ACT_HID_0082] = 60, 78 [BNXT_ULP_ACT_HID_06bb] = 61, 79 [BNXT_ULP_ACT_HID_021d] = 62, 80 [BNXT_ULP_ACT_HID_0641] = 63, 81 [BNXT_ULP_ACT_HID_0512] = 64, 82 [BNXT_ULP_ACT_HID_03c8] = 65, 83 [BNXT_ULP_ACT_HID_0084] = 66, 84 [BNXT_ULP_ACT_HID_06bd] = 67, 85 [BNXT_ULP_ACT_HID_06d7] = 68, 86 [BNXT_ULP_ACT_HID_02c4] = 69, 87 [BNXT_ULP_ACT_HID_042a] = 70, 88 [BNXT_ULP_ACT_HID_036e] = 71, 89 [BNXT_ULP_ACT_HID_06c4] = 72, 90 [BNXT_ULP_ACT_HID_0417] = 73, 91 [BNXT_ULP_ACT_HID_06d9] = 74, 92 [BNXT_ULP_ACT_HID_02c6] = 75, 93 [BNXT_ULP_ACT_HID_042c] = 76, 94 [BNXT_ULP_ACT_HID_0370] = 77, 95 [BNXT_ULP_ACT_HID_06c6] = 78, 96 [BNXT_ULP_ACT_HID_0419] = 79, 97 [BNXT_ULP_ACT_HID_0119] = 80, 98 [BNXT_ULP_ACT_HID_046f] = 81, 99 [BNXT_ULP_ACT_HID_05d5] = 82, 100 [BNXT_ULP_ACT_HID_0519] = 83, 101 [BNXT_ULP_ACT_HID_0106] = 84, 102 [BNXT_ULP_ACT_HID_05c2] = 85, 103 [BNXT_ULP_ACT_HID_011b] = 86, 104 [BNXT_ULP_ACT_HID_0471] = 87, 105 [BNXT_ULP_ACT_HID_05d7] = 88, 106 [BNXT_ULP_ACT_HID_051b] = 89, 107 [BNXT_ULP_ACT_HID_0108] = 90, 108 [BNXT_ULP_ACT_HID_05c4] = 91, 109 [BNXT_ULP_ACT_HID_00a2] = 92, 110 [BNXT_ULP_ACT_HID_00a4] = 93 111 }; 112 113 /* Array for the act matcher list */ 114 struct bnxt_ulp_act_match_info ulp_act_match_list[] = { 115 [1] = { 116 .act_hid = BNXT_ULP_ACT_HID_0000, 117 .act_pattern_id = 0, 118 .app_sig = 0, 119 .act_sig = { .bits = 120 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 121 .act_tid = 1 122 }, 123 [2] = { 124 .act_hid = BNXT_ULP_ACT_HID_0001, 125 .act_pattern_id = 1, 126 .app_sig = 0, 127 .act_sig = { .bits = 128 BNXT_ULP_ACT_BIT_DROP | 129 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 130 .act_tid = 1 131 }, 132 [3] = { 133 .act_hid = BNXT_ULP_ACT_HID_0400, 134 .act_pattern_id = 2, 135 .app_sig = 0, 136 .act_sig = { .bits = 137 BNXT_ULP_ACT_BIT_POP_VLAN | 138 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 139 .act_tid = 1 140 }, 141 [4] = { 142 .act_hid = BNXT_ULP_ACT_HID_01ab, 143 .act_pattern_id = 3, 144 .app_sig = 0, 145 .act_sig = { .bits = 146 BNXT_ULP_ACT_BIT_DEC_TTL | 147 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 148 .act_tid = 1 149 }, 150 [5] = { 151 .act_hid = BNXT_ULP_ACT_HID_0010, 152 .act_pattern_id = 4, 153 .app_sig = 0, 154 .act_sig = { .bits = 155 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 156 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 157 .act_tid = 1 158 }, 159 [6] = { 160 .act_hid = BNXT_ULP_ACT_HID_05ab, 161 .act_pattern_id = 5, 162 .app_sig = 0, 163 .act_sig = { .bits = 164 BNXT_ULP_ACT_BIT_DEC_TTL | 165 BNXT_ULP_ACT_BIT_POP_VLAN | 166 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 167 .act_tid = 1 168 }, 169 [7] = { 170 .act_hid = BNXT_ULP_ACT_HID_01bb, 171 .act_pattern_id = 6, 172 .app_sig = 0, 173 .act_sig = { .bits = 174 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 175 BNXT_ULP_ACT_BIT_DEC_TTL | 176 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 177 .act_tid = 1 178 }, 179 [8] = { 180 .act_hid = BNXT_ULP_ACT_HID_0002, 181 .act_pattern_id = 7, 182 .app_sig = 0, 183 .act_sig = { .bits = 184 BNXT_ULP_ACT_BIT_COUNT | 185 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 186 .act_tid = 1 187 }, 188 [9] = { 189 .act_hid = BNXT_ULP_ACT_HID_0003, 190 .act_pattern_id = 8, 191 .app_sig = 0, 192 .act_sig = { .bits = 193 BNXT_ULP_ACT_BIT_COUNT | 194 BNXT_ULP_ACT_BIT_DROP | 195 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 196 .act_tid = 1 197 }, 198 [10] = { 199 .act_hid = BNXT_ULP_ACT_HID_0402, 200 .act_pattern_id = 9, 201 .app_sig = 0, 202 .act_sig = { .bits = 203 BNXT_ULP_ACT_BIT_COUNT | 204 BNXT_ULP_ACT_BIT_POP_VLAN | 205 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 206 .act_tid = 1 207 }, 208 [11] = { 209 .act_hid = BNXT_ULP_ACT_HID_01ad, 210 .act_pattern_id = 10, 211 .app_sig = 0, 212 .act_sig = { .bits = 213 BNXT_ULP_ACT_BIT_COUNT | 214 BNXT_ULP_ACT_BIT_DEC_TTL | 215 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 216 .act_tid = 1 217 }, 218 [12] = { 219 .act_hid = BNXT_ULP_ACT_HID_0012, 220 .act_pattern_id = 11, 221 .app_sig = 0, 222 .act_sig = { .bits = 223 BNXT_ULP_ACT_BIT_COUNT | 224 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 225 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 226 .act_tid = 1 227 }, 228 [13] = { 229 .act_hid = BNXT_ULP_ACT_HID_05ad, 230 .act_pattern_id = 12, 231 .app_sig = 0, 232 .act_sig = { .bits = 233 BNXT_ULP_ACT_BIT_COUNT | 234 BNXT_ULP_ACT_BIT_DEC_TTL | 235 BNXT_ULP_ACT_BIT_POP_VLAN | 236 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 237 .act_tid = 1 238 }, 239 [14] = { 240 .act_hid = BNXT_ULP_ACT_HID_01bd, 241 .act_pattern_id = 13, 242 .app_sig = 0, 243 .act_sig = { .bits = 244 BNXT_ULP_ACT_BIT_COUNT | 245 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 246 BNXT_ULP_ACT_BIT_DEC_TTL | 247 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 248 .act_tid = 1 249 }, 250 [15] = { 251 .act_hid = BNXT_ULP_ACT_HID_0613, 252 .act_pattern_id = 14, 253 .app_sig = 0, 254 .act_sig = { .bits = 255 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 256 BNXT_ULP_ACT_BIT_DROP | 257 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 258 .act_tid = 1 259 }, 260 [16] = { 261 .act_hid = BNXT_ULP_ACT_HID_02a9, 262 .act_pattern_id = 15, 263 .app_sig = 0, 264 .act_sig = { .bits = 265 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 266 BNXT_ULP_ACT_BIT_POP_VLAN | 267 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 268 .act_tid = 1 269 }, 270 [17] = { 271 .act_hid = BNXT_ULP_ACT_HID_0054, 272 .act_pattern_id = 16, 273 .app_sig = 0, 274 .act_sig = { .bits = 275 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 276 BNXT_ULP_ACT_BIT_DEC_TTL | 277 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 278 .act_tid = 1 279 }, 280 [18] = { 281 .act_hid = BNXT_ULP_ACT_HID_0622, 282 .act_pattern_id = 17, 283 .app_sig = 0, 284 .act_sig = { .bits = 285 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 286 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 287 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 288 .act_tid = 1 289 }, 290 [19] = { 291 .act_hid = BNXT_ULP_ACT_HID_0454, 292 .act_pattern_id = 18, 293 .app_sig = 0, 294 .act_sig = { .bits = 295 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 296 BNXT_ULP_ACT_BIT_DEC_TTL | 297 BNXT_ULP_ACT_BIT_POP_VLAN | 298 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 299 .act_tid = 1 300 }, 301 [20] = { 302 .act_hid = BNXT_ULP_ACT_HID_0064, 303 .act_pattern_id = 19, 304 .app_sig = 0, 305 .act_sig = { .bits = 306 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 307 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 308 BNXT_ULP_ACT_BIT_DEC_TTL | 309 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 310 .act_tid = 1 311 }, 312 [21] = { 313 .act_hid = BNXT_ULP_ACT_HID_0614, 314 .act_pattern_id = 20, 315 .app_sig = 0, 316 .act_sig = { .bits = 317 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 318 BNXT_ULP_ACT_BIT_COUNT | 319 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 320 .act_tid = 1 321 }, 322 [22] = { 323 .act_hid = BNXT_ULP_ACT_HID_0615, 324 .act_pattern_id = 21, 325 .app_sig = 0, 326 .act_sig = { .bits = 327 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 328 BNXT_ULP_ACT_BIT_COUNT | 329 BNXT_ULP_ACT_BIT_DROP | 330 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 331 .act_tid = 1 332 }, 333 [23] = { 334 .act_hid = BNXT_ULP_ACT_HID_02ab, 335 .act_pattern_id = 22, 336 .app_sig = 0, 337 .act_sig = { .bits = 338 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 339 BNXT_ULP_ACT_BIT_COUNT | 340 BNXT_ULP_ACT_BIT_POP_VLAN | 341 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 342 .act_tid = 1 343 }, 344 [24] = { 345 .act_hid = BNXT_ULP_ACT_HID_0056, 346 .act_pattern_id = 23, 347 .app_sig = 0, 348 .act_sig = { .bits = 349 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 350 BNXT_ULP_ACT_BIT_COUNT | 351 BNXT_ULP_ACT_BIT_DEC_TTL | 352 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 353 .act_tid = 1 354 }, 355 [25] = { 356 .act_hid = BNXT_ULP_ACT_HID_0624, 357 .act_pattern_id = 24, 358 .app_sig = 0, 359 .act_sig = { .bits = 360 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 361 BNXT_ULP_ACT_BIT_COUNT | 362 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 363 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 364 .act_tid = 1 365 }, 366 [26] = { 367 .act_hid = BNXT_ULP_ACT_HID_0456, 368 .act_pattern_id = 25, 369 .app_sig = 0, 370 .act_sig = { .bits = 371 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 372 BNXT_ULP_ACT_BIT_COUNT | 373 BNXT_ULP_ACT_BIT_DEC_TTL | 374 BNXT_ULP_ACT_BIT_POP_VLAN | 375 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 376 .act_tid = 1 377 }, 378 [27] = { 379 .act_hid = BNXT_ULP_ACT_HID_0066, 380 .act_pattern_id = 26, 381 .app_sig = 0, 382 .act_sig = { .bits = 383 BNXT_ULP_ACT_BIT_SHARED_SAMPLE | 384 BNXT_ULP_ACT_BIT_COUNT | 385 BNXT_ULP_ACT_BIT_VXLAN_DECAP | 386 BNXT_ULP_ACT_BIT_DEC_TTL | 387 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 388 .act_tid = 1 389 }, 390 [28] = { 391 .act_hid = BNXT_ULP_ACT_HID_048d, 392 .act_pattern_id = 0, 393 .app_sig = 0, 394 .act_sig = { .bits = 395 BNXT_ULP_ACT_BIT_SHARED | 396 BNXT_ULP_ACT_BIT_SAMPLE | 397 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 398 .act_tid = 2 399 }, 400 [29] = { 401 .act_hid = BNXT_ULP_ACT_HID_048f, 402 .act_pattern_id = 1, 403 .app_sig = 0, 404 .act_sig = { .bits = 405 BNXT_ULP_ACT_BIT_SHARED | 406 BNXT_ULP_ACT_BIT_SAMPLE | 407 BNXT_ULP_ACT_BIT_COUNT | 408 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 409 .act_tid = 2 410 }, 411 [30] = { 412 .act_hid = BNXT_ULP_ACT_HID_04bc, 413 .act_pattern_id = 0, 414 .app_sig = 0, 415 .act_sig = { .bits = 416 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 417 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 418 .act_tid = 3 419 }, 420 [31] = { 421 .act_hid = BNXT_ULP_ACT_HID_00a9, 422 .act_pattern_id = 1, 423 .app_sig = 0, 424 .act_sig = { .bits = 425 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 426 BNXT_ULP_ACT_BIT_SET_TP_SRC | 427 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 428 .act_tid = 3 429 }, 430 [32] = { 431 .act_hid = BNXT_ULP_ACT_HID_020f, 432 .act_pattern_id = 2, 433 .app_sig = 0, 434 .act_sig = { .bits = 435 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 436 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 437 .act_tid = 3 438 }, 439 [33] = { 440 .act_hid = BNXT_ULP_ACT_HID_0153, 441 .act_pattern_id = 3, 442 .app_sig = 0, 443 .act_sig = { .bits = 444 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 445 BNXT_ULP_ACT_BIT_SET_TP_DST | 446 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 447 .act_tid = 3 448 }, 449 [34] = { 450 .act_hid = BNXT_ULP_ACT_HID_04a9, 451 .act_pattern_id = 4, 452 .app_sig = 0, 453 .act_sig = { .bits = 454 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 455 BNXT_ULP_ACT_BIT_SET_TP_SRC | 456 BNXT_ULP_ACT_BIT_SET_TP_DST | 457 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 458 .act_tid = 3 459 }, 460 [35] = { 461 .act_hid = BNXT_ULP_ACT_HID_01fc, 462 .act_pattern_id = 5, 463 .app_sig = 0, 464 .act_sig = { .bits = 465 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 466 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 467 BNXT_ULP_ACT_BIT_SET_TP_SRC | 468 BNXT_ULP_ACT_BIT_SET_TP_DST | 469 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 470 .act_tid = 3 471 }, 472 [36] = { 473 .act_hid = BNXT_ULP_ACT_HID_04be, 474 .act_pattern_id = 6, 475 .app_sig = 0, 476 .act_sig = { .bits = 477 BNXT_ULP_ACT_BIT_COUNT | 478 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 479 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 480 .act_tid = 3 481 }, 482 [37] = { 483 .act_hid = BNXT_ULP_ACT_HID_00ab, 484 .act_pattern_id = 7, 485 .app_sig = 0, 486 .act_sig = { .bits = 487 BNXT_ULP_ACT_BIT_COUNT | 488 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 489 BNXT_ULP_ACT_BIT_SET_TP_SRC | 490 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 491 .act_tid = 3 492 }, 493 [38] = { 494 .act_hid = BNXT_ULP_ACT_HID_0211, 495 .act_pattern_id = 8, 496 .app_sig = 0, 497 .act_sig = { .bits = 498 BNXT_ULP_ACT_BIT_COUNT | 499 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 500 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 501 .act_tid = 3 502 }, 503 [39] = { 504 .act_hid = BNXT_ULP_ACT_HID_0155, 505 .act_pattern_id = 9, 506 .app_sig = 0, 507 .act_sig = { .bits = 508 BNXT_ULP_ACT_BIT_COUNT | 509 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 510 BNXT_ULP_ACT_BIT_SET_TP_DST | 511 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 512 .act_tid = 3 513 }, 514 [40] = { 515 .act_hid = BNXT_ULP_ACT_HID_04ab, 516 .act_pattern_id = 10, 517 .app_sig = 0, 518 .act_sig = { .bits = 519 BNXT_ULP_ACT_BIT_COUNT | 520 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 521 BNXT_ULP_ACT_BIT_SET_TP_SRC | 522 BNXT_ULP_ACT_BIT_SET_TP_DST | 523 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 524 .act_tid = 3 525 }, 526 [41] = { 527 .act_hid = BNXT_ULP_ACT_HID_01fe, 528 .act_pattern_id = 11, 529 .app_sig = 0, 530 .act_sig = { .bits = 531 BNXT_ULP_ACT_BIT_COUNT | 532 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 533 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 534 BNXT_ULP_ACT_BIT_SET_TP_SRC | 535 BNXT_ULP_ACT_BIT_SET_TP_DST | 536 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 537 .act_tid = 3 538 }, 539 [42] = { 540 .act_hid = BNXT_ULP_ACT_HID_0667, 541 .act_pattern_id = 12, 542 .app_sig = 0, 543 .act_sig = { .bits = 544 BNXT_ULP_ACT_BIT_DEC_TTL | 545 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 546 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 547 .act_tid = 3 548 }, 549 [43] = { 550 .act_hid = BNXT_ULP_ACT_HID_0254, 551 .act_pattern_id = 13, 552 .app_sig = 0, 553 .act_sig = { .bits = 554 BNXT_ULP_ACT_BIT_DEC_TTL | 555 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 556 BNXT_ULP_ACT_BIT_SET_TP_SRC | 557 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 558 .act_tid = 3 559 }, 560 [44] = { 561 .act_hid = BNXT_ULP_ACT_HID_03ba, 562 .act_pattern_id = 14, 563 .app_sig = 0, 564 .act_sig = { .bits = 565 BNXT_ULP_ACT_BIT_DEC_TTL | 566 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 567 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 568 .act_tid = 3 569 }, 570 [45] = { 571 .act_hid = BNXT_ULP_ACT_HID_02fe, 572 .act_pattern_id = 15, 573 .app_sig = 0, 574 .act_sig = { .bits = 575 BNXT_ULP_ACT_BIT_DEC_TTL | 576 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 577 BNXT_ULP_ACT_BIT_SET_TP_DST | 578 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 579 .act_tid = 3 580 }, 581 [46] = { 582 .act_hid = BNXT_ULP_ACT_HID_0654, 583 .act_pattern_id = 16, 584 .app_sig = 0, 585 .act_sig = { .bits = 586 BNXT_ULP_ACT_BIT_DEC_TTL | 587 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 588 BNXT_ULP_ACT_BIT_SET_TP_SRC | 589 BNXT_ULP_ACT_BIT_SET_TP_DST | 590 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 591 .act_tid = 3 592 }, 593 [47] = { 594 .act_hid = BNXT_ULP_ACT_HID_03a7, 595 .act_pattern_id = 17, 596 .app_sig = 0, 597 .act_sig = { .bits = 598 BNXT_ULP_ACT_BIT_DEC_TTL | 599 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 600 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 601 BNXT_ULP_ACT_BIT_SET_TP_SRC | 602 BNXT_ULP_ACT_BIT_SET_TP_DST | 603 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 604 .act_tid = 3 605 }, 606 [48] = { 607 .act_hid = BNXT_ULP_ACT_HID_0669, 608 .act_pattern_id = 18, 609 .app_sig = 0, 610 .act_sig = { .bits = 611 BNXT_ULP_ACT_BIT_DEC_TTL | 612 BNXT_ULP_ACT_BIT_COUNT | 613 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 614 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 615 .act_tid = 3 616 }, 617 [49] = { 618 .act_hid = BNXT_ULP_ACT_HID_0256, 619 .act_pattern_id = 19, 620 .app_sig = 0, 621 .act_sig = { .bits = 622 BNXT_ULP_ACT_BIT_DEC_TTL | 623 BNXT_ULP_ACT_BIT_COUNT | 624 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 625 BNXT_ULP_ACT_BIT_SET_TP_SRC | 626 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 627 .act_tid = 3 628 }, 629 [50] = { 630 .act_hid = BNXT_ULP_ACT_HID_03bc, 631 .act_pattern_id = 20, 632 .app_sig = 0, 633 .act_sig = { .bits = 634 BNXT_ULP_ACT_BIT_DEC_TTL | 635 BNXT_ULP_ACT_BIT_COUNT | 636 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 637 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 638 .act_tid = 3 639 }, 640 [51] = { 641 .act_hid = BNXT_ULP_ACT_HID_0300, 642 .act_pattern_id = 21, 643 .app_sig = 0, 644 .act_sig = { .bits = 645 BNXT_ULP_ACT_BIT_DEC_TTL | 646 BNXT_ULP_ACT_BIT_COUNT | 647 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 648 BNXT_ULP_ACT_BIT_SET_TP_DST | 649 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 650 .act_tid = 3 651 }, 652 [52] = { 653 .act_hid = BNXT_ULP_ACT_HID_0656, 654 .act_pattern_id = 22, 655 .app_sig = 0, 656 .act_sig = { .bits = 657 BNXT_ULP_ACT_BIT_DEC_TTL | 658 BNXT_ULP_ACT_BIT_COUNT | 659 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 660 BNXT_ULP_ACT_BIT_SET_TP_SRC | 661 BNXT_ULP_ACT_BIT_SET_TP_DST | 662 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 663 .act_tid = 3 664 }, 665 [53] = { 666 .act_hid = BNXT_ULP_ACT_HID_03a9, 667 .act_pattern_id = 23, 668 .app_sig = 0, 669 .act_sig = { .bits = 670 BNXT_ULP_ACT_BIT_DEC_TTL | 671 BNXT_ULP_ACT_BIT_COUNT | 672 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 673 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 674 BNXT_ULP_ACT_BIT_SET_TP_SRC | 675 BNXT_ULP_ACT_BIT_SET_TP_DST | 676 BNXT_ULP_FLOW_DIR_BITMASK_ING }, 677 .act_tid = 3 678 }, 679 [54] = { 680 .act_hid = BNXT_ULP_ACT_HID_021b, 681 .act_pattern_id = 0, 682 .app_sig = 0, 683 .act_sig = { .bits = 684 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 685 .act_tid = 4 686 }, 687 [55] = { 688 .act_hid = BNXT_ULP_ACT_HID_021c, 689 .act_pattern_id = 1, 690 .app_sig = 0, 691 .act_sig = { .bits = 692 BNXT_ULP_ACT_BIT_DROP | 693 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 694 .act_tid = 4 695 }, 696 [56] = { 697 .act_hid = BNXT_ULP_ACT_HID_021e, 698 .act_pattern_id = 2, 699 .app_sig = 0, 700 .act_sig = { .bits = 701 BNXT_ULP_ACT_BIT_DROP | 702 BNXT_ULP_ACT_BIT_COUNT | 703 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 704 .act_tid = 4 705 }, 706 [57] = { 707 .act_hid = BNXT_ULP_ACT_HID_063f, 708 .act_pattern_id = 3, 709 .app_sig = 0, 710 .act_sig = { .bits = 711 BNXT_ULP_ACT_BIT_SET_VLAN_PCP | 712 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 713 BNXT_ULP_ACT_BIT_PUSH_VLAN | 714 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 715 .act_tid = 4 716 }, 717 [58] = { 718 .act_hid = BNXT_ULP_ACT_HID_0510, 719 .act_pattern_id = 4, 720 .app_sig = 0, 721 .act_sig = { .bits = 722 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 723 BNXT_ULP_ACT_BIT_PUSH_VLAN | 724 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 725 .act_tid = 4 726 }, 727 [59] = { 728 .act_hid = BNXT_ULP_ACT_HID_03c6, 729 .act_pattern_id = 5, 730 .app_sig = 0, 731 .act_sig = { .bits = 732 BNXT_ULP_ACT_BIT_DEC_TTL | 733 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 734 .act_tid = 4 735 }, 736 [60] = { 737 .act_hid = BNXT_ULP_ACT_HID_0082, 738 .act_pattern_id = 6, 739 .app_sig = 0, 740 .act_sig = { .bits = 741 BNXT_ULP_ACT_BIT_DEC_TTL | 742 BNXT_ULP_ACT_BIT_SET_VLAN_PCP | 743 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 744 BNXT_ULP_ACT_BIT_PUSH_VLAN | 745 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 746 .act_tid = 4 747 }, 748 [61] = { 749 .act_hid = BNXT_ULP_ACT_HID_06bb, 750 .act_pattern_id = 7, 751 .app_sig = 0, 752 .act_sig = { .bits = 753 BNXT_ULP_ACT_BIT_DEC_TTL | 754 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 755 BNXT_ULP_ACT_BIT_PUSH_VLAN | 756 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 757 .act_tid = 4 758 }, 759 [62] = { 760 .act_hid = BNXT_ULP_ACT_HID_021d, 761 .act_pattern_id = 8, 762 .app_sig = 0, 763 .act_sig = { .bits = 764 BNXT_ULP_ACT_BIT_COUNT | 765 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 766 .act_tid = 4 767 }, 768 [63] = { 769 .act_hid = BNXT_ULP_ACT_HID_0641, 770 .act_pattern_id = 9, 771 .app_sig = 0, 772 .act_sig = { .bits = 773 BNXT_ULP_ACT_BIT_COUNT | 774 BNXT_ULP_ACT_BIT_SET_VLAN_PCP | 775 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 776 BNXT_ULP_ACT_BIT_PUSH_VLAN | 777 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 778 .act_tid = 4 779 }, 780 [64] = { 781 .act_hid = BNXT_ULP_ACT_HID_0512, 782 .act_pattern_id = 10, 783 .app_sig = 0, 784 .act_sig = { .bits = 785 BNXT_ULP_ACT_BIT_COUNT | 786 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 787 BNXT_ULP_ACT_BIT_PUSH_VLAN | 788 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 789 .act_tid = 4 790 }, 791 [65] = { 792 .act_hid = BNXT_ULP_ACT_HID_03c8, 793 .act_pattern_id = 11, 794 .app_sig = 0, 795 .act_sig = { .bits = 796 BNXT_ULP_ACT_BIT_COUNT | 797 BNXT_ULP_ACT_BIT_DEC_TTL | 798 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 799 .act_tid = 4 800 }, 801 [66] = { 802 .act_hid = BNXT_ULP_ACT_HID_0084, 803 .act_pattern_id = 12, 804 .app_sig = 0, 805 .act_sig = { .bits = 806 BNXT_ULP_ACT_BIT_COUNT | 807 BNXT_ULP_ACT_BIT_DEC_TTL | 808 BNXT_ULP_ACT_BIT_SET_VLAN_PCP | 809 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 810 BNXT_ULP_ACT_BIT_PUSH_VLAN | 811 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 812 .act_tid = 4 813 }, 814 [67] = { 815 .act_hid = BNXT_ULP_ACT_HID_06bd, 816 .act_pattern_id = 13, 817 .app_sig = 0, 818 .act_sig = { .bits = 819 BNXT_ULP_ACT_BIT_COUNT | 820 BNXT_ULP_ACT_BIT_DEC_TTL | 821 BNXT_ULP_ACT_BIT_SET_VLAN_VID | 822 BNXT_ULP_ACT_BIT_PUSH_VLAN | 823 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 824 .act_tid = 4 825 }, 826 [68] = { 827 .act_hid = BNXT_ULP_ACT_HID_06d7, 828 .act_pattern_id = 0, 829 .app_sig = 0, 830 .act_sig = { .bits = 831 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 832 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 833 .act_tid = 5 834 }, 835 [69] = { 836 .act_hid = BNXT_ULP_ACT_HID_02c4, 837 .act_pattern_id = 1, 838 .app_sig = 0, 839 .act_sig = { .bits = 840 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 841 BNXT_ULP_ACT_BIT_SET_TP_SRC | 842 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 843 .act_tid = 5 844 }, 845 [70] = { 846 .act_hid = BNXT_ULP_ACT_HID_042a, 847 .act_pattern_id = 2, 848 .app_sig = 0, 849 .act_sig = { .bits = 850 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 851 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 852 .act_tid = 5 853 }, 854 [71] = { 855 .act_hid = BNXT_ULP_ACT_HID_036e, 856 .act_pattern_id = 3, 857 .app_sig = 0, 858 .act_sig = { .bits = 859 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 860 BNXT_ULP_ACT_BIT_SET_TP_DST | 861 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 862 .act_tid = 5 863 }, 864 [72] = { 865 .act_hid = BNXT_ULP_ACT_HID_06c4, 866 .act_pattern_id = 4, 867 .app_sig = 0, 868 .act_sig = { .bits = 869 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 870 BNXT_ULP_ACT_BIT_SET_TP_SRC | 871 BNXT_ULP_ACT_BIT_SET_TP_DST | 872 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 873 .act_tid = 5 874 }, 875 [73] = { 876 .act_hid = BNXT_ULP_ACT_HID_0417, 877 .act_pattern_id = 5, 878 .app_sig = 0, 879 .act_sig = { .bits = 880 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 881 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 882 BNXT_ULP_ACT_BIT_SET_TP_SRC | 883 BNXT_ULP_ACT_BIT_SET_TP_DST | 884 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 885 .act_tid = 5 886 }, 887 [74] = { 888 .act_hid = BNXT_ULP_ACT_HID_06d9, 889 .act_pattern_id = 6, 890 .app_sig = 0, 891 .act_sig = { .bits = 892 BNXT_ULP_ACT_BIT_COUNT | 893 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 894 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 895 .act_tid = 5 896 }, 897 [75] = { 898 .act_hid = BNXT_ULP_ACT_HID_02c6, 899 .act_pattern_id = 7, 900 .app_sig = 0, 901 .act_sig = { .bits = 902 BNXT_ULP_ACT_BIT_COUNT | 903 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 904 BNXT_ULP_ACT_BIT_SET_TP_SRC | 905 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 906 .act_tid = 5 907 }, 908 [76] = { 909 .act_hid = BNXT_ULP_ACT_HID_042c, 910 .act_pattern_id = 8, 911 .app_sig = 0, 912 .act_sig = { .bits = 913 BNXT_ULP_ACT_BIT_COUNT | 914 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 915 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 916 .act_tid = 5 917 }, 918 [77] = { 919 .act_hid = BNXT_ULP_ACT_HID_0370, 920 .act_pattern_id = 9, 921 .app_sig = 0, 922 .act_sig = { .bits = 923 BNXT_ULP_ACT_BIT_COUNT | 924 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 925 BNXT_ULP_ACT_BIT_SET_TP_DST | 926 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 927 .act_tid = 5 928 }, 929 [78] = { 930 .act_hid = BNXT_ULP_ACT_HID_06c6, 931 .act_pattern_id = 10, 932 .app_sig = 0, 933 .act_sig = { .bits = 934 BNXT_ULP_ACT_BIT_COUNT | 935 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 936 BNXT_ULP_ACT_BIT_SET_TP_SRC | 937 BNXT_ULP_ACT_BIT_SET_TP_DST | 938 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 939 .act_tid = 5 940 }, 941 [79] = { 942 .act_hid = BNXT_ULP_ACT_HID_0419, 943 .act_pattern_id = 11, 944 .app_sig = 0, 945 .act_sig = { .bits = 946 BNXT_ULP_ACT_BIT_COUNT | 947 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 948 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 949 BNXT_ULP_ACT_BIT_SET_TP_SRC | 950 BNXT_ULP_ACT_BIT_SET_TP_DST | 951 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 952 .act_tid = 5 953 }, 954 [80] = { 955 .act_hid = BNXT_ULP_ACT_HID_0119, 956 .act_pattern_id = 12, 957 .app_sig = 0, 958 .act_sig = { .bits = 959 BNXT_ULP_ACT_BIT_DEC_TTL | 960 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 961 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 962 .act_tid = 5 963 }, 964 [81] = { 965 .act_hid = BNXT_ULP_ACT_HID_046f, 966 .act_pattern_id = 13, 967 .app_sig = 0, 968 .act_sig = { .bits = 969 BNXT_ULP_ACT_BIT_DEC_TTL | 970 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 971 BNXT_ULP_ACT_BIT_SET_TP_SRC | 972 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 973 .act_tid = 5 974 }, 975 [82] = { 976 .act_hid = BNXT_ULP_ACT_HID_05d5, 977 .act_pattern_id = 14, 978 .app_sig = 0, 979 .act_sig = { .bits = 980 BNXT_ULP_ACT_BIT_DEC_TTL | 981 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 982 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 983 .act_tid = 5 984 }, 985 [83] = { 986 .act_hid = BNXT_ULP_ACT_HID_0519, 987 .act_pattern_id = 15, 988 .app_sig = 0, 989 .act_sig = { .bits = 990 BNXT_ULP_ACT_BIT_DEC_TTL | 991 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 992 BNXT_ULP_ACT_BIT_SET_TP_DST | 993 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 994 .act_tid = 5 995 }, 996 [84] = { 997 .act_hid = BNXT_ULP_ACT_HID_0106, 998 .act_pattern_id = 16, 999 .app_sig = 0, 1000 .act_sig = { .bits = 1001 BNXT_ULP_ACT_BIT_DEC_TTL | 1002 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 1003 BNXT_ULP_ACT_BIT_SET_TP_SRC | 1004 BNXT_ULP_ACT_BIT_SET_TP_DST | 1005 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1006 .act_tid = 5 1007 }, 1008 [85] = { 1009 .act_hid = BNXT_ULP_ACT_HID_05c2, 1010 .act_pattern_id = 17, 1011 .app_sig = 0, 1012 .act_sig = { .bits = 1013 BNXT_ULP_ACT_BIT_DEC_TTL | 1014 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 1015 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 1016 BNXT_ULP_ACT_BIT_SET_TP_SRC | 1017 BNXT_ULP_ACT_BIT_SET_TP_DST | 1018 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1019 .act_tid = 5 1020 }, 1021 [86] = { 1022 .act_hid = BNXT_ULP_ACT_HID_011b, 1023 .act_pattern_id = 18, 1024 .app_sig = 0, 1025 .act_sig = { .bits = 1026 BNXT_ULP_ACT_BIT_DEC_TTL | 1027 BNXT_ULP_ACT_BIT_COUNT | 1028 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 1029 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1030 .act_tid = 5 1031 }, 1032 [87] = { 1033 .act_hid = BNXT_ULP_ACT_HID_0471, 1034 .act_pattern_id = 19, 1035 .app_sig = 0, 1036 .act_sig = { .bits = 1037 BNXT_ULP_ACT_BIT_DEC_TTL | 1038 BNXT_ULP_ACT_BIT_COUNT | 1039 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 1040 BNXT_ULP_ACT_BIT_SET_TP_SRC | 1041 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1042 .act_tid = 5 1043 }, 1044 [88] = { 1045 .act_hid = BNXT_ULP_ACT_HID_05d7, 1046 .act_pattern_id = 20, 1047 .app_sig = 0, 1048 .act_sig = { .bits = 1049 BNXT_ULP_ACT_BIT_DEC_TTL | 1050 BNXT_ULP_ACT_BIT_COUNT | 1051 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 1052 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1053 .act_tid = 5 1054 }, 1055 [89] = { 1056 .act_hid = BNXT_ULP_ACT_HID_051b, 1057 .act_pattern_id = 21, 1058 .app_sig = 0, 1059 .act_sig = { .bits = 1060 BNXT_ULP_ACT_BIT_DEC_TTL | 1061 BNXT_ULP_ACT_BIT_COUNT | 1062 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 1063 BNXT_ULP_ACT_BIT_SET_TP_DST | 1064 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1065 .act_tid = 5 1066 }, 1067 [90] = { 1068 .act_hid = BNXT_ULP_ACT_HID_0108, 1069 .act_pattern_id = 22, 1070 .app_sig = 0, 1071 .act_sig = { .bits = 1072 BNXT_ULP_ACT_BIT_DEC_TTL | 1073 BNXT_ULP_ACT_BIT_COUNT | 1074 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 1075 BNXT_ULP_ACT_BIT_SET_TP_SRC | 1076 BNXT_ULP_ACT_BIT_SET_TP_DST | 1077 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1078 .act_tid = 5 1079 }, 1080 [91] = { 1081 .act_hid = BNXT_ULP_ACT_HID_05c4, 1082 .act_pattern_id = 23, 1083 .app_sig = 0, 1084 .act_sig = { .bits = 1085 BNXT_ULP_ACT_BIT_DEC_TTL | 1086 BNXT_ULP_ACT_BIT_COUNT | 1087 BNXT_ULP_ACT_BIT_SET_IPV4_SRC | 1088 BNXT_ULP_ACT_BIT_SET_IPV4_DST | 1089 BNXT_ULP_ACT_BIT_SET_TP_SRC | 1090 BNXT_ULP_ACT_BIT_SET_TP_DST | 1091 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1092 .act_tid = 5 1093 }, 1094 [92] = { 1095 .act_hid = BNXT_ULP_ACT_HID_00a2, 1096 .act_pattern_id = 0, 1097 .app_sig = 0, 1098 .act_sig = { .bits = 1099 BNXT_ULP_ACT_BIT_VXLAN_ENCAP | 1100 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1101 .act_tid = 6 1102 }, 1103 [93] = { 1104 .act_hid = BNXT_ULP_ACT_HID_00a4, 1105 .act_pattern_id = 1, 1106 .app_sig = 0, 1107 .act_sig = { .bits = 1108 BNXT_ULP_ACT_BIT_VXLAN_ENCAP | 1109 BNXT_ULP_ACT_BIT_COUNT | 1110 BNXT_ULP_FLOW_DIR_BITMASK_EGR }, 1111 .act_tid = 6 1112 } 1113 }; 1114