1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
4 */
5
6 #include "txgbe_type.h"
7 #include "txgbe_mbx.h"
8 #include "txgbe_phy.h"
9 #include "txgbe_dcb.h"
10 #include "txgbe_vf.h"
11 #include "txgbe_eeprom.h"
12 #include "txgbe_mng.h"
13 #include "txgbe_hw.h"
14
15 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
16 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
17 #define TXGBE_RAPTOR_RAR_ENTRIES 128
18 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
19 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
20 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
21
22 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
23 u32 speed,
24 bool autoneg_wait_to_complete);
25
26 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
27 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
28 u16 *san_mac_offset);
29
30 /**
31 * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
32 * of flow control
33 * @hw: pointer to hardware structure
34 *
35 * This function returns true if the device supports flow control
36 * autonegotiation, and false if it does not.
37 *
38 **/
txgbe_device_supports_autoneg_fc(struct txgbe_hw * hw)39 bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
40 {
41 bool supported = false;
42 u32 speed;
43 bool link_up;
44
45 switch (hw->phy.media_type) {
46 case txgbe_media_type_fiber_qsfp:
47 case txgbe_media_type_fiber:
48 hw->mac.check_link(hw, &speed, &link_up, false);
49 /* if link is down, assume supported */
50 if (link_up)
51 supported = speed == TXGBE_LINK_SPEED_1GB_FULL ?
52 true : false;
53 else
54 supported = true;
55
56 break;
57 case txgbe_media_type_backplane:
58 supported = true;
59 break;
60 case txgbe_media_type_copper:
61 /* only some copper devices support flow control autoneg */
62 switch (hw->subsystem_device_id & 0xFF) {
63 case TXGBE_DEV_ID_XAUI:
64 case TXGBE_DEV_ID_SGMII:
65 supported = true;
66 break;
67 default:
68 supported = false;
69 }
70 default:
71 break;
72 }
73
74 if (!supported)
75 DEBUGOUT("Device %x does not support flow control autoneg",
76 hw->device_id);
77 return supported;
78 }
79
80 /**
81 * txgbe_setup_fc - Set up flow control
82 * @hw: pointer to hardware structure
83 *
84 * Called at init time to set up flow control.
85 **/
txgbe_setup_fc(struct txgbe_hw * hw)86 s32 txgbe_setup_fc(struct txgbe_hw *hw)
87 {
88 s32 err = 0;
89 u32 reg = 0;
90 u16 reg_cu = 0;
91 u32 value = 0;
92 u64 reg_bp = 0;
93
94 /* Validate the requested mode */
95 if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
96 DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode");
97 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
98 goto out;
99 }
100
101 /*
102 * 10gig parts do not have a word in the EEPROM to determine the
103 * default flow control setting, so we explicitly set it to full.
104 */
105 if (hw->fc.requested_mode == txgbe_fc_default)
106 hw->fc.requested_mode = txgbe_fc_full;
107
108 /*
109 * The possible values of fc.requested_mode are:
110 * 0: Flow control is completely disabled
111 * 1: Rx flow control is enabled (we can receive pause frames,
112 * but not send pause frames).
113 * 2: Tx flow control is enabled (we can send pause frames but
114 * we do not support receiving pause frames).
115 * 3: Both Rx and Tx flow control (symmetric) are enabled.
116 * other: Invalid.
117 */
118 switch (hw->fc.requested_mode) {
119 case txgbe_fc_none:
120 /* Flow control completely disabled by software override. */
121 break;
122 case txgbe_fc_tx_pause:
123 /*
124 * Tx Flow control is enabled, and Rx Flow control is
125 * disabled by software override.
126 */
127 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
128 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
129 break;
130 case txgbe_fc_rx_pause:
131 /*
132 * Rx Flow control is enabled and Tx Flow control is
133 * disabled by software override. Since there really
134 * isn't a way to advertise that we are capable of RX
135 * Pause ONLY, we will advertise that we support both
136 * symmetric and asymmetric Rx PAUSE, as such we fall
137 * through to the fc_full statement. Later, we will
138 * disable the adapter's ability to send PAUSE frames.
139 */
140 case txgbe_fc_full:
141 /* Flow control (both Rx and Tx) is enabled by SW override. */
142 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
143 SR_MII_MMD_AN_ADV_PAUSE_ASM;
144 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
145 SR_AN_MMD_ADV_REG1_PAUSE_ASM;
146 break;
147 default:
148 DEBUGOUT("Flow control param set incorrectly");
149 err = TXGBE_ERR_CONFIG;
150 goto out;
151 }
152
153 /*
154 * Enable auto-negotiation between the MAC & PHY;
155 * the MAC will advertise clause 37 flow control.
156 */
157 value = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
158 value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM |
159 SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg;
160 wr32_epcs(hw, SR_MII_MMD_AN_ADV, value);
161
162 /*
163 * AUTOC restart handles negotiation of 1G and 10G on backplane
164 * and copper. There is no need to set the PCS1GCTL register.
165 *
166 */
167 if (hw->phy.media_type == txgbe_media_type_backplane) {
168 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
169 value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM |
170 SR_AN_MMD_ADV_REG1_PAUSE_SYM)) |
171 reg_bp;
172 wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value);
173 } else if ((hw->phy.media_type == txgbe_media_type_copper) &&
174 (txgbe_device_supports_autoneg_fc(hw))) {
175 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
176 TXGBE_MD_DEV_AUTO_NEG, reg_cu);
177 }
178
179 DEBUGOUT("Set up FC; reg = 0x%08X", reg);
180 out:
181 return err;
182 }
183
184 /**
185 * txgbe_start_hw - Prepare hardware for Tx/Rx
186 * @hw: pointer to hardware structure
187 *
188 * Starts the hardware by filling the bus info structure and media type, clears
189 * all on chip counters, initializes receive address registers, multicast
190 * table, VLAN filter table, calls routine to set up link and flow control
191 * settings, and leaves transmit and receive units disabled and uninitialized
192 **/
txgbe_start_hw(struct txgbe_hw * hw)193 s32 txgbe_start_hw(struct txgbe_hw *hw)
194 {
195 s32 err;
196 u16 device_caps;
197
198 /* Set the media type */
199 hw->phy.media_type = hw->phy.get_media_type(hw);
200
201 /* Clear the VLAN filter table */
202 hw->mac.clear_vfta(hw);
203
204 /* Clear statistics registers */
205 hw->mac.clear_hw_cntrs(hw);
206
207 /* Setup flow control */
208 err = txgbe_setup_fc(hw);
209 if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) {
210 DEBUGOUT("Flow control setup failed, returning %d", err);
211 return err;
212 }
213
214 /* Cache bit indicating need for crosstalk fix */
215 switch (hw->mac.type) {
216 case txgbe_mac_raptor:
217 hw->mac.get_device_caps(hw, &device_caps);
218 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
219 hw->need_crosstalk_fix = false;
220 else
221 hw->need_crosstalk_fix = true;
222 break;
223 default:
224 hw->need_crosstalk_fix = false;
225 break;
226 }
227
228 /* Clear adapter stopped flag */
229 hw->adapter_stopped = false;
230
231 return 0;
232 }
233
234 /**
235 * txgbe_start_hw_gen2 - Init sequence for common device family
236 * @hw: pointer to hw structure
237 *
238 * Performs the init sequence common to the second generation
239 * of 10 GbE devices.
240 **/
txgbe_start_hw_gen2(struct txgbe_hw * hw)241 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
242 {
243 u32 i;
244
245 /* Clear the rate limiters */
246 for (i = 0; i < hw->mac.max_tx_queues; i++) {
247 wr32(hw, TXGBE_ARBPOOLIDX, i);
248 wr32(hw, TXGBE_ARBTXRATE, 0);
249 }
250 txgbe_flush(hw);
251
252 /* We need to run link autotry after the driver loads */
253 hw->mac.autotry_restart = true;
254
255 return 0;
256 }
257
258 /**
259 * txgbe_init_hw - Generic hardware initialization
260 * @hw: pointer to hardware structure
261 *
262 * Initialize the hardware by resetting the hardware, filling the bus info
263 * structure and media type, clears all on chip counters, initializes receive
264 * address registers, multicast table, VLAN filter table, calls routine to set
265 * up link and flow control settings, and leaves transmit and receive units
266 * disabled and uninitialized
267 **/
txgbe_init_hw(struct txgbe_hw * hw)268 s32 txgbe_init_hw(struct txgbe_hw *hw)
269 {
270 s32 status;
271
272 /* Get firmware version */
273 hw->phy.get_fw_version(hw, &hw->fw_version);
274
275 /* Reset the hardware */
276 status = hw->mac.reset_hw(hw);
277 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
278 /* Start the HW */
279 status = hw->mac.start_hw(hw);
280 }
281
282 if (status != 0)
283 DEBUGOUT("Failed to initialize HW, STATUS = %d", status);
284
285 return status;
286 }
287
288 /**
289 * txgbe_clear_hw_cntrs - Generic clear hardware counters
290 * @hw: pointer to hardware structure
291 *
292 * Clears all hardware statistics counters by reading them from the hardware
293 * Statistics counters are clear on read.
294 **/
txgbe_clear_hw_cntrs(struct txgbe_hw * hw)295 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
296 {
297 u16 i = 0;
298
299 /* QP Stats */
300 /* don't write clear queue stats */
301 for (i = 0; i < TXGBE_MAX_QP; i++) {
302 hw->qp_last[i].rx_qp_packets = 0;
303 hw->qp_last[i].tx_qp_packets = 0;
304 hw->qp_last[i].rx_qp_bytes = 0;
305 hw->qp_last[i].tx_qp_bytes = 0;
306 hw->qp_last[i].rx_qp_mc_packets = 0;
307 }
308
309 /* PB Stats */
310 for (i = 0; i < TXGBE_MAX_UP; i++) {
311 rd32(hw, TXGBE_PBRXUPXON(i));
312 rd32(hw, TXGBE_PBRXUPXOFF(i));
313 rd32(hw, TXGBE_PBTXUPXON(i));
314 rd32(hw, TXGBE_PBTXUPXOFF(i));
315 rd32(hw, TXGBE_PBTXUPOFF(i));
316
317 rd32(hw, TXGBE_PBRXMISS(i));
318 }
319 rd32(hw, TXGBE_PBRXLNKXON);
320 rd32(hw, TXGBE_PBRXLNKXOFF);
321 rd32(hw, TXGBE_PBTXLNKXON);
322 rd32(hw, TXGBE_PBTXLNKXOFF);
323
324 /* DMA Stats */
325 rd32(hw, TXGBE_DMARXPKT);
326 rd32(hw, TXGBE_DMATXPKT);
327
328 rd64(hw, TXGBE_DMARXOCTL);
329 rd64(hw, TXGBE_DMATXOCTL);
330
331 /* MAC Stats */
332 rd64(hw, TXGBE_MACRXERRCRCL);
333 rd64(hw, TXGBE_MACRXMPKTL);
334 rd64(hw, TXGBE_MACTXMPKTL);
335
336 rd64(hw, TXGBE_MACRXPKTL);
337 rd64(hw, TXGBE_MACTXPKTL);
338 rd64(hw, TXGBE_MACRXGBOCTL);
339
340 rd64(hw, TXGBE_MACRXOCTL);
341 rd32(hw, TXGBE_MACTXOCTL);
342
343 rd64(hw, TXGBE_MACRX1TO64L);
344 rd64(hw, TXGBE_MACRX65TO127L);
345 rd64(hw, TXGBE_MACRX128TO255L);
346 rd64(hw, TXGBE_MACRX256TO511L);
347 rd64(hw, TXGBE_MACRX512TO1023L);
348 rd64(hw, TXGBE_MACRX1024TOMAXL);
349 rd64(hw, TXGBE_MACTX1TO64L);
350 rd64(hw, TXGBE_MACTX65TO127L);
351 rd64(hw, TXGBE_MACTX128TO255L);
352 rd64(hw, TXGBE_MACTX256TO511L);
353 rd64(hw, TXGBE_MACTX512TO1023L);
354 rd64(hw, TXGBE_MACTX1024TOMAXL);
355
356 rd64(hw, TXGBE_MACRXERRLENL);
357 rd32(hw, TXGBE_MACRXOVERSIZE);
358 rd32(hw, TXGBE_MACRXJABBER);
359
360 /* FCoE Stats */
361 rd32(hw, TXGBE_FCOECRC);
362 rd32(hw, TXGBE_FCOELAST);
363 rd32(hw, TXGBE_FCOERPDC);
364 rd32(hw, TXGBE_FCOEPRC);
365 rd32(hw, TXGBE_FCOEPTC);
366 rd32(hw, TXGBE_FCOEDWRC);
367 rd32(hw, TXGBE_FCOEDWTC);
368
369 /* Flow Director Stats */
370 rd32(hw, TXGBE_FDIRMATCH);
371 rd32(hw, TXGBE_FDIRMISS);
372 rd32(hw, TXGBE_FDIRUSED);
373 rd32(hw, TXGBE_FDIRUSED);
374 rd32(hw, TXGBE_FDIRFAIL);
375 rd32(hw, TXGBE_FDIRFAIL);
376
377 /* MACsec Stats */
378 rd32(hw, TXGBE_LSECTX_UTPKT);
379 rd32(hw, TXGBE_LSECTX_ENCPKT);
380 rd32(hw, TXGBE_LSECTX_PROTPKT);
381 rd32(hw, TXGBE_LSECTX_ENCOCT);
382 rd32(hw, TXGBE_LSECTX_PROTOCT);
383 rd32(hw, TXGBE_LSECRX_UTPKT);
384 rd32(hw, TXGBE_LSECRX_BTPKT);
385 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
386 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
387 rd32(hw, TXGBE_LSECRX_DECOCT);
388 rd32(hw, TXGBE_LSECRX_VLDOCT);
389 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
390 rd32(hw, TXGBE_LSECRX_DLYPKT);
391 rd32(hw, TXGBE_LSECRX_LATEPKT);
392 for (i = 0; i < 2; i++) {
393 rd32(hw, TXGBE_LSECRX_OKPKT(i));
394 rd32(hw, TXGBE_LSECRX_INVPKT(i));
395 rd32(hw, TXGBE_LSECRX_BADPKT(i));
396 }
397 rd32(hw, TXGBE_LSECRX_INVSAPKT);
398 rd32(hw, TXGBE_LSECRX_BADSAPKT);
399
400 return 0;
401 }
402
403 /**
404 * txgbe_get_mac_addr - Generic get MAC address
405 * @hw: pointer to hardware structure
406 * @mac_addr: Adapter MAC address
407 *
408 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
409 * A reset of the adapter must be performed prior to calling this function
410 * in order for the MAC address to have been loaded from the EEPROM into RAR0
411 **/
txgbe_get_mac_addr(struct txgbe_hw * hw,u8 * mac_addr)412 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
413 {
414 u32 rar_high;
415 u32 rar_low;
416 u16 i;
417
418 wr32(hw, TXGBE_ETHADDRIDX, 0);
419 rar_high = rd32(hw, TXGBE_ETHADDRH);
420 rar_low = rd32(hw, TXGBE_ETHADDRL);
421
422 for (i = 0; i < 2; i++)
423 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
424
425 for (i = 0; i < 4; i++)
426 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
427
428 return 0;
429 }
430
431 /**
432 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
433 * @hw: pointer to the HW structure
434 *
435 * Determines the LAN function id by reading memory-mapped registers and swaps
436 * the port value if requested, and set MAC instance for devices.
437 **/
txgbe_set_lan_id_multi_port(struct txgbe_hw * hw)438 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
439 {
440 struct txgbe_bus_info *bus = &hw->bus;
441 u32 reg;
442
443 reg = rd32(hw, TXGBE_PORTSTAT);
444 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
445
446 /* check for single port */
447 reg = rd32(hw, TXGBE_PWR);
448 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
449 bus->func = 0;
450 else
451 bus->func = bus->lan_id;
452 }
453
454 /**
455 * txgbe_stop_hw - Generic stop Tx/Rx units
456 * @hw: pointer to hardware structure
457 *
458 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
459 * disables transmit and receive units. The adapter_stopped flag is used by
460 * the shared code and drivers to determine if the adapter is in a stopped
461 * state and should not touch the hardware.
462 **/
txgbe_stop_hw(struct txgbe_hw * hw)463 s32 txgbe_stop_hw(struct txgbe_hw *hw)
464 {
465 u32 reg_val;
466 u16 i;
467
468 /*
469 * Set the adapter_stopped flag so other driver functions stop touching
470 * the hardware
471 */
472 hw->adapter_stopped = true;
473
474 /* Disable the receive unit */
475 txgbe_disable_rx(hw);
476
477 /* Clear interrupt mask to stop interrupts from being generated */
478 wr32(hw, TXGBE_IENMISC, 0);
479 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
480 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
481
482 /* Clear any pending interrupts, flush previous writes */
483 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
484 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
485 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
486
487 /* Disable the transmit unit. Each queue must be disabled. */
488 for (i = 0; i < hw->mac.max_tx_queues; i++)
489 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
490
491 /* Disable the receive unit by stopping each queue */
492 for (i = 0; i < hw->mac.max_rx_queues; i++) {
493 reg_val = rd32(hw, TXGBE_RXCFG(i));
494 reg_val &= ~TXGBE_RXCFG_ENA;
495 wr32(hw, TXGBE_RXCFG(i), reg_val);
496 }
497
498 /* flush all queues disables */
499 txgbe_flush(hw);
500 msec_delay(2);
501
502 return 0;
503 }
504
505 /**
506 * txgbe_led_on - Turns on the software controllable LEDs.
507 * @hw: pointer to hardware structure
508 * @index: led number to turn on
509 **/
txgbe_led_on(struct txgbe_hw * hw,u32 index)510 s32 txgbe_led_on(struct txgbe_hw *hw, u32 index)
511 {
512 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
513
514 /* To turn on the LED, set mode to ON. */
515 led_reg |= index << TXGBE_LEDCTL_ORD_SHIFT;
516 led_reg |= index;
517 wr32(hw, TXGBE_LEDCTL, led_reg);
518 txgbe_flush(hw);
519
520 return 0;
521 }
522
523 /**
524 * txgbe_led_off - Turns off the software controllable LEDs.
525 * @hw: pointer to hardware structure
526 * @index: led number to turn off
527 **/
txgbe_led_off(struct txgbe_hw * hw,u32 index)528 s32 txgbe_led_off(struct txgbe_hw *hw, u32 index)
529 {
530 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
531
532 /* To turn off the LED, set mode to OFF. */
533 led_reg &= ~(index << TXGBE_LEDCTL_ORD_SHIFT);
534 led_reg |= index;
535 wr32(hw, TXGBE_LEDCTL, led_reg);
536 txgbe_flush(hw);
537
538 return 0;
539 }
540
541 /**
542 * txgbe_validate_mac_addr - Validate MAC address
543 * @mac_addr: pointer to MAC address.
544 *
545 * Tests a MAC address to ensure it is a valid Individual Address.
546 **/
txgbe_validate_mac_addr(u8 * mac_addr)547 s32 txgbe_validate_mac_addr(u8 *mac_addr)
548 {
549 s32 status = 0;
550
551 /* Make sure it is not a multicast address */
552 if (TXGBE_IS_MULTICAST(mac_addr)) {
553 status = TXGBE_ERR_INVALID_MAC_ADDR;
554 /* Not a broadcast address */
555 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
556 status = TXGBE_ERR_INVALID_MAC_ADDR;
557 /* Reject the zero address */
558 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
559 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
560 status = TXGBE_ERR_INVALID_MAC_ADDR;
561 }
562 return status;
563 }
564
565 /**
566 * txgbe_set_rar - Set Rx address register
567 * @hw: pointer to hardware structure
568 * @index: Receive address register to write
569 * @addr: Address to put into receive address register
570 * @vmdq: VMDq "set" or "pool" index
571 * @enable_addr: set flag that address is active
572 *
573 * Puts an ethernet address into a receive address register.
574 **/
txgbe_set_rar(struct txgbe_hw * hw,u32 index,u8 * addr,u32 vmdq,u32 enable_addr)575 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
576 u32 enable_addr)
577 {
578 u32 rar_low, rar_high;
579 u32 rar_entries = hw->mac.num_rar_entries;
580
581 /* Make sure we are using a valid rar index range */
582 if (index >= rar_entries) {
583 DEBUGOUT("RAR index %d is out of range.", index);
584 return TXGBE_ERR_INVALID_ARGUMENT;
585 }
586
587 /* setup VMDq pool selection before this RAR gets enabled */
588 hw->mac.set_vmdq(hw, index, vmdq);
589
590 /*
591 * HW expects these in little endian so we reverse the byte
592 * order from network order (big endian) to little endian
593 */
594 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
595 TXGBE_ETHADDRL_AD1(addr[4]) |
596 TXGBE_ETHADDRL_AD2(addr[3]) |
597 TXGBE_ETHADDRL_AD3(addr[2]);
598 /*
599 * Some parts put the VMDq setting in the extra RAH bits,
600 * so save everything except the lower 16 bits that hold part
601 * of the address and the address valid bit.
602 */
603 rar_high = rd32(hw, TXGBE_ETHADDRH);
604 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
605 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
606 TXGBE_ETHADDRH_AD5(addr[0]));
607
608 rar_high &= ~TXGBE_ETHADDRH_VLD;
609 if (enable_addr != 0)
610 rar_high |= TXGBE_ETHADDRH_VLD;
611
612 wr32(hw, TXGBE_ETHADDRIDX, index);
613 wr32(hw, TXGBE_ETHADDRL, rar_low);
614 wr32(hw, TXGBE_ETHADDRH, rar_high);
615
616 return 0;
617 }
618
619 /**
620 * txgbe_clear_rar - Remove Rx address register
621 * @hw: pointer to hardware structure
622 * @index: Receive address register to write
623 *
624 * Clears an ethernet address from a receive address register.
625 **/
txgbe_clear_rar(struct txgbe_hw * hw,u32 index)626 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
627 {
628 u32 rar_high;
629 u32 rar_entries = hw->mac.num_rar_entries;
630
631 /* Make sure we are using a valid rar index range */
632 if (index >= rar_entries) {
633 DEBUGOUT("RAR index %d is out of range.", index);
634 return TXGBE_ERR_INVALID_ARGUMENT;
635 }
636
637 /*
638 * Some parts put the VMDq setting in the extra RAH bits,
639 * so save everything except the lower 16 bits that hold part
640 * of the address and the address valid bit.
641 */
642 wr32(hw, TXGBE_ETHADDRIDX, index);
643 rar_high = rd32(hw, TXGBE_ETHADDRH);
644 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
645
646 wr32(hw, TXGBE_ETHADDRL, 0);
647 wr32(hw, TXGBE_ETHADDRH, rar_high);
648
649 /* clear VMDq pool/queue selection for this RAR */
650 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
651
652 return 0;
653 }
654
655 /**
656 * txgbe_init_rx_addrs - Initializes receive address filters.
657 * @hw: pointer to hardware structure
658 *
659 * Places the MAC address in receive address register 0 and clears the rest
660 * of the receive address registers. Clears the multicast table. Assumes
661 * the receiver is in reset when the routine is called.
662 **/
txgbe_init_rx_addrs(struct txgbe_hw * hw)663 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
664 {
665 u32 i;
666 u32 psrctl;
667 u32 rar_entries = hw->mac.num_rar_entries;
668
669 /*
670 * If the current mac address is valid, assume it is a software override
671 * to the permanent address.
672 * Otherwise, use the permanent address from the eeprom.
673 */
674 if (txgbe_validate_mac_addr(hw->mac.addr) ==
675 TXGBE_ERR_INVALID_MAC_ADDR) {
676 /* Get the MAC address from the RAR0 for later reference */
677 hw->mac.get_mac_addr(hw, hw->mac.addr);
678
679 DEBUGOUT(" Keeping Current RAR0 Addr = "
680 RTE_ETHER_ADDR_PRT_FMT,
681 hw->mac.addr[0], hw->mac.addr[1],
682 hw->mac.addr[2], hw->mac.addr[3],
683 hw->mac.addr[4], hw->mac.addr[5]);
684 } else {
685 /* Setup the receive address. */
686 DEBUGOUT("Overriding MAC Address in RAR[0]");
687 DEBUGOUT(" New MAC Addr = "
688 RTE_ETHER_ADDR_PRT_FMT,
689 hw->mac.addr[0], hw->mac.addr[1],
690 hw->mac.addr[2], hw->mac.addr[3],
691 hw->mac.addr[4], hw->mac.addr[5]);
692
693 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
694 }
695
696 /* clear VMDq pool/queue selection for RAR 0 */
697 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
698
699 hw->addr_ctrl.overflow_promisc = 0;
700
701 hw->addr_ctrl.rar_used_count = 1;
702
703 /* Zero out the other receive addresses. */
704 DEBUGOUT("Clearing RAR[1-%d]", rar_entries - 1);
705 for (i = 1; i < rar_entries; i++) {
706 wr32(hw, TXGBE_ETHADDRIDX, i);
707 wr32(hw, TXGBE_ETHADDRL, 0);
708 wr32(hw, TXGBE_ETHADDRH, 0);
709 }
710
711 /* Clear the MTA */
712 hw->addr_ctrl.mta_in_use = 0;
713 psrctl = rd32(hw, TXGBE_PSRCTL);
714 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
715 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
716 wr32(hw, TXGBE_PSRCTL, psrctl);
717
718 DEBUGOUT(" Clearing MTA");
719 for (i = 0; i < hw->mac.mcft_size; i++)
720 wr32(hw, TXGBE_MCADDRTBL(i), 0);
721
722 txgbe_init_uta_tables(hw);
723
724 return 0;
725 }
726
727 /**
728 * txgbe_mta_vector - Determines bit-vector in multicast table to set
729 * @hw: pointer to hardware structure
730 * @mc_addr: the multicast address
731 *
732 * Extracts the 12 bits, from a multicast address, to determine which
733 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
734 * incoming rx multicast addresses, to determine the bit-vector to check in
735 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
736 * by the MO field of the PSRCTRL. The MO field is set during initialization
737 * to mc_filter_type.
738 **/
txgbe_mta_vector(struct txgbe_hw * hw,u8 * mc_addr)739 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
740 {
741 u32 vector = 0;
742
743 switch (hw->mac.mc_filter_type) {
744 case 0: /* use bits [47:36] of the address */
745 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
746 break;
747 case 1: /* use bits [46:35] of the address */
748 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
749 break;
750 case 2: /* use bits [45:34] of the address */
751 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
752 break;
753 case 3: /* use bits [43:32] of the address */
754 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
755 break;
756 default: /* Invalid mc_filter_type */
757 DEBUGOUT("MC filter type param set incorrectly");
758 ASSERT(0);
759 break;
760 }
761
762 /* vector can only be 12-bits or boundary will be exceeded */
763 vector &= 0xFFF;
764 return vector;
765 }
766
767 /**
768 * txgbe_set_mta - Set bit-vector in multicast table
769 * @hw: pointer to hardware structure
770 * @mc_addr: Multicast address
771 *
772 * Sets the bit-vector in the multicast table.
773 **/
txgbe_set_mta(struct txgbe_hw * hw,u8 * mc_addr)774 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
775 {
776 u32 vector;
777 u32 vector_bit;
778 u32 vector_reg;
779
780 hw->addr_ctrl.mta_in_use++;
781
782 vector = txgbe_mta_vector(hw, mc_addr);
783 DEBUGOUT(" bit-vector = 0x%03X", vector);
784
785 /*
786 * The MTA is a register array of 128 32-bit registers. It is treated
787 * like an array of 4096 bits. We want to set bit
788 * BitArray[vector_value]. So we figure out what register the bit is
789 * in, read it, OR in the new bit, then write back the new value. The
790 * register is determined by the upper 7 bits of the vector value and
791 * the bit within that register are determined by the lower 5 bits of
792 * the value.
793 */
794 vector_reg = (vector >> 5) & 0x7F;
795 vector_bit = vector & 0x1F;
796 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
797 }
798
799 /**
800 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
801 * @hw: pointer to hardware structure
802 * @mc_addr_list: the list of new multicast addresses
803 * @mc_addr_count: number of addresses
804 * @next: iterator function to walk the multicast address list
805 * @clear: flag, when set clears the table beforehand
806 *
807 * When the clear flag is set, the given list replaces any existing list.
808 * Hashes the given addresses into the multicast table.
809 **/
txgbe_update_mc_addr_list(struct txgbe_hw * hw,u8 * mc_addr_list,u32 mc_addr_count,txgbe_mc_addr_itr next,bool clear)810 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
811 u32 mc_addr_count, txgbe_mc_addr_itr next,
812 bool clear)
813 {
814 u32 i;
815 u32 vmdq;
816
817 /*
818 * Set the new number of MC addresses that we are being requested to
819 * use.
820 */
821 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
822 hw->addr_ctrl.mta_in_use = 0;
823
824 /* Clear mta_shadow */
825 if (clear) {
826 DEBUGOUT(" Clearing MTA");
827 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
828 }
829
830 /* Update mta_shadow */
831 for (i = 0; i < mc_addr_count; i++) {
832 DEBUGOUT(" Adding the multicast addresses:");
833 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
834 }
835
836 /* Enable mta */
837 for (i = 0; i < hw->mac.mcft_size; i++)
838 wr32a(hw, TXGBE_MCADDRTBL(0), i,
839 hw->mac.mta_shadow[i]);
840
841 if (hw->addr_ctrl.mta_in_use > 0) {
842 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
843 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
844 psrctl |= TXGBE_PSRCTL_MCHFENA |
845 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
846 wr32(hw, TXGBE_PSRCTL, psrctl);
847 }
848
849 DEBUGOUT("txgbe update mc addr list complete");
850 return 0;
851 }
852
853 /**
854 * txgbe_fc_enable - Enable flow control
855 * @hw: pointer to hardware structure
856 *
857 * Enable flow control according to the current settings.
858 **/
txgbe_fc_enable(struct txgbe_hw * hw)859 s32 txgbe_fc_enable(struct txgbe_hw *hw)
860 {
861 s32 err = 0;
862 u32 mflcn_reg, fccfg_reg;
863 u32 pause_time;
864 u32 fcrtl, fcrth;
865 int i;
866
867 /* Validate the water mark configuration */
868 if (!hw->fc.pause_time) {
869 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
870 goto out;
871 }
872
873 /* Low water mark of zero causes XOFF floods */
874 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
875 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
876 hw->fc.high_water[i]) {
877 if (!hw->fc.low_water[i] ||
878 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
879 DEBUGOUT("Invalid water mark configuration");
880 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
881 goto out;
882 }
883 }
884 }
885
886 /* Negotiate the fc mode to use */
887 hw->mac.fc_autoneg(hw);
888
889 /* Disable any previous flow control settings */
890 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
891 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
892
893 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
894 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
895
896 /*
897 * The possible values of fc.current_mode are:
898 * 0: Flow control is completely disabled
899 * 1: Rx flow control is enabled (we can receive pause frames,
900 * but not send pause frames).
901 * 2: Tx flow control is enabled (we can send pause frames but
902 * we do not support receiving pause frames).
903 * 3: Both Rx and Tx flow control (symmetric) are enabled.
904 * other: Invalid.
905 */
906 switch (hw->fc.current_mode) {
907 case txgbe_fc_none:
908 /*
909 * Flow control is disabled by software override or autoneg.
910 * The code below will actually disable it in the HW.
911 */
912 break;
913 case txgbe_fc_rx_pause:
914 /*
915 * Rx Flow control is enabled and Tx Flow control is
916 * disabled by software override. Since there really
917 * isn't a way to advertise that we are capable of RX
918 * Pause ONLY, we will advertise that we support both
919 * symmetric and asymmetric Rx PAUSE. Later, we will
920 * disable the adapter's ability to send PAUSE frames.
921 */
922 mflcn_reg |= TXGBE_RXFCCFG_FC;
923 break;
924 case txgbe_fc_tx_pause:
925 /*
926 * Tx Flow control is enabled, and Rx Flow control is
927 * disabled by software override.
928 */
929 fccfg_reg |= TXGBE_TXFCCFG_FC;
930 break;
931 case txgbe_fc_full:
932 /* Flow control (both Rx and Tx) is enabled by SW override. */
933 mflcn_reg |= TXGBE_RXFCCFG_FC;
934 fccfg_reg |= TXGBE_TXFCCFG_FC;
935 break;
936 default:
937 DEBUGOUT("Flow control param set incorrectly");
938 err = TXGBE_ERR_CONFIG;
939 goto out;
940 }
941
942 /* Set 802.3x based flow control settings. */
943 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
944 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
945
946 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
947 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
948 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
949 hw->fc.high_water[i]) {
950 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
951 TXGBE_FCWTRLO_XON;
952 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
953 TXGBE_FCWTRHI_XOFF;
954 } else {
955 /*
956 * In order to prevent Tx hangs when the internal Tx
957 * switch is enabled we must set the high water mark
958 * to the Rx packet buffer size - 24KB. This allows
959 * the Tx switch to function even under heavy Rx
960 * workloads.
961 */
962 fcrtl = 0;
963 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
964 }
965 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
966 wr32(hw, TXGBE_FCWTRHI(i), fcrth);
967 }
968
969 /* Configure pause time (2 TCs per register) */
970 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
971 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
972 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
973
974 /* Configure flow control refresh threshold value */
975 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
976
977 out:
978 return err;
979 }
980
981 /**
982 * txgbe_negotiate_fc - Negotiate flow control
983 * @hw: pointer to hardware structure
984 * @adv_reg: flow control advertised settings
985 * @lp_reg: link partner's flow control settings
986 * @adv_sym: symmetric pause bit in advertisement
987 * @adv_asm: asymmetric pause bit in advertisement
988 * @lp_sym: symmetric pause bit in link partner advertisement
989 * @lp_asm: asymmetric pause bit in link partner advertisement
990 *
991 * Find the intersection between advertised settings and link partner's
992 * advertised settings
993 **/
txgbe_negotiate_fc(struct txgbe_hw * hw,u32 adv_reg,u32 lp_reg,u32 adv_sym,u32 adv_asm,u32 lp_sym,u32 lp_asm)994 s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
995 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
996 {
997 if ((!(adv_reg)) || (!(lp_reg))) {
998 DEBUGOUT("Local or link partner's advertised flow control settings are NULL. Local: %x, link partner: %x",
999 adv_reg, lp_reg);
1000 return TXGBE_ERR_FC_NOT_NEGOTIATED;
1001 }
1002
1003 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1004 /*
1005 * Now we need to check if the user selected Rx ONLY
1006 * of pause frames. In this case, we had to advertise
1007 * FULL flow control because we could not advertise RX
1008 * ONLY. Hence, we must now check to see if we need to
1009 * turn OFF the TRANSMISSION of PAUSE frames.
1010 */
1011 if (hw->fc.requested_mode == txgbe_fc_full) {
1012 hw->fc.current_mode = txgbe_fc_full;
1013 DEBUGOUT("Flow Control = FULL.");
1014 } else {
1015 hw->fc.current_mode = txgbe_fc_rx_pause;
1016 DEBUGOUT("Flow Control=RX PAUSE frames only");
1017 }
1018 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1019 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1020 hw->fc.current_mode = txgbe_fc_tx_pause;
1021 DEBUGOUT("Flow Control = TX PAUSE frames only.");
1022 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1023 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1024 hw->fc.current_mode = txgbe_fc_rx_pause;
1025 DEBUGOUT("Flow Control = RX PAUSE frames only.");
1026 } else {
1027 hw->fc.current_mode = txgbe_fc_none;
1028 DEBUGOUT("Flow Control = NONE.");
1029 }
1030 return 0;
1031 }
1032
1033 /**
1034 * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1035 * @hw: pointer to hardware structure
1036 *
1037 * Enable flow control according on 1 gig fiber.
1038 **/
txgbe_fc_autoneg_fiber(struct txgbe_hw * hw)1039 STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw)
1040 {
1041 u32 pcs_anadv_reg, pcs_lpab_reg;
1042 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1043
1044 /*
1045 * On multispeed fiber at 1g, bail out if
1046 * - link is up but AN did not complete, or if
1047 * - link is up and AN completed but timed out
1048 */
1049
1050 pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
1051 pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL);
1052
1053 err = txgbe_negotiate_fc(hw, pcs_anadv_reg,
1054 pcs_lpab_reg,
1055 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1056 SR_MII_MMD_AN_ADV_PAUSE_ASM,
1057 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1058 SR_MII_MMD_AN_ADV_PAUSE_ASM);
1059
1060 return err;
1061 }
1062
1063 /**
1064 * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1065 * @hw: pointer to hardware structure
1066 *
1067 * Enable flow control according to IEEE clause 37.
1068 **/
txgbe_fc_autoneg_backplane(struct txgbe_hw * hw)1069 STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw)
1070 {
1071 u32 anlp1_reg, autoc_reg;
1072 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1073
1074 /*
1075 * Read the 10g AN autoc and LP ability registers and resolve
1076 * local flow control settings accordingly
1077 */
1078 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1079 anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
1080
1081 err = txgbe_negotiate_fc(hw, autoc_reg,
1082 anlp1_reg,
1083 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1084 SR_AN_MMD_ADV_REG1_PAUSE_ASM,
1085 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1086 SR_AN_MMD_ADV_REG1_PAUSE_ASM);
1087
1088 return err;
1089 }
1090
1091 /**
1092 * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1093 * @hw: pointer to hardware structure
1094 *
1095 * Enable flow control according to IEEE clause 37.
1096 **/
txgbe_fc_autoneg_copper(struct txgbe_hw * hw)1097 STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw)
1098 {
1099 u16 technology_ability_reg = 0;
1100 u16 lp_technology_ability_reg = 0;
1101
1102 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
1103 TXGBE_MD_DEV_AUTO_NEG,
1104 &technology_ability_reg);
1105 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP,
1106 TXGBE_MD_DEV_AUTO_NEG,
1107 &lp_technology_ability_reg);
1108
1109 return txgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1110 (u32)lp_technology_ability_reg,
1111 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE,
1112 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE);
1113 }
1114
1115 /**
1116 * txgbe_fc_autoneg - Configure flow control
1117 * @hw: pointer to hardware structure
1118 *
1119 * Compares our advertised flow control capabilities to those advertised by
1120 * our link partner, and determines the proper flow control mode to use.
1121 **/
txgbe_fc_autoneg(struct txgbe_hw * hw)1122 void txgbe_fc_autoneg(struct txgbe_hw *hw)
1123 {
1124 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1125 u32 speed;
1126 bool link_up;
1127
1128 /*
1129 * AN should have completed when the cable was plugged in.
1130 * Look for reasons to bail out. Bail out if:
1131 * - FC autoneg is disabled, or if
1132 * - link is not up.
1133 */
1134 if (hw->fc.disable_fc_autoneg) {
1135 DEBUGOUT("Flow control autoneg is disabled");
1136 goto out;
1137 }
1138
1139 hw->mac.check_link(hw, &speed, &link_up, false);
1140 if (!link_up) {
1141 DEBUGOUT("The link is down");
1142 goto out;
1143 }
1144
1145 switch (hw->phy.media_type) {
1146 /* Autoneg flow control on fiber adapters */
1147 case txgbe_media_type_fiber_qsfp:
1148 case txgbe_media_type_fiber:
1149 if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1150 err = txgbe_fc_autoneg_fiber(hw);
1151 break;
1152
1153 /* Autoneg flow control on backplane adapters */
1154 case txgbe_media_type_backplane:
1155 err = txgbe_fc_autoneg_backplane(hw);
1156 break;
1157
1158 /* Autoneg flow control on copper adapters */
1159 case txgbe_media_type_copper:
1160 if (txgbe_device_supports_autoneg_fc(hw))
1161 err = txgbe_fc_autoneg_copper(hw);
1162 break;
1163
1164 default:
1165 break;
1166 }
1167
1168 out:
1169 if (err == 0) {
1170 hw->fc.fc_was_autonegged = true;
1171 } else {
1172 hw->fc.fc_was_autonegged = false;
1173 hw->fc.current_mode = hw->fc.requested_mode;
1174 }
1175 }
1176
1177 /**
1178 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
1179 * @hw: pointer to hardware structure
1180 * @mask: Mask to specify which semaphore to acquire
1181 *
1182 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1183 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1184 **/
txgbe_acquire_swfw_sync(struct txgbe_hw * hw,u32 mask)1185 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
1186 {
1187 u32 mngsem = 0;
1188 u32 swmask = TXGBE_MNGSEM_SW(mask);
1189 u32 fwmask = TXGBE_MNGSEM_FW(mask);
1190 u32 timeout = 200;
1191 u32 i;
1192
1193 for (i = 0; i < timeout; i++) {
1194 /*
1195 * SW NVM semaphore bit is used for access to all
1196 * SW_FW_SYNC bits (not just NVM)
1197 */
1198 if (txgbe_get_eeprom_semaphore(hw))
1199 return TXGBE_ERR_SWFW_SYNC;
1200
1201 mngsem = rd32(hw, TXGBE_MNGSEM);
1202 if (mngsem & (fwmask | swmask)) {
1203 /* Resource is currently in use by FW or SW */
1204 txgbe_release_eeprom_semaphore(hw);
1205 msec_delay(5);
1206 } else {
1207 mngsem |= swmask;
1208 wr32(hw, TXGBE_MNGSEM, mngsem);
1209 txgbe_release_eeprom_semaphore(hw);
1210 return 0;
1211 }
1212 }
1213
1214 /* If time expired clear the bits holding the lock and retry */
1215 if (mngsem & (fwmask | swmask))
1216 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1217
1218 msec_delay(5);
1219 return TXGBE_ERR_SWFW_SYNC;
1220 }
1221
1222 /**
1223 * txgbe_release_swfw_sync - Release SWFW semaphore
1224 * @hw: pointer to hardware structure
1225 * @mask: Mask to specify which semaphore to release
1226 *
1227 * Releases the SWFW semaphore through the MNGSEM register for the specified
1228 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1229 **/
txgbe_release_swfw_sync(struct txgbe_hw * hw,u32 mask)1230 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
1231 {
1232 u32 mngsem;
1233 u32 swmask = mask;
1234
1235 txgbe_get_eeprom_semaphore(hw);
1236
1237 mngsem = rd32(hw, TXGBE_MNGSEM);
1238 mngsem &= ~swmask;
1239 wr32(hw, TXGBE_MNGSEM, mngsem);
1240
1241 txgbe_release_eeprom_semaphore(hw);
1242 }
1243
1244 /**
1245 * txgbe_disable_sec_rx_path - Stops the receive data path
1246 * @hw: pointer to hardware structure
1247 *
1248 * Stops the receive data path and waits for the HW to internally empty
1249 * the Rx security block
1250 **/
txgbe_disable_sec_rx_path(struct txgbe_hw * hw)1251 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
1252 {
1253 #define TXGBE_MAX_SECRX_POLL 4000
1254
1255 int i;
1256 u32 secrxreg;
1257
1258 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1259 secrxreg |= TXGBE_SECRXCTL_XDSA;
1260 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1261 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
1262 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
1263 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
1264 /* Use interrupt-safe sleep just in case */
1265 usec_delay(10);
1266 else
1267 break;
1268 }
1269
1270 /* For informational purposes only */
1271 if (i >= TXGBE_MAX_SECRX_POLL)
1272 DEBUGOUT("Rx unit being enabled before security path fully disabled. Continuing with init.");
1273
1274 return 0;
1275 }
1276
1277 /**
1278 * txgbe_enable_sec_rx_path - Enables the receive data path
1279 * @hw: pointer to hardware structure
1280 *
1281 * Enables the receive data path.
1282 **/
txgbe_enable_sec_rx_path(struct txgbe_hw * hw)1283 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
1284 {
1285 u32 secrxreg;
1286
1287 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1288 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
1289 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1290 txgbe_flush(hw);
1291
1292 return 0;
1293 }
1294
1295 /**
1296 * txgbe_disable_sec_tx_path - Stops the transmit data path
1297 * @hw: pointer to hardware structure
1298 *
1299 * Stops the transmit data path and waits for the HW to internally empty
1300 * the Tx security block
1301 **/
txgbe_disable_sec_tx_path(struct txgbe_hw * hw)1302 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
1303 {
1304 #define TXGBE_MAX_SECTX_POLL 40
1305
1306 int i;
1307 u32 sectxreg;
1308
1309 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1310 sectxreg |= TXGBE_SECTXCTL_XDSA;
1311 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1312 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
1313 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
1314 if (sectxreg & TXGBE_SECTXSTAT_RDY)
1315 break;
1316 /* Use interrupt-safe sleep just in case */
1317 usec_delay(1000);
1318 }
1319
1320 /* For informational purposes only */
1321 if (i >= TXGBE_MAX_SECTX_POLL)
1322 DEBUGOUT("Tx unit being enabled before security path fully disabled. Continuing with init.");
1323
1324 return 0;
1325 }
1326
1327 /**
1328 * txgbe_enable_sec_tx_path - Enables the transmit data path
1329 * @hw: pointer to hardware structure
1330 *
1331 * Enables the transmit data path.
1332 **/
txgbe_enable_sec_tx_path(struct txgbe_hw * hw)1333 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
1334 {
1335 uint32_t sectxreg;
1336
1337 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1338 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
1339 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1340 txgbe_flush(hw);
1341
1342 return 0;
1343 }
1344
1345 /**
1346 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
1347 * @hw: pointer to hardware structure
1348 * @san_mac_offset: SAN MAC address offset
1349 *
1350 * This function will read the EEPROM location for the SAN MAC address
1351 * pointer, and returns the value at that location. This is used in both
1352 * get and set mac_addr routines.
1353 **/
txgbe_get_san_mac_addr_offset(struct txgbe_hw * hw,u16 * san_mac_offset)1354 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
1355 u16 *san_mac_offset)
1356 {
1357 s32 err;
1358
1359 /*
1360 * First read the EEPROM pointer to see if the MAC addresses are
1361 * available.
1362 */
1363 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
1364 san_mac_offset);
1365 if (err) {
1366 DEBUGOUT("eeprom at offset %d failed",
1367 TXGBE_SAN_MAC_ADDR_PTR);
1368 }
1369
1370 return err;
1371 }
1372
1373 /**
1374 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
1375 * @hw: pointer to hardware structure
1376 * @san_mac_addr: SAN MAC address
1377 *
1378 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1379 * per-port, so set_lan_id() must be called before reading the addresses.
1380 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1381 * upon for non-SFP connections, so we must call it here.
1382 **/
txgbe_get_san_mac_addr(struct txgbe_hw * hw,u8 * san_mac_addr)1383 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1384 {
1385 u16 san_mac_data, san_mac_offset;
1386 u8 i;
1387 s32 err;
1388
1389 /*
1390 * First read the EEPROM pointer to see if the MAC addresses are
1391 * available. If they're not, no point in calling set_lan_id() here.
1392 */
1393 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1394 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1395 goto san_mac_addr_out;
1396
1397 /* apply the port offset to the address offset */
1398 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1399 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1400 for (i = 0; i < 3; i++) {
1401 err = hw->rom.read16(hw, san_mac_offset,
1402 &san_mac_data);
1403 if (err) {
1404 DEBUGOUT("eeprom read at offset %d failed",
1405 san_mac_offset);
1406 goto san_mac_addr_out;
1407 }
1408 san_mac_addr[i * 2] = (u8)(san_mac_data);
1409 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1410 san_mac_offset++;
1411 }
1412 return 0;
1413
1414 san_mac_addr_out:
1415 /*
1416 * No addresses available in this EEPROM. It's not an
1417 * error though, so just wipe the local address and return.
1418 */
1419 for (i = 0; i < 6; i++)
1420 san_mac_addr[i] = 0xFF;
1421 return 0;
1422 }
1423
1424 /**
1425 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
1426 * @hw: pointer to hardware structure
1427 * @san_mac_addr: SAN MAC address
1428 *
1429 * Write a SAN MAC address to the EEPROM.
1430 **/
txgbe_set_san_mac_addr(struct txgbe_hw * hw,u8 * san_mac_addr)1431 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1432 {
1433 s32 err;
1434 u16 san_mac_data, san_mac_offset;
1435 u8 i;
1436
1437 /* Look for SAN mac address pointer. If not defined, return */
1438 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1439 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1440 return TXGBE_ERR_NO_SAN_ADDR_PTR;
1441
1442 /* Apply the port offset to the address offset */
1443 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1444 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1445
1446 for (i = 0; i < 3; i++) {
1447 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
1448 san_mac_data |= (u16)(san_mac_addr[i * 2]);
1449 hw->rom.write16(hw, san_mac_offset, san_mac_data);
1450 san_mac_offset++;
1451 }
1452
1453 return 0;
1454 }
1455
1456 /**
1457 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1458 * @hw: pointer to hardware struct
1459 * @rar: receive address register index to disassociate
1460 * @vmdq: VMDq pool index to remove from the rar
1461 **/
txgbe_clear_vmdq(struct txgbe_hw * hw,u32 rar,u32 vmdq)1462 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1463 {
1464 u32 mpsar_lo, mpsar_hi;
1465 u32 rar_entries = hw->mac.num_rar_entries;
1466
1467 /* Make sure we are using a valid rar index range */
1468 if (rar >= rar_entries) {
1469 DEBUGOUT("RAR index %d is out of range.", rar);
1470 return TXGBE_ERR_INVALID_ARGUMENT;
1471 }
1472
1473 wr32(hw, TXGBE_ETHADDRIDX, rar);
1474 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
1475 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
1476
1477 if (TXGBE_REMOVED(hw->hw_addr))
1478 goto done;
1479
1480 if (!mpsar_lo && !mpsar_hi)
1481 goto done;
1482
1483 if (vmdq == BIT_MASK32) {
1484 if (mpsar_lo) {
1485 wr32(hw, TXGBE_ETHADDRASSL, 0);
1486 mpsar_lo = 0;
1487 }
1488 if (mpsar_hi) {
1489 wr32(hw, TXGBE_ETHADDRASSH, 0);
1490 mpsar_hi = 0;
1491 }
1492 } else if (vmdq < 32) {
1493 mpsar_lo &= ~(1 << vmdq);
1494 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1495 } else {
1496 mpsar_hi &= ~(1 << (vmdq - 32));
1497 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1498 }
1499
1500 /* was that the last pool using this rar? */
1501 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1502 rar != 0 && rar != hw->mac.san_mac_rar_index)
1503 hw->mac.clear_rar(hw, rar);
1504 done:
1505 return 0;
1506 }
1507
1508 /**
1509 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1510 * @hw: pointer to hardware struct
1511 * @rar: receive address register index to associate with a VMDq index
1512 * @vmdq: VMDq pool index
1513 **/
txgbe_set_vmdq(struct txgbe_hw * hw,u32 rar,u32 vmdq)1514 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1515 {
1516 u32 mpsar;
1517 u32 rar_entries = hw->mac.num_rar_entries;
1518
1519 /* Make sure we are using a valid rar index range */
1520 if (rar >= rar_entries) {
1521 DEBUGOUT("RAR index %d is out of range.", rar);
1522 return TXGBE_ERR_INVALID_ARGUMENT;
1523 }
1524
1525 wr32(hw, TXGBE_ETHADDRIDX, rar);
1526 if (vmdq < 32) {
1527 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1528 mpsar |= 1 << vmdq;
1529 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1530 } else {
1531 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1532 mpsar |= 1 << (vmdq - 32);
1533 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1534 }
1535 return 0;
1536 }
1537
1538 /**
1539 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1540 * @hw: pointer to hardware structure
1541 **/
txgbe_init_uta_tables(struct txgbe_hw * hw)1542 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1543 {
1544 int i;
1545
1546 DEBUGOUT(" Clearing UTA");
1547
1548 for (i = 0; i < 128; i++)
1549 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1550
1551 return 0;
1552 }
1553
1554 /**
1555 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1556 * @hw: pointer to hardware structure
1557 * @vlan: VLAN id to write to VLAN filter
1558 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1559 * vlanid not found
1560 *
1561 *
1562 * return the VLVF index where this VLAN id should be placed
1563 *
1564 **/
txgbe_find_vlvf_slot(struct txgbe_hw * hw,u32 vlan,bool vlvf_bypass)1565 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1566 {
1567 s32 regindex, first_empty_slot;
1568 u32 bits;
1569
1570 /* short cut the special case */
1571 if (vlan == 0)
1572 return 0;
1573
1574 /* if vlvf_bypass is set we don't want to use an empty slot, we
1575 * will simply bypass the VLVF if there are no entries present in the
1576 * VLVF that contain our VLAN
1577 */
1578 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1579
1580 /* add VLAN enable bit for comparison */
1581 vlan |= TXGBE_PSRVLAN_EA;
1582
1583 /* Search for the vlan id in the VLVF entries. Save off the first empty
1584 * slot found along the way.
1585 *
1586 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1587 */
1588 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1589 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1590 bits = rd32(hw, TXGBE_PSRVLAN);
1591 if (bits == vlan)
1592 return regindex;
1593 if (!first_empty_slot && !bits)
1594 first_empty_slot = regindex;
1595 }
1596
1597 /* If we are here then we didn't find the VLAN. Return first empty
1598 * slot we found during our search, else error.
1599 */
1600 if (!first_empty_slot)
1601 DEBUGOUT("No space in VLVF.");
1602
1603 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1604 }
1605
1606 /**
1607 * txgbe_set_vfta - Set VLAN filter table
1608 * @hw: pointer to hardware structure
1609 * @vlan: VLAN id to write to VLAN filter
1610 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1611 * @vlan_on: boolean flag to turn on/off VLAN
1612 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1613 *
1614 * Turn on/off specified VLAN in the VLAN filter table.
1615 **/
txgbe_set_vfta(struct txgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool vlvf_bypass)1616 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1617 bool vlan_on, bool vlvf_bypass)
1618 {
1619 u32 regidx, vfta_delta, vfta;
1620 s32 err;
1621
1622 if (vlan > 4095 || vind > 63)
1623 return TXGBE_ERR_PARAM;
1624
1625 /*
1626 * this is a 2 part operation - first the VFTA, then the
1627 * VLVF and VLVFB if VT Mode is set
1628 * We don't write the VFTA until we know the VLVF part succeeded.
1629 */
1630
1631 /* Part 1
1632 * The VFTA is a bitstring made up of 128 32-bit registers
1633 * that enable the particular VLAN id, much like the MTA:
1634 * bits[11-5]: which register
1635 * bits[4-0]: which bit in the register
1636 */
1637 regidx = vlan / 32;
1638 vfta_delta = 1 << (vlan % 32);
1639 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1640
1641 /*
1642 * vfta_delta represents the difference between the current value
1643 * of vfta and the value we want in the register. Since the diff
1644 * is an XOR mask we can just update the vfta using an XOR
1645 */
1646 vfta_delta &= vlan_on ? ~vfta : vfta;
1647 vfta ^= vfta_delta;
1648
1649 /* Part 2
1650 * Call txgbe_set_vlvf to set VLVFB and VLVF
1651 */
1652 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1653 vfta, vlvf_bypass);
1654 if (err != 0) {
1655 if (vlvf_bypass)
1656 goto vfta_update;
1657 return err;
1658 }
1659
1660 vfta_update:
1661 /* Update VFTA now that we are ready for traffic */
1662 if (vfta_delta)
1663 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1664
1665 return 0;
1666 }
1667
1668 /**
1669 * txgbe_set_vlvf - Set VLAN Pool Filter
1670 * @hw: pointer to hardware structure
1671 * @vlan: VLAN id to write to VLAN filter
1672 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1673 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1674 * @vfta_delta: pointer to the difference between the current value
1675 * of PSRVLANPLM and the desired value
1676 * @vfta: the desired value of the VFTA
1677 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1678 *
1679 * Turn on/off specified bit in VLVF table.
1680 **/
txgbe_set_vlvf(struct txgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,u32 * vfta_delta,u32 vfta,bool vlvf_bypass)1681 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1682 bool vlan_on, u32 *vfta_delta, u32 vfta,
1683 bool vlvf_bypass)
1684 {
1685 u32 bits;
1686 u32 portctl;
1687 s32 vlvf_index;
1688
1689 if (vlan > 4095 || vind > 63)
1690 return TXGBE_ERR_PARAM;
1691
1692 /* If VT Mode is set
1693 * Either vlan_on
1694 * make sure the vlan is in PSRVLAN
1695 * set the vind bit in the matching PSRVLANPLM
1696 * Or !vlan_on
1697 * clear the pool bit and possibly the vind
1698 */
1699 portctl = rd32(hw, TXGBE_PORTCTL);
1700 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1701 return 0;
1702
1703 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1704 if (vlvf_index < 0)
1705 return vlvf_index;
1706
1707 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1708 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1709
1710 /* set the pool bit */
1711 bits |= 1 << (vind % 32);
1712 if (vlan_on)
1713 goto vlvf_update;
1714
1715 /* clear the pool bit */
1716 bits ^= 1 << (vind % 32);
1717
1718 if (!bits &&
1719 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1720 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1721 * we run the risk of stray packets leaking into
1722 * the PF via the default pool
1723 */
1724 if (*vfta_delta)
1725 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1726
1727 /* disable VLVF and clear remaining bit from pool */
1728 wr32(hw, TXGBE_PSRVLAN, 0);
1729 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1730
1731 return 0;
1732 }
1733
1734 /* If there are still bits set in the PSRVLANPLM registers
1735 * for the VLAN ID indicated we need to see if the
1736 * caller is requesting that we clear the PSRVLANPLM entry bit.
1737 * If the caller has requested that we clear the PSRVLANPLM
1738 * entry bit but there are still pools/VFs using this VLAN
1739 * ID entry then ignore the request. We're not worried
1740 * about the case where we're turning the PSRVLANPLM VLAN ID
1741 * entry bit on, only when requested to turn it off as
1742 * there may be multiple pools and/or VFs using the
1743 * VLAN ID entry. In that case we cannot clear the
1744 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1745 * been cleared. This will be indicated by "bits" being
1746 * zero.
1747 */
1748 *vfta_delta = 0;
1749
1750 vlvf_update:
1751 /* record pool change and enable VLAN ID if not already enabled */
1752 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1753 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1754
1755 return 0;
1756 }
1757
1758 /**
1759 * txgbe_clear_vfta - Clear VLAN filter table
1760 * @hw: pointer to hardware structure
1761 *
1762 * Clears the VLAN filer table, and the VMDq index associated with the filter
1763 **/
txgbe_clear_vfta(struct txgbe_hw * hw)1764 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1765 {
1766 u32 offset;
1767
1768 for (offset = 0; offset < hw->mac.vft_size; offset++)
1769 wr32(hw, TXGBE_VLANTBL(offset), 0);
1770
1771 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1772 wr32(hw, TXGBE_PSRVLANIDX, offset);
1773 wr32(hw, TXGBE_PSRVLAN, 0);
1774 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1775 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1776 }
1777
1778 return 0;
1779 }
1780
1781 /**
1782 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1783 * @hw: pointer to hardware structure
1784 *
1785 * Contains the logic to identify if we need to verify link for the
1786 * crosstalk fix
1787 **/
txgbe_need_crosstalk_fix(struct txgbe_hw * hw)1788 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1789 {
1790 /* Does FW say we need the fix */
1791 if (!hw->need_crosstalk_fix)
1792 return false;
1793
1794 /* Only consider SFP+ PHYs i.e. media type fiber */
1795 switch (hw->phy.media_type) {
1796 case txgbe_media_type_fiber:
1797 case txgbe_media_type_fiber_qsfp:
1798 break;
1799 default:
1800 return false;
1801 }
1802
1803 return true;
1804 }
1805
1806 /**
1807 * txgbe_check_mac_link - Determine link and speed status
1808 * @hw: pointer to hardware structure
1809 * @speed: pointer to link speed
1810 * @link_up: true when link is up
1811 * @link_up_wait_to_complete: bool used to wait for link up or not
1812 *
1813 * Reads the links register to determine if link is up and the current speed
1814 **/
txgbe_check_mac_link(struct txgbe_hw * hw,u32 * speed,bool * link_up,bool link_up_wait_to_complete)1815 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1816 bool *link_up, bool link_up_wait_to_complete)
1817 {
1818 u32 links_reg, links_orig;
1819 u32 i;
1820
1821 /* If Crosstalk fix enabled do the sanity check of making sure
1822 * the SFP+ cage is full.
1823 */
1824 if (txgbe_need_crosstalk_fix(hw)) {
1825 u32 sfp_cage_full;
1826
1827 switch (hw->mac.type) {
1828 case txgbe_mac_raptor:
1829 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1830 TXGBE_GPIOBIT_2);
1831 break;
1832 default:
1833 /* sanity check - No SFP+ devices here */
1834 sfp_cage_full = false;
1835 break;
1836 }
1837
1838 if (!sfp_cage_full) {
1839 *link_up = false;
1840 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1841 return 0;
1842 }
1843 }
1844
1845 /* clear the old state */
1846 links_orig = rd32(hw, TXGBE_PORTSTAT);
1847
1848 links_reg = rd32(hw, TXGBE_PORTSTAT);
1849
1850 if (links_orig != links_reg) {
1851 DEBUGOUT("LINKS changed from %08X to %08X",
1852 links_orig, links_reg);
1853 }
1854
1855 if (link_up_wait_to_complete) {
1856 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1857 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1858 *link_up = false;
1859 } else {
1860 *link_up = true;
1861 break;
1862 }
1863 msec_delay(100);
1864 links_reg = rd32(hw, TXGBE_PORTSTAT);
1865 }
1866 } else {
1867 if (links_reg & TXGBE_PORTSTAT_UP)
1868 *link_up = true;
1869 else
1870 *link_up = false;
1871 }
1872
1873 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1874 case TXGBE_PORTSTAT_BW_10G:
1875 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1876 break;
1877 case TXGBE_PORTSTAT_BW_1G:
1878 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1879 break;
1880 case TXGBE_PORTSTAT_BW_100M:
1881 *speed = TXGBE_LINK_SPEED_100M_FULL;
1882 break;
1883 default:
1884 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1885 }
1886
1887 return 0;
1888 }
1889
1890 /**
1891 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1892 * the EEPROM
1893 * @hw: pointer to hardware structure
1894 * @wwnn_prefix: the alternative WWNN prefix
1895 * @wwpn_prefix: the alternative WWPN prefix
1896 *
1897 * This function will read the EEPROM from the alternative SAN MAC address
1898 * block to check the support for the alternative WWNN/WWPN prefix support.
1899 **/
txgbe_get_wwn_prefix(struct txgbe_hw * hw,u16 * wwnn_prefix,u16 * wwpn_prefix)1900 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1901 u16 *wwpn_prefix)
1902 {
1903 u16 offset, caps;
1904 u16 alt_san_mac_blk_offset;
1905
1906 /* clear output first */
1907 *wwnn_prefix = 0xFFFF;
1908 *wwpn_prefix = 0xFFFF;
1909
1910 /* check if alternative SAN MAC is supported */
1911 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1912 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1913 goto wwn_prefix_err;
1914
1915 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1916 goto wwn_prefix_out;
1917
1918 /* check capability in alternative san mac address block */
1919 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1920 if (hw->rom.read16(hw, offset, &caps))
1921 goto wwn_prefix_err;
1922 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1923 goto wwn_prefix_out;
1924
1925 /* get the corresponding prefix for WWNN/WWPN */
1926 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
1927 if (hw->rom.read16(hw, offset, wwnn_prefix))
1928 DEBUGOUT("eeprom read at offset %d failed", offset);
1929
1930 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
1931 if (hw->rom.read16(hw, offset, wwpn_prefix))
1932 goto wwn_prefix_err;
1933
1934 wwn_prefix_out:
1935 return 0;
1936
1937 wwn_prefix_err:
1938 DEBUGOUT("eeprom read at offset %d failed", offset);
1939 return 0;
1940 }
1941
1942 /**
1943 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1944 * @hw: pointer to hardware structure
1945 * @enable: enable or disable switch for MAC anti-spoofing
1946 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1947 *
1948 **/
txgbe_set_mac_anti_spoofing(struct txgbe_hw * hw,bool enable,int vf)1949 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
1950 {
1951 int vf_target_reg = vf >> 3;
1952 int vf_target_shift = vf % 8;
1953 u32 pfvfspoof;
1954
1955 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
1956 if (enable)
1957 pfvfspoof |= (1 << vf_target_shift);
1958 else
1959 pfvfspoof &= ~(1 << vf_target_shift);
1960 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
1961 }
1962
1963 /**
1964 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
1965 * @hw: pointer to hardware structure
1966 * @enable: enable or disable switch for Ethertype anti-spoofing
1967 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1968 *
1969 **/
txgbe_set_ethertype_anti_spoofing(struct txgbe_hw * hw,bool enable,int vf)1970 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
1971 bool enable, int vf)
1972 {
1973 int vf_target_reg = vf >> 3;
1974 int vf_target_shift = vf % 8;
1975 u32 pfvfspoof;
1976
1977 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
1978 if (enable)
1979 pfvfspoof |= (1 << vf_target_shift);
1980 else
1981 pfvfspoof &= ~(1 << vf_target_shift);
1982 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
1983 }
1984
1985 /**
1986 * txgbe_get_device_caps - Get additional device capabilities
1987 * @hw: pointer to hardware structure
1988 * @device_caps: the EEPROM word with the extra device capabilities
1989 *
1990 * This function will read the EEPROM location for the device capabilities,
1991 * and return the word through device_caps.
1992 **/
txgbe_get_device_caps(struct txgbe_hw * hw,u16 * device_caps)1993 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
1994 {
1995 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
1996
1997 return 0;
1998 }
1999
2000 /**
2001 * txgbe_set_pba - Initialize Rx packet buffer
2002 * @hw: pointer to hardware structure
2003 * @num_pb: number of packet buffers to allocate
2004 * @headroom: reserve n KB of headroom
2005 * @strategy: packet buffer allocation strategy
2006 **/
txgbe_set_pba(struct txgbe_hw * hw,int num_pb,u32 headroom,int strategy)2007 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
2008 int strategy)
2009 {
2010 u32 pbsize = hw->mac.rx_pb_size;
2011 int i = 0;
2012 u32 rxpktsize, txpktsize, txpbthresh;
2013
2014 UNREFERENCED_PARAMETER(hw);
2015
2016 /* Reserve headroom */
2017 pbsize -= headroom;
2018
2019 if (!num_pb)
2020 num_pb = 1;
2021
2022 /* Divide remaining packet buffer space amongst the number of packet
2023 * buffers requested using supplied strategy.
2024 */
2025 switch (strategy) {
2026 case PBA_STRATEGY_WEIGHTED:
2027 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
2028 * buffer with 5/8 of the packet buffer space.
2029 */
2030 rxpktsize = (pbsize * 5) / (num_pb * 4);
2031 pbsize -= rxpktsize * (num_pb / 2);
2032 rxpktsize <<= 10;
2033 for (; i < (num_pb / 2); i++)
2034 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2035 /* fall through - configure remaining packet buffers */
2036 case PBA_STRATEGY_EQUAL:
2037 rxpktsize = (pbsize / (num_pb - i));
2038 rxpktsize <<= 10;
2039 for (; i < num_pb; i++)
2040 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2041 break;
2042 default:
2043 break;
2044 }
2045
2046 /* Only support an equally distributed Tx packet buffer strategy. */
2047 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
2048 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
2049 for (i = 0; i < num_pb; i++) {
2050 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
2051 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
2052 }
2053
2054 /* Clear unused TCs, if any, to zero buffer size*/
2055 for (; i < TXGBE_MAX_UP; i++) {
2056 wr32(hw, TXGBE_PBRXSIZE(i), 0);
2057 wr32(hw, TXGBE_PBTXSIZE(i), 0);
2058 wr32(hw, TXGBE_PBTXDMATH(i), 0);
2059 }
2060 }
2061
2062 /**
2063 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
2064 * @hw: pointer to the hardware structure
2065 *
2066 * The MACs can experience issues if TX work is still pending
2067 * when a reset occurs. This function prevents this by flushing the PCIe
2068 * buffers on the system.
2069 **/
txgbe_clear_tx_pending(struct txgbe_hw * hw)2070 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
2071 {
2072 u32 hlreg0, i, poll;
2073
2074 /*
2075 * If double reset is not requested then all transactions should
2076 * already be clear and as such there is no work to do
2077 */
2078 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
2079 return;
2080
2081 hlreg0 = rd32(hw, TXGBE_PSRCTL);
2082 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
2083
2084 /* Wait for a last completion before clearing buffers */
2085 txgbe_flush(hw);
2086 msec_delay(3);
2087
2088 /*
2089 * Before proceeding, make sure that the PCIe block does not have
2090 * transactions pending.
2091 */
2092 poll = (800 * 11) / 10;
2093 for (i = 0; i < poll; i++)
2094 usec_delay(100);
2095
2096 /* Flush all writes and allow 20usec for all transactions to clear */
2097 txgbe_flush(hw);
2098 usec_delay(20);
2099
2100 /* restore previous register values */
2101 wr32(hw, TXGBE_PSRCTL, hlreg0);
2102 }
2103
2104 /**
2105 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
2106 * @hw: pointer to hardware structure
2107 *
2108 * Returns the thermal sensor data structure
2109 **/
txgbe_get_thermal_sensor_data(struct txgbe_hw * hw)2110 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
2111 {
2112 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2113 s64 tsv;
2114 u32 ts_stat;
2115
2116 /* Only support thermal sensors attached to physical port 0 */
2117 if (hw->bus.lan_id != 0)
2118 return TXGBE_NOT_IMPLEMENTED;
2119
2120 ts_stat = rd32(hw, TXGBE_TSSTAT);
2121 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
2122 tsv = tsv > 1200 ? tsv : 1200;
2123 tsv = -(48380 << 8) / 1000
2124 + tsv * (31020 << 8) / 100000
2125 - tsv * tsv * (18201 << 8) / 100000000
2126 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
2127 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
2128 tsv >>= 8;
2129
2130 data->sensor[0].temp = (s16)tsv;
2131
2132 return 0;
2133 }
2134
2135 /**
2136 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
2137 * @hw: pointer to hardware structure
2138 *
2139 * Inits the thermal sensor thresholds according to the NVM map
2140 * and save off the threshold and location values into mac.thermal_sensor_data
2141 **/
txgbe_init_thermal_sensor_thresh(struct txgbe_hw * hw)2142 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
2143 {
2144 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2145
2146 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
2147
2148 if (hw->bus.lan_id != 0)
2149 return TXGBE_NOT_IMPLEMENTED;
2150
2151 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
2152 wr32(hw, TXGBE_TSINTR,
2153 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
2154 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
2155
2156
2157 data->sensor[0].alarm_thresh = 100;
2158 wr32(hw, TXGBE_TSATHRE, 677);
2159 data->sensor[0].dalarm_thresh = 90;
2160 wr32(hw, TXGBE_TSDTHRE, 614);
2161
2162 return 0;
2163 }
2164
txgbe_disable_rx(struct txgbe_hw * hw)2165 void txgbe_disable_rx(struct txgbe_hw *hw)
2166 {
2167 u32 pfdtxgswc;
2168
2169 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2170 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
2171 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
2172 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2173 hw->mac.set_lben = true;
2174 } else {
2175 hw->mac.set_lben = false;
2176 }
2177
2178 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
2179 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
2180 }
2181
txgbe_enable_rx(struct txgbe_hw * hw)2182 void txgbe_enable_rx(struct txgbe_hw *hw)
2183 {
2184 u32 pfdtxgswc;
2185
2186 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
2187 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
2188
2189 if (hw->mac.set_lben) {
2190 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2191 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
2192 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2193 hw->mac.set_lben = false;
2194 }
2195 }
2196
2197 /**
2198 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2199 * @hw: pointer to hardware structure
2200 * @speed: new link speed
2201 * @autoneg_wait_to_complete: true when waiting for completion is needed
2202 *
2203 * Set the link speed in the MAC and/or PHY register and restarts link.
2204 **/
txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw * hw,u32 speed,bool autoneg_wait_to_complete)2205 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
2206 u32 speed,
2207 bool autoneg_wait_to_complete)
2208 {
2209 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2210 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2211 s32 status = 0;
2212 u32 speedcnt = 0;
2213 u32 i = 0;
2214 bool autoneg, link_up = false;
2215
2216 /* Mask off requested but non-supported speeds */
2217 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
2218 if (status != 0)
2219 return status;
2220
2221 speed &= link_speed;
2222
2223 /* Try each speed one by one, highest priority first. We do this in
2224 * software because 10Gb fiber doesn't support speed autonegotiation.
2225 */
2226 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2227 speedcnt++;
2228 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
2229
2230 /* Set the module link speed */
2231 switch (hw->phy.media_type) {
2232 case txgbe_media_type_fiber:
2233 hw->mac.set_rate_select_speed(hw,
2234 TXGBE_LINK_SPEED_10GB_FULL);
2235 break;
2236 case txgbe_media_type_fiber_qsfp:
2237 /* QSFP module automatically detects MAC link speed */
2238 break;
2239 default:
2240 DEBUGOUT("Unexpected media type.");
2241 break;
2242 }
2243
2244 /* Allow module to change analog characteristics (1G->10G) */
2245 msec_delay(40);
2246
2247 status = hw->mac.setup_mac_link(hw,
2248 TXGBE_LINK_SPEED_10GB_FULL,
2249 autoneg_wait_to_complete);
2250 if (status != 0)
2251 return status;
2252
2253 /* Flap the Tx laser if it has not already been done */
2254 hw->mac.flap_tx_laser(hw);
2255
2256 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
2257 * Section 73.10.2, we may have to wait up to 500ms if KR is
2258 * attempted. uses the same timing for 10g SFI.
2259 */
2260 for (i = 0; i < 5; i++) {
2261 /* Wait for the link partner to also set speed */
2262 msec_delay(100);
2263
2264 /* If we have link, just jump out */
2265 status = hw->mac.check_link(hw, &link_speed,
2266 &link_up, false);
2267 if (status != 0)
2268 return status;
2269
2270 if (link_up)
2271 goto out;
2272 }
2273 }
2274
2275 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
2276 speedcnt++;
2277 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
2278 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
2279
2280 /* Set the module link speed */
2281 switch (hw->phy.media_type) {
2282 case txgbe_media_type_fiber:
2283 hw->mac.set_rate_select_speed(hw,
2284 TXGBE_LINK_SPEED_1GB_FULL);
2285 break;
2286 case txgbe_media_type_fiber_qsfp:
2287 /* QSFP module automatically detects link speed */
2288 break;
2289 default:
2290 DEBUGOUT("Unexpected media type.");
2291 break;
2292 }
2293
2294 /* Allow module to change analog characteristics (10G->1G) */
2295 msec_delay(40);
2296
2297 status = hw->mac.setup_mac_link(hw,
2298 TXGBE_LINK_SPEED_1GB_FULL,
2299 autoneg_wait_to_complete);
2300 if (status != 0)
2301 return status;
2302
2303 /* Flap the Tx laser if it has not already been done */
2304 hw->mac.flap_tx_laser(hw);
2305
2306 /* Wait for the link partner to also set speed */
2307 msec_delay(100);
2308
2309 /* If we have link, just jump out */
2310 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2311 if (status != 0)
2312 return status;
2313
2314 if (link_up)
2315 goto out;
2316 }
2317
2318 /* We didn't get link. Configure back to the highest speed we tried,
2319 * (if there was more than one). We call ourselves back with just the
2320 * single highest speed that the user requested.
2321 */
2322 if (speedcnt > 1)
2323 status = txgbe_setup_mac_link_multispeed_fiber(hw,
2324 highest_link_speed,
2325 autoneg_wait_to_complete);
2326
2327 out:
2328 /* Set autoneg_advertised value based on input link speed */
2329 hw->phy.autoneg_advertised = 0;
2330
2331 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2332 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2333
2334 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2335 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2336
2337 return status;
2338 }
2339
2340 /**
2341 * txgbe_init_shared_code - Initialize the shared code
2342 * @hw: pointer to hardware structure
2343 *
2344 * This will assign function pointers and assign the MAC type and PHY code.
2345 * Does not touch the hardware. This function must be called prior to any
2346 * other function in the shared code. The txgbe_hw structure should be
2347 * memset to 0 prior to calling this function. The following fields in
2348 * hw structure should be filled in prior to calling this function:
2349 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
2350 * subsystem_vendor_id, and revision_id
2351 **/
txgbe_init_shared_code(struct txgbe_hw * hw)2352 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
2353 {
2354 s32 status;
2355
2356 /*
2357 * Set the mac type
2358 */
2359 txgbe_set_mac_type(hw);
2360
2361 txgbe_init_ops_dummy(hw);
2362 switch (hw->mac.type) {
2363 case txgbe_mac_raptor:
2364 status = txgbe_init_ops_pf(hw);
2365 break;
2366 case txgbe_mac_raptor_vf:
2367 status = txgbe_init_ops_vf(hw);
2368 break;
2369 default:
2370 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2371 break;
2372 }
2373 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
2374
2375 hw->bus.set_lan_id(hw);
2376
2377 return status;
2378 }
2379
2380 /**
2381 * txgbe_set_mac_type - Sets MAC type
2382 * @hw: pointer to the HW structure
2383 *
2384 * This function sets the mac type of the adapter based on the
2385 * vendor ID and device ID stored in the hw structure.
2386 **/
txgbe_set_mac_type(struct txgbe_hw * hw)2387 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
2388 {
2389 s32 err = 0;
2390
2391 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
2392 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
2393 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2394 }
2395
2396 switch (hw->device_id) {
2397 case TXGBE_DEV_ID_SP1000:
2398 case TXGBE_DEV_ID_WX1820:
2399 hw->mac.type = txgbe_mac_raptor;
2400 break;
2401 case TXGBE_DEV_ID_SP1000_VF:
2402 case TXGBE_DEV_ID_WX1820_VF:
2403 hw->phy.media_type = txgbe_media_type_virtual;
2404 hw->mac.type = txgbe_mac_raptor_vf;
2405 break;
2406 default:
2407 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2408 DEBUGOUT("Unsupported device id: %x", hw->device_id);
2409 break;
2410 }
2411
2412 DEBUGOUT("found mac: %d, returns: %d",
2413 hw->mac.type, err);
2414 return err;
2415 }
2416
txgbe_init_mac_link_ops(struct txgbe_hw * hw)2417 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
2418 {
2419 struct txgbe_mac_info *mac = &hw->mac;
2420
2421 /*
2422 * enable the laser control functions for SFP+ fiber
2423 * and MNG not enabled
2424 */
2425 if (hw->phy.media_type == txgbe_media_type_fiber &&
2426 !txgbe_mng_enabled(hw)) {
2427 mac->disable_tx_laser =
2428 txgbe_disable_tx_laser_multispeed_fiber;
2429 mac->enable_tx_laser =
2430 txgbe_enable_tx_laser_multispeed_fiber;
2431 mac->flap_tx_laser =
2432 txgbe_flap_tx_laser_multispeed_fiber;
2433 }
2434
2435 if ((hw->phy.media_type == txgbe_media_type_fiber ||
2436 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
2437 hw->phy.multispeed_fiber) {
2438 /* Set up dual speed SFP+ support */
2439 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
2440 mac->setup_mac_link = txgbe_setup_mac_link;
2441 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2442 } else {
2443 mac->setup_link = txgbe_setup_mac_link;
2444 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2445 }
2446 }
2447
2448 /**
2449 * txgbe_init_phy_raptor - PHY/SFP specific init
2450 * @hw: pointer to hardware structure
2451 *
2452 * Initialize any function pointers that were not able to be
2453 * set during init_shared_code because the PHY/SFP type was
2454 * not known. Perform the SFP init if necessary.
2455 *
2456 **/
txgbe_init_phy_raptor(struct txgbe_hw * hw)2457 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2458 {
2459 struct txgbe_mac_info *mac = &hw->mac;
2460 struct txgbe_phy_info *phy = &hw->phy;
2461 s32 err = 0;
2462
2463 if ((hw->device_id & 0xFF) == TXGBE_DEV_ID_QSFP) {
2464 /* Store flag indicating I2C bus access control unit. */
2465 hw->phy.qsfp_shared_i2c_bus = TRUE;
2466
2467 /* Initialize access to QSFP+ I2C bus */
2468 txgbe_flush(hw);
2469 }
2470
2471 /* Identify the PHY or SFP module */
2472 err = phy->identify(hw);
2473 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2474 goto init_phy_ops_out;
2475
2476 /* Setup function pointers based on detected SFP module and speeds */
2477 txgbe_init_mac_link_ops(hw);
2478
2479 /* If copper media, overwrite with copper function pointers */
2480 if (phy->media_type == txgbe_media_type_copper) {
2481 mac->setup_link = txgbe_setup_copper_link_raptor;
2482 mac->get_link_capabilities =
2483 txgbe_get_copper_link_capabilities;
2484 }
2485
2486 if (phy->media_type == txgbe_media_type_backplane) {
2487 mac->kr_handle = txgbe_kr_handle;
2488 mac->bp_down_event = txgbe_bp_down_event;
2489 }
2490
2491 /* Set necessary function pointers based on PHY type */
2492 switch (hw->phy.type) {
2493 case txgbe_phy_tn:
2494 phy->setup_link = txgbe_setup_phy_link_tnx;
2495 phy->check_link = txgbe_check_phy_link_tnx;
2496 break;
2497 default:
2498 break;
2499 }
2500
2501 init_phy_ops_out:
2502 return err;
2503 }
2504
txgbe_setup_sfp_modules(struct txgbe_hw * hw)2505 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2506 {
2507 s32 err = 0;
2508
2509 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2510 return 0;
2511
2512 txgbe_init_mac_link_ops(hw);
2513
2514 /* PHY config will finish before releasing the semaphore */
2515 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2516 if (err != 0)
2517 return TXGBE_ERR_SWFW_SYNC;
2518
2519 /* Release the semaphore */
2520 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2521
2522 /* Delay obtaining semaphore again to allow FW access
2523 * prot_autoc_write uses the semaphore too.
2524 */
2525 msec_delay(hw->rom.semaphore_delay);
2526
2527 if (err) {
2528 DEBUGOUT("sfp module setup not complete");
2529 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2530 }
2531
2532 return err;
2533 }
2534
2535 /**
2536 * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read
2537 * @hw: pointer to hardware structure
2538 * @locked: Return the if we locked for this read.
2539 * @value: Value we read from AUTOC
2540 *
2541 * For this part we need to wrap read-modify-writes with a possible
2542 * FW/SW lock. It is assumed this lock will be freed with the next
2543 * prot_autoc_write_raptor().
2544 */
txgbe_prot_autoc_read_raptor(struct txgbe_hw * hw,bool * locked,u64 * value)2545 s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value)
2546 {
2547 s32 err;
2548 bool lock_state = false;
2549
2550 /* If LESM is on then we need to hold the SW/FW semaphore. */
2551 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2552 err = hw->mac.acquire_swfw_sync(hw,
2553 TXGBE_MNGSEM_SWPHY);
2554 if (err != 0)
2555 return TXGBE_ERR_SWFW_SYNC;
2556
2557 lock_state = true;
2558 }
2559
2560 if (locked)
2561 *locked = lock_state;
2562
2563 *value = txgbe_autoc_read(hw);
2564 return 0;
2565 }
2566
2567 /**
2568 * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write
2569 * @hw: pointer to hardware structure
2570 * @autoc: value to write to AUTOC
2571 * @locked: bool to indicate whether the SW/FW lock was already taken by
2572 * previous prot_autoc_read_raptor.
2573 *
2574 * This part may need to hold the SW/FW lock around all writes to
2575 * AUTOC. Likewise after a write we need to do a pipeline reset.
2576 */
txgbe_prot_autoc_write_raptor(struct txgbe_hw * hw,bool locked,u64 autoc)2577 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
2578 {
2579 int err = 0;
2580
2581 /* Blocked by MNG FW so bail */
2582 if (txgbe_check_reset_blocked(hw))
2583 goto out;
2584
2585 /* We only need to get the lock if:
2586 * - We didn't do it already (in the read part of a read-modify-write)
2587 * - LESM is enabled.
2588 */
2589 if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2590 err = hw->mac.acquire_swfw_sync(hw,
2591 TXGBE_MNGSEM_SWPHY);
2592 if (err != 0)
2593 return TXGBE_ERR_SWFW_SYNC;
2594
2595 locked = true;
2596 }
2597
2598 txgbe_autoc_write(hw, autoc);
2599 err = txgbe_reset_pipeline_raptor(hw);
2600
2601 out:
2602 /* Free the SW/FW semaphore as we either grabbed it here or
2603 * already had it when this function was called.
2604 */
2605 if (locked)
2606 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2607
2608 return err;
2609 }
2610
2611 /**
2612 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2613 * @hw: pointer to hardware structure
2614 *
2615 * Initialize the function pointers and assign the MAC type.
2616 * Does not touch the hardware.
2617 **/
txgbe_init_ops_pf(struct txgbe_hw * hw)2618 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2619 {
2620 struct txgbe_bus_info *bus = &hw->bus;
2621 struct txgbe_mac_info *mac = &hw->mac;
2622 struct txgbe_phy_info *phy = &hw->phy;
2623 struct txgbe_rom_info *rom = &hw->rom;
2624 struct txgbe_mbx_info *mbx = &hw->mbx;
2625
2626 /* BUS */
2627 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2628
2629 /* PHY */
2630 phy->get_media_type = txgbe_get_media_type_raptor;
2631 phy->identify = txgbe_identify_phy;
2632 phy->init = txgbe_init_phy_raptor;
2633 phy->read_reg = txgbe_read_phy_reg;
2634 phy->write_reg = txgbe_write_phy_reg;
2635 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2636 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2637 phy->setup_link = txgbe_setup_phy_link;
2638 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2639 phy->get_fw_version = txgbe_get_phy_fw_version;
2640 phy->read_i2c_byte = txgbe_read_i2c_byte;
2641 phy->write_i2c_byte = txgbe_write_i2c_byte;
2642 phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
2643 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2644 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2645 phy->identify_sfp = txgbe_identify_module;
2646 phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
2647 phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
2648 phy->reset = txgbe_reset_phy;
2649
2650 /* MAC */
2651 mac->init_hw = txgbe_init_hw;
2652 mac->start_hw = txgbe_start_hw_raptor;
2653 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2654 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2655 mac->get_mac_addr = txgbe_get_mac_addr;
2656 mac->stop_hw = txgbe_stop_hw;
2657 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2658 mac->release_swfw_sync = txgbe_release_swfw_sync;
2659 mac->reset_hw = txgbe_reset_hw;
2660 mac->update_mc_addr_list = txgbe_update_mc_addr_list;
2661
2662 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2663 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2664 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2665 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2666 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2667 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2668 mac->get_device_caps = txgbe_get_device_caps;
2669 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2670 mac->autoc_read = txgbe_autoc_read;
2671 mac->autoc_write = txgbe_autoc_write;
2672 mac->prot_autoc_read = txgbe_prot_autoc_read_raptor;
2673 mac->prot_autoc_write = txgbe_prot_autoc_write_raptor;
2674
2675 /* RAR, Multicast, VLAN */
2676 mac->set_rar = txgbe_set_rar;
2677 mac->clear_rar = txgbe_clear_rar;
2678 mac->init_rx_addrs = txgbe_init_rx_addrs;
2679 mac->enable_rx = txgbe_enable_rx;
2680 mac->disable_rx = txgbe_disable_rx;
2681 mac->set_vmdq = txgbe_set_vmdq;
2682 mac->clear_vmdq = txgbe_clear_vmdq;
2683 mac->set_vfta = txgbe_set_vfta;
2684 mac->set_vlvf = txgbe_set_vlvf;
2685 mac->clear_vfta = txgbe_clear_vfta;
2686 mac->init_uta_tables = txgbe_init_uta_tables;
2687 mac->setup_sfp = txgbe_setup_sfp_modules;
2688 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2689 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2690
2691 /* Flow Control */
2692 mac->fc_enable = txgbe_fc_enable;
2693 mac->setup_fc = txgbe_setup_fc;
2694 mac->fc_autoneg = txgbe_fc_autoneg;
2695
2696 /* Link */
2697 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2698 mac->check_link = txgbe_check_mac_link;
2699 mac->setup_pba = txgbe_set_pba;
2700
2701 /* Manageability interface */
2702 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2703 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2704 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2705
2706 mbx->init_params = txgbe_init_mbx_params_pf;
2707 mbx->read = txgbe_read_mbx_pf;
2708 mbx->write = txgbe_write_mbx_pf;
2709 mbx->check_for_msg = txgbe_check_for_msg_pf;
2710 mbx->check_for_ack = txgbe_check_for_ack_pf;
2711 mbx->check_for_rst = txgbe_check_for_rst_pf;
2712
2713 /* EEPROM */
2714 rom->init_params = txgbe_init_eeprom_params;
2715 rom->read16 = txgbe_ee_read16;
2716 rom->readw_buffer = txgbe_ee_readw_buffer;
2717 rom->readw_sw = txgbe_ee_readw_sw;
2718 rom->read32 = txgbe_ee_read32;
2719 rom->write16 = txgbe_ee_write16;
2720 rom->writew_buffer = txgbe_ee_writew_buffer;
2721 rom->writew_sw = txgbe_ee_writew_sw;
2722 rom->write32 = txgbe_ee_write32;
2723 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2724 rom->update_checksum = txgbe_update_eeprom_checksum;
2725 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2726
2727 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2728 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2729 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2730 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2731 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2732 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2733
2734 return 0;
2735 }
2736
2737 /**
2738 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2739 * @hw: pointer to hardware structure
2740 * @speed: pointer to link speed
2741 * @autoneg: true when autoneg or autotry is enabled
2742 *
2743 * Determines the link capabilities by reading the AUTOC register.
2744 **/
txgbe_get_link_capabilities_raptor(struct txgbe_hw * hw,u32 * speed,bool * autoneg)2745 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2746 u32 *speed,
2747 bool *autoneg)
2748 {
2749 s32 status = 0;
2750 u32 autoc = 0;
2751
2752 /* Check if 1G SFP module. */
2753 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2754 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2755 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2756 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2757 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2758 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2759 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2760 *autoneg = true;
2761 return 0;
2762 }
2763
2764 /*
2765 * Determine link capabilities based on the stored value of AUTOC,
2766 * which represents EEPROM defaults. If AUTOC value has not
2767 * been stored, use the current register values.
2768 */
2769 if (hw->mac.orig_link_settings_stored)
2770 autoc = hw->mac.orig_autoc;
2771 else
2772 autoc = hw->mac.autoc_read(hw);
2773
2774 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2775 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2776 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2777 *autoneg = false;
2778 break;
2779
2780 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2781 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2782 *autoneg = false;
2783 break;
2784
2785 case TXGBE_AUTOC_LMS_1G_AN:
2786 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2787 *autoneg = true;
2788 break;
2789
2790 case TXGBE_AUTOC_LMS_10G:
2791 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2792 *autoneg = false;
2793 break;
2794
2795 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2796 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2797 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2798 if (autoc & TXGBE_AUTOC_KR_SUPP)
2799 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2800 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2801 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2802 if (autoc & TXGBE_AUTOC_KX_SUPP)
2803 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2804 *autoneg = true;
2805 break;
2806
2807 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2808 *speed = TXGBE_LINK_SPEED_100M_FULL;
2809 if (autoc & TXGBE_AUTOC_KR_SUPP)
2810 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2811 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2812 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2813 if (autoc & TXGBE_AUTOC_KX_SUPP)
2814 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2815 *autoneg = true;
2816 break;
2817
2818 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2819 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2820 TXGBE_LINK_SPEED_100M_FULL |
2821 TXGBE_LINK_SPEED_10M_FULL;
2822 *autoneg = false;
2823 break;
2824
2825 default:
2826 return TXGBE_ERR_LINK_SETUP;
2827 }
2828
2829 if (hw->phy.multispeed_fiber) {
2830 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2831 TXGBE_LINK_SPEED_1GB_FULL;
2832
2833 /* QSFP must not enable full auto-negotiation
2834 * Limited autoneg is enabled at 1G
2835 */
2836 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2837 *autoneg = false;
2838 else
2839 *autoneg = true;
2840 }
2841
2842 return status;
2843 }
2844
2845 /**
2846 * txgbe_get_media_type_raptor - Get media type
2847 * @hw: pointer to hardware structure
2848 *
2849 * Returns the media type (fiber, copper, backplane)
2850 **/
txgbe_get_media_type_raptor(struct txgbe_hw * hw)2851 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
2852 {
2853 u32 media_type;
2854
2855 if (hw->phy.ffe_set)
2856 txgbe_bp_mode_set(hw);
2857
2858 /* Detect if there is a copper PHY attached. */
2859 switch (hw->phy.type) {
2860 case txgbe_phy_cu_unknown:
2861 case txgbe_phy_tn:
2862 media_type = txgbe_media_type_copper;
2863 return media_type;
2864 default:
2865 break;
2866 }
2867
2868 switch (hw->subsystem_device_id & 0xFF) {
2869 case TXGBE_DEV_ID_KR_KX_KX4:
2870 case TXGBE_DEV_ID_MAC_SGMII:
2871 case TXGBE_DEV_ID_MAC_XAUI:
2872 /* Default device ID is mezzanine card KX/KX4 */
2873 media_type = txgbe_media_type_backplane;
2874 break;
2875 case TXGBE_DEV_ID_SFP:
2876 media_type = txgbe_media_type_fiber;
2877 break;
2878 case TXGBE_DEV_ID_QSFP:
2879 media_type = txgbe_media_type_fiber_qsfp;
2880 break;
2881 case TXGBE_DEV_ID_XAUI:
2882 case TXGBE_DEV_ID_SGMII:
2883 media_type = txgbe_media_type_copper;
2884 break;
2885 case TXGBE_DEV_ID_SFI_XAUI:
2886 if (hw->bus.lan_id == 0)
2887 media_type = txgbe_media_type_fiber;
2888 else
2889 media_type = txgbe_media_type_copper;
2890 break;
2891 default:
2892 media_type = txgbe_media_type_unknown;
2893 break;
2894 }
2895
2896 return media_type;
2897 }
2898
2899 /**
2900 * txgbe_start_mac_link_raptor - Setup MAC link settings
2901 * @hw: pointer to hardware structure
2902 * @autoneg_wait_to_complete: true when waiting for completion is needed
2903 *
2904 * Configures link settings based on values in the txgbe_hw struct.
2905 * Restarts the link. Performs autonegotiation if needed.
2906 **/
txgbe_start_mac_link_raptor(struct txgbe_hw * hw,bool autoneg_wait_to_complete)2907 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
2908 bool autoneg_wait_to_complete)
2909 {
2910 s32 status = 0;
2911 bool got_lock = false;
2912
2913 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
2914
2915 /* reset_pipeline requires us to hold this lock as it writes to
2916 * AUTOC.
2917 */
2918 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2919 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2920 if (status != 0)
2921 goto out;
2922
2923 got_lock = true;
2924 }
2925
2926 /* Restart link */
2927 txgbe_reset_pipeline_raptor(hw);
2928
2929 if (got_lock)
2930 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2931
2932 /* Add delay to filter out noises during initial link setup */
2933 msec_delay(50);
2934
2935 out:
2936 return status;
2937 }
2938
2939 /**
2940 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
2941 * @hw: pointer to hardware structure
2942 *
2943 * The base drivers may require better control over SFP+ module
2944 * PHY states. This includes selectively shutting down the Tx
2945 * laser on the PHY, effectively halting physical link.
2946 **/
txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw * hw)2947 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2948 {
2949 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2950
2951 /* Blocked by MNG FW so bail */
2952 if (txgbe_check_reset_blocked(hw))
2953 return;
2954
2955 if (txgbe_close_notify(hw))
2956 txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G |
2957 TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE);
2958
2959 /* Disable Tx laser; allow 100us to go dark per spec */
2960 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2961 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2962 txgbe_flush(hw);
2963 usec_delay(100);
2964 }
2965
2966 /**
2967 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
2968 * @hw: pointer to hardware structure
2969 *
2970 * The base drivers may require better control over SFP+ module
2971 * PHY states. This includes selectively turning on the Tx
2972 * laser on the PHY, effectively starting physical link.
2973 **/
txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw * hw)2974 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2975 {
2976 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2977
2978 if (txgbe_open_notify(hw))
2979 wr32(hw, TXGBE_LEDCTL, 0);
2980
2981 /* Enable Tx laser; allow 100ms to light up */
2982 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2983 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2984 txgbe_flush(hw);
2985 msec_delay(100);
2986 }
2987
2988 /**
2989 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
2990 * @hw: pointer to hardware structure
2991 *
2992 * When the driver changes the link speeds that it can support,
2993 * it sets autotry_restart to true to indicate that we need to
2994 * initiate a new autotry session with the link partner. To do
2995 * so, we set the speed then disable and re-enable the Tx laser, to
2996 * alert the link partner that it also needs to restart autotry on its
2997 * end. This is consistent with true clause 37 autoneg, which also
2998 * involves a loss of signal.
2999 **/
txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw * hw)3000 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3001 {
3002 /* Blocked by MNG FW so bail */
3003 if (txgbe_check_reset_blocked(hw))
3004 return;
3005
3006 if (hw->mac.autotry_restart) {
3007 txgbe_disable_tx_laser_multispeed_fiber(hw);
3008 txgbe_enable_tx_laser_multispeed_fiber(hw);
3009 hw->mac.autotry_restart = false;
3010 }
3011 }
3012
3013 /**
3014 * txgbe_set_hard_rate_select_speed - Set module link speed
3015 * @hw: pointer to hardware structure
3016 * @speed: link speed to set
3017 *
3018 * Set module link speed via RS0/RS1 rate select pins.
3019 */
txgbe_set_hard_rate_select_speed(struct txgbe_hw * hw,u32 speed)3020 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
3021 u32 speed)
3022 {
3023 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3024
3025 switch (speed) {
3026 case TXGBE_LINK_SPEED_10GB_FULL:
3027 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3028 break;
3029 case TXGBE_LINK_SPEED_1GB_FULL:
3030 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3031 break;
3032 default:
3033 DEBUGOUT("Invalid fixed module speed");
3034 return;
3035 }
3036
3037 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3038 txgbe_flush(hw);
3039 }
3040
3041 /**
3042 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
3043 * @hw: pointer to hardware structure
3044 * @speed: new link speed
3045 * @autoneg_wait_to_complete: true when waiting for completion is needed
3046 *
3047 * Implements the Intel SmartSpeed algorithm.
3048 **/
txgbe_setup_mac_link_smartspeed(struct txgbe_hw * hw,u32 speed,bool autoneg_wait_to_complete)3049 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
3050 u32 speed,
3051 bool autoneg_wait_to_complete)
3052 {
3053 s32 status = 0;
3054 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
3055 s32 i, j;
3056 bool link_up = false;
3057 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
3058
3059 /* Set autoneg_advertised value based on input link speed */
3060 hw->phy.autoneg_advertised = 0;
3061
3062 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
3063 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
3064
3065 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3066 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
3067
3068 if (speed & TXGBE_LINK_SPEED_100M_FULL)
3069 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
3070
3071 /*
3072 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
3073 * autoneg advertisement if link is unable to be established at the
3074 * highest negotiated rate. This can sometimes happen due to integrity
3075 * issues with the physical media connection.
3076 */
3077
3078 /* First, try to get link with full advertisement */
3079 hw->phy.smart_speed_active = false;
3080 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
3081 status = txgbe_setup_mac_link(hw, speed,
3082 autoneg_wait_to_complete);
3083 if (status != 0)
3084 goto out;
3085
3086 /*
3087 * Wait for the controller to acquire link. Per IEEE 802.3ap,
3088 * Section 73.10.2, we may have to wait up to 500ms if KR is
3089 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
3090 * Table 9 in the AN MAS.
3091 */
3092 for (i = 0; i < 5; i++) {
3093 msec_delay(100);
3094
3095 /* If we have link, just jump out */
3096 status = hw->mac.check_link(hw, &link_speed, &link_up,
3097 false);
3098 if (status != 0)
3099 goto out;
3100
3101 if (link_up)
3102 goto out;
3103 }
3104 }
3105
3106 /*
3107 * We didn't get link. If we advertised KR plus one of KX4/KX
3108 * (or BX4/BX), then disable KR and try again.
3109 */
3110 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
3111 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
3112 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
3113 goto out;
3114
3115 /* Turn SmartSpeed on to disable KR support */
3116 hw->phy.smart_speed_active = true;
3117 status = txgbe_setup_mac_link(hw, speed,
3118 autoneg_wait_to_complete);
3119 if (status != 0)
3120 goto out;
3121
3122 /*
3123 * Wait for the controller to acquire link. 600ms will allow for
3124 * the AN link_fail_inhibit_timer as well for multiple cycles of
3125 * parallel detect, both 10g and 1g. This allows for the maximum
3126 * connect attempts as defined in the AN MAS table 73-7.
3127 */
3128 for (i = 0; i < 6; i++) {
3129 msec_delay(100);
3130
3131 /* If we have link, just jump out */
3132 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
3133 if (status != 0)
3134 goto out;
3135
3136 if (link_up)
3137 goto out;
3138 }
3139
3140 /* We didn't get link. Turn SmartSpeed back off. */
3141 hw->phy.smart_speed_active = false;
3142 status = txgbe_setup_mac_link(hw, speed,
3143 autoneg_wait_to_complete);
3144
3145 out:
3146 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
3147 DEBUGOUT("Smartspeed has downgraded the link speed from the maximum advertised");
3148 return status;
3149 }
3150
3151 /**
3152 * txgbe_setup_mac_link - Set MAC link speed
3153 * @hw: pointer to hardware structure
3154 * @speed: new link speed
3155 * @autoneg_wait_to_complete: true when waiting for completion is needed
3156 *
3157 * Set the link speed in the AUTOC register and restarts link.
3158 **/
txgbe_setup_mac_link(struct txgbe_hw * hw,u32 speed,bool autoneg_wait_to_complete)3159 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
3160 u32 speed,
3161 bool autoneg_wait_to_complete)
3162 {
3163 bool autoneg = false;
3164 s32 status = 0;
3165
3166 u64 autoc = hw->mac.autoc_read(hw);
3167 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
3168 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3169 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3170 u64 orig_autoc = 0;
3171 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
3172
3173 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3174
3175 /* Check to see if speed passed in is supported. */
3176 status = hw->mac.get_link_capabilities(hw,
3177 &link_capabilities, &autoneg);
3178 if (status)
3179 return status;
3180
3181 speed &= link_capabilities;
3182 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
3183 return TXGBE_ERR_LINK_SETUP;
3184
3185 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
3186 if (hw->mac.orig_link_settings_stored)
3187 orig_autoc = hw->mac.orig_autoc;
3188 else
3189 orig_autoc = autoc;
3190
3191 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3192 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3193
3194 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3195 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3196 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3197 /* Set KX4/KX/KR support according to speed requested */
3198 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
3199 TXGBE_AUTOC_KX4_SUPP |
3200 TXGBE_AUTOC_KR_SUPP);
3201 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
3202 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
3203 autoc |= TXGBE_AUTOC_KX4_SUPP;
3204 if (orig_autoc & TXGBE_AUTOC_KR_SUPP)
3205 autoc |= TXGBE_AUTOC_KR_SUPP;
3206 }
3207 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3208 autoc |= TXGBE_AUTOC_KX_SUPP;
3209 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
3210 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
3211 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
3212 /* Switch from 1G SFI to 10G SFI if requested */
3213 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
3214 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
3215 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3216 autoc |= TXGBE_AUTOC_LMS_10G;
3217 }
3218 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
3219 (link_mode == TXGBE_AUTOC_LMS_10G)) {
3220 /* Switch from 10G SFI to 1G SFI if requested */
3221 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
3222 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
3223 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3224 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
3225 autoc |= TXGBE_AUTOC_LMS_1G_AN;
3226 else
3227 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
3228 }
3229 }
3230
3231 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
3232 autoc |= TXGBE_AUTOC_SPEED(speed);
3233 autoc &= ~TXGBE_AUTOC_AUTONEG;
3234 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
3235
3236 /* Restart link */
3237 hw->mac.autoc_write(hw, autoc);
3238
3239 /* Add delay to filter out noises during initial link setup */
3240 msec_delay(50);
3241
3242 return status;
3243 }
3244
3245 /**
3246 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
3247 * @hw: pointer to hardware structure
3248 * @speed: new link speed
3249 * @autoneg_wait_to_complete: true if waiting is needed to complete
3250 *
3251 * Restarts link on PHY and MAC based on settings passed in.
3252 **/
txgbe_setup_copper_link_raptor(struct txgbe_hw * hw,u32 speed,bool autoneg_wait_to_complete)3253 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
3254 u32 speed,
3255 bool autoneg_wait_to_complete)
3256 {
3257 s32 status;
3258
3259 /* Setup the PHY according to input speed */
3260 status = hw->phy.setup_link_speed(hw, speed,
3261 autoneg_wait_to_complete);
3262 /* Set up MAC */
3263 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
3264
3265 return status;
3266 }
3267
3268 static int
txgbe_check_flash_load(struct txgbe_hw * hw,u32 check_bit)3269 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
3270 {
3271 u32 reg = 0;
3272 u32 i;
3273 int err = 0;
3274 /* if there's flash existing */
3275 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
3276 /* wait hw load flash done */
3277 for (i = 0; i < 10; i++) {
3278 reg = rd32(hw, TXGBE_ILDRSTAT);
3279 if (!(reg & check_bit)) {
3280 /* done */
3281 break;
3282 }
3283 msleep(100);
3284 }
3285 if (i == 10)
3286 err = TXGBE_ERR_FLASH_LOADING_FAILED;
3287 }
3288 return err;
3289 }
3290
3291 static void
txgbe_reset_misc(struct txgbe_hw * hw)3292 txgbe_reset_misc(struct txgbe_hw *hw)
3293 {
3294 int i;
3295 u32 value;
3296
3297 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
3298 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
3299
3300 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
3301 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
3302 hw->link_status = TXGBE_LINK_STATUS_NONE;
3303
3304 /* receive packets that size > 2048 */
3305 wr32m(hw, TXGBE_MACRXCFG,
3306 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
3307
3308 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3309 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
3310
3311 /* clear counters on read */
3312 wr32m(hw, TXGBE_MACCNTCTL,
3313 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
3314
3315 wr32m(hw, TXGBE_RXFCCFG,
3316 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
3317 wr32m(hw, TXGBE_TXFCCFG,
3318 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
3319
3320 wr32m(hw, TXGBE_MACRXFLT,
3321 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
3322
3323 wr32m(hw, TXGBE_RSTSTAT,
3324 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
3325
3326 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
3327 wr32(hw, TXGBE_MNGFLEXSEL, 0);
3328 for (i = 0; i < 16; i++) {
3329 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
3330 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
3331 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
3332 }
3333 wr32(hw, TXGBE_LANFLEXSEL, 0);
3334 for (i = 0; i < 16; i++) {
3335 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
3336 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
3337 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
3338 }
3339
3340 /* set pause frame dst mac addr */
3341 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
3342 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
3343
3344 hw->mac.init_thermal_sensor_thresh(hw);
3345
3346 /* enable mac transmitter */
3347 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
3348
3349 hw->mac.autoc = hw->mac.orig_autoc;
3350 for (i = 0; i < 4; i++)
3351 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
3352 }
3353
3354 /**
3355 * txgbe_reset_hw - Perform hardware reset
3356 * @hw: pointer to hardware structure
3357 *
3358 * Resets the hardware by resetting the transmit and receive units, masks
3359 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3360 * reset.
3361 **/
txgbe_reset_hw(struct txgbe_hw * hw)3362 s32 txgbe_reset_hw(struct txgbe_hw *hw)
3363 {
3364 s32 status;
3365 u32 autoc;
3366
3367 /* Call adapter stop to disable tx/rx and clear interrupts */
3368 status = hw->mac.stop_hw(hw);
3369 if (status != 0)
3370 return status;
3371
3372 /* flush pending Tx transactions */
3373 txgbe_clear_tx_pending(hw);
3374
3375 /* Identify PHY and related function pointers */
3376 status = hw->phy.init(hw);
3377 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3378 return status;
3379
3380 /* Setup SFP module if there is one present. */
3381 if (hw->phy.sfp_setup_needed) {
3382 status = hw->mac.setup_sfp(hw);
3383 hw->phy.sfp_setup_needed = false;
3384 }
3385 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3386 return status;
3387
3388 /* Reset PHY */
3389 if (!hw->phy.reset_disable)
3390 hw->phy.reset(hw);
3391
3392 /* remember AUTOC from before we reset */
3393 autoc = hw->mac.autoc_read(hw);
3394
3395 mac_reset_top:
3396 /*
3397 * Issue global reset to the MAC. Needs to be SW reset if link is up.
3398 * If link reset is used when link is up, it might reset the PHY when
3399 * mng is using it. If link is down or the flag to force full link
3400 * reset is set, then perform link reset.
3401 */
3402 if (txgbe_mng_present(hw)) {
3403 txgbe_hic_reset(hw);
3404 } else {
3405 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
3406 txgbe_flush(hw);
3407 }
3408 usec_delay(10);
3409
3410 txgbe_reset_misc(hw);
3411
3412 if (hw->bus.lan_id == 0) {
3413 status = txgbe_check_flash_load(hw,
3414 TXGBE_ILDRSTAT_SWRST_LAN0);
3415 } else {
3416 status = txgbe_check_flash_load(hw,
3417 TXGBE_ILDRSTAT_SWRST_LAN1);
3418 }
3419 if (status != 0)
3420 return status;
3421
3422 msec_delay(50);
3423
3424 /*
3425 * Double resets are required for recovery from certain error
3426 * conditions. Between resets, it is necessary to stall to
3427 * allow time for any pending HW events to complete.
3428 */
3429 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3430 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3431 goto mac_reset_top;
3432 }
3433
3434 /*
3435 * Store the original AUTOC/AUTOC2 values if they have not been
3436 * stored off yet. Otherwise restore the stored original
3437 * values since the reset operation sets back to defaults.
3438 */
3439 if (!hw->mac.orig_link_settings_stored) {
3440 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
3441 hw->mac.orig_link_settings_stored = true;
3442 } else {
3443 hw->mac.orig_autoc = autoc;
3444 }
3445
3446 if (hw->phy.ffe_set) {
3447 /* Make sure phy power is up */
3448 msec_delay(50);
3449
3450 /* A temporary solution to set phy */
3451 txgbe_set_phy_temp(hw);
3452 }
3453
3454 /* Store the permanent mac address */
3455 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
3456
3457 /*
3458 * Store MAC address from RAR0, clear receive address registers, and
3459 * clear the multicast table. Also reset num_rar_entries to 128,
3460 * since we modify this value when programming the SAN MAC address.
3461 */
3462 hw->mac.num_rar_entries = 128;
3463 hw->mac.init_rx_addrs(hw);
3464
3465 /* Store the permanent SAN mac address */
3466 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
3467
3468 /* Add the SAN MAC address to the RAR only if it's a valid address */
3469 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
3470 /* Save the SAN MAC RAR index */
3471 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
3472
3473 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
3474 hw->mac.san_addr, 0, true);
3475
3476 /* clear VMDq pool/queue selection for this RAR */
3477 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
3478 BIT_MASK32);
3479
3480 /* Reserve the last RAR for the SAN MAC address */
3481 hw->mac.num_rar_entries--;
3482 }
3483
3484 /* Store the alternative WWNN/WWPN prefix */
3485 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
3486 &hw->mac.wwpn_prefix);
3487
3488 return status;
3489 }
3490
3491 /**
3492 * txgbe_fdir_check_cmd_complete - poll to check whether FDIRPICMD is complete
3493 * @hw: pointer to hardware structure
3494 * @fdircmd: current value of FDIRCMD register
3495 */
txgbe_fdir_check_cmd_complete(struct txgbe_hw * hw,u32 * fdircmd)3496 static s32 txgbe_fdir_check_cmd_complete(struct txgbe_hw *hw, u32 *fdircmd)
3497 {
3498 int i;
3499
3500 for (i = 0; i < TXGBE_FDIRCMD_CMD_POLL; i++) {
3501 *fdircmd = rd32(hw, TXGBE_FDIRPICMD);
3502 if (!(*fdircmd & TXGBE_FDIRPICMD_OP_MASK))
3503 return 0;
3504 usec_delay(10);
3505 }
3506
3507 return TXGBE_ERR_FDIR_CMD_INCOMPLETE;
3508 }
3509
3510 /**
3511 * txgbe_reinit_fdir_tables - Reinitialize Flow Director tables.
3512 * @hw: pointer to hardware structure
3513 **/
txgbe_reinit_fdir_tables(struct txgbe_hw * hw)3514 s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw)
3515 {
3516 s32 err;
3517 int i;
3518 u32 fdirctrl = rd32(hw, TXGBE_FDIRCTL);
3519 u32 fdircmd;
3520 fdirctrl &= ~TXGBE_FDIRCTL_INITDONE;
3521
3522 /*
3523 * Before starting reinitialization process,
3524 * FDIRPICMD.OP must be zero.
3525 */
3526 err = txgbe_fdir_check_cmd_complete(hw, &fdircmd);
3527 if (err) {
3528 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.");
3529 return err;
3530 }
3531
3532 wr32(hw, TXGBE_FDIRFREE, 0);
3533 txgbe_flush(hw);
3534 /*
3535 * adapters flow director init flow cannot be restarted,
3536 * Workaround silicon errata by performing the following steps
3537 * before re-writing the FDIRCTL control register with the same value.
3538 * - write 1 to bit 8 of FDIRPICMD register &
3539 * - write 0 to bit 8 of FDIRPICMD register
3540 */
3541 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, TXGBE_FDIRPICMD_CLR);
3542 txgbe_flush(hw);
3543 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, 0);
3544 txgbe_flush(hw);
3545 /*
3546 * Clear FDIR Hash register to clear any leftover hashes
3547 * waiting to be programmed.
3548 */
3549 wr32(hw, TXGBE_FDIRPIHASH, 0x00);
3550 txgbe_flush(hw);
3551
3552 wr32(hw, TXGBE_FDIRCTL, fdirctrl);
3553 txgbe_flush(hw);
3554
3555 /* Poll init-done after we write FDIRCTL register */
3556 for (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) {
3557 if (rd32m(hw, TXGBE_FDIRCTL, TXGBE_FDIRCTL_INITDONE))
3558 break;
3559 msec_delay(1);
3560 }
3561 if (i >= TXGBE_FDIR_INIT_DONE_POLL) {
3562 DEBUGOUT("Flow Director Signature poll time exceeded!");
3563 return TXGBE_ERR_FDIR_REINIT_FAILED;
3564 }
3565
3566 /* Clear FDIR statistics registers (read to clear) */
3567 rd32(hw, TXGBE_FDIRUSED);
3568 rd32(hw, TXGBE_FDIRFAIL);
3569 rd32(hw, TXGBE_FDIRMATCH);
3570 rd32(hw, TXGBE_FDIRMISS);
3571 rd32(hw, TXGBE_FDIRLEN);
3572
3573 return 0;
3574 }
3575
3576 /**
3577 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
3578 * @hw: pointer to hardware structure
3579 *
3580 * Starts the hardware using the generic start_hw function
3581 * and the generation start_hw function.
3582 * Then performs revision-specific operations, if any.
3583 **/
txgbe_start_hw_raptor(struct txgbe_hw * hw)3584 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
3585 {
3586 s32 err = 0;
3587
3588 err = txgbe_start_hw(hw);
3589 if (err != 0)
3590 goto out;
3591
3592 err = txgbe_start_hw_gen2(hw);
3593 if (err != 0)
3594 goto out;
3595
3596 /* We need to run link autotry after the driver loads */
3597 hw->mac.autotry_restart = true;
3598
3599 out:
3600 return err;
3601 }
3602
3603 /**
3604 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3605 * @hw: pointer to hardware structure
3606 * @regval: register value to write to RXCTRL
3607 *
3608 * Enables the Rx DMA unit
3609 **/
txgbe_enable_rx_dma_raptor(struct txgbe_hw * hw,u32 regval)3610 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3611 {
3612 /*
3613 * Workaround silicon errata when enabling the Rx datapath.
3614 * If traffic is incoming before we enable the Rx unit, it could hang
3615 * the Rx DMA unit. Therefore, make sure the security engine is
3616 * completely disabled prior to enabling the Rx unit.
3617 */
3618
3619 hw->mac.disable_sec_rx_path(hw);
3620
3621 if (regval & TXGBE_PBRXCTL_ENA)
3622 txgbe_enable_rx(hw);
3623 else
3624 txgbe_disable_rx(hw);
3625
3626 hw->mac.enable_sec_rx_path(hw);
3627
3628 return 0;
3629 }
3630
3631 /**
3632 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3633 * @hw: pointer to hardware structure
3634 *
3635 * Returns true if the LESM FW module is present and enabled. Otherwise
3636 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3637 **/
txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw * hw)3638 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3639 {
3640 bool lesm_enabled = false;
3641 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3642 s32 status;
3643
3644 /* get the offset to the Firmware Module block */
3645 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3646
3647 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3648 goto out;
3649
3650 /* get the offset to the LESM Parameters block */
3651 status = hw->rom.read16(hw, (fw_offset +
3652 TXGBE_FW_LESM_PARAMETERS_PTR),
3653 &fw_lesm_param_offset);
3654
3655 if (status != 0 ||
3656 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3657 goto out;
3658
3659 /* get the LESM state word */
3660 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3661 TXGBE_FW_LESM_STATE_1),
3662 &fw_lesm_state);
3663
3664 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3665 lesm_enabled = true;
3666
3667 out:
3668 lesm_enabled = false;
3669 return lesm_enabled;
3670 }
3671
3672 /**
3673 * txgbe_reset_pipeline_raptor - perform pipeline reset
3674 *
3675 * @hw: pointer to hardware structure
3676 *
3677 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3678 * full pipeline reset. This function assumes the SW/FW lock is held.
3679 **/
txgbe_reset_pipeline_raptor(struct txgbe_hw * hw)3680 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3681 {
3682 s32 err = 0;
3683 u64 autoc;
3684
3685 autoc = hw->mac.autoc_read(hw);
3686
3687 /* Enable link if disabled in NVM */
3688 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3689 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3690
3691 autoc |= TXGBE_AUTOC_AN_RESTART;
3692 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3693 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3694
3695 /* Write AUTOC register with original LMS field and Restart_AN */
3696 hw->mac.autoc_write(hw, autoc);
3697 txgbe_flush(hw);
3698
3699 return err;
3700 }
3701
3702