1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
3 */
4
5 #include "txgbe_hw.h"
6 #include "txgbe_eeprom.h"
7 #include "txgbe_mng.h"
8 #include "txgbe_phy.h"
9
10 static void txgbe_i2c_start(struct txgbe_hw *hw);
11 static void txgbe_i2c_stop(struct txgbe_hw *hw);
12
13 /**
14 * txgbe_identify_extphy - Identify a single address for a PHY
15 * @hw: pointer to hardware structure
16 * @phy_addr: PHY address to probe
17 *
18 * Returns true if PHY found
19 */
txgbe_identify_extphy(struct txgbe_hw * hw)20 static bool txgbe_identify_extphy(struct txgbe_hw *hw)
21 {
22 u16 phy_addr = 0;
23
24 if (!txgbe_validate_phy_addr(hw, phy_addr)) {
25 DEBUGOUT("Unable to validate PHY address 0x%04X\n",
26 phy_addr);
27 return false;
28 }
29
30 if (txgbe_get_phy_id(hw))
31 return false;
32
33 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id);
34 if (hw->phy.type == txgbe_phy_unknown) {
35 u16 ext_ability = 0;
36 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY,
37 TXGBE_MD_DEV_PMA_PMD,
38 &ext_ability);
39
40 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY |
41 TXGBE_MD_PHY_1000BASET_ABILITY))
42 hw->phy.type = txgbe_phy_cu_unknown;
43 else
44 hw->phy.type = txgbe_phy_generic;
45 }
46
47 return true;
48 }
49
50 /**
51 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register
52 * @hw: pointer to hardware structure
53 *
54 * Read TXGBE_ETHPHYIF register and save field values,
55 * and check for valid field values.
56 **/
txgbe_read_phy_if(struct txgbe_hw * hw)57 static s32 txgbe_read_phy_if(struct txgbe_hw *hw)
58 {
59 hw->phy.media_type = hw->phy.get_media_type(hw);
60
61 /* Save NW management interface connected on board. This is used
62 * to determine internal PHY mode.
63 */
64 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF);
65
66 /* If MDIO is connected to external PHY, then set PHY address. */
67 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT)
68 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel);
69
70 if (!hw->phy.phy_semaphore_mask) {
71 if (hw->bus.lan_id)
72 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
73 else
74 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
75 }
76
77 return 0;
78 }
79
80 /**
81 * txgbe_identify_phy - Get physical layer module
82 * @hw: pointer to hardware structure
83 *
84 * Determines the physical layer module found on the current adapter.
85 **/
txgbe_identify_phy(struct txgbe_hw * hw)86 s32 txgbe_identify_phy(struct txgbe_hw *hw)
87 {
88 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
89
90 DEBUGFUNC("txgbe_identify_phy");
91
92 txgbe_read_phy_if(hw);
93
94 if (hw->phy.type != txgbe_phy_unknown)
95 return 0;
96
97 /* Raptor 10GBASE-T requires an external PHY */
98 if (hw->phy.media_type == txgbe_media_type_copper) {
99 err = txgbe_identify_extphy(hw);
100 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
101 err = txgbe_identify_module(hw);
102 } else {
103 hw->phy.type = txgbe_phy_none;
104 return 0;
105 }
106
107 /* Return error if SFP module has been detected but is not supported */
108 if (hw->phy.type == txgbe_phy_sfp_unsupported)
109 return TXGBE_ERR_SFP_NOT_SUPPORTED;
110
111 return err;
112 }
113
114 /**
115 * txgbe_check_reset_blocked - check status of MNG FW veto bit
116 * @hw: pointer to the hardware structure
117 *
118 * This function checks the STAT.MNGVETO bit to see if there are
119 * any constraints on link from manageability. For MAC's that don't
120 * have this bit just return faluse since the link can not be blocked
121 * via this method.
122 **/
txgbe_check_reset_blocked(struct txgbe_hw * hw)123 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw)
124 {
125 u32 mmngc;
126
127 DEBUGFUNC("txgbe_check_reset_blocked");
128
129 mmngc = rd32(hw, TXGBE_STAT);
130 if (mmngc & TXGBE_STAT_MNGVETO) {
131 DEBUGOUT("MNG_VETO bit detected.\n");
132 return true;
133 }
134
135 return false;
136 }
137
138 /**
139 * txgbe_validate_phy_addr - Determines phy address is valid
140 * @hw: pointer to hardware structure
141 * @phy_addr: PHY address
142 *
143 **/
txgbe_validate_phy_addr(struct txgbe_hw * hw,u32 phy_addr)144 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr)
145 {
146 u16 phy_id = 0;
147 bool valid = false;
148
149 DEBUGFUNC("txgbe_validate_phy_addr");
150
151 hw->phy.addr = phy_addr;
152 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
153 TXGBE_MD_DEV_PMA_PMD, &phy_id);
154
155 if (phy_id != 0xFFFF && phy_id != 0x0)
156 valid = true;
157
158 DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id);
159
160 return valid;
161 }
162
163 /**
164 * txgbe_get_phy_id - Get the phy type
165 * @hw: pointer to hardware structure
166 *
167 **/
txgbe_get_phy_id(struct txgbe_hw * hw)168 s32 txgbe_get_phy_id(struct txgbe_hw *hw)
169 {
170 u32 err;
171 u16 phy_id_high = 0;
172 u16 phy_id_low = 0;
173
174 DEBUGFUNC("txgbe_get_phy_id");
175
176 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
177 TXGBE_MD_DEV_PMA_PMD,
178 &phy_id_high);
179
180 if (err == 0) {
181 hw->phy.id = (u32)(phy_id_high << 16);
182 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW,
183 TXGBE_MD_DEV_PMA_PMD,
184 &phy_id_low);
185 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK);
186 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK);
187 }
188 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
189 phy_id_high, phy_id_low);
190
191 return err;
192 }
193
194 /**
195 * txgbe_get_phy_type_from_id - Get the phy type
196 * @phy_id: PHY ID information
197 *
198 **/
txgbe_get_phy_type_from_id(u32 phy_id)199 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id)
200 {
201 enum txgbe_phy_type phy_type;
202
203 DEBUGFUNC("txgbe_get_phy_type_from_id");
204
205 switch (phy_id) {
206 case TXGBE_PHYID_TN1010:
207 phy_type = txgbe_phy_tn;
208 break;
209 case TXGBE_PHYID_QT2022:
210 phy_type = txgbe_phy_qt;
211 break;
212 case TXGBE_PHYID_ATH:
213 phy_type = txgbe_phy_nl;
214 break;
215 case TXGBE_PHYID_MTD3310:
216 phy_type = txgbe_phy_cu_mtd;
217 break;
218 default:
219 phy_type = txgbe_phy_unknown;
220 break;
221 }
222
223 return phy_type;
224 }
225
226 static s32
txgbe_reset_extphy(struct txgbe_hw * hw)227 txgbe_reset_extphy(struct txgbe_hw *hw)
228 {
229 u16 ctrl = 0;
230 int err, i;
231
232 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
233 TXGBE_MD_DEV_GENERAL, &ctrl);
234 if (err != 0)
235 return err;
236 ctrl |= TXGBE_MD_PORT_CTRL_RESET;
237 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL,
238 TXGBE_MD_DEV_GENERAL, ctrl);
239 if (err != 0)
240 return err;
241
242 /*
243 * Poll for reset bit to self-clear indicating reset is complete.
244 * Some PHYs could take up to 3 seconds to complete and need about
245 * 1.7 usec delay after the reset is complete.
246 */
247 for (i = 0; i < 30; i++) {
248 msec_delay(100);
249 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
250 TXGBE_MD_DEV_GENERAL, &ctrl);
251 if (err != 0)
252 return err;
253
254 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) {
255 usec_delay(2);
256 break;
257 }
258 }
259
260 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) {
261 err = TXGBE_ERR_RESET_FAILED;
262 DEBUGOUT("PHY reset polling failed to complete.\n");
263 }
264
265 return err;
266 }
267
268 /**
269 * txgbe_reset_phy - Performs a PHY reset
270 * @hw: pointer to hardware structure
271 **/
txgbe_reset_phy(struct txgbe_hw * hw)272 s32 txgbe_reset_phy(struct txgbe_hw *hw)
273 {
274 s32 err = 0;
275
276 DEBUGFUNC("txgbe_reset_phy");
277
278 if (hw->phy.type == txgbe_phy_unknown)
279 err = txgbe_identify_phy(hw);
280
281 if (err != 0 || hw->phy.type == txgbe_phy_none)
282 return err;
283
284 /* Don't reset PHY if it's shut down due to overtemp. */
285 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP)
286 return err;
287
288 /* Blocked by MNG FW so bail */
289 if (txgbe_check_reset_blocked(hw))
290 return err;
291
292 switch (hw->phy.type) {
293 case txgbe_phy_cu_mtd:
294 err = txgbe_reset_extphy(hw);
295 break;
296 default:
297 break;
298 }
299
300 return err;
301 }
302
303 /**
304 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without
305 * the SWFW lock
306 * @hw: pointer to hardware structure
307 * @reg_addr: 32 bit address of PHY register to read
308 * @device_type: 5 bit device type
309 * @phy_data: Pointer to read data from PHY register
310 **/
txgbe_read_phy_reg_mdi(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)311 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
312 u16 *phy_data)
313 {
314 u32 command, data;
315
316 /* Setup and write the address cycle command */
317 command = TXGBE_MDIOSCA_REG(reg_addr) |
318 TXGBE_MDIOSCA_DEV(device_type) |
319 TXGBE_MDIOSCA_PORT(hw->phy.addr);
320 wr32(hw, TXGBE_MDIOSCA, command);
321
322 command = TXGBE_MDIOSCD_CMD_READ |
323 TXGBE_MDIOSCD_BUSY;
324 wr32(hw, TXGBE_MDIOSCD, command);
325
326 /*
327 * Check every 10 usec to see if the address cycle completed.
328 * The MDI Command bit will clear when the operation is
329 * complete
330 */
331 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
332 0, NULL, 100, 100)) {
333 DEBUGOUT("PHY address command did not complete\n");
334 return TXGBE_ERR_PHY;
335 }
336
337 data = rd32(hw, TXGBE_MDIOSCD);
338 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data);
339
340 return 0;
341 }
342
343 /**
344 * txgbe_read_phy_reg - Reads a value from a specified PHY register
345 * using the SWFW lock - this function is needed in most cases
346 * @hw: pointer to hardware structure
347 * @reg_addr: 32 bit address of PHY register to read
348 * @device_type: 5 bit device type
349 * @phy_data: Pointer to read data from PHY register
350 **/
txgbe_read_phy_reg(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)351 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
352 u32 device_type, u16 *phy_data)
353 {
354 s32 err;
355 u32 gssr = hw->phy.phy_semaphore_mask;
356
357 DEBUGFUNC("txgbe_read_phy_reg");
358
359 if (hw->mac.acquire_swfw_sync(hw, gssr))
360 return TXGBE_ERR_SWFW_SYNC;
361
362 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data);
363
364 hw->mac.release_swfw_sync(hw, gssr);
365
366 return err;
367 }
368
369 /**
370 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register
371 * without SWFW lock
372 * @hw: pointer to hardware structure
373 * @reg_addr: 32 bit PHY register to write
374 * @device_type: 5 bit device type
375 * @phy_data: Data to write to the PHY register
376 **/
txgbe_write_phy_reg_mdi(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)377 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr,
378 u32 device_type, u16 phy_data)
379 {
380 u32 command;
381
382 /* write command */
383 command = TXGBE_MDIOSCA_REG(reg_addr) |
384 TXGBE_MDIOSCA_DEV(device_type) |
385 TXGBE_MDIOSCA_PORT(hw->phy.addr);
386 wr32(hw, TXGBE_MDIOSCA, command);
387
388 command = TXGBE_MDIOSCD_CMD_WRITE |
389 TXGBE_MDIOSCD_DAT(phy_data) |
390 TXGBE_MDIOSCD_BUSY;
391 wr32(hw, TXGBE_MDIOSCD, command);
392
393 /* wait for completion */
394 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
395 0, NULL, 100, 100)) {
396 TLOG_DEBUG("PHY write cmd didn't complete\n");
397 return -TERR_PHY;
398 }
399
400 return 0;
401 }
402
403 /**
404 * txgbe_write_phy_reg - Writes a value to specified PHY register
405 * using SWFW lock- this function is needed in most cases
406 * @hw: pointer to hardware structure
407 * @reg_addr: 32 bit PHY register to write
408 * @device_type: 5 bit device type
409 * @phy_data: Data to write to the PHY register
410 **/
txgbe_write_phy_reg(struct txgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)411 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
412 u32 device_type, u16 phy_data)
413 {
414 s32 err;
415 u32 gssr = hw->phy.phy_semaphore_mask;
416
417 DEBUGFUNC("txgbe_write_phy_reg");
418
419 if (hw->mac.acquire_swfw_sync(hw, gssr))
420 err = TXGBE_ERR_SWFW_SYNC;
421
422 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type,
423 phy_data);
424 hw->mac.release_swfw_sync(hw, gssr);
425
426 return err;
427 }
428
429 /**
430 * txgbe_setup_phy_link - Set and restart auto-neg
431 * @hw: pointer to hardware structure
432 *
433 * Restart auto-negotiation and PHY and waits for completion.
434 **/
txgbe_setup_phy_link(struct txgbe_hw * hw)435 s32 txgbe_setup_phy_link(struct txgbe_hw *hw)
436 {
437 s32 err = 0;
438 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
439 bool autoneg = false;
440 u32 speed;
441
442 DEBUGFUNC("txgbe_setup_phy_link");
443
444 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
445
446 /* Set or unset auto-negotiation 10G advertisement */
447 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
448 TXGBE_MD_DEV_AUTO_NEG,
449 &autoneg_reg);
450
451 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
452 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) &&
453 (speed & TXGBE_LINK_SPEED_10GB_FULL))
454 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
455
456 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
457 TXGBE_MD_DEV_AUTO_NEG,
458 autoneg_reg);
459
460 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
461 TXGBE_MD_DEV_AUTO_NEG,
462 &autoneg_reg);
463
464 /* Set or unset auto-negotiation 5G advertisement */
465 autoneg_reg &= ~TXGBE_MII_5GBASE_T_ADVERTISE;
466 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_5GB_FULL) &&
467 (speed & TXGBE_LINK_SPEED_5GB_FULL))
468 autoneg_reg |= TXGBE_MII_5GBASE_T_ADVERTISE;
469
470 /* Set or unset auto-negotiation 2.5G advertisement */
471 autoneg_reg &= ~TXGBE_MII_2_5GBASE_T_ADVERTISE;
472 if ((hw->phy.autoneg_advertised &
473 TXGBE_LINK_SPEED_2_5GB_FULL) &&
474 (speed & TXGBE_LINK_SPEED_2_5GB_FULL))
475 autoneg_reg |= TXGBE_MII_2_5GBASE_T_ADVERTISE;
476 /* Set or unset auto-negotiation 1G advertisement */
477 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE;
478 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) &&
479 (speed & TXGBE_LINK_SPEED_1GB_FULL))
480 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE;
481
482 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
483 TXGBE_MD_DEV_AUTO_NEG,
484 autoneg_reg);
485
486 /* Set or unset auto-negotiation 100M advertisement */
487 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
488 TXGBE_MD_DEV_AUTO_NEG,
489 &autoneg_reg);
490
491 autoneg_reg &= ~(TXGBE_MII_100BASE_T_ADVERTISE |
492 TXGBE_MII_100BASE_T_ADVERTISE_HALF);
493 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) &&
494 (speed & TXGBE_LINK_SPEED_100M_FULL))
495 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
496
497 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
498 TXGBE_MD_DEV_AUTO_NEG,
499 autoneg_reg);
500
501 /* Blocked by MNG FW so don't reset PHY */
502 if (txgbe_check_reset_blocked(hw))
503 return err;
504
505 /* Restart PHY auto-negotiation. */
506 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
507 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
508
509 autoneg_reg |= TXGBE_MII_RESTART;
510
511 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
512 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
513
514 return err;
515 }
516
517 /**
518 * txgbe_setup_phy_link_speed - Sets the auto advertised capabilities
519 * @hw: pointer to hardware structure
520 * @speed: new link speed
521 * @autoneg_wait_to_complete: unused
522 **/
txgbe_setup_phy_link_speed(struct txgbe_hw * hw,u32 speed,bool autoneg_wait_to_complete)523 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
524 u32 speed,
525 bool autoneg_wait_to_complete)
526 {
527 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
528
529 DEBUGFUNC("txgbe_setup_phy_link_speed");
530
531 /*
532 * Clear autoneg_advertised and set new values based on input link
533 * speed.
534 */
535 hw->phy.autoneg_advertised = 0;
536
537 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
538 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
539
540 if (speed & TXGBE_LINK_SPEED_5GB_FULL)
541 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_5GB_FULL;
542
543 if (speed & TXGBE_LINK_SPEED_2_5GB_FULL)
544 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_2_5GB_FULL;
545
546 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
547 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
548
549 if (speed & TXGBE_LINK_SPEED_100M_FULL)
550 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
551
552 if (speed & TXGBE_LINK_SPEED_10M_FULL)
553 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10M_FULL;
554
555 /* Setup link based on the new speed settings */
556 hw->phy.setup_link(hw);
557
558 return 0;
559 }
560
561 /**
562 * txgbe_get_copper_speeds_supported - Get copper link speeds from phy
563 * @hw: pointer to hardware structure
564 *
565 * Determines the supported link capabilities by reading the PHY auto
566 * negotiation register.
567 **/
txgbe_get_copper_speeds_supported(struct txgbe_hw * hw)568 static s32 txgbe_get_copper_speeds_supported(struct txgbe_hw *hw)
569 {
570 s32 err;
571 u16 speed_ability;
572
573 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_SPEED_ABILITY,
574 TXGBE_MD_DEV_PMA_PMD,
575 &speed_ability);
576 if (err)
577 return err;
578
579 if (speed_ability & TXGBE_MD_PHY_SPEED_10G)
580 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_10GB_FULL;
581 if (speed_ability & TXGBE_MD_PHY_SPEED_1G)
582 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_1GB_FULL;
583 if (speed_ability & TXGBE_MD_PHY_SPEED_100M)
584 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_100M_FULL;
585
586 return err;
587 }
588
589 /**
590 * txgbe_get_copper_link_capabilities - Determines link capabilities
591 * @hw: pointer to hardware structure
592 * @speed: pointer to link speed
593 * @autoneg: boolean auto-negotiation value
594 **/
txgbe_get_copper_link_capabilities(struct txgbe_hw * hw,u32 * speed,bool * autoneg)595 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
596 u32 *speed,
597 bool *autoneg)
598 {
599 s32 err = 0;
600
601 DEBUGFUNC("txgbe_get_copper_link_capabilities");
602
603 *autoneg = true;
604 if (!hw->phy.speeds_supported)
605 err = txgbe_get_copper_speeds_supported(hw);
606
607 *speed = hw->phy.speeds_supported;
608 return err;
609 }
610
611 /**
612 * txgbe_check_phy_link_tnx - Determine link and speed status
613 * @hw: pointer to hardware structure
614 * @speed: current link speed
615 * @link_up: true is link is up, false otherwise
616 *
617 * Reads the VS1 register to determine if link is up and the current speed for
618 * the PHY.
619 **/
txgbe_check_phy_link_tnx(struct txgbe_hw * hw,u32 * speed,bool * link_up)620 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, u32 *speed,
621 bool *link_up)
622 {
623 s32 err = 0;
624 u32 time_out;
625 u32 max_time_out = 10;
626 u16 phy_link = 0;
627 u16 phy_speed = 0;
628 u16 phy_data = 0;
629
630 DEBUGFUNC("txgbe_check_phy_link_tnx");
631
632 /* Initialize speed and link to default case */
633 *link_up = false;
634 *speed = TXGBE_LINK_SPEED_10GB_FULL;
635
636 /*
637 * Check current speed and link status of the PHY register.
638 * This is a vendor specific register and may have to
639 * be changed for other copper PHYs.
640 */
641 for (time_out = 0; time_out < max_time_out; time_out++) {
642 usec_delay(10);
643 err = hw->phy.read_reg(hw,
644 TXGBE_MD_VENDOR_SPECIFIC_1_STATUS,
645 TXGBE_MD_DEV_VENDOR_1,
646 &phy_data);
647 phy_link = phy_data & TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS;
648 phy_speed = phy_data &
649 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS;
650 if (phy_link == TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS) {
651 *link_up = true;
652 if (phy_speed ==
653 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS)
654 *speed = TXGBE_LINK_SPEED_1GB_FULL;
655 break;
656 }
657 }
658
659 return err;
660 }
661
662 /**
663 * txgbe_setup_phy_link_tnx - Set and restart auto-neg
664 * @hw: pointer to hardware structure
665 *
666 * Restart auto-negotiation and PHY and waits for completion.
667 **/
txgbe_setup_phy_link_tnx(struct txgbe_hw * hw)668 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw)
669 {
670 s32 err = 0;
671 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
672 bool autoneg = false;
673 u32 speed;
674
675 DEBUGFUNC("txgbe_setup_phy_link_tnx");
676
677 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
678
679 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
680 /* Set or unset auto-negotiation 10G advertisement */
681 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
682 TXGBE_MD_DEV_AUTO_NEG,
683 &autoneg_reg);
684
685 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
686 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL)
687 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
688
689 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
690 TXGBE_MD_DEV_AUTO_NEG,
691 autoneg_reg);
692 }
693
694 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
695 /* Set or unset auto-negotiation 1G advertisement */
696 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
697 TXGBE_MD_DEV_AUTO_NEG,
698 &autoneg_reg);
699
700 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
701 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL)
702 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
703
704 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
705 TXGBE_MD_DEV_AUTO_NEG,
706 autoneg_reg);
707 }
708
709 if (speed & TXGBE_LINK_SPEED_100M_FULL) {
710 /* Set or unset auto-negotiation 100M advertisement */
711 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
712 TXGBE_MD_DEV_AUTO_NEG,
713 &autoneg_reg);
714
715 autoneg_reg &= ~TXGBE_MII_100BASE_T_ADVERTISE;
716 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL)
717 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
718
719 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
720 TXGBE_MD_DEV_AUTO_NEG,
721 autoneg_reg);
722 }
723
724 /* Blocked by MNG FW so don't reset PHY */
725 if (txgbe_check_reset_blocked(hw))
726 return err;
727
728 /* Restart PHY auto-negotiation. */
729 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
730 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
731
732 autoneg_reg |= TXGBE_MII_RESTART;
733
734 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
735 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
736
737 return err;
738 }
739
740 /**
741 * txgbe_identify_module - Identifies module type
742 * @hw: pointer to hardware structure
743 *
744 * Determines HW type and calls appropriate function.
745 **/
txgbe_identify_module(struct txgbe_hw * hw)746 s32 txgbe_identify_module(struct txgbe_hw *hw)
747 {
748 s32 err = TXGBE_ERR_SFP_NOT_PRESENT;
749
750 DEBUGFUNC("txgbe_identify_module");
751
752 switch (hw->phy.media_type) {
753 case txgbe_media_type_fiber:
754 err = txgbe_identify_sfp_module(hw);
755 break;
756
757 case txgbe_media_type_fiber_qsfp:
758 err = txgbe_identify_qsfp_module(hw);
759 break;
760
761 default:
762 hw->phy.sfp_type = txgbe_sfp_type_not_present;
763 err = TXGBE_ERR_SFP_NOT_PRESENT;
764 break;
765 }
766
767 return err;
768 }
769
770 /**
771 * txgbe_identify_sfp_module - Identifies SFP modules
772 * @hw: pointer to hardware structure
773 *
774 * Searches for and identifies the SFP module and assigns appropriate PHY type.
775 **/
txgbe_identify_sfp_module(struct txgbe_hw * hw)776 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
777 {
778 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
779 u32 vendor_oui = 0;
780 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
781 u8 identifier = 0;
782 u8 comp_codes_1g = 0;
783 u8 comp_codes_10g = 0;
784 u8 oui_bytes[3] = {0, 0, 0};
785 u8 cable_tech = 0;
786 u8 cable_spec = 0;
787 u16 enforce_sfp = 0;
788
789 DEBUGFUNC("txgbe_identify_sfp_module");
790
791 if (hw->phy.media_type != txgbe_media_type_fiber) {
792 hw->phy.sfp_type = txgbe_sfp_type_not_present;
793 return TXGBE_ERR_SFP_NOT_PRESENT;
794 }
795
796 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
797 &identifier);
798 if (err != 0) {
799 ERR_I2C:
800 hw->phy.sfp_type = txgbe_sfp_type_not_present;
801 if (hw->phy.type != txgbe_phy_nl) {
802 hw->phy.id = 0;
803 hw->phy.type = txgbe_phy_unknown;
804 }
805 return TXGBE_ERR_SFP_NOT_PRESENT;
806 }
807
808 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
809 hw->phy.type = txgbe_phy_sfp_unsupported;
810 return TXGBE_ERR_SFP_NOT_SUPPORTED;
811 }
812
813 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES,
814 &comp_codes_1g);
815 if (err != 0)
816 goto ERR_I2C;
817
818 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES,
819 &comp_codes_10g);
820 if (err != 0)
821 goto ERR_I2C;
822
823 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
824 &cable_tech);
825 if (err != 0)
826 goto ERR_I2C;
827
828 /* ID Module
829 * =========
830 * 0 SFP_DA_CU
831 * 1 SFP_SR
832 * 2 SFP_LR
833 * 3 SFP_DA_CORE0 - chip-specific
834 * 4 SFP_DA_CORE1 - chip-specific
835 * 5 SFP_SR/LR_CORE0 - chip-specific
836 * 6 SFP_SR/LR_CORE1 - chip-specific
837 * 7 SFP_act_lmt_DA_CORE0 - chip-specific
838 * 8 SFP_act_lmt_DA_CORE1 - chip-specific
839 * 9 SFP_1g_cu_CORE0 - chip-specific
840 * 10 SFP_1g_cu_CORE1 - chip-specific
841 * 11 SFP_1g_sx_CORE0 - chip-specific
842 * 12 SFP_1g_sx_CORE1 - chip-specific
843 */
844 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
845 if (hw->bus.lan_id == 0)
846 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
847 else
848 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
849 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
850 err = hw->phy.read_i2c_eeprom(hw,
851 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
852 if (err != 0)
853 goto ERR_I2C;
854 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
855 hw->phy.sfp_type = (hw->bus.lan_id == 0
856 ? txgbe_sfp_type_da_act_lmt_core0
857 : txgbe_sfp_type_da_act_lmt_core1);
858 } else {
859 hw->phy.sfp_type = txgbe_sfp_type_unknown;
860 }
861 } else if (comp_codes_10g &
862 (TXGBE_SFF_10GBASESR_CAPABLE |
863 TXGBE_SFF_10GBASELR_CAPABLE)) {
864 hw->phy.sfp_type = (hw->bus.lan_id == 0
865 ? txgbe_sfp_type_srlr_core0
866 : txgbe_sfp_type_srlr_core1);
867 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) {
868 hw->phy.sfp_type = (hw->bus.lan_id == 0
869 ? txgbe_sfp_type_1g_cu_core0
870 : txgbe_sfp_type_1g_cu_core1);
871 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) {
872 hw->phy.sfp_type = (hw->bus.lan_id == 0
873 ? txgbe_sfp_type_1g_sx_core0
874 : txgbe_sfp_type_1g_sx_core1);
875 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) {
876 hw->phy.sfp_type = (hw->bus.lan_id == 0
877 ? txgbe_sfp_type_1g_lx_core0
878 : txgbe_sfp_type_1g_lx_core1);
879 } else {
880 hw->phy.sfp_type = txgbe_sfp_type_unknown;
881 }
882
883 if (hw->phy.sfp_type != stored_sfp_type)
884 hw->phy.sfp_setup_needed = true;
885
886 /* Determine if the SFP+ PHY is dual speed or not. */
887 hw->phy.multispeed_fiber = false;
888 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
889 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
890 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
891 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
892 hw->phy.multispeed_fiber = true;
893
894 /* Determine PHY vendor */
895 if (hw->phy.type != txgbe_phy_nl) {
896 hw->phy.id = identifier;
897 err = hw->phy.read_i2c_eeprom(hw,
898 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
899 if (err != 0)
900 goto ERR_I2C;
901
902 err = hw->phy.read_i2c_eeprom(hw,
903 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
904 if (err != 0)
905 goto ERR_I2C;
906
907 err = hw->phy.read_i2c_eeprom(hw,
908 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
909 if (err != 0)
910 goto ERR_I2C;
911
912 vendor_oui = ((u32)oui_bytes[0] << 24) |
913 ((u32)oui_bytes[1] << 16) |
914 ((u32)oui_bytes[2] << 8);
915 switch (vendor_oui) {
916 case TXGBE_SFF_VENDOR_OUI_TYCO:
917 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
918 hw->phy.type = txgbe_phy_sfp_tyco_passive;
919 break;
920 case TXGBE_SFF_VENDOR_OUI_FTL:
921 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
922 hw->phy.type = txgbe_phy_sfp_ftl_active;
923 else
924 hw->phy.type = txgbe_phy_sfp_ftl;
925 break;
926 case TXGBE_SFF_VENDOR_OUI_AVAGO:
927 hw->phy.type = txgbe_phy_sfp_avago;
928 break;
929 case TXGBE_SFF_VENDOR_OUI_INTEL:
930 hw->phy.type = txgbe_phy_sfp_intel;
931 break;
932 default:
933 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
934 hw->phy.type = txgbe_phy_sfp_unknown_passive;
935 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
936 hw->phy.type = txgbe_phy_sfp_unknown_active;
937 else
938 hw->phy.type = txgbe_phy_sfp_unknown;
939 break;
940 }
941 }
942
943 /* Allow any DA cable vendor */
944 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
945 TXGBE_SFF_CABLE_DA_ACTIVE)) {
946 return 0;
947 }
948
949 /* Verify supported 1G SFP modules */
950 if (comp_codes_10g == 0 &&
951 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
952 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
953 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
954 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
955 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
956 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
957 hw->phy.type = txgbe_phy_sfp_unsupported;
958 return TXGBE_ERR_SFP_NOT_SUPPORTED;
959 }
960
961 hw->mac.get_device_caps(hw, &enforce_sfp);
962 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
963 !hw->allow_unsupported_sfp &&
964 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
965 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
966 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
967 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
968 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
969 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
970 DEBUGOUT("SFP+ module not supported\n");
971 hw->phy.type = txgbe_phy_sfp_unsupported;
972 return TXGBE_ERR_SFP_NOT_SUPPORTED;
973 }
974
975 return err;
976 }
977
978 /**
979 * txgbe_identify_qsfp_module - Identifies QSFP modules
980 * @hw: pointer to hardware structure
981 *
982 * Searches for and identifies the QSFP module and assigns appropriate PHY type
983 **/
txgbe_identify_qsfp_module(struct txgbe_hw * hw)984 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
985 {
986 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
987 u32 vendor_oui = 0;
988 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
989 u8 identifier = 0;
990 u8 comp_codes_1g = 0;
991 u8 comp_codes_10g = 0;
992 u8 oui_bytes[3] = {0, 0, 0};
993 u16 enforce_sfp = 0;
994 u8 connector = 0;
995 u8 cable_length = 0;
996 u8 device_tech = 0;
997 bool active_cable = false;
998
999 DEBUGFUNC("txgbe_identify_qsfp_module");
1000
1001 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
1002 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1003 err = TXGBE_ERR_SFP_NOT_PRESENT;
1004 goto out;
1005 }
1006
1007 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
1008 &identifier);
1009 ERR_I2C:
1010 if (err != 0) {
1011 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1012 hw->phy.id = 0;
1013 hw->phy.type = txgbe_phy_unknown;
1014 return TXGBE_ERR_SFP_NOT_PRESENT;
1015 }
1016 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1017 hw->phy.type = txgbe_phy_sfp_unsupported;
1018 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1019 goto out;
1020 }
1021
1022 hw->phy.id = identifier;
1023
1024 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
1025 &comp_codes_10g);
1026
1027 if (err != 0)
1028 goto ERR_I2C;
1029
1030 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
1031 &comp_codes_1g);
1032
1033 if (err != 0)
1034 goto ERR_I2C;
1035
1036 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1037 hw->phy.type = txgbe_phy_qsfp_unknown_passive;
1038 if (hw->bus.lan_id == 0)
1039 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
1040 else
1041 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
1042 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1043 TXGBE_SFF_10GBASELR_CAPABLE)) {
1044 if (hw->bus.lan_id == 0)
1045 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
1046 else
1047 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
1048 } else {
1049 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1050 active_cable = true;
1051
1052 if (!active_cable) {
1053 hw->phy.read_i2c_eeprom(hw,
1054 TXGBE_SFF_QSFP_CONNECTOR,
1055 &connector);
1056
1057 hw->phy.read_i2c_eeprom(hw,
1058 TXGBE_SFF_QSFP_CABLE_LENGTH,
1059 &cable_length);
1060
1061 hw->phy.read_i2c_eeprom(hw,
1062 TXGBE_SFF_QSFP_DEVICE_TECH,
1063 &device_tech);
1064
1065 if (connector ==
1066 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
1067 cable_length > 0 &&
1068 ((device_tech >> 4) ==
1069 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
1070 active_cable = true;
1071 }
1072
1073 if (active_cable) {
1074 hw->phy.type = txgbe_phy_qsfp_unknown_active;
1075 if (hw->bus.lan_id == 0)
1076 hw->phy.sfp_type =
1077 txgbe_sfp_type_da_act_lmt_core0;
1078 else
1079 hw->phy.sfp_type =
1080 txgbe_sfp_type_da_act_lmt_core1;
1081 } else {
1082 /* unsupported module type */
1083 hw->phy.type = txgbe_phy_sfp_unsupported;
1084 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1085 goto out;
1086 }
1087 }
1088
1089 if (hw->phy.sfp_type != stored_sfp_type)
1090 hw->phy.sfp_setup_needed = true;
1091
1092 /* Determine if the QSFP+ PHY is dual speed or not. */
1093 hw->phy.multispeed_fiber = false;
1094 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
1095 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
1096 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
1097 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
1098 hw->phy.multispeed_fiber = true;
1099
1100 /* Determine PHY vendor for optical modules */
1101 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1102 TXGBE_SFF_10GBASELR_CAPABLE)) {
1103 err = hw->phy.read_i2c_eeprom(hw,
1104 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1105 &oui_bytes[0]);
1106
1107 if (err != 0)
1108 goto ERR_I2C;
1109
1110 err = hw->phy.read_i2c_eeprom(hw,
1111 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1112 &oui_bytes[1]);
1113
1114 if (err != 0)
1115 goto ERR_I2C;
1116
1117 err = hw->phy.read_i2c_eeprom(hw,
1118 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1119 &oui_bytes[2]);
1120
1121 if (err != 0)
1122 goto ERR_I2C;
1123
1124 vendor_oui =
1125 ((oui_bytes[0] << 24) |
1126 (oui_bytes[1] << 16) |
1127 (oui_bytes[2] << 8));
1128
1129 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
1130 hw->phy.type = txgbe_phy_qsfp_intel;
1131 else
1132 hw->phy.type = txgbe_phy_qsfp_unknown;
1133
1134 hw->mac.get_device_caps(hw, &enforce_sfp);
1135 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1136 /* Make sure we're a supported PHY type */
1137 if (hw->phy.type == txgbe_phy_qsfp_intel) {
1138 err = 0;
1139 } else {
1140 if (hw->allow_unsupported_sfp) {
1141 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
1142 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1143 "Wangxun Corporation is not responsible for any harm caused by using untested modules.\n");
1144 err = 0;
1145 } else {
1146 DEBUGOUT("QSFP module not supported\n");
1147 hw->phy.type =
1148 txgbe_phy_sfp_unsupported;
1149 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1150 }
1151 }
1152 } else {
1153 err = 0;
1154 }
1155 }
1156
1157 out:
1158 return err;
1159 }
1160
1161 /**
1162 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1163 * @hw: pointer to hardware structure
1164 * @byte_offset: EEPROM byte offset to read
1165 * @eeprom_data: value read
1166 *
1167 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1168 **/
txgbe_read_i2c_eeprom(struct txgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1169 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1170 u8 *eeprom_data)
1171 {
1172 DEBUGFUNC("txgbe_read_i2c_eeprom");
1173
1174 return hw->phy.read_i2c_byte(hw, byte_offset,
1175 TXGBE_I2C_EEPROM_DEV_ADDR,
1176 eeprom_data);
1177 }
1178
1179 /**
1180 * txgbe_read_i2c_sff8472 - Reads 8 bit word over I2C interface
1181 * @hw: pointer to hardware structure
1182 * @byte_offset: byte offset at address 0xA2
1183 * @sff8472_data: value read
1184 *
1185 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1186 **/
txgbe_read_i2c_sff8472(struct txgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1187 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
1188 u8 *sff8472_data)
1189 {
1190 return hw->phy.read_i2c_byte(hw, byte_offset,
1191 TXGBE_I2C_EEPROM_DEV_ADDR2,
1192 sff8472_data);
1193 }
1194
1195 /**
1196 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1197 * @hw: pointer to hardware structure
1198 * @byte_offset: EEPROM byte offset to write
1199 * @eeprom_data: value to write
1200 *
1201 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1202 **/
txgbe_write_i2c_eeprom(struct txgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1203 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1204 u8 eeprom_data)
1205 {
1206 DEBUGFUNC("txgbe_write_i2c_eeprom");
1207
1208 return hw->phy.write_i2c_byte(hw, byte_offset,
1209 TXGBE_I2C_EEPROM_DEV_ADDR,
1210 eeprom_data);
1211 }
1212
1213 /**
1214 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
1215 * @hw: pointer to hardware structure
1216 * @byte_offset: byte offset to read
1217 * @dev_addr: address to read from
1218 * @data: value read
1219 *
1220 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1221 * a specified device address.
1222 **/
txgbe_read_i2c_byte_unlocked(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)1223 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1224 u8 dev_addr, u8 *data)
1225 {
1226 UNREFERENCED_PARAMETER(dev_addr);
1227
1228 DEBUGFUNC("txgbe_read_i2c_byte");
1229
1230 txgbe_i2c_start(hw);
1231
1232 /* wait tx empty */
1233 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1234 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1235 return -TERR_TIMEOUT;
1236 }
1237
1238 /* read data */
1239 wr32(hw, TXGBE_I2CDATA,
1240 byte_offset | TXGBE_I2CDATA_STOP);
1241 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ);
1242
1243 /* wait for read complete */
1244 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1245 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1246 return -TERR_TIMEOUT;
1247 }
1248
1249 txgbe_i2c_stop(hw);
1250
1251 *data = 0xFF & rd32(hw, TXGBE_I2CDATA);
1252
1253 return 0;
1254 }
1255
1256 /**
1257 * txgbe_read_i2c_byte - Reads 8 bit word over I2C
1258 * @hw: pointer to hardware structure
1259 * @byte_offset: byte offset to read
1260 * @dev_addr: address to read from
1261 * @data: value read
1262 *
1263 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1264 * a specified device address.
1265 **/
txgbe_read_i2c_byte(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)1266 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1267 u8 dev_addr, u8 *data)
1268 {
1269 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1270 int err = 0;
1271
1272 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1273 return TXGBE_ERR_SWFW_SYNC;
1274 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1275 hw->mac.release_swfw_sync(hw, swfw_mask);
1276 return err;
1277 }
1278
1279 /**
1280 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1281 * @hw: pointer to hardware structure
1282 * @byte_offset: byte offset to write
1283 * @dev_addr: address to write to
1284 * @data: value to write
1285 *
1286 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1287 * a specified device address.
1288 **/
txgbe_write_i2c_byte_unlocked(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)1289 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1290 u8 dev_addr, u8 data)
1291 {
1292 UNREFERENCED_PARAMETER(dev_addr);
1293
1294 DEBUGFUNC("txgbe_write_i2c_byte");
1295
1296 txgbe_i2c_start(hw);
1297
1298 /* wait tx empty */
1299 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1300 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1301 return -TERR_TIMEOUT;
1302 }
1303
1304 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
1305 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
1306
1307 /* wait for write complete */
1308 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1309 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1310 return -TERR_TIMEOUT;
1311 }
1312 txgbe_i2c_stop(hw);
1313
1314 return 0;
1315 }
1316
1317 /**
1318 * txgbe_write_i2c_byte - Writes 8 bit word over I2C
1319 * @hw: pointer to hardware structure
1320 * @byte_offset: byte offset to write
1321 * @dev_addr: address to write to
1322 * @data: value to write
1323 *
1324 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1325 * a specified device address.
1326 **/
txgbe_write_i2c_byte(struct txgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)1327 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1328 u8 dev_addr, u8 data)
1329 {
1330 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1331 int err = 0;
1332
1333 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1334 return TXGBE_ERR_SWFW_SYNC;
1335 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1336 hw->mac.release_swfw_sync(hw, swfw_mask);
1337
1338 return err;
1339 }
1340
1341 /**
1342 * txgbe_i2c_start - Sets I2C start condition
1343 * @hw: pointer to hardware structure
1344 *
1345 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1346 **/
txgbe_i2c_start(struct txgbe_hw * hw)1347 static void txgbe_i2c_start(struct txgbe_hw *hw)
1348 {
1349 DEBUGFUNC("txgbe_i2c_start");
1350
1351 wr32(hw, TXGBE_I2CENA, 0);
1352
1353 wr32(hw, TXGBE_I2CCON,
1354 (TXGBE_I2CCON_MENA |
1355 TXGBE_I2CCON_SPEED(1) |
1356 TXGBE_I2CCON_RESTART |
1357 TXGBE_I2CCON_SDIA));
1358 wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR);
1359 wr32(hw, TXGBE_I2CSSSCLHCNT, 600);
1360 wr32(hw, TXGBE_I2CSSSCLLCNT, 600);
1361 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
1362 wr32(hw, TXGBE_I2CTXTL, 4);
1363 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
1364 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF);
1365
1366 wr32(hw, TXGBE_I2CICM, 0);
1367 wr32(hw, TXGBE_I2CENA, 1);
1368 }
1369
1370 /**
1371 * txgbe_i2c_stop - Sets I2C stop condition
1372 * @hw: pointer to hardware structure
1373 *
1374 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1375 **/
txgbe_i2c_stop(struct txgbe_hw * hw)1376 static void txgbe_i2c_stop(struct txgbe_hw *hw)
1377 {
1378 DEBUGFUNC("txgbe_i2c_stop");
1379
1380 /* wait for completion */
1381 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST,
1382 0, NULL, 100, 100)) {
1383 DEBUGFUNC("i2c stop timeout.");
1384 }
1385
1386 wr32(hw, TXGBE_I2CENA, 0);
1387 }
1388
1389 static s32
txgbe_set_sgmii_an37_ability(struct txgbe_hw * hw)1390 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
1391 {
1392 u32 value;
1393
1394 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002);
1395 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);
1396 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200);
1397 value = rd32_epcs(hw, SR_MII_MMD_CTL);
1398 value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);
1399 wr32_epcs(hw, SR_MII_MMD_CTL, value);
1400 return 0;
1401 }
1402
1403 static s32
txgbe_set_link_to_kr(struct txgbe_hw * hw,bool autoneg)1404 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
1405 {
1406 u32 i;
1407 s32 err = 0;
1408
1409 /* 1. Wait xpcs power-up good */
1410 for (i = 0; i < 100; i++) {
1411 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1412 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1413 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1414 break;
1415 msec_delay(10);
1416 }
1417 if (i == 100) {
1418 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1419 goto out;
1420 }
1421
1422 if (!autoneg) {
1423 /* 2. Disable xpcs AN-73 */
1424 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1425 /* Disable PHY MPLLA for eth mode change(after ECO) */
1426 wr32_ephy(hw, 0x4, 0x243A);
1427 txgbe_flush(hw);
1428 msec_delay(1);
1429 /* Set the eth change_mode bit first in mis_rst register
1430 * for corresponding LAN port
1431 */
1432 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1433
1434 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1435 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)
1436 */
1437 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1438 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR);
1439
1440 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1441 * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11)
1442 */
1443 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1444
1445 /* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1446 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
1447 * Bit[7:5](CTLE_POLE_0) = 3'h2
1448 * Bit[4:0](CTLE_BOOST_0) = 4'hA
1449 */
1450 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A);
1451
1452 /* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register
1453 * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3)
1454 */
1455 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004);
1456
1457 /* 7. Initialize the mode by setting VR XS or PCS MMD Digital
1458 * Control1 Register Bit[15](VR_RST)
1459 */
1460 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1461
1462 /* Wait phy initialization done */
1463 for (i = 0; i < 100; i++) {
1464 if ((rd32_epcs(hw,
1465 VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1466 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1467 break;
1468 msleep(100);
1469 }
1470 if (i == 100) {
1471 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1472 goto out;
1473 }
1474 } else {
1475 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);
1476 }
1477 out:
1478 return err;
1479 }
1480
1481 static s32
txgbe_set_link_to_kx4(struct txgbe_hw * hw,bool autoneg)1482 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
1483 {
1484 u32 i;
1485 s32 err = 0;
1486 u32 value;
1487
1488 /* Check link status, if already set, skip setting it again */
1489 if (hw->link_status == TXGBE_LINK_STATUS_KX4)
1490 goto out;
1491
1492 /* 1. Wait xpcs power-up good */
1493 for (i = 0; i < 100; i++) {
1494 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1495 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1496 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1497 break;
1498 msec_delay(10);
1499 }
1500 if (i == 100) {
1501 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1502 goto out;
1503 }
1504
1505 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1506 ~TXGBE_MACTXCFG_TXE);
1507
1508 /* 2. Disable xpcs AN-73 */
1509 if (!autoneg)
1510 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1511 else
1512 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1513
1514 /* Disable PHY MPLLA for eth mode change(after ECO) */
1515 wr32_ephy(hw, 0x4, 0x250A);
1516 txgbe_flush(hw);
1517 msec_delay(1);
1518
1519 /* Set the eth change_mode bit first in mis_rst register
1520 * for corresponding LAN port
1521 */
1522 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1523
1524 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1525 * PCS_TYPE_SEL: non KR
1526 */
1527 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1528 SR_PCS_CTRL2_TYPE_SEL_X);
1529
1530 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b1
1531 * SS13: 10G speed
1532 */
1533 wr32_epcs(hw, SR_PMA_CTRL1,
1534 SR_PMA_CTRL1_SS13_KX4);
1535
1536 value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0x10;
1537 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1538
1539 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1540
1541 value = (0x1804 & ~0x3F3F);
1542 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1543
1544 value = (0x50 & ~0x7F) | 40 | (1 << 6);
1545 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1546
1547 for (i = 0; i < 4; i++) {
1548 if (i == 0)
1549 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1550 (0x7 << 8) | 0x6;
1551 else
1552 value = (0xff06 & ~0xFFFF) | (0x7 << 12) |
1553 (0x7 << 8) | 0x6;
1554 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1555 }
1556
1557 value = 0x0 & ~0x7777;
1558 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1559
1560 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1561
1562 value = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1;
1563 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1564
1565 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA
1566 * Control 0 Register Bit[7:0] = 8'd40 //MPLLA_MULTIPLIER
1567 */
1568 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1569 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER);
1570
1571 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA
1572 * Control 3 Register Bit[10:0] = 11'd86 //MPLLA_BANDWIDTH
1573 */
1574 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1575 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER);
1576
1577 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1578 * Calibration Load 0 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_0
1579 */
1580 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1581 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1582
1583 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1584 * Calibration Load 1 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_1
1585 */
1586 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1,
1587 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1588
1589 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1590 * Calibration Load 2 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_2
1591 */
1592 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2,
1593 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1594 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1595 * Calibration Load 3 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_3
1596 */
1597 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3,
1598 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1599 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1600 * Calibration Reference 0 Register Bit[5:0] = 6'd34 //VCO_REF_LD_0/1
1601 */
1602 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222);
1603
1604 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1605 * Calibration Reference 1 Register Bit[5:0] = 6'd34 //VCO_REF_LD_2/3
1606 */
1607 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222);
1608
1609 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1610 * Enable Register Bit[7:0] = 8'd0 //AFE_EN_0/3_1, DFE_EN_0/3_1
1611 */
1612 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
1613
1614 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1615 * Equalization Control 4 Register Bit[3:0] = 4'd0 //CONT_ADAPT_0/3_1
1616 */
1617 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0);
1618
1619 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1620 * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0],
1621 * all rates to 3'b010 //TX0/1/2/3_RATE
1622 */
1623 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222);
1624
1625 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1626 * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0],
1627 * all rates to 2'b10 //RX0/1/2/3_RATE
1628 */
1629 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222);
1630
1631 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1632 * Control 2 Register Bit[15:8] = 2'b01 //TX0/1/2/3_WIDTH: 10bits
1633 */
1634 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500);
1635
1636 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1637 * Control 2 Register Bit[15:8] = 2'b01 //RX0/1/2/3_WIDTH: 10bits
1638 */
1639 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500);
1640
1641 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1642 * 2 Register Bit[10:8] = 3'b010
1643 * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1644 */
1645 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1646 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1647
1648 wr32_epcs(hw, 0x1f0000, 0x0);
1649 wr32_epcs(hw, 0x1f8001, 0x0);
1650 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0);
1651
1652 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1653 * Register Bit[15](VR_RST)
1654 */
1655 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1656
1657 /* Wait phy initialization done */
1658 for (i = 0; i < 100; i++) {
1659 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1660 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1661 break;
1662 msleep(100);
1663 }
1664
1665 /* If success, set link status */
1666 hw->link_status = TXGBE_LINK_STATUS_KX4;
1667
1668 if (i == 100) {
1669 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1670 goto out;
1671 }
1672
1673 out:
1674 return err;
1675 }
1676
1677 static s32
txgbe_set_link_to_kx(struct txgbe_hw * hw,u32 speed,bool autoneg)1678 txgbe_set_link_to_kx(struct txgbe_hw *hw,
1679 u32 speed,
1680 bool autoneg)
1681 {
1682 u32 i;
1683 s32 err = 0;
1684 u32 wdata = 0;
1685 u32 value;
1686
1687 /* Check link status, if already set, skip setting it again */
1688 if (hw->link_status == TXGBE_LINK_STATUS_KX)
1689 goto out;
1690
1691 /* 1. Wait xpcs power-up good */
1692 for (i = 0; i < 100; i++) {
1693 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1694 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1695 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1696 break;
1697 msec_delay(10);
1698 }
1699 if (i == 100) {
1700 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1701 goto out;
1702 }
1703
1704 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1705 ~TXGBE_MACTXCFG_TXE);
1706
1707 /* 2. Disable xpcs AN-73 */
1708 if (!autoneg)
1709 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1710 else
1711 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1712
1713 /* Disable PHY MPLLA for eth mode change(after ECO) */
1714 wr32_ephy(hw, 0x4, 0x240A);
1715 txgbe_flush(hw);
1716 msec_delay(1);
1717
1718 /* Set the eth change_mode bit first in mis_rst register
1719 * for corresponding LAN port
1720 */
1721 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1722
1723 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1724 * PCS_TYPE_SEL: non KR
1725 */
1726 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1727 SR_PCS_CTRL2_TYPE_SEL_X);
1728
1729 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
1730 * SS13: 1G speed
1731 */
1732 wr32_epcs(hw, SR_PMA_CTRL1,
1733 SR_PMA_CTRL1_SS13_KX);
1734
1735 /* Set SR MII MMD Control Register to corresponding speed: {Bit[6],
1736 * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G]
1737 */
1738 if (speed == TXGBE_LINK_SPEED_100M_FULL)
1739 wdata = 0x2100;
1740 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1741 wdata = 0x0140;
1742 else if (speed == TXGBE_LINK_SPEED_10M_FULL)
1743 wdata = 0x0100;
1744 wr32_epcs(hw, SR_MII_MMD_CTL,
1745 wdata);
1746
1747 value = (0xf5f0 & ~0x710) | (0x5 << 8);
1748 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1749
1750 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1751
1752 value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
1753 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1754
1755 value = (0x50 & ~0x7F) | 16 | (1 << 6);
1756 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1757
1758 for (i = 0; i < 4; i++) {
1759 if (i) {
1760 value = 0xff06;
1761 } else {
1762 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1763 (0x7 << 8) | 0x6;
1764 }
1765 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1766 }
1767
1768 value = 0x0 & ~0x7;
1769 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1770
1771 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1772
1773 value = (0x6db & ~0x7) | 0x4;
1774 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1775
1776 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1777 * 0 Register Bit[7:0] = 8'd32 //MPLLA_MULTIPLIER
1778 */
1779 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1780 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX);
1781
1782 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA Control
1783 * 3 Register Bit[10:0] = 11'd70 //MPLLA_BANDWIDTH
1784 */
1785 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1786 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX);
1787
1788 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1789 * Calibration Load 0 Register Bit[12:0] = 13'd1344 //VCO_LD_VAL_0
1790 */
1791 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1792 TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX);
1793
1794 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549);
1795 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549);
1796 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549);
1797
1798 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1799 * Calibration Reference 0 Register Bit[5:0] = 6'd42 //VCO_REF_LD_0
1800 */
1801 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0,
1802 TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX);
1803
1804 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929);
1805
1806 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1807 * Enable Register Bit[4], Bit[0] = 1'b0 //AFE_EN_0, DFE_EN_0
1808 */
1809 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE,
1810 0x0);
1811 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1812 * Equalization Control 4 Register Bit[0] = 1'b0 //CONT_ADAPT_0
1813 */
1814 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL,
1815 0x0010);
1816 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1817 * Control Register Bit[2:0] = 3'b011 //TX0_RATE
1818 */
1819 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL,
1820 TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX);
1821
1822 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1823 * Control Register Bit[2:0] = 3'b011 //RX0_RATE
1824 */
1825 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL,
1826 TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX);
1827
1828 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1829 * Control 2 Register Bit[9:8] = 2'b01 //TX0_WIDTH: 10bits
1830 */
1831 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2,
1832 TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER);
1833 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1834 * Control 2 Register Bit[9:8] = 2'b01 //RX0_WIDTH: 10bits
1835 */
1836 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2,
1837 TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER);
1838 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1839 * 2 Register Bit[10:8] = 3'b010 //MPLLA_DIV16P5_CLK_EN=0,
1840 * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1841 */
1842 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1843 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1844
1845 /* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL
1846 * Set to 8bit MII (required in 10M/100M SGMII)
1847 */
1848 wr32_epcs(hw, SR_MII_MMD_AN_CTL,
1849 0x0100);
1850
1851 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1852 * Register Bit[15](VR_RST)
1853 */
1854 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1855
1856 /* Wait phy initialization done */
1857 for (i = 0; i < 100; i++) {
1858 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1859 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1860 break;
1861 msleep(100);
1862 }
1863
1864 /* If success, set link status */
1865 hw->link_status = TXGBE_LINK_STATUS_KX;
1866
1867 if (i == 100) {
1868 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1869 goto out;
1870 }
1871
1872 out:
1873 return err;
1874 }
1875
1876 static s32
txgbe_set_link_to_sfi(struct txgbe_hw * hw,u32 speed)1877 txgbe_set_link_to_sfi(struct txgbe_hw *hw,
1878 u32 speed)
1879 {
1880 u32 i;
1881 s32 err = 0;
1882 u32 value = 0;
1883
1884 /* Set the module link speed */
1885 hw->mac.set_rate_select_speed(hw, speed);
1886 /* 1. Wait xpcs power-up good */
1887 for (i = 0; i < 100; i++) {
1888 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1889 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1890 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1891 break;
1892 msec_delay(10);
1893 }
1894 if (i == 100) {
1895 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1896 goto out;
1897 }
1898
1899 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1900 ~TXGBE_MACTXCFG_TXE);
1901
1902 /* 2. Disable xpcs AN-73 */
1903 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1904
1905 /* Disable PHY MPLLA for eth mode change(after ECO) */
1906 wr32_ephy(hw, 0x4, 0x243A);
1907 txgbe_flush(hw);
1908 msec_delay(1);
1909 /* Set the eth change_mode bit first in mis_rst register
1910 * for corresponding LAN port
1911 */
1912 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1913
1914 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
1915 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
1916 * PCS_TYPE_SEL: KR
1917 */
1918 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0);
1919 value = rd32_epcs(hw, SR_PMA_CTRL1);
1920 value = value | 0x2000;
1921 wr32_epcs(hw, SR_PMA_CTRL1, value);
1922 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33
1923 * MPLLA_MULTIPLIER
1924 */
1925 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021);
1926 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1927 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0
1928 */
1929 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0);
1930 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
1931 value = (value & ~0x700) | 0x500;
1932 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1933 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1934 * Bit[12:8](RX_VREF_CTRL) = 5'hF
1935 */
1936 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1937 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register
1938 * Bit[12:0] = 13'd1353 //VCO_LD_VAL_0
1939 */
1940 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549);
1941 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register
1942 * Bit[5:0] = 6'd41 //VCO_REF_LD_0
1943 */
1944 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029);
1945 /* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register
1946 * Bit[2:0] = 3'b000 //TX0_RATE
1947 */
1948 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0);
1949 /* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register
1950 * Bit[2:0] = 3'b000 //RX0_RATE
1951 */
1952 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0);
1953 /* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11
1954 * TX0_WIDTH: 20bits
1955 */
1956 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300);
1957 /* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11
1958 * RX0_WIDTH: 20bits
1959 */
1960 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300);
1961 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register
1962 * Bit[10:8] = 3'b110
1963 * MPLLA_DIV16P5_CLK_EN=1
1964 * MPLLA_DIV10_CLK_EN=1
1965 * MPLLA_DIV8_CLK_EN=0
1966 */
1967 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);
1968 /* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register
1969 * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4
1970 */
1971 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
1972 value = (value & ~0x3F3F) | (24 << 8) | 4;
1973 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1974 /* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register
1975 * Bit[6](TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36
1976 */
1977 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
1978 value = (value & ~0x7F) | 16 | (1 << 6);
1979 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1980 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
1981 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
1982 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1983 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
1984 * Bit[7:5](CTLE_POLE_0) = 3'h2
1985 * Bit[4:0](CTLE_BOOST_0) = 4'hF
1986 */
1987 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
1988
1989 } else {
1990 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1991 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
1992 * Bit[7:5](CTLE_POLE_0) = 3'h2
1993 * Bit[4:0](CTLE_BOOST_0) = 4'hA
1994 */
1995 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
1996 value = (value & ~0xFFFF) | (2 << 5) | 0x05;
1997 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
1998 }
1999 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2000 value = (value & ~0x7) | 0x0;
2001 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2002
2003 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2004 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2005 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2006 * Bit[7:0](DFE_TAP1_0) = 8'd20
2007 */
2008 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014);
2009 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2010 value = (value & ~0x11) | 0x11;
2011 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2012 } else {
2013 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2014 * Bit[7:0](DFE_TAP1_0) = 8'd20
2015 */
2016 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE);
2017 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2018 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2019 */
2020 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2021 value = (value & ~0x11) | 0x0;
2022 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2023 }
2024 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL);
2025 value = value & ~0x1;
2026 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value);
2027 } else {
2028 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
2029 * PCS_TYPE_SEL: KR
2030 */
2031 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1);
2032 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
2033 * SS13: 1G speed
2034 */
2035 wr32_epcs(hw, SR_PMA_CTRL1, 0x0000);
2036 /* Set SR MII MMD Control Register to corresponding speed */
2037 wr32_epcs(hw, SR_MII_MMD_CTL, 0x0140);
2038
2039 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
2040 value = (value & ~0x710) | 0x500;
2041 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
2042 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
2043 * Bit[12:8](RX_VREF_CTRL) = 5'hF
2044 */
2045 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
2046 /* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register
2047 * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4
2048 */
2049 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2050 value = (value & ~0x3F3F) | (24 << 8) | 4;
2051 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2052 /* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register Bit[6]
2053 * (TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36
2054 */
2055 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2056 value = (value & ~0x7F) | 16 | (1 << 6);
2057 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2058 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2059 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2060 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2061 } else {
2062 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2063 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2064 * Bit[7:5](CTLE_POLE_0) = 3'h2
2065 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2066 */
2067 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2068 value = (value & ~0xFFFF) | 0x7706;
2069 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2070 }
2071 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2072 value = (value & ~0x7) | 0x0;
2073 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2074 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2075 * Bit[7:0](DFE_TAP1_0) = 8'd00
2076 */
2077 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
2078 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2079 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2080 */
2081 value = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3);
2082 value = (value & ~0x7) | 0x4;
2083 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
2084 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020);
2085 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046);
2086 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540);
2087 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A);
2088 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
2089 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010);
2090 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003);
2091 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003);
2092 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100);
2093 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100);
2094 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200);
2095 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100);
2096 }
2097 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
2098 * Register Bit[15](VR_RST)
2099 */
2100 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
2101
2102 /* Wait phy initialization done */
2103 for (i = 0; i < 100; i++) {
2104 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
2105 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
2106 break;
2107 msleep(100);
2108 }
2109 if (i == 100) {
2110 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
2111 goto out;
2112 }
2113
2114 out:
2115 return err;
2116 }
2117
2118 /**
2119 * txgbe_autoc_read - Hides MAC differences needed for AUTOC read
2120 * @hw: pointer to hardware structure
2121 */
txgbe_autoc_read(struct txgbe_hw * hw)2122 u64 txgbe_autoc_read(struct txgbe_hw *hw)
2123 {
2124 u64 autoc = 0;
2125 u32 sr_pcs_ctl;
2126 u32 sr_pma_ctl1;
2127 u32 sr_an_ctl;
2128 u32 sr_an_adv_reg2;
2129
2130 if (hw->phy.multispeed_fiber) {
2131 autoc |= TXGBE_AUTOC_LMS_10G;
2132 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||
2133 hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {
2134 autoc |= TXGBE_AUTOC_LMS_10G |
2135 TXGBE_AUTOC_10GS_SFI;
2136 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
2137 autoc = 0; /*TBD*/
2138 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI) {
2139 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN |
2140 TXGBE_AUTOC_10G_XAUI;
2141 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T;
2142 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {
2143 autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M;
2144 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T |
2145 TXGBE_PHYSICAL_LAYER_100BASE_TX;
2146 }
2147
2148 if (hw->device_id != TXGBE_DEV_ID_RAPTOR_SGMII)
2149 return autoc;
2150
2151 sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2152 sr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1);
2153 sr_an_ctl = rd32_epcs(hw, SR_AN_CTRL);
2154 sr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2155
2156 if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X &&
2157 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX &&
2158 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2159 /* 1G or KX - no backplane auto-negotiation */
2160 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN |
2161 TXGBE_AUTOC_1G_KX;
2162 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2163 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2164 SR_PCS_CTRL2_TYPE_SEL_X &&
2165 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 &&
2166 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2167 autoc |= TXGBE_AUTOC_LMS_10G |
2168 TXGBE_AUTOC_10G_KX4;
2169 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2170 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2171 SR_PCS_CTRL2_TYPE_SEL_R &&
2172 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2173 /* 10 GbE serial link (KR -no backplane auto-negotiation) */
2174 autoc |= TXGBE_AUTOC_LMS_10G |
2175 TXGBE_AUTOC_10GS_KR;
2176 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR;
2177 } else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {
2178 /* KX/KX4/KR backplane auto-negotiation enable */
2179 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR)
2180 autoc |= TXGBE_AUTOC_10G_KR;
2181 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4)
2182 autoc |= TXGBE_AUTOC_10G_KX4;
2183 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX)
2184 autoc |= TXGBE_AUTOC_1G_KX;
2185 autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;
2186 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |
2187 TXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2188 TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2189 }
2190
2191 return autoc;
2192 }
2193
2194 /**
2195 * txgbe_autoc_write - Hides MAC differences needed for AUTOC write
2196 * @hw: pointer to hardware structure
2197 * @autoc: value to write to AUTOC
2198 */
txgbe_autoc_write(struct txgbe_hw * hw,u64 autoc)2199 void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
2200 {
2201 bool autoneg;
2202 u32 speed;
2203 u32 mactxcfg = 0;
2204
2205 speed = TXGBE_AUTOC_SPEED(autoc);
2206 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2207 autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);
2208 autoc &= ~TXGBE_AUTOC_AUTONEG;
2209
2210 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_KR_KX_KX4) {
2211 if (!autoneg) {
2212 switch (hw->phy.link_mode) {
2213 case TXGBE_PHYSICAL_LAYER_10GBASE_KR:
2214 txgbe_set_link_to_kr(hw, autoneg);
2215 break;
2216 case TXGBE_PHYSICAL_LAYER_10GBASE_KX4:
2217 txgbe_set_link_to_kx4(hw, autoneg);
2218 break;
2219 case TXGBE_PHYSICAL_LAYER_1000BASE_KX:
2220 txgbe_set_link_to_kx(hw, speed, autoneg);
2221 break;
2222 default:
2223 return;
2224 }
2225 }
2226 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI ||
2227 hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {
2228 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
2229 txgbe_set_link_to_kx4(hw, autoneg);
2230 } else {
2231 txgbe_set_link_to_kx(hw, speed, 0);
2232 txgbe_set_sgmii_an37_ability(hw);
2233 }
2234 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||
2235 hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {
2236 txgbe_set_link_to_sfi(hw, speed);
2237 }
2238
2239 if (speed == TXGBE_LINK_SPEED_10GB_FULL)
2240 mactxcfg = TXGBE_MACTXCFG_SPEED_10G;
2241 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
2242 mactxcfg = TXGBE_MACTXCFG_SPEED_1G;
2243
2244 /* enable mac transmitter */
2245 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_SPEED_MASK, mactxcfg);
2246 }
2247
2248