1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
3 */
4
5 #ifndef _HNS3_RXTX_H_
6 #define _HNS3_RXTX_H_
7
8 #include <stdint.h>
9 #include <rte_mbuf_core.h>
10
11 #define HNS3_MIN_RING_DESC 64
12 #define HNS3_MAX_RING_DESC 32768
13 #define HNS3_DEFAULT_RING_DESC 1024
14 #define HNS3_ALIGN_RING_DESC 32
15 #define HNS3_RING_BASE_ALIGN 128
16 #define HNS3_BULK_ALLOC_MBUF_NUM 32
17
18 #define HNS3_DEFAULT_RX_FREE_THRESH 32
19 #define HNS3_DEFAULT_TX_FREE_THRESH 32
20 #define HNS3_DEFAULT_TX_RS_THRESH 32
21 #define HNS3_TX_FAST_FREE_AHEAD 64
22
23 #define HNS3_DEFAULT_RX_BURST 64
24 #if (HNS3_DEFAULT_RX_BURST > 64)
25 #error "PMD HNS3: HNS3_DEFAULT_RX_BURST must <= 64\n"
26 #endif
27 #define HNS3_DEFAULT_DESCS_PER_LOOP 4
28 #define HNS3_SVE_DEFAULT_DESCS_PER_LOOP 8
29 #if (HNS3_DEFAULT_DESCS_PER_LOOP > HNS3_SVE_DEFAULT_DESCS_PER_LOOP)
30 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_DEFAULT_DESCS_PER_LOOP
31 #else
32 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_SVE_DEFAULT_DESCS_PER_LOOP
33 #endif
34 #define HNS3_DEFAULT_RXQ_REARM_THRESH 64
35 #define HNS3_UINT8_BIT 8
36 #define HNS3_UINT16_BIT 16
37 #define HNS3_UINT32_BIT 32
38
39 #define HNS3_512_BD_BUF_SIZE 512
40 #define HNS3_1K_BD_BUF_SIZE 1024
41 #define HNS3_2K_BD_BUF_SIZE 2048
42 #define HNS3_4K_BD_BUF_SIZE 4096
43
44 #define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
45 #define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
46
47 #define HNS3_BD_SIZE_512_TYPE 0
48 #define HNS3_BD_SIZE_1024_TYPE 1
49 #define HNS3_BD_SIZE_2048_TYPE 2
50 #define HNS3_BD_SIZE_4096_TYPE 3
51
52 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
53 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
54 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
55 #define HNS3_RX_FLAG_L4ID_UDP 0x0
56 #define HNS3_RX_FLAG_L4ID_TCP 0x1
57
58 #define HNS3_RXD_DMAC_S 0
59 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
60 #define HNS3_RXD_VLAN_S 2
61 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
62 #define HNS3_RXD_L3ID_S 4
63 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
64 #define HNS3_RXD_L4ID_S 8
65 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
66 #define HNS3_RXD_FRAG_B 12
67 #define HNS3_RXD_STRP_TAGP_S 13
68 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
69
70 #define HNS3_RXD_L2E_B 16
71 #define HNS3_RXD_L3E_B 17
72 #define HNS3_RXD_L4E_B 18
73 #define HNS3_RXD_TRUNCATE_B 19
74 #define HNS3_RXD_HOI_B 20
75 #define HNS3_RXD_DOI_B 21
76 #define HNS3_RXD_OL3E_B 22
77 #define HNS3_RXD_OL4E_B 23
78 #define HNS3_RXD_GRO_COUNT_S 24
79 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
80 #define HNS3_RXD_GRO_FIXID_B 30
81 #define HNS3_RXD_GRO_ECN_B 31
82
83 #define HNS3_RXD_ODMAC_S 0
84 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
85 #define HNS3_RXD_OVLAN_S 2
86 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
87 #define HNS3_RXD_OL3ID_S 4
88 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
89 #define HNS3_RXD_OL4ID_S 8
90 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
91 #define HNS3_RXD_PTYPE_S 4
92 #define HNS3_RXD_PTYPE_M (0xff << HNS3_RXD_PTYPE_S)
93 #define HNS3_RXD_FBHI_S 12
94 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
95 #define HNS3_RXD_FBLI_S 14
96 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
97
98 #define HNS3_RXD_BDTYPE_S 0
99 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
100 #define HNS3_RXD_VLD_B 4
101 #define HNS3_RXD_UDP0_B 5
102 #define HNS3_RXD_EXTEND_B 7
103 #define HNS3_RXD_FE_B 8
104 #define HNS3_RXD_LUM_B 9
105 #define HNS3_RXD_CRCP_B 10
106 #define HNS3_RXD_L3L4P_B 11
107
108 #define HNS3_RXD_TS_VLD_B 14
109 #define HNS3_RXD_GRO_SIZE_S 16
110 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
111
112 #define HNS3_TXD_L3T_S 0
113 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
114 #define HNS3_TXD_L4T_S 2
115 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
116 #define HNS3_TXD_L3CS_B 4
117 #define HNS3_TXD_L4CS_B 5
118 #define HNS3_TXD_VLAN_B 6
119 #define HNS3_TXD_TSO_B 7
120
121 #define HNS3_TXD_L2LEN_S 8
122 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
123 #define HNS3_TXD_L3LEN_S 16
124 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
125 #define HNS3_TXD_L4LEN_S 24
126 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
127
128 #define HNS3_TXD_OL3T_S 0
129 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
130 #define HNS3_TXD_OVLAN_B 2
131 #define HNS3_TXD_MACSEC_B 3
132 #define HNS3_TXD_TUNTYPE_S 4
133 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
134
135 #define HNS3_TXD_BDTYPE_S 0
136 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
137 #define HNS3_TXD_FE_B 4
138 #define HNS3_TXD_SC_S 5
139 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
140 #define HNS3_TXD_EXTEND_B 7
141 #define HNS3_TXD_VLD_B 8
142 #define HNS3_TXD_RI_B 9
143 #define HNS3_TXD_RA_B 10
144 #define HNS3_TXD_TSYN_B 11
145 #define HNS3_TXD_DECTTL_S 12
146 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
147
148 #define HNS3_TXD_MSS_S 0
149 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
150
151 #define HNS3_TXD_OL4CS_B 22
152 #define HNS3_L2_LEN_UNIT 1UL
153 #define HNS3_L3_LEN_UNIT 2UL
154 #define HNS3_L4_LEN_UNIT 2UL
155
156 #define HNS3_TXD_DEFAULT_BDTYPE 0
157 #define HNS3_TXD_VLD_CMD (0x1 << HNS3_TXD_VLD_B)
158 #define HNS3_TXD_FE_CMD (0x1 << HNS3_TXD_FE_B)
159 #define HNS3_TXD_DEFAULT_VLD_FE_BDTYPE \
160 (HNS3_TXD_VLD_CMD | HNS3_TXD_FE_CMD | HNS3_TXD_DEFAULT_BDTYPE)
161 #define HNS3_TXD_SEND_SIZE_SHIFT 16
162
163 enum hns3_pkt_l2t_type {
164 HNS3_L2_TYPE_UNICAST,
165 HNS3_L2_TYPE_MULTICAST,
166 HNS3_L2_TYPE_BROADCAST,
167 HNS3_L2_TYPE_INVALID,
168 };
169
170 enum hns3_pkt_l3t_type {
171 HNS3_L3T_NONE,
172 HNS3_L3T_IPV6,
173 HNS3_L3T_IPV4,
174 HNS3_L3T_RESERVED
175 };
176
177 enum hns3_pkt_l4t_type {
178 HNS3_L4T_UNKNOWN,
179 HNS3_L4T_TCP,
180 HNS3_L4T_UDP,
181 HNS3_L4T_SCTP
182 };
183
184 enum hns3_pkt_ol3t_type {
185 HNS3_OL3T_NONE,
186 HNS3_OL3T_IPV6,
187 HNS3_OL3T_IPV4_NO_CSUM,
188 HNS3_OL3T_IPV4_CSUM
189 };
190
191 enum hns3_pkt_tun_type {
192 HNS3_TUN_NONE,
193 HNS3_TUN_MAC_IN_UDP,
194 HNS3_TUN_NVGRE,
195 HNS3_TUN_OTHER
196 };
197
198 /* hardware spec ring buffer format */
199 struct hns3_desc {
200 union {
201 uint64_t addr;
202 uint64_t timestamp;
203
204 struct {
205 uint32_t addr0;
206 uint32_t addr1;
207 };
208 };
209 union {
210 struct {
211 uint16_t vlan_tag;
212 uint16_t send_size;
213 union {
214 /*
215 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
216 * L2_LEN
217 */
218 uint32_t type_cs_vlan_tso_len;
219 struct {
220 uint8_t type_cs_vlan_tso;
221 uint8_t l2_len;
222 uint8_t l3_len;
223 uint8_t l4_len;
224 };
225 };
226 uint16_t outer_vlan_tag;
227 uint16_t tv;
228 union {
229 /* OL3T | OVALAN | MACSEC */
230 uint32_t ol_type_vlan_len_msec;
231 struct {
232 uint8_t ol_type_vlan_msec;
233 uint8_t ol2_len;
234 uint8_t ol3_len;
235 uint8_t ol4_len;
236 };
237 };
238
239 uint32_t paylen_fd_dop_ol4cs;
240 uint16_t tp_fe_sc_vld_ra_ri;
241 uint16_t mss;
242 } tx;
243
244 struct {
245 uint32_t l234_info;
246 uint16_t pkt_len;
247 uint16_t size;
248 uint32_t rss_hash;
249 uint16_t fd_id;
250 uint16_t vlan_tag;
251 union {
252 uint32_t ol_info;
253 struct {
254 uint16_t o_dm_vlan_id_fb;
255 uint16_t ot_vlan_tag;
256 };
257 };
258 union {
259 uint32_t bd_base_info;
260 struct {
261 uint16_t bdtype_vld_udp0;
262 uint16_t fe_lum_crcp_l3l4p;
263 };
264 };
265 } rx;
266 };
267 } __rte_packed;
268
269 struct hns3_entry {
270 struct rte_mbuf *mbuf;
271 };
272
273 struct hns3_rx_basic_stats {
274 uint64_t packets;
275 uint64_t bytes;
276 uint64_t errors;
277 };
278
279 struct hns3_rx_dfx_stats {
280 uint64_t l3_csum_errors;
281 uint64_t l4_csum_errors;
282 uint64_t ol3_csum_errors;
283 uint64_t ol4_csum_errors;
284 };
285
286 struct hns3_rx_bd_errors_stats {
287 uint64_t l2_errors;
288 uint64_t pkt_len_errors;
289 };
290
291 struct hns3_rx_queue {
292 volatile void *io_head_reg;
293 struct hns3_ptype_table *ptype_tbl;
294 struct rte_mempool *mb_pool;
295 struct hns3_desc *rx_ring;
296 struct hns3_entry *sw_ring;
297
298 uint16_t port_id;
299 uint16_t nb_rx_desc;
300 /*
301 * threshold for the number of BDs waited to passed to hardware. If the
302 * number exceeds the threshold, driver will pass these BDs to hardware.
303 */
304 uint16_t rx_free_thresh;
305 uint16_t next_to_use; /* index of next BD to be polled */
306 uint16_t rx_free_hold; /* num of BDs waited to passed to hardware */
307 uint16_t rx_rearm_start; /* index of BD that driver re-arming from */
308 uint16_t rx_rearm_nb; /* number of remaining BDs to be re-armed */
309
310 /* 4 if RTE_ETH_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
311 uint8_t crc_len;
312
313 /*
314 * Indicate whether ignore the outer VLAN field in the Rx BD reported
315 * by the Hardware. Because the outer VLAN is the PVID if the PVID is
316 * set for some version of hardware network engine whose vlan mode is
317 * HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920. And this VLAN
318 * should not be transitted to the upper-layer application. For hardware
319 * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,
320 * such as kunpeng 930, PVID will not be reported to the BDs. So, PMD
321 * does not need to perform PVID-related operation in Rx. At this
322 * point, the pvid_sw_discard_en will be false.
323 */
324 uint8_t pvid_sw_discard_en:1;
325 uint8_t ptype_en:1; /* indicate if the ptype field enabled */
326
327 uint64_t mbuf_initializer; /* value to init mbufs used with vector rx */
328 /* offset_table: used for vector, to solve execute re-order problem */
329 uint8_t offset_table[HNS3_VECTOR_RX_OFFSET_TABLE_LEN + 1];
330
331 uint16_t bulk_mbuf_num; /* indicate bulk_mbuf valid nums */
332
333 struct hns3_rx_basic_stats basic_stats;
334
335 struct rte_mbuf *pkt_first_seg;
336 struct rte_mbuf *pkt_last_seg;
337
338 struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
339
340 /* DFX statistics that driver does not need to discard packets */
341 struct hns3_rx_dfx_stats dfx_stats;
342 /* Error statistics that driver needs to discard packets */
343 struct hns3_rx_bd_errors_stats err_stats;
344
345 struct rte_mbuf fake_mbuf; /* fake mbuf used with vector rx */
346
347 /*
348 * The following fields are not accessed in the I/O path, so they are
349 * placed at the end.
350 */
351 void *io_base __rte_cache_aligned;
352 struct hns3_adapter *hns;
353 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
354 const struct rte_memzone *mz;
355
356 uint16_t queue_id;
357 uint16_t rx_buf_len;
358
359 bool configured; /* indicate if rx queue has been configured */
360 bool rx_deferred_start; /* don't start this queue in dev start */
361 bool enabled; /* indicate if Rx queue has been enabled */
362 };
363
364 struct hns3_tx_basic_stats {
365 uint64_t packets;
366 uint64_t bytes;
367 };
368
369 /*
370 * The following items are used for the abnormal errors statistics in
371 * the Tx datapath. When upper level application calls the
372 * rte_eth_tx_burst API function to send multiple packets at a time with
373 * burst mode based on hns3 network engine, there are some abnormal
374 * conditions that cause the driver to fail to operate the hardware to
375 * send packets correctly.
376 * Note: When using burst mode to call the rte_eth_tx_burst API function
377 * to send multiple packets at a time. When the first abnormal error is
378 * detected, add one to the relevant error statistics item, and then
379 * exit the loop of sending multiple packets of the function. That is to
380 * say, even if there are multiple packets in which abnormal errors may
381 * be detected in the burst, the relevant error statistics in the driver
382 * will only be increased by one.
383 * The detail description of the Tx abnormal errors statistic items as
384 * below:
385 * - over_length_pkt_cnt
386 * Total number of greater than HNS3_MAX_FRAME_LEN the driver
387 * supported.
388 *
389 * - exceed_limit_bd_pkt_cnt
390 * Total number of exceeding the hardware limited bd which process
391 * a packet needed bd numbers.
392 *
393 * - exceed_limit_bd_reassem_fail
394 * Total number of exceeding the hardware limited bd fail which
395 * process a packet needed bd numbers and reassemble fail.
396 *
397 * - unsupported_tunnel_pkt_cnt
398 * Total number of unsupported tunnel packet. The unsupported tunnel
399 * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet
400 * with MPLS-in-UDP RFC 7510 header.
401 *
402 * - queue_full_cnt
403 * Total count which the available bd numbers in current bd queue is
404 * less than the bd numbers with the pkt process needed.
405 *
406 * - pkt_padding_fail_cnt
407 * Total count which the packet length is less than minimum packet
408 * length(struct hns3_tx_queue::min_tx_pkt_len) supported by
409 * hardware in Tx direction and fail to be appended with 0.
410 */
411 struct hns3_tx_dfx_stats {
412 uint64_t over_length_pkt_cnt;
413 uint64_t exceed_limit_bd_pkt_cnt;
414 uint64_t exceed_limit_bd_reassem_fail;
415 uint64_t unsupported_tunnel_pkt_cnt;
416 uint64_t queue_full_cnt;
417 uint64_t pkt_padding_fail_cnt;
418 };
419
420 struct hns3_tx_queue {
421 /* The io_tail_reg is write-only if working in tx push mode */
422 volatile void *io_tail_reg;
423 struct hns3_desc *tx_ring;
424 struct hns3_entry *sw_ring;
425
426 uint16_t nb_tx_desc;
427 /*
428 * index of next BD whose corresponding rte_mbuf can be released by
429 * driver.
430 */
431 uint16_t next_to_clean;
432 /* index of next BD to be filled by driver to send packet */
433 uint16_t next_to_use;
434 /* num of remaining BDs ready to be filled by driver to send packet */
435 uint16_t tx_bd_ready;
436
437 /* threshold for free tx buffer if available BDs less than this value */
438 uint16_t tx_free_thresh;
439
440 /*
441 * The minimum length of the packet supported by hardware in the Tx
442 * direction.
443 */
444 uint8_t min_tx_pkt_len;
445
446 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
447
448 /*
449 * tso mode.
450 * value range:
451 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
452 *
453 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
454 * In this mode, because of the hardware constraint, network driver
455 * software need erase the L4 len value of the TCP pseudo header
456 * and recalculate the TCP pseudo header checksum of packets that
457 * need TSO.
458 *
459 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
460 * In this mode, hardware support recalculate the TCP pseudo header
461 * checksum of packets that need TSO, so network driver software
462 * not need to recalculate it.
463 */
464 uint16_t tso_mode:1;
465 /*
466 * udp checksum mode.
467 * value range:
468 * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE
469 *
470 * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE
471 * In this mode, HW can not do checksum for special UDP port like
472 * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel
473 * packets without the RTE_MBUF_F_TX_TUNEL_MASK in the mbuf. So, PMD need
474 * do the checksum for these packets to avoid a checksum error.
475 *
476 * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE
477 * In this mode, HW does not have the preceding problems and can
478 * directly calculate the checksum of these UDP packets.
479 */
480 uint16_t udp_cksum_mode:1;
481
482 uint16_t simple_bd_enable:1;
483 uint16_t tx_push_enable:1; /* check whether the tx push is enabled */
484 /*
485 * Indicate whether add the vlan_tci of the mbuf to the inner VLAN field
486 * of Tx BD. Because the outer VLAN will always be the PVID when the
487 * PVID is set and for some version of hardware network engine whose
488 * vlan mode is HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920, the
489 * PVID will overwrite the outer VLAN field of Tx BD. For the hardware
490 * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,
491 * such as kunpeng 930, if the PVID is set, the hardware will shift the
492 * VLAN field automatically. So, PMD does not need to do
493 * PVID-related operations in Tx. And pvid_sw_shift_en will be false at
494 * this point.
495 */
496 uint16_t pvid_sw_shift_en:1;
497 /* check whether the mbuf fast free offload is enabled */
498 uint16_t mbuf_fast_free_en:1;
499
500 /*
501 * For better performance in tx datapath, releasing mbuf in batches is
502 * required.
503 * Only checking the VLD bit of the last descriptor in a batch of the
504 * thresh descriptors does not mean that these descriptors are all sent
505 * by hardware successfully. So we need to check that the VLD bits of
506 * all descriptors are cleared. and then free all mbufs in the batch.
507 * - tx_rs_thresh
508 * Number of mbufs released at a time.
509 *
510 * - free
511 * Tx mbuf free array used for preserving temporarily address of mbuf
512 * released back to mempool, when releasing mbuf in batches.
513 */
514 uint16_t tx_rs_thresh;
515 struct rte_mbuf **free;
516
517 struct hns3_tx_basic_stats basic_stats;
518 struct hns3_tx_dfx_stats dfx_stats;
519
520 /*
521 * The following fields are not accessed in the I/O path, so they are
522 * placed at the end.
523 */
524 void *io_base __rte_cache_aligned;
525 struct hns3_adapter *hns;
526 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
527 const struct rte_memzone *mz;
528
529 uint16_t port_id;
530 uint16_t queue_id;
531
532 bool configured; /* indicate if tx queue has been configured */
533 bool tx_deferred_start; /* don't start this queue in dev start */
534 bool enabled; /* indicate if Tx queue has been enabled */
535 };
536
537 #define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
538 ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
539
540 struct hns3_queue_info {
541 const char *type; /* point to queue memory name */
542 const char *ring_name; /* point to hardware ring name */
543 uint16_t idx;
544 uint16_t nb_desc;
545 unsigned int socket_id;
546 };
547
548 #define HNS3_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_OUTER_UDP_CKSUM | \
549 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \
550 RTE_MBUF_F_TX_IP_CKSUM | \
551 RTE_MBUF_F_TX_TCP_SEG | \
552 RTE_MBUF_F_TX_L4_MASK)
553
554 enum hns3_cksum_status {
555 HNS3_CKSUM_NONE = 0,
556 HNS3_L3_CKSUM_ERR = 1,
557 HNS3_L4_CKSUM_ERR = 2,
558 HNS3_OUTER_L3_CKSUM_ERR = 4,
559 HNS3_OUTER_L4_CKSUM_ERR = 8
560 };
561
562 extern uint64_t hns3_timestamp_rx_dynflag;
563 extern int hns3_timestamp_dynfield_offset;
564
565 static inline void
hns3_rx_set_cksum_flag(struct hns3_rx_queue * rxq,struct rte_mbuf * rxm,uint32_t l234_info)566 hns3_rx_set_cksum_flag(struct hns3_rx_queue *rxq,
567 struct rte_mbuf *rxm,
568 uint32_t l234_info)
569 {
570 #define HNS3_RXD_CKSUM_ERR_MASK (BIT(HNS3_RXD_L3E_B) | \
571 BIT(HNS3_RXD_L4E_B) | \
572 BIT(HNS3_RXD_OL3E_B) | \
573 BIT(HNS3_RXD_OL4E_B))
574
575 if (likely((l234_info & HNS3_RXD_CKSUM_ERR_MASK) == 0)) {
576 rxm->ol_flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
577 return;
578 }
579
580 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
581 rxm->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
582 rxq->dfx_stats.l3_csum_errors++;
583 } else {
584 rxm->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
585 }
586
587 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
588 rxm->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
589 rxq->dfx_stats.l4_csum_errors++;
590 } else {
591 rxm->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
592 }
593
594 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B)))
595 rxq->dfx_stats.ol3_csum_errors++;
596
597 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
598 rxm->ol_flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
599 rxq->dfx_stats.ol4_csum_errors++;
600 }
601 }
602
603 static inline int
hns3_handle_bdinfo(struct hns3_rx_queue * rxq,struct rte_mbuf * rxm,uint32_t bd_base_info,uint32_t l234_info)604 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
605 uint32_t bd_base_info, uint32_t l234_info)
606 {
607 #define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
608 BIT(HNS3_RXD_TRUNCATE_B))
609
610 /*
611 * If packet len bigger than mtu when recv with no-scattered algorithm,
612 * the first n bd will without FE bit, we need process this situation.
613 * Note: we don't need add statistic counter because latest BD which
614 * with FE bit will mark HNS3_RXD_L2E_B bit.
615 */
616 if (unlikely((bd_base_info & BIT(HNS3_RXD_FE_B)) == 0))
617 return -EINVAL;
618
619 if (unlikely((l234_info & L2E_TRUNC_ERR_FLAG) || rxm->pkt_len == 0)) {
620 if (l234_info & BIT(HNS3_RXD_L2E_B))
621 rxq->err_stats.l2_errors++;
622 else
623 rxq->err_stats.pkt_len_errors++;
624 return -EINVAL;
625 }
626
627 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
628 hns3_rx_set_cksum_flag(rxq, rxm, l234_info);
629
630 return 0;
631 }
632
633 static inline uint32_t
hns3_rx_calc_ptype(struct hns3_rx_queue * rxq,const uint32_t l234_info,const uint32_t ol_info)634 hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,
635 const uint32_t ol_info)
636 {
637 const struct hns3_ptype_table * const ptype_tbl = rxq->ptype_tbl;
638 uint32_t ol3id, ol4id;
639 uint32_t l3id, l4id;
640 uint32_t ptype;
641
642 if (rxq->ptype_en) {
643 ptype = hns3_get_field(ol_info, HNS3_RXD_PTYPE_M,
644 HNS3_RXD_PTYPE_S);
645 return ptype_tbl->ptype[ptype];
646 }
647
648 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
649 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
650 l3id = hns3_get_field(l234_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
651 l4id = hns3_get_field(l234_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
652
653 if (unlikely(ptype_tbl->ol4table[ol4id]))
654 return ptype_tbl->inner_l3table[l3id] |
655 ptype_tbl->inner_l4table[l4id] |
656 ptype_tbl->ol3table[ol3id] |
657 ptype_tbl->ol4table[ol4id];
658 else
659 return ptype_tbl->l3table[l3id] | ptype_tbl->l4table[l4id];
660 }
661
662 /*
663 * If enable using Tx push feature and also device support it, then use quick
664 * doorbell (bar45) to inform the hardware.
665 *
666 * The other cases (such as: device don't support or user don't enable using)
667 * then use normal doorbell (bar23) to inform the hardware.
668 */
669 static inline void
hns3_write_txq_tail_reg(struct hns3_tx_queue * txq,uint32_t value)670 hns3_write_txq_tail_reg(struct hns3_tx_queue *txq, uint32_t value)
671 {
672 rte_io_wmb();
673 if (txq->tx_push_enable)
674 rte_write64_relaxed(rte_cpu_to_le_32(value), txq->io_tail_reg);
675 else
676 rte_write32_relaxed(rte_cpu_to_le_32(value), txq->io_tail_reg);
677 }
678
679 void hns3_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id);
680 void hns3_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id);
681 void hns3_free_all_queues(struct rte_eth_dev *dev);
682 int hns3_reset_all_tqps(struct hns3_adapter *hns);
683 void hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en);
684 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
685 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
686 void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
687 int hns3_init_queues(struct hns3_adapter *hns, bool reset_queue);
688 void hns3_start_tqps(struct hns3_hw *hw);
689 void hns3_stop_tqps(struct hns3_hw *hw);
690 int hns3_rxq_iterate(struct rte_eth_dev *dev,
691 int (*callback)(struct hns3_rx_queue *, void *), void *arg);
692 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
693 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
694 unsigned int socket, const struct rte_eth_rxconf *conf,
695 struct rte_mempool *mp);
696 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
697 unsigned int socket, const struct rte_eth_txconf *conf);
698 uint32_t hns3_rx_queue_count(void *rx_queue);
699 int hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
700 int hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
701 int hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
702 int hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
703 uint16_t hns3_recv_pkts_simple(void *rx_queue, struct rte_mbuf **rx_pkts,
704 uint16_t nb_pkts);
705 uint16_t hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
706 uint16_t nb_pkts);
707 uint16_t hns3_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
708 uint16_t nb_pkts);
709 uint16_t hns3_recv_pkts_vec_sve(void *rx_queue, struct rte_mbuf **rx_pkts,
710 uint16_t nb_pkts);
711 int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
712 __rte_unused uint16_t queue_id,
713 struct rte_eth_burst_mode *mode);
714 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
715 uint16_t nb_pkts);
716 uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
717 uint16_t nb_pkts);
718 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
719 uint16_t nb_pkts);
720 uint16_t hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
721 uint16_t nb_pkts);
722 uint16_t hns3_xmit_pkts_vec_sve(void *tx_queue, struct rte_mbuf **tx_pkts,
723 uint16_t nb_pkts);
724 int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
725 __rte_unused uint16_t queue_id,
726 struct rte_eth_burst_mode *mode);
727 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
728 void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
729 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
730 eth_tx_burst_t hns3_get_tx_function(struct rte_eth_dev *dev,
731 eth_tx_prep_t *prep);
732
733 uint32_t hns3_get_tqp_intr_reg_offset(uint16_t tqp_intr_id);
734 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
735 uint8_t gl_idx, uint16_t gl_value);
736 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
737 uint16_t rl_value);
738 void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,
739 uint16_t ql_value);
740 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
741 uint16_t nb_tx_q);
742 int hns3_config_gro(struct hns3_hw *hw, bool en);
743 int hns3_restore_gro_conf(struct hns3_hw *hw);
744 void hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw);
745 void hns3_rx_scattered_reset(struct rte_eth_dev *dev);
746 void hns3_rx_scattered_calc(struct rte_eth_dev *dev);
747 int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
748 int hns3_tx_check_vec_support(struct rte_eth_dev *dev);
749 void hns3_rxq_vec_setup(struct hns3_rx_queue *rxq);
750 void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
751 struct rte_eth_rxq_info *qinfo);
752 void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
753 struct rte_eth_txq_info *qinfo);
754 uint32_t hns3_get_tqp_reg_offset(uint16_t idx);
755 int hns3_start_all_txqs(struct rte_eth_dev *dev);
756 int hns3_start_all_rxqs(struct rte_eth_dev *dev);
757 void hns3_stop_all_txqs(struct rte_eth_dev *dev);
758 void hns3_restore_tqp_enable_state(struct hns3_hw *hw);
759 int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt);
760 void hns3_enable_rxd_adv_layout(struct hns3_hw *hw);
761 int hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
762 int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
763 void hns3_tx_push_init(struct rte_eth_dev *dev);
764 void hns3_stop_tx_datapath(struct rte_eth_dev *dev);
765 void hns3_start_tx_datapath(struct rte_eth_dev *dev);
766
767 #endif /* _HNS3_RXTX_H_ */
768