1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2021 NXP
5 *
6 */
7
8 #ifndef _DPAA2_HW_PVT_H_
9 #define _DPAA2_HW_PVT_H_
10
11 #include <rte_eventdev.h>
12 #include <dpaax_iova_table.h>
13
14 #include <mc/fsl_mc_sys.h>
15 #include <fsl_qbman_portal.h>
16
17 #ifndef false
18 #define false 0
19 #endif
20 #ifndef true
21 #define true 1
22 #endif
23 #define lower_32_bits(x) ((uint32_t)(x))
24 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
25
26 #ifndef VLAN_TAG_SIZE
27 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */
28 #endif
29
30 /* Maximum number of slots available in TX ring */
31 #define MAX_TX_RING_SLOTS 32
32 #define MAX_EQ_RESP_ENTRIES (MAX_TX_RING_SLOTS + 1)
33
34 /* Maximum number of slots available in RX ring */
35 #define DPAA2_EQCR_RING_SIZE 8
36 /* Maximum number of slots available in RX ring on LX2 */
37 #define DPAA2_LX2_EQCR_RING_SIZE 32
38
39 /* Maximum number of slots available in RX ring */
40 #define DPAA2_DQRR_RING_SIZE 16
41 /* Maximum number of slots available in RX ring on LX2 */
42 #define DPAA2_LX2_DQRR_RING_SIZE 32
43
44 /* EQCR shift to get EQCR size (2 >> 3) = 8 for LS2/LS2 */
45 #define DPAA2_EQCR_SHIFT 3
46 /* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */
47 #define DPAA2_LX2_EQCR_SHIFT 5
48
49 /* Flag to determine an ordered queue mbuf */
50 #define DPAA2_ENQUEUE_FLAG_ORP (1ULL << 30)
51 /* ORP ID shift and mask */
52 #define DPAA2_EQCR_OPRID_SHIFT 16
53 #define DPAA2_EQCR_OPRID_MASK 0x3FFF0000
54 /* Sequence number shift and mask */
55 #define DPAA2_EQCR_SEQNUM_SHIFT 0
56 #define DPAA2_EQCR_SEQNUM_MASK 0x0000FFFF
57
58 #define DPAA2_SWP_CENA_REGION 0
59 #define DPAA2_SWP_CINH_REGION 1
60 #define DPAA2_SWP_CENA_MEM_REGION 2
61
62 #define DPAA2_MAX_TX_RETRY_COUNT 10000
63
64 #define MC_PORTAL_INDEX 0
65 #define NUM_DPIO_REGIONS 2
66 #define NUM_DQS_PER_QUEUE 2
67
68 /* Maximum release/acquire from QBMAN */
69 #define DPAA2_MBUF_MAX_ACQ_REL 7
70
71 #define DPAA2_MEMPOOL_OPS_NAME "dpaa2"
72
73 #define MAX_BPID 256
74 #define DPAA2_MBUF_HW_ANNOTATION 64
75 #define DPAA2_FD_PTA_SIZE 0
76
77 /* we will re-use the HEADROOM for annotation in RX */
78 #define DPAA2_HW_BUF_RESERVE 0
79 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
80
81 #define DPAA2_DPCI_MAX_QUEUES 2
82
83 struct dpaa2_queue;
84
85 struct eqresp_metadata {
86 struct dpaa2_queue *dpaa2_q;
87 struct rte_mempool *mp;
88 };
89
90 #define DPAA2_PORTAL_DEQUEUE_DEPTH 32
91 struct dpaa2_portal_dqrr {
92 struct rte_mbuf *mbuf[DPAA2_PORTAL_DEQUEUE_DEPTH];
93 uint64_t dqrr_held;
94 uint8_t dqrr_size;
95 };
96
97 struct dpaa2_dpio_dev {
98 TAILQ_ENTRY(dpaa2_dpio_dev) next;
99 /**< Pointer to Next device instance */
100 uint16_t index; /**< Index of a instance in the list */
101 rte_atomic16_t ref_count;
102 /**< How many thread contexts are sharing this.*/
103 uint16_t eqresp_ci;
104 uint16_t eqresp_pi;
105 struct qbman_result *eqresp;
106 struct eqresp_metadata *eqresp_meta;
107 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
108 uint16_t token;
109 struct qbman_swp *sw_portal; /** SW portal object */
110 const struct qbman_result *dqrr[4];
111 /**< DQRR Entry for this SW portal */
112 void *mc_portal; /**< MC Portal for configuring this device */
113 uintptr_t qbman_portal_ce_paddr;
114 /**< Physical address of Cache Enabled Area */
115 uintptr_t ce_size; /**< Size of the CE region */
116 uintptr_t qbman_portal_ci_paddr;
117 /**< Physical address of Cache Inhibit Area */
118 uintptr_t ci_size; /**< Size of the CI region */
119 struct rte_intr_handle *intr_handle; /* Interrupt related info */
120 int32_t epoll_fd; /**< File descriptor created for interrupt polling */
121 int32_t hw_id; /**< An unique ID of this DPIO device instance */
122 struct dpaa2_portal_dqrr dpaa2_held_bufs;
123 };
124
125 struct dpaa2_dpbp_dev {
126 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
127 /**< Pointer to Next device instance */
128 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
129 uint16_t token;
130 rte_atomic16_t in_use;
131 uint32_t dpbp_id; /*HW ID for DPBP object */
132 };
133
134 struct queue_storage_info_t {
135 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
136 struct qbman_result *active_dqs;
137 uint8_t active_dpio_id;
138 uint8_t toggle;
139 uint8_t last_num_pkts;
140 };
141
142 struct dpaa2_queue;
143
144 typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
145 const struct qbman_fd *fd,
146 const struct qbman_result *dq,
147 struct dpaa2_queue *rxq,
148 struct rte_event *ev);
149
150 typedef void (dpaa2_queue_cb_eqresp_free_t)(uint16_t eqresp_ci,
151 struct dpaa2_queue *dpaa2_q);
152
153 struct dpaa2_queue {
154 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
155 union {
156 struct rte_eth_dev_data *eth_data;
157 struct rte_cryptodev_data *crypto_data;
158 };
159 uint32_t fqid; /*!< Unique ID of this queue */
160 uint16_t flow_id; /*!< To be used by DPAA2 framework */
161 uint8_t tc_index; /*!< traffic class identifier */
162 uint8_t cgid; /*! < Congestion Group id for this queue */
163 uint64_t rx_pkts;
164 uint64_t tx_pkts;
165 uint64_t err_pkts;
166 union {
167 struct queue_storage_info_t *q_storage;
168 struct qbman_result *cscn;
169 };
170 struct rte_event ev;
171 dpaa2_queue_cb_dqrr_t *cb;
172 dpaa2_queue_cb_eqresp_free_t *cb_eqresp_free;
173 struct dpaa2_bp_info *bp_array;
174 /*to store tx_conf_queue corresponding to tx_queue*/
175 struct dpaa2_queue *tx_conf_queue;
176 int32_t eventfd; /*!< Event Fd of this queue */
177 uint16_t nb_desc;
178 uint16_t resv;
179 uint64_t offloads;
180 uint64_t lpbk_cntx;
181 } __rte_cache_aligned;
182
183 struct swp_active_dqs {
184 struct qbman_result *global_active_dqs;
185 uint64_t reserved[7];
186 };
187
188 #define NUM_MAX_SWP 64
189
190 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
191
192 /**
193 * A structure describing a DPAA2 container.
194 */
195 struct dpaa2_dprc_dev {
196 TAILQ_ENTRY(dpaa2_dprc_dev) next;
197 /**< Pointer to Next device instance */
198 const char *name;
199 struct fsl_mc_io dprc; /** handle to DPRC portal object */
200 uint16_t token;
201 uint32_t dprc_id; /*HW ID for DPRC object */
202 };
203
204 struct dpaa2_dpci_dev {
205 TAILQ_ENTRY(dpaa2_dpci_dev) next;
206 /**< Pointer to Next device instance */
207 struct fsl_mc_io dpci; /** handle to DPCI portal object */
208 uint16_t token;
209 rte_atomic16_t in_use;
210 uint32_t dpci_id; /*HW ID for DPCI object */
211 struct dpaa2_queue rx_queue[DPAA2_DPCI_MAX_QUEUES];
212 struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
213 };
214
215 struct dpaa2_dpcon_dev {
216 TAILQ_ENTRY(dpaa2_dpcon_dev) next;
217 struct fsl_mc_io dpcon;
218 uint16_t token;
219 rte_atomic16_t in_use;
220 uint32_t dpcon_id;
221 uint16_t qbman_ch_id;
222 uint8_t num_priorities;
223 uint8_t channel_index;
224 };
225
226 /* Refer to Table 7-3 in SEC BG */
227 #define QBMAN_FLE_WORD4_FMT_SBF 0x0 /* Single buffer frame */
228 #define QBMAN_FLE_WORD4_FMT_SGE 0x2 /* Scatter gather frame */
229
230 struct qbman_fle_word4 {
231 uint32_t bpid:14; /* Frame buffer pool ID */
232 uint32_t ivp:1; /* Invalid Pool ID. */
233 uint32_t bmt:1; /* Bypass Memory Translation */
234 uint32_t offset:12; /* Frame offset */
235 uint32_t fmt:2; /* Frame Format */
236 uint32_t sl:1; /* Short Length */
237 uint32_t f:1; /* Final bit */
238 };
239
240 struct qbman_fle {
241 uint32_t addr_lo;
242 uint32_t addr_hi;
243 uint32_t length;
244 /* FMT must be 00, MSB is final bit */
245 union {
246 uint32_t fin_bpid_offset;
247 struct qbman_fle_word4 word4;
248 };
249 uint32_t frc;
250 uint32_t reserved[3]; /* Not used currently */
251 };
252
253 struct qbman_sge {
254 uint32_t addr_lo;
255 uint32_t addr_hi;
256 uint32_t length;
257 uint32_t fin_bpid_offset;
258 };
259
260 /* There are three types of frames: Single, Scatter Gather and Frame Lists */
261 enum qbman_fd_format {
262 qbman_fd_single = 0,
263 qbman_fd_list,
264 qbman_fd_sg
265 };
266 /*Macros to define operations on FD*/
267 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
268 (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \
269 (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
270 } while (0)
271 #define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
272 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
273 #define DPAA2_SET_ONLY_FD_BPID(fd, bpid) \
274 ((fd)->simple.bpid_offset = bpid)
275 #define DPAA2_SET_FD_IVP(fd) (((fd)->simple.bpid_offset |= 0x00004000))
276 #define DPAA2_SET_FD_OFFSET(fd, offset) \
277 (((fd)->simple.bpid_offset |= (uint32_t)(offset) << 16))
278 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) \
279 ((fd)->simple.frc = (0x80000000 | (len)))
280 #define DPAA2_GET_FD_FRC_PARSE_SUM(fd) \
281 ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16))
282 #define DPAA2_RESET_FD_FRC(fd) ((fd)->simple.frc = 0)
283 #define DPAA2_SET_FD_FRC(fd, _frc) ((fd)->simple.frc = _frc)
284 #define DPAA2_RESET_FD_CTRL(fd) ((fd)->simple.ctrl = 0)
285
286 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
287
288 #define DPAA2_RESET_FD_FLC(fd) do { \
289 (fd)->simple.flc_lo = 0; \
290 (fd)->simple.flc_hi = 0; \
291 } while (0)
292
293 #define DPAA2_SET_FD_FLC(fd, addr) do { \
294 (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \
295 (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
296 } while (0)
297 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
298 #define DPAA2_GET_FLE_ADDR(fle) \
299 (size_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
300 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
301 (fle)->addr_lo = lower_32_bits((size_t)addr); \
302 (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
303 } while (0)
304 #define DPAA2_GET_FLE_CTXT(fle) \
305 ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0])
306 #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
307 (fle)->reserved[0] = lower_32_bits((size_t)addr); \
308 (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
309 } while (0)
310 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
311 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
312 #define DPAA2_SET_FLE_LEN(fle, len) ((fle)->length = len)
313 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid)
314 #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
315 #define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31)
316 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
317 #define DPAA2_SET_FLE_BMT(fle) (((fle)->fin_bpid_offset |= 0x00008000))
318 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
319 ((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
320 #define DPAA2_GET_FD_ADDR(fd) \
321 (((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
322
323 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
324 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
325 #define DPAA2_GET_FD_IVP(fd) (((fd)->simple.bpid_offset & 0x00004000) >> 14)
326 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
327 #define DPAA2_GET_FD_FRC(fd) ((fd)->simple.frc)
328 #define DPAA2_GET_FD_FLC(fd) \
329 (((uint64_t)((fd)->simple.flc_hi) << 32) + (fd)->simple.flc_lo)
330 #define DPAA2_GET_FD_ERR(fd) ((fd)->simple.ctrl & 0x000000FF)
331 #define DPAA2_GET_FD_FA_ERR(fd) ((fd)->simple.ctrl & 0x00000040)
332 #define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16)
333 #define DPAA2_SET_FLE_SG_EXT(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 29)
334 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
335 (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
336
337 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
338 ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size)))
339
340 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
341
342 #define DPAA2_FD_SET_FORMAT(fd, format) do { \
343 (fd)->simple.bpid_offset &= 0xCFFFFFFF; \
344 (fd)->simple.bpid_offset |= (uint32_t)format << 28; \
345 } while (0)
346 #define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3)
347
348 #define DPAA2_SG_SET_FORMAT(sg, format) do { \
349 (sg)->fin_bpid_offset &= 0xCFFFFFFF; \
350 (sg)->fin_bpid_offset |= (uint32_t)format << 28; \
351 } while (0)
352
353 #define DPAA2_SG_SET_FINAL(sg, fin) do { \
354 (sg)->fin_bpid_offset &= 0x7FFFFFFF; \
355 (sg)->fin_bpid_offset |= (uint32_t)fin << 31; \
356 } while (0)
357 #define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31))
358 /* Only Enqueue Error responses will be
359 * pushed on FQID_ERR of Enqueue FQ
360 */
361 #define DPAA2_EQ_RESP_ERR_FQ 0
362 /* All Enqueue responses will be pushed on address
363 * set with qbman_eq_desc_set_response
364 */
365 #define DPAA2_EQ_RESP_ALWAYS 1
366
367 /* Various structures representing contiguous memory maps */
368 struct dpaa2_memseg {
369 TAILQ_ENTRY(dpaa2_memseg) next;
370 char *vaddr;
371 rte_iova_t iova;
372 size_t len;
373 };
374
375 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
376 extern uint8_t dpaa2_virt_mode;
377 static void *dpaa2_mem_ptov(phys_addr_t paddr) __rte_unused;
378
dpaa2_mem_ptov(phys_addr_t paddr)379 static void *dpaa2_mem_ptov(phys_addr_t paddr)
380 {
381 void *va;
382
383 if (dpaa2_virt_mode)
384 return (void *)(size_t)paddr;
385
386 va = (void *)dpaax_iova_table_get_va(paddr);
387 if (likely(va != NULL))
388 return va;
389
390 /* If not, Fallback to full memseg list searching */
391 va = rte_mem_iova2virt(paddr);
392
393 return va;
394 }
395
396 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __rte_unused;
397
dpaa2_mem_vtop(uint64_t vaddr)398 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
399 {
400 const struct rte_memseg *memseg;
401
402 if (dpaa2_virt_mode)
403 return vaddr;
404
405 memseg = rte_mem_virt2memseg((void *)(uintptr_t)vaddr, NULL);
406 if (memseg)
407 return memseg->iova + RTE_PTR_DIFF(vaddr, memseg->addr);
408 return (size_t)NULL;
409 }
410
411 /**
412 * When we are using Physical addresses as IO Virtual Addresses,
413 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
414 * wherever required.
415 * These routines are called with help of below MACRO's
416 */
417
418 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_iova)
419
420 /**
421 * macro to convert Virtual address to IOVA
422 */
423 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr))
424
425 /**
426 * macro to convert IOVA to Virtual address
427 */
428 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova))
429
430 /**
431 * macro to convert modify the memory containing IOVA to Virtual address
432 */
433 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
434 {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); }
435
436 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
437
438 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
439 #define DPAA2_VADDR_TO_IOVA(_vaddr) (phys_addr_t)(_vaddr)
440 #define DPAA2_IOVA_TO_VADDR(_iova) (void *)(_iova)
441 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
442
443 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
444
445 static inline
check_swp_active_dqs(uint16_t dpio_index)446 int check_swp_active_dqs(uint16_t dpio_index)
447 {
448 if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
449 return 1;
450 return 0;
451 }
452
453 static inline
clear_swp_active_dqs(uint16_t dpio_index)454 void clear_swp_active_dqs(uint16_t dpio_index)
455 {
456 rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
457 }
458
459 static inline
get_swp_active_dqs(uint16_t dpio_index)460 struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
461 {
462 return rte_global_active_dqs_list[dpio_index].global_active_dqs;
463 }
464
465 static inline
set_swp_active_dqs(uint16_t dpio_index,struct qbman_result * dqs)466 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
467 {
468 rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
469 }
470
471 __rte_internal
472 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
473
474 __rte_internal
475 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
476
477 __rte_internal
478 int dpaa2_dpbp_supported(void);
479
480 __rte_internal
481 struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
482
483 __rte_internal
484 void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);
485
486 /* Global MCP pointer */
487 __rte_internal
488 void *dpaa2_get_mcp_ptr(int portal_idx);
489
490 #endif
491