1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
5 * Copyright (c) 2004-05 Vinod Kashyap.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 /*
33 * AMCC'S 3ware driver for 9000 series storage controllers.
34 *
35 * Author: Vinod Kashyap
36 * Modifications by: Adam Radford
37 * Modifications by: Manjunath Ranganathaiah
38 */
39
40
41
42 #ifndef TW_OSL_H
43
44 #define TW_OSL_H
45
46
47 /*
48 * OS Layer internal macros, structures and functions.
49 */
50
51
52 #define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller"
53
54 #define TW_OSLI_MALLOC_CLASS M_TWA
55 #define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS
56 /* Reserve two command packets. One for ioctls and one for AENs */
57 #define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2)
58 #define TW_OSLI_MAX_NUM_AENS 0x100
59
60 /* Possible values of req->state. */
61 #define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */
62 #define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */
63 #define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */
64 #define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */
65
66 /* Possible values of req->flags. */
67 #define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */
68 #define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */
69 #define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned,
70 have to copy to/from private buffer */
71 #define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */
72 #define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned
73 EINPROGRESS */
74 #define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */
75 #define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */
76 #define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */
77 #define TW_OSLI_REQ_FLAGS_CCB (1<<8) /* req is ccb. */
78
79
80 #ifdef TW_OSL_DEBUG
81 struct tw_osli_q_stats {
82 TW_UINT32 cur_len; /* current # of items in q */
83 TW_UINT32 max_len; /* max value reached by q_length */
84 };
85 #endif /* TW_OSL_DEBUG */
86
87
88 /* Queues of OSL internal request context packets. */
89 #define TW_OSLI_FREE_Q 0 /* free q */
90 #define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */
91 #define TW_OSLI_Q_COUNT 2 /* total number of queues */
92
93 /* Driver's request packet. */
94 struct tw_osli_req_context {
95 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */
96 struct mtx ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */
97 struct mtx *ioctl_wake_timeout_lock;/* ptr to above lock */
98 struct twa_softc *ctlr; /* ptr to OSL's controller context */
99 TW_VOID *data; /* ptr to data being passed to CL */
100 TW_UINT32 length; /* length of buf being passed to CL */
101 TW_UINT64 deadline;/* request timeout (in absolute time) */
102
103 /*
104 * ptr to, and length of data passed to us from above, in case a buffer
105 * copy was done due to non-compliance to alignment requirements
106 */
107 TW_VOID *real_data;
108 TW_UINT32 real_length;
109
110 TW_UINT32 state; /* request state */
111 TW_UINT32 flags; /* request flags */
112
113 /* error encountered before request submission to CL */
114 TW_UINT32 error_code;
115
116 /* ptr to orig req for use during callback */
117 TW_VOID *orig_req;
118
119 struct tw_cl_link link; /* to link this request in a list */
120 bus_dmamap_t dma_map;/* DMA map for data */
121 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */
122 };
123
124
125 /* Per-controller structure. */
126 struct twa_softc {
127 struct tw_cl_ctlr_handle ctlr_handle;
128 struct tw_osli_req_context *req_ctx_buf;
129
130 /* Controller state. */
131 TW_UINT8 open;
132 TW_UINT32 flags;
133
134 TW_INT32 device_id;
135 TW_UINT32 alignment;
136 TW_UINT32 sg_size_factor;
137
138 TW_VOID *non_dma_mem;
139 TW_VOID *dma_mem;
140 TW_UINT64 dma_mem_phys;
141
142 /* Request queues and arrays. */
143 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
144
145 struct task deferred_intr_callback;/* taskqueue function */
146 struct mtx io_lock_handle;/* general purpose lock */
147 struct mtx *io_lock;/* ptr to general purpose lock */
148 struct mtx q_lock_handle; /* queue manipulation lock */
149 struct mtx *q_lock;/* ptr to queue manipulation lock */
150 struct mtx sim_lock_handle;/* sim lock shared with cam */
151 struct mtx *sim_lock;/* ptr to sim lock */
152
153 struct callout watchdog_callout[2]; /* For command timeout */
154 TW_UINT32 watchdog_index;
155
156 #ifdef TW_OSL_DEBUG
157 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */
158 #endif /* TW_OSL_DEBUG */
159
160 device_t bus_dev; /* bus device */
161 struct cdev *ctrl_dev; /* control device */
162 struct resource *reg_res; /* register interface window */
163 TW_INT32 reg_res_id; /* register resource id */
164 bus_space_handle_t bus_handle; /* bus space handle */
165 bus_space_tag_t bus_tag; /* bus space tag */
166 bus_dma_tag_t parent_tag; /* parent DMA tag */
167 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */
168 bus_dma_tag_t dma_tag; /* data buffer DMA tag */
169 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
170 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
171 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
172 struct resource *irq_res; /* interrupt resource */
173 TW_INT32 irq_res_id; /* register resource id */
174 TW_VOID *intr_handle; /* interrupt handle */
175
176 struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */
177 struct sysctl_oid *sysctl_tree; /* sysctl oid */
178
179 struct cam_sim *sim; /* sim for this controller */
180 struct cam_path *path; /* peripheral, path, tgt, lun
181 associated with this controller */
182 };
183
184
185
186 /*
187 * Queue primitives.
188 */
189
190 #ifdef TW_OSL_DEBUG
191
192 #define TW_OSLI_Q_INIT(sc, q_type) do { \
193 (sc)->q_stats[q_type].cur_len = 0; \
194 (sc)->q_stats[q_type].max_len = 0; \
195 } while(0)
196
197
198 #define TW_OSLI_Q_INSERT(sc, q_type) do { \
199 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \
200 \
201 if (++(q_stats->cur_len) > q_stats->max_len) \
202 q_stats->max_len = q_stats->cur_len; \
203 } while(0)
204
205
206 #define TW_OSLI_Q_REMOVE(sc, q_type) \
207 (sc)->q_stats[q_type].cur_len--
208
209
210 #else /* TW_OSL_DEBUG */
211
212 #define TW_OSLI_Q_INIT(sc, q_index)
213 #define TW_OSLI_Q_INSERT(sc, q_index)
214 #define TW_OSLI_Q_REMOVE(sc, q_index)
215
216 #endif /* TW_OSL_DEBUG */
217
218
219
220 /* Initialize a queue of requests. */
221 static __inline TW_VOID
tw_osli_req_q_init(struct twa_softc * sc,TW_UINT8 q_type)222 tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type)
223 {
224 TW_CL_Q_INIT(&(sc->req_q_head[q_type]));
225 TW_OSLI_Q_INIT(sc, q_type);
226 }
227
228
229
230 /* Insert the given request at the head of the given queue (q_type). */
231 static __inline TW_VOID
tw_osli_req_q_insert_head(struct tw_osli_req_context * req,TW_UINT8 q_type)232 tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type)
233 {
234 mtx_lock_spin(req->ctlr->q_lock);
235 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link));
236 TW_OSLI_Q_INSERT(req->ctlr, q_type);
237 mtx_unlock_spin(req->ctlr->q_lock);
238 }
239
240
241
242 /* Insert the given request at the tail of the given queue (q_type). */
243 static __inline TW_VOID
tw_osli_req_q_insert_tail(struct tw_osli_req_context * req,TW_UINT8 q_type)244 tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type)
245 {
246 mtx_lock_spin(req->ctlr->q_lock);
247 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link));
248 TW_OSLI_Q_INSERT(req->ctlr, q_type);
249 mtx_unlock_spin(req->ctlr->q_lock);
250 }
251
252
253
254 /* Remove and return the request at the head of the given queue (q_type). */
255 static __inline struct tw_osli_req_context *
tw_osli_req_q_remove_head(struct twa_softc * sc,TW_UINT8 q_type)256 tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type)
257 {
258 struct tw_osli_req_context *req = NULL;
259 struct tw_cl_link *link;
260
261 mtx_lock_spin(sc->q_lock);
262 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) !=
263 TW_CL_NULL) {
264 req = TW_CL_STRUCT_HEAD(link,
265 struct tw_osli_req_context, link);
266 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link));
267 TW_OSLI_Q_REMOVE(sc, q_type);
268 }
269 mtx_unlock_spin(sc->q_lock);
270 return(req);
271 }
272
273
274
275 /* Remove the given request from the given queue (q_type). */
276 static __inline TW_VOID
tw_osli_req_q_remove_item(struct tw_osli_req_context * req,TW_UINT8 q_type)277 tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type)
278 {
279 mtx_lock_spin(req->ctlr->q_lock);
280 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link));
281 TW_OSLI_Q_REMOVE(req->ctlr, q_type);
282 mtx_unlock_spin(req->ctlr->q_lock);
283 }
284
285
286
287 #ifdef TW_OSL_DEBUG
288
289 extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL;
290
291 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \
292 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
293 device_printf(sc->bus_dev, "%s: " fmt "\n", \
294 __func__, ##args)
295
296
297 #define tw_osli_dbg_printf(dbg_level, fmt, args...) \
298 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
299 printf("%s: " fmt "\n", __func__, ##args)
300
301 #else /* TW_OSL_DEBUG */
302
303 #define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...)
304 #define tw_osli_dbg_printf(dbg_level, fmt, args...)
305
306 #endif /* TW_OSL_DEBUG */
307
308
309 /* For regular printing. */
310 #define twa_printf(sc, fmt, args...) \
311 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args)
312
313 /* For printing in the "consistent error reporting" format. */
314 #define tw_osli_printf(sc, err_specific_desc, args...) \
315 device_printf((sc)->bus_dev, \
316 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args)
317
318
319
320 #endif /* TW_OSL_H */
321