1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013-2014 Kevin Lo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 /*
33 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
34 */
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/condvar.h>
40 #include <sys/endian.h>
41 #include <sys/kernel.h>
42 #include <sys/lock.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
45 #include <sys/socket.h>
46 #include <sys/sysctl.h>
47 #include <sys/unistd.h>
48
49 #include <net/if.h>
50 #include <net/if_var.h>
51 #include <net/if_media.h>
52
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
55
56 #include <dev/usb/usb.h>
57 #include <dev/usb/usbdi.h>
58 #include <dev/usb/usbdi_util.h>
59 #include "usbdevs.h"
60
61 #define USB_DEBUG_VAR axge_debug
62 #include <dev/usb/usb_debug.h>
63 #include <dev/usb/usb_process.h>
64
65 #include <dev/usb/net/usb_ethernet.h>
66 #include <dev/usb/net/if_axgereg.h>
67
68 #include "miibus_if.h"
69
70 /*
71 * Various supported device vendors/products.
72 */
73
74 static const STRUCT_USB_HOST_ID axge_devs[] = {
75 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
76 AXGE_DEV(ASIX, AX88178A),
77 AXGE_DEV(ASIX, AX88179),
78 AXGE_DEV(BELKIN, B2B128),
79 AXGE_DEV(DLINK, DUB1312),
80 AXGE_DEV(LENOVO, GIGALAN),
81 AXGE_DEV(SITECOMEU, LN032),
82 #undef AXGE_DEV
83 };
84
85 static const struct {
86 uint8_t ctrl;
87 uint8_t timer_l;
88 uint8_t timer_h;
89 uint8_t size;
90 uint8_t ifg;
91 } __packed axge_bulk_size[] = {
92 { 7, 0x4f, 0x00, 0x12, 0xff },
93 { 7, 0x20, 0x03, 0x16, 0xff },
94 { 7, 0xae, 0x07, 0x18, 0xff },
95 { 7, 0xcc, 0x4c, 0x18, 0x08 }
96 };
97
98 /* prototypes */
99
100 static device_probe_t axge_probe;
101 static device_attach_t axge_attach;
102 static device_detach_t axge_detach;
103
104 static usb_callback_t axge_bulk_read_callback;
105 static usb_callback_t axge_bulk_write_callback;
106
107 static miibus_readreg_t axge_miibus_readreg;
108 static miibus_writereg_t axge_miibus_writereg;
109 static miibus_statchg_t axge_miibus_statchg;
110
111 static uether_fn_t axge_attach_post;
112 static uether_fn_t axge_init;
113 static uether_fn_t axge_stop;
114 static uether_fn_t axge_start;
115 static uether_fn_t axge_tick;
116 static uether_fn_t axge_rxfilter;
117
118 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
119 uint16_t, void *, int);
120 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
121 uint16_t, void *, int);
122 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t);
123 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
124 uint16_t);
125 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
126 uint8_t);
127 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
128 uint16_t, uint16_t);
129 static void axge_chip_init(struct axge_softc *);
130 static void axge_reset(struct axge_softc *);
131
132 static int axge_attach_post_sub(struct usb_ether *);
133 static int axge_ifmedia_upd(struct ifnet *);
134 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135 static int axge_ioctl(struct ifnet *, u_long, caddr_t);
136 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
137 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *,
138 unsigned int, unsigned int, uint32_t);
139 static void axge_csum_cfg(struct usb_ether *);
140
141 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
142
143 #ifdef USB_DEBUG
144 static int axge_debug = 0;
145
146 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
147 "USB axge");
148 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0,
149 "Debug level");
150 #endif
151
152 static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
153 [AXGE_BULK_DT_WR] = {
154 .type = UE_BULK,
155 .endpoint = UE_ADDR_ANY,
156 .direction = UE_DIR_OUT,
157 .frames = AXGE_N_FRAMES,
158 .bufsize = AXGE_N_FRAMES * MCLBYTES,
159 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
160 .callback = axge_bulk_write_callback,
161 .timeout = 10000, /* 10 seconds */
162 },
163 [AXGE_BULK_DT_RD] = {
164 .type = UE_BULK,
165 .endpoint = UE_ADDR_ANY,
166 .direction = UE_DIR_IN,
167 .bufsize = 65536,
168 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
169 .callback = axge_bulk_read_callback,
170 .timeout = 0, /* no timeout */
171 },
172 };
173
174 static device_method_t axge_methods[] = {
175 /* Device interface. */
176 DEVMETHOD(device_probe, axge_probe),
177 DEVMETHOD(device_attach, axge_attach),
178 DEVMETHOD(device_detach, axge_detach),
179
180 /* MII interface. */
181 DEVMETHOD(miibus_readreg, axge_miibus_readreg),
182 DEVMETHOD(miibus_writereg, axge_miibus_writereg),
183 DEVMETHOD(miibus_statchg, axge_miibus_statchg),
184
185 DEVMETHOD_END
186 };
187
188 static driver_t axge_driver = {
189 .name = "axge",
190 .methods = axge_methods,
191 .size = sizeof(struct axge_softc),
192 };
193
194 static devclass_t axge_devclass;
195
196 DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL);
197 DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL);
198 MODULE_DEPEND(axge, uether, 1, 1, 1);
199 MODULE_DEPEND(axge, usb, 1, 1, 1);
200 MODULE_DEPEND(axge, ether, 1, 1, 1);
201 MODULE_DEPEND(axge, miibus, 1, 1, 1);
202 MODULE_VERSION(axge, 1);
203 USB_PNP_HOST_INFO(axge_devs);
204
205 static const struct usb_ether_methods axge_ue_methods = {
206 .ue_attach_post = axge_attach_post,
207 .ue_attach_post_sub = axge_attach_post_sub,
208 .ue_start = axge_start,
209 .ue_init = axge_init,
210 .ue_stop = axge_stop,
211 .ue_tick = axge_tick,
212 .ue_setmulti = axge_rxfilter,
213 .ue_setpromisc = axge_rxfilter,
214 .ue_mii_upd = axge_ifmedia_upd,
215 .ue_mii_sts = axge_ifmedia_sts,
216 };
217
218 static int
axge_read_mem(struct axge_softc * sc,uint8_t cmd,uint16_t index,uint16_t val,void * buf,int len)219 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
220 uint16_t val, void *buf, int len)
221 {
222 struct usb_device_request req;
223
224 AXGE_LOCK_ASSERT(sc, MA_OWNED);
225
226 req.bmRequestType = UT_READ_VENDOR_DEVICE;
227 req.bRequest = cmd;
228 USETW(req.wValue, val);
229 USETW(req.wIndex, index);
230 USETW(req.wLength, len);
231
232 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
233 }
234
235 static void
axge_write_mem(struct axge_softc * sc,uint8_t cmd,uint16_t index,uint16_t val,void * buf,int len)236 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
237 uint16_t val, void *buf, int len)
238 {
239 struct usb_device_request req;
240
241 AXGE_LOCK_ASSERT(sc, MA_OWNED);
242
243 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
244 req.bRequest = cmd;
245 USETW(req.wValue, val);
246 USETW(req.wIndex, index);
247 USETW(req.wLength, len);
248
249 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
250 /* Error ignored. */
251 }
252 }
253
254 static uint8_t
axge_read_cmd_1(struct axge_softc * sc,uint8_t cmd,uint16_t reg)255 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg)
256 {
257 uint8_t val;
258
259 axge_read_mem(sc, cmd, 1, reg, &val, 1);
260 return (val);
261 }
262
263 static uint16_t
axge_read_cmd_2(struct axge_softc * sc,uint8_t cmd,uint16_t index,uint16_t reg)264 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
265 uint16_t reg)
266 {
267 uint8_t val[2];
268
269 axge_read_mem(sc, cmd, index, reg, &val, 2);
270 return (UGETW(val));
271 }
272
273 static void
axge_write_cmd_1(struct axge_softc * sc,uint8_t cmd,uint16_t reg,uint8_t val)274 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val)
275 {
276 axge_write_mem(sc, cmd, 1, reg, &val, 1);
277 }
278
279 static void
axge_write_cmd_2(struct axge_softc * sc,uint8_t cmd,uint16_t index,uint16_t reg,uint16_t val)280 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
281 uint16_t reg, uint16_t val)
282 {
283 uint8_t temp[2];
284
285 USETW(temp, val);
286 axge_write_mem(sc, cmd, index, reg, &temp, 2);
287 }
288
289 static int
axge_miibus_readreg(device_t dev,int phy,int reg)290 axge_miibus_readreg(device_t dev, int phy, int reg)
291 {
292 struct axge_softc *sc;
293 uint16_t val;
294 int locked;
295
296 sc = device_get_softc(dev);
297 locked = mtx_owned(&sc->sc_mtx);
298 if (!locked)
299 AXGE_LOCK(sc);
300
301 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);
302
303 if (!locked)
304 AXGE_UNLOCK(sc);
305
306 return (val);
307 }
308
309 static int
axge_miibus_writereg(device_t dev,int phy,int reg,int val)310 axge_miibus_writereg(device_t dev, int phy, int reg, int val)
311 {
312 struct axge_softc *sc;
313 int locked;
314
315 sc = device_get_softc(dev);
316 locked = mtx_owned(&sc->sc_mtx);
317 if (!locked)
318 AXGE_LOCK(sc);
319
320 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);
321
322 if (!locked)
323 AXGE_UNLOCK(sc);
324
325 return (0);
326 }
327
328 static void
axge_miibus_statchg(device_t dev)329 axge_miibus_statchg(device_t dev)
330 {
331 struct axge_softc *sc;
332 struct mii_data *mii;
333 struct ifnet *ifp;
334 uint8_t link_status, tmp[5];
335 uint16_t val;
336 int locked;
337
338 sc = device_get_softc(dev);
339 mii = GET_MII(sc);
340 locked = mtx_owned(&sc->sc_mtx);
341 if (!locked)
342 AXGE_LOCK(sc);
343
344 ifp = uether_getifp(&sc->sc_ue);
345 if (mii == NULL || ifp == NULL ||
346 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
347 goto done;
348
349 sc->sc_flags &= ~AXGE_FLAG_LINK;
350 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
351 (IFM_ACTIVE | IFM_AVALID)) {
352 switch (IFM_SUBTYPE(mii->mii_media_active)) {
353 case IFM_10_T:
354 case IFM_100_TX:
355 case IFM_1000_T:
356 sc->sc_flags |= AXGE_FLAG_LINK;
357 break;
358 default:
359 break;
360 }
361 }
362
363 /* Lost link, do nothing. */
364 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
365 goto done;
366
367 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR);
368
369 val = 0;
370 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
371 val |= MSR_FD;
372 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
373 val |= MSR_TFC;
374 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
375 val |= MSR_RFC;
376 }
377 val |= MSR_RE;
378 switch (IFM_SUBTYPE(mii->mii_media_active)) {
379 case IFM_1000_T:
380 val |= MSR_GM | MSR_EN_125MHZ;
381 if (link_status & PLSR_USB_SS)
382 memcpy(tmp, &axge_bulk_size[0], 5);
383 else if (link_status & PLSR_USB_HS)
384 memcpy(tmp, &axge_bulk_size[1], 5);
385 else
386 memcpy(tmp, &axge_bulk_size[3], 5);
387 break;
388 case IFM_100_TX:
389 val |= MSR_PS;
390 if (link_status & (PLSR_USB_SS | PLSR_USB_HS))
391 memcpy(tmp, &axge_bulk_size[2], 5);
392 else
393 memcpy(tmp, &axge_bulk_size[3], 5);
394 break;
395 case IFM_10_T:
396 memcpy(tmp, &axge_bulk_size[3], 5);
397 break;
398 }
399 /* Rx bulk configuration. */
400 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
401 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
402 done:
403 if (!locked)
404 AXGE_UNLOCK(sc);
405 }
406
407 static void
axge_chip_init(struct axge_softc * sc)408 axge_chip_init(struct axge_softc *sc)
409 {
410 /* Power up ethernet PHY. */
411 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0);
412 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL);
413 uether_pause(&sc->sc_ue, hz / 4);
414 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT,
415 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
416 uether_pause(&sc->sc_ue, hz / 10);
417 }
418
419 static void
axge_reset(struct axge_softc * sc)420 axge_reset(struct axge_softc *sc)
421 {
422 struct usb_config_descriptor *cd;
423 usb_error_t err;
424
425 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
426
427 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
428 cd->bConfigurationValue);
429 if (err)
430 DPRINTF("reset failed (ignored)\n");
431
432 /* Wait a little while for the chip to get its brains in order. */
433 uether_pause(&sc->sc_ue, hz / 100);
434
435 /* Reinitialize controller to achieve full reset. */
436 axge_chip_init(sc);
437 }
438
439 static void
axge_attach_post(struct usb_ether * ue)440 axge_attach_post(struct usb_ether *ue)
441 {
442 struct axge_softc *sc;
443
444 sc = uether_getsc(ue);
445
446 /* Initialize controller and get station address. */
447 axge_chip_init(sc);
448 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
449 ue->ue_eaddr, ETHER_ADDR_LEN);
450 }
451
452 static int
axge_attach_post_sub(struct usb_ether * ue)453 axge_attach_post_sub(struct usb_ether *ue)
454 {
455 struct ifnet *ifp;
456 int error;
457
458 ifp = ue->ue_ifp;
459 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
460 ifp->if_start = uether_start;
461 ifp->if_ioctl = axge_ioctl;
462 ifp->if_init = uether_init;
463 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
464 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
465 IFQ_SET_READY(&ifp->if_snd);
466
467 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM;
468 ifp->if_hwassist = AXGE_CSUM_FEATURES;
469 ifp->if_capenable = ifp->if_capabilities;
470
471 mtx_lock(&Giant);
472 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
473 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
474 BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE);
475 mtx_unlock(&Giant);
476
477 return (error);
478 }
479
480 /*
481 * Set media options.
482 */
483 static int
axge_ifmedia_upd(struct ifnet * ifp)484 axge_ifmedia_upd(struct ifnet *ifp)
485 {
486 struct axge_softc *sc;
487 struct mii_data *mii;
488 struct mii_softc *miisc;
489 int error;
490
491 sc = ifp->if_softc;
492 mii = GET_MII(sc);
493 AXGE_LOCK_ASSERT(sc, MA_OWNED);
494
495 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
496 PHY_RESET(miisc);
497 error = mii_mediachg(mii);
498
499 return (error);
500 }
501
502 /*
503 * Report current media status.
504 */
505 static void
axge_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)506 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
507 {
508 struct axge_softc *sc;
509 struct mii_data *mii;
510
511 sc = ifp->if_softc;
512 mii = GET_MII(sc);
513 AXGE_LOCK(sc);
514 mii_pollstat(mii);
515 ifmr->ifm_active = mii->mii_media_active;
516 ifmr->ifm_status = mii->mii_media_status;
517 AXGE_UNLOCK(sc);
518 }
519
520 /*
521 * Probe for a AX88179 chip.
522 */
523 static int
axge_probe(device_t dev)524 axge_probe(device_t dev)
525 {
526 struct usb_attach_arg *uaa;
527
528 uaa = device_get_ivars(dev);
529 if (uaa->usb_mode != USB_MODE_HOST)
530 return (ENXIO);
531 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX)
532 return (ENXIO);
533 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX)
534 return (ENXIO);
535
536 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa));
537 }
538
539 /*
540 * Attach the interface. Allocate softc structures, do ifmedia
541 * setup and ethernet/BPF attach.
542 */
543 static int
axge_attach(device_t dev)544 axge_attach(device_t dev)
545 {
546 struct usb_attach_arg *uaa;
547 struct axge_softc *sc;
548 struct usb_ether *ue;
549 uint8_t iface_index;
550 int error;
551
552 uaa = device_get_ivars(dev);
553 sc = device_get_softc(dev);
554 ue = &sc->sc_ue;
555
556 device_set_usb_desc(dev);
557 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
558
559 iface_index = AXGE_IFACE_IDX;
560 error = usbd_transfer_setup(uaa->device, &iface_index,
561 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx);
562 if (error) {
563 device_printf(dev, "allocating USB transfers failed\n");
564 mtx_destroy(&sc->sc_mtx);
565 return (ENXIO);
566 }
567
568 ue->ue_sc = sc;
569 ue->ue_dev = dev;
570 ue->ue_udev = uaa->device;
571 ue->ue_mtx = &sc->sc_mtx;
572 ue->ue_methods = &axge_ue_methods;
573
574 error = uether_ifattach(ue);
575 if (error) {
576 device_printf(dev, "could not attach interface\n");
577 goto detach;
578 }
579 return (0); /* success */
580
581 detach:
582 axge_detach(dev);
583 return (ENXIO); /* failure */
584 }
585
586 static int
axge_detach(device_t dev)587 axge_detach(device_t dev)
588 {
589 struct axge_softc *sc;
590 struct usb_ether *ue;
591 uint16_t val;
592
593 sc = device_get_softc(dev);
594 ue = &sc->sc_ue;
595 if (device_is_attached(dev)) {
596 /* wait for any post attach or other command to complete */
597 usb_proc_drain(&ue->ue_tq);
598
599 AXGE_LOCK(sc);
600 /*
601 * XXX
602 * ether_ifdetach(9) should be called first.
603 */
604 axge_stop(ue);
605 /* Force bulk-in to return a zero-length USB packet. */
606 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR);
607 val |= EPPRCR_BZ | EPPRCR_IPRL;
608 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val);
609 /* Change clock. */
610 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0);
611 /* Disable MAC. */
612 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0);
613 AXGE_UNLOCK(sc);
614 }
615 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER);
616 uether_ifdetach(ue);
617 mtx_destroy(&sc->sc_mtx);
618
619 return (0);
620 }
621
622 static void
axge_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)623 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
624 {
625 struct axge_softc *sc;
626 struct usb_ether *ue;
627 struct usb_page_cache *pc;
628 int actlen;
629
630 sc = usbd_xfer_softc(xfer);
631 ue = &sc->sc_ue;
632 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
633
634 switch (USB_GET_STATE(xfer)) {
635 case USB_ST_TRANSFERRED:
636 pc = usbd_xfer_get_frame(xfer, 0);
637 axge_rx_frame(ue, pc, actlen);
638
639 /* FALLTHROUGH */
640 case USB_ST_SETUP:
641 tr_setup:
642 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
643 usbd_transfer_submit(xfer);
644 uether_rxflush(ue);
645 break;
646
647 default:
648 if (error != USB_ERR_CANCELLED) {
649 usbd_xfer_set_stall(xfer);
650 goto tr_setup;
651 }
652 break;
653 }
654 }
655
656 static void
axge_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)657 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
658 {
659 struct axge_softc *sc;
660 struct ifnet *ifp;
661 struct usb_page_cache *pc;
662 struct mbuf *m;
663 struct axge_frame_txhdr txhdr;
664 int nframes, pos;
665
666 sc = usbd_xfer_softc(xfer);
667 ifp = uether_getifp(&sc->sc_ue);
668
669 switch (USB_GET_STATE(xfer)) {
670 case USB_ST_TRANSFERRED:
671 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
672 /* FALLTHROUGH */
673 case USB_ST_SETUP:
674 tr_setup:
675 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 ||
676 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
677 /*
678 * Don't send anything if there is no link or
679 * controller is busy.
680 */
681 return;
682 }
683
684 for (nframes = 0; nframes < AXGE_N_FRAMES &&
685 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
686 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
687 if (m == NULL)
688 break;
689 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
690 nframes);
691 pc = usbd_xfer_get_frame(xfer, nframes);
692 txhdr.mss = 0;
693 txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len));
694 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0 &&
695 (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0)
696 txhdr.len |= htole32(AXGE_CSUM_DISABLE);
697
698 pos = 0;
699 usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr));
700 pos += sizeof(txhdr);
701 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
702 pos += m->m_pkthdr.len;
703
704 /*
705 * if there's a BPF listener, bounce a copy
706 * of this frame to him:
707 */
708 BPF_MTAP(ifp, m);
709
710 m_freem(m);
711
712 /* Set frame length. */
713 usbd_xfer_set_frame_len(xfer, nframes, pos);
714 }
715 if (nframes != 0) {
716 /*
717 * XXX
718 * Update TX packet counter here. This is not
719 * correct way but it seems that there is no way
720 * to know how many packets are sent at the end
721 * of transfer because controller combines
722 * multiple writes into single one if there is
723 * room in TX buffer of controller.
724 */
725 if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes);
726 usbd_xfer_set_frames(xfer, nframes);
727 usbd_transfer_submit(xfer);
728 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
729 }
730 return;
731 /* NOTREACHED */
732 default:
733 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
734 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
735
736 if (error != USB_ERR_CANCELLED) {
737 usbd_xfer_set_stall(xfer);
738 goto tr_setup;
739 }
740 return;
741 }
742 }
743
744 static void
axge_tick(struct usb_ether * ue)745 axge_tick(struct usb_ether *ue)
746 {
747 struct axge_softc *sc;
748 struct mii_data *mii;
749
750 sc = uether_getsc(ue);
751 mii = GET_MII(sc);
752 AXGE_LOCK_ASSERT(sc, MA_OWNED);
753
754 mii_tick(mii);
755 }
756
757 static u_int
axge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)758 axge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
759 {
760 uint8_t *hashtbl = arg;
761 uint32_t h;
762
763 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
764 hashtbl[h / 8] |= 1 << (h % 8);
765
766 return (1);
767 }
768
769 static void
axge_rxfilter(struct usb_ether * ue)770 axge_rxfilter(struct usb_ether *ue)
771 {
772 struct axge_softc *sc;
773 struct ifnet *ifp;
774 uint16_t rxmode;
775 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
776
777 sc = uether_getsc(ue);
778 ifp = uether_getifp(ue);
779 AXGE_LOCK_ASSERT(sc, MA_OWNED);
780
781 /*
782 * Configure RX settings.
783 * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable
784 * inserting extra padding bytes. This wastes ethernet to USB host
785 * bandwidth as well as complicating RX handling logic. Current USB
786 * framework requires copying RX frames to mbufs so there is no need
787 * to worry about alignment.
788 */
789 rxmode = RCR_DROP_CRCERR | RCR_START;
790 if (ifp->if_flags & IFF_BROADCAST)
791 rxmode |= RCR_ACPT_BCAST;
792 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
793 if (ifp->if_flags & IFF_PROMISC)
794 rxmode |= RCR_PROMISC;
795 rxmode |= RCR_ACPT_ALL_MCAST;
796 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
797 return;
798 }
799
800 rxmode |= RCR_ACPT_MCAST;
801 if_foreach_llmaddr(ifp, axge_hash_maddr, &hashtbl);
802
803 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8);
804 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
805 }
806
807 static void
axge_start(struct usb_ether * ue)808 axge_start(struct usb_ether *ue)
809 {
810 struct axge_softc *sc;
811
812 sc = uether_getsc(ue);
813 /*
814 * Start the USB transfers, if not already started.
815 */
816 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]);
817 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]);
818 }
819
820 static void
axge_init(struct usb_ether * ue)821 axge_init(struct usb_ether *ue)
822 {
823 struct axge_softc *sc;
824 struct ifnet *ifp;
825
826 sc = uether_getsc(ue);
827 ifp = uether_getifp(ue);
828 AXGE_LOCK_ASSERT(sc, MA_OWNED);
829
830 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
831 return;
832
833 /*
834 * Cancel pending I/O and free all RX/TX buffers.
835 */
836 axge_stop(ue);
837
838 axge_reset(sc);
839
840 /* Set MAC address. */
841 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
842 IF_LLADDR(ifp), ETHER_ADDR_LEN);
843
844 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34);
845 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52);
846
847 /* Configure TX/RX checksum offloading. */
848 axge_csum_cfg(ue);
849
850 /* Configure RX filters. */
851 axge_rxfilter(ue);
852
853 /*
854 * XXX
855 * Controller supports wakeup on link change detection,
856 * magic packet and wakeup frame recpetion. But it seems
857 * there is no framework for USB ethernet suspend/wakeup.
858 * Disable all wakeup functions.
859 */
860 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0);
861 (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR);
862
863 /* Configure default medium type. */
864 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD |
865 MSR_RFC | MSR_TFC | MSR_RE);
866
867 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
868
869 ifp->if_drv_flags |= IFF_DRV_RUNNING;
870 /* Switch to selected media. */
871 axge_ifmedia_upd(ifp);
872 }
873
874 static void
axge_stop(struct usb_ether * ue)875 axge_stop(struct usb_ether *ue)
876 {
877 struct axge_softc *sc;
878 struct ifnet *ifp;
879 uint16_t val;
880
881 sc = uether_getsc(ue);
882 ifp = uether_getifp(ue);
883
884 AXGE_LOCK_ASSERT(sc, MA_OWNED);
885
886 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR);
887 val &= ~MSR_RE;
888 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
889
890 if (ifp != NULL)
891 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
892 sc->sc_flags &= ~AXGE_FLAG_LINK;
893
894 /*
895 * Stop all the transfers, if not already stopped:
896 */
897 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]);
898 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]);
899 }
900
901 static int
axge_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)902 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
903 {
904 struct usb_ether *ue;
905 struct axge_softc *sc;
906 struct ifreq *ifr;
907 int error, mask, reinit;
908
909 ue = ifp->if_softc;
910 sc = uether_getsc(ue);
911 ifr = (struct ifreq *)data;
912 error = 0;
913 reinit = 0;
914 if (cmd == SIOCSIFCAP) {
915 AXGE_LOCK(sc);
916 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
917 if ((mask & IFCAP_TXCSUM) != 0 &&
918 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
919 ifp->if_capenable ^= IFCAP_TXCSUM;
920 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
921 ifp->if_hwassist |= AXGE_CSUM_FEATURES;
922 else
923 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES;
924 reinit++;
925 }
926 if ((mask & IFCAP_RXCSUM) != 0 &&
927 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
928 ifp->if_capenable ^= IFCAP_RXCSUM;
929 reinit++;
930 }
931 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
932 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
933 else
934 reinit = 0;
935 AXGE_UNLOCK(sc);
936 if (reinit > 0)
937 uether_init(ue);
938 } else
939 error = uether_ioctl(ifp, cmd, data);
940
941 return (error);
942 }
943
944 static void
axge_rx_frame(struct usb_ether * ue,struct usb_page_cache * pc,int actlen)945 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
946 {
947 struct axge_frame_rxhdr pkt_hdr;
948 uint32_t rxhdr;
949 uint32_t pos;
950 uint32_t pkt_cnt, pkt_end;
951 uint32_t hdr_off;
952 uint32_t pktlen;
953
954 /* verify we have enough data */
955 if (actlen < (int)sizeof(rxhdr))
956 return;
957
958 pos = 0;
959
960 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
961 rxhdr = le32toh(rxhdr);
962
963 pkt_cnt = rxhdr & 0xFFFF;
964 hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF;
965
966 /*
967 * <----------------------- actlen ------------------------>
968 * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr]
969 * Each RX frame would be aligned on 8 bytes boundary. If
970 * RCR_IPE bit is set in AXGE_RCR register, there would be 2
971 * padding bytes and 6 dummy bytes(as the padding also should
972 * be aligned on 8 bytes boundary) for each RX frame to align
973 * IP header on 32bits boundary. Driver don't set RCR_IPE bit
974 * of AXGE_RCR register, so there should be no padding bytes
975 * which simplifies RX logic a lot.
976 */
977 while (pkt_cnt--) {
978 /* verify the header offset */
979 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) {
980 DPRINTF("End of packet headers\n");
981 break;
982 }
983 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr));
984 pkt_hdr.status = le32toh(pkt_hdr.status);
985 pktlen = AXGE_RXBYTES(pkt_hdr.status);
986 if (pos + pktlen > pkt_end) {
987 DPRINTF("Data position reached end\n");
988 break;
989 }
990
991 if (AXGE_RX_ERR(pkt_hdr.status) != 0) {
992 DPRINTF("Dropped a packet\n");
993 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1);
994 } else
995 axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status);
996 pos += (pktlen + 7) & ~7;
997 hdr_off += sizeof(pkt_hdr);
998 }
999 }
1000
1001 static void
axge_rxeof(struct usb_ether * ue,struct usb_page_cache * pc,unsigned int offset,unsigned int len,uint32_t status)1002 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1003 unsigned int len, uint32_t status)
1004 {
1005 struct ifnet *ifp;
1006 struct mbuf *m;
1007
1008 ifp = ue->ue_ifp;
1009 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1010 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1011 return;
1012 }
1013
1014 if (len > MHLEN - ETHER_ALIGN)
1015 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1016 else
1017 m = m_gethdr(M_NOWAIT, MT_DATA);
1018 if (m == NULL) {
1019 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1020 return;
1021 }
1022 m->m_pkthdr.rcvif = ifp;
1023 m->m_len = m->m_pkthdr.len = len;
1024 m->m_data += ETHER_ALIGN;
1025
1026 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1027
1028 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1029 if ((status & AXGE_RX_L3_CSUM_ERR) == 0 &&
1030 (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4)
1031 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1032 CSUM_IP_VALID;
1033 if ((status & AXGE_RX_L4_CSUM_ERR) == 0 &&
1034 ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP ||
1035 (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) {
1036 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1037 CSUM_PSEUDO_HDR;
1038 m->m_pkthdr.csum_data = 0xffff;
1039 }
1040 }
1041 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1042
1043 (void)mbufq_enqueue(&ue->ue_rxq, m);
1044 }
1045
1046 static void
axge_csum_cfg(struct usb_ether * ue)1047 axge_csum_cfg(struct usb_ether *ue)
1048 {
1049 struct axge_softc *sc;
1050 struct ifnet *ifp;
1051 uint8_t csum;
1052
1053 sc = uether_getsc(ue);
1054 AXGE_LOCK_ASSERT(sc, MA_OWNED);
1055 ifp = uether_getifp(ue);
1056
1057 csum = 0;
1058 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1059 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP;
1060 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum);
1061
1062 csum = 0;
1063 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1064 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP;
1065 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum);
1066 }
1067