1 /*-
2 * Copyright (c) 2016 Michal Meloun <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/lock.h>
34 #include <sys/mutex.h>
35 #include <sys/rman.h>
36
37 #include <machine/bus.h>
38
39 #include <dev/extres/clk/clk.h>
40
41 #include <dt-bindings/clock/tegra124-car.h>
42 #include "tegra124_car.h"
43
44 /* #define TEGRA_PLL_DEBUG */
45 #ifdef TEGRA_PLL_DEBUG
46 #define dprintf(...) printf(__VA_ARGS__)
47 #else
48 #define dprintf(...)
49 #endif
50
51 /* All PLLs. */
52 enum pll_type {
53 PLL_M,
54 PLL_X,
55 PLL_C,
56 PLL_C2,
57 PLL_C3,
58 PLL_C4,
59 PLL_P,
60 PLL_A,
61 PLL_U,
62 PLL_D,
63 PLL_D2,
64 PLL_DP,
65 PLL_E,
66 PLL_REFE};
67
68 /* Common base register bits. */
69 #define PLL_BASE_BYPASS (1U << 31)
70 #define PLL_BASE_ENABLE (1 << 30)
71 #define PLL_BASE_REFDISABLE (1 << 29)
72 #define PLL_BASE_LOCK (1 << 27)
73 #define PLL_BASE_DIVM_SHIFT 0
74 #define PLL_BASE_DIVN_SHIFT 8
75
76 #define PLLRE_MISC_LOCK (1 << 24)
77
78 #define PLL_MISC_LOCK_ENABLE (1 << 18)
79 #define PLLC_MISC_LOCK_ENABLE (1 << 24)
80 #define PLLDU_MISC_LOCK_ENABLE (1 << 22)
81 #define PLLRE_MISC_LOCK_ENABLE (1 << 30)
82 #define PLLSS_MISC_LOCK_ENABLE (1 << 30)
83
84 #define PLLC_IDDQ_BIT 26
85 #define PLLX_IDDQ_BIT 3
86 #define PLLRE_IDDQ_BIT 16
87 #define PLLSS_IDDQ_BIT 19
88
89 #define PLL_LOCK_TIMEOUT 5000
90
91 /* Post divider <-> register value mapping. */
92 struct pdiv_table {
93 uint32_t divider; /* real divider */
94 uint32_t value; /* register value */
95 };
96
97 /* Bits definition of M, N and P fields. */
98 struct mnp_bits {
99 uint32_t m_width;
100 uint32_t n_width;
101 uint32_t p_width;
102 uint32_t p_shift;
103 };
104
105 struct clk_pll_def {
106 struct clknode_init_def clkdef;
107 enum pll_type type;
108 uint32_t base_reg;
109 uint32_t misc_reg;
110 uint32_t lock_mask;
111 uint32_t lock_enable;
112 uint32_t iddq_reg;
113 uint32_t iddq_mask;
114 uint32_t flags;
115 struct pdiv_table *pdiv_table;
116 struct mnp_bits mnp_bits;
117 };
118
119 #define PLL(_id, cname, pname) \
120 .clkdef.id = _id, \
121 .clkdef.name = cname, \
122 .clkdef.parent_names = (const char *[]){pname}, \
123 .clkdef.parent_cnt = 1, \
124 .clkdef.flags = CLK_NODE_STATIC_STRINGS
125
126 /* Tegra K1 PLLs
127 PLLM: Clock source for EMC 2x clock
128 PLLX: Clock source for the fast CPU cluster and the shadow CPU
129 PLLC: Clock source for general use
130 PLLC2: Clock source for engine scaling
131 PLLC3: Clock source for engine scaling
132 PLLC4: Clock source for ISP/VI units
133 PLLP: Clock source for most peripherals
134 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
135 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLD: Clock sources for the DSI and display subsystem
137 PLLD2: Clock sources for the DSI and display subsystem
138 refPLLe:
139 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
140 PLLDP: Clock source for eDP/LVDS (spread spectrum)
141
142 DFLLCPU: DFLL clock source for the fast CPU cluster
143 GPCPLL: Clock source for the GPU
144 */
145
146 static struct pdiv_table pllm_map[] = {
147 {1, 0},
148 {2, 1},
149 {0, 0}
150 };
151
152 static struct pdiv_table pllxc_map[] = {
153 { 1, 0},
154 { 2, 1},
155 { 3, 2},
156 { 4, 3},
157 { 5, 4},
158 { 6, 5},
159 { 8, 6},
160 {10, 7},
161 {12, 8},
162 {16, 9},
163 {12, 10},
164 {16, 11},
165 {20, 12},
166 {24, 13},
167 {32, 14},
168 { 0, 0}
169 };
170
171 static struct pdiv_table pllc_map[] = {
172 { 1, 0},
173 { 2, 1},
174 { 3, 2},
175 { 4, 3},
176 { 6, 4},
177 { 8, 5},
178 {12, 6},
179 {16, 7},
180 { 0, 0}
181 };
182
183 static struct pdiv_table pll12g_ssd_esd_map[] = {
184 { 1, 0},
185 { 2, 1},
186 { 3, 2},
187 { 4, 3},
188 { 5, 4},
189 { 6, 5},
190 { 8, 6},
191 {10, 7},
192 {12, 8},
193 {16, 9},
194 {12, 10},
195 {16, 11},
196 {20, 12},
197 {24, 13},
198 {32, 14},
199 { 0, 0}
200 };
201
202 static struct pdiv_table pllu_map[] = {
203 {1, 1},
204 {2, 0},
205 {0, 0}
206 };
207
208 static struct pdiv_table pllrefe_map[] = {
209 {1, 0},
210 {2, 1},
211 {3, 2},
212 {4, 3},
213 {5, 4},
214 {6, 5},
215 {0, 0},
216 };
217
218 static struct clk_pll_def pll_clks[] = {
219 /* PLLM: 880 MHz Clock source for EMC 2x clock */
220 {
221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
222 .type = PLL_M,
223 .base_reg = PLLM_BASE,
224 .misc_reg = PLLM_MISC,
225 .lock_mask = PLL_BASE_LOCK,
226 .lock_enable = PLL_MISC_LOCK_ENABLE,
227 .pdiv_table = pllm_map,
228 .mnp_bits = {8, 8, 1, 20},
229 },
230 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
231 {
232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
233 .type = PLL_X,
234 .base_reg = PLLX_BASE,
235 .misc_reg = PLLX_MISC,
236 .lock_mask = PLL_BASE_LOCK,
237 .lock_enable = PLL_MISC_LOCK_ENABLE,
238 .iddq_reg = PLLX_MISC3,
239 .iddq_mask = 1 << PLLX_IDDQ_BIT,
240 .pdiv_table = pllxc_map,
241 .mnp_bits = {8, 8, 4, 20},
242 },
243 /* PLLC: 600 MHz Clock source for general use */
244 {
245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
246 .type = PLL_C,
247 .base_reg = PLLC_BASE,
248 .misc_reg = PLLC_MISC,
249 .lock_mask = PLL_BASE_LOCK,
250 .lock_enable = PLLC_MISC_LOCK_ENABLE,
251 .iddq_reg = PLLC_MISC,
252 .iddq_mask = 1 << PLLC_IDDQ_BIT,
253 .pdiv_table = pllc_map,
254 .mnp_bits = {8, 8, 4, 20},
255 },
256 /* PLLC2: 600 MHz Clock source for engine scaling */
257 {
258 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
259 .type = PLL_C2,
260 .base_reg = PLLC2_BASE,
261 .misc_reg = PLLC2_MISC,
262 .lock_mask = PLL_BASE_LOCK,
263 .lock_enable = PLL_MISC_LOCK_ENABLE,
264 .pdiv_table = pllc_map,
265 .mnp_bits = {2, 8, 3, 20},
266 },
267 /* PLLC3: 600 MHz Clock source for engine scaling */
268 {
269 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
270 .type = PLL_C3,
271 .base_reg = PLLC3_BASE,
272 .misc_reg = PLLC3_MISC,
273 .lock_mask = PLL_BASE_LOCK,
274 .lock_enable = PLL_MISC_LOCK_ENABLE,
275 .pdiv_table = pllc_map,
276 .mnp_bits = {2, 8, 3, 20},
277 },
278 /* PLLC4: 600 MHz Clock source for ISP/VI units */
279 {
280 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),
281 .type = PLL_C4,
282 .base_reg = PLLC4_BASE,
283 .misc_reg = PLLC4_MISC,
284 .lock_mask = PLL_BASE_LOCK,
285 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
286 .iddq_reg = PLLC4_BASE,
287 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
288 .pdiv_table = pll12g_ssd_esd_map,
289 .mnp_bits = {8, 8, 4, 20},
290 },
291 /* PLLP: 408 MHz Clock source for most peripherals */
292 {
293 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
294 .type = PLL_P,
295 .base_reg = PLLP_BASE,
296 .misc_reg = PLLP_MISC,
297 .lock_mask = PLL_BASE_LOCK,
298 .lock_enable = PLL_MISC_LOCK_ENABLE,
299 .mnp_bits = {5, 10, 3, 20},
300 },
301 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */
302 {
303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
304 .type = PLL_A,
305 .base_reg = PLLA_BASE,
306 .misc_reg = PLLA_MISC,
307 .lock_mask = PLL_BASE_LOCK,
308 .lock_enable = PLL_MISC_LOCK_ENABLE,
309 .mnp_bits = {5, 10, 3, 20},
310 },
311 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
312 {
313 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
314 .type = PLL_U,
315 .base_reg = PLLU_BASE,
316 .misc_reg = PLLU_MISC,
317 .lock_mask = PLL_BASE_LOCK,
318 .lock_enable = PLLDU_MISC_LOCK_ENABLE,
319 .pdiv_table = pllu_map,
320 .mnp_bits = {5, 10, 1, 20},
321 },
322 /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */
323 {
324 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),
325 .type = PLL_D,
326 .base_reg = PLLD_BASE,
327 .misc_reg = PLLD_MISC,
328 .lock_mask = PLL_BASE_LOCK,
329 .lock_enable = PLL_MISC_LOCK_ENABLE,
330 .mnp_bits = {5, 11, 3, 20},
331 },
332 /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */
333 {
334 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
335 .type = PLL_D2,
336 .base_reg = PLLD2_BASE,
337 .misc_reg = PLLD2_MISC,
338 .lock_mask = PLL_BASE_LOCK,
339 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
340 .iddq_reg = PLLD2_BASE,
341 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
342 .pdiv_table = pll12g_ssd_esd_map,
343 .mnp_bits = {8, 8, 4, 20},
344 },
345 /* refPLLe: */
346 {
347 PLL(0, "pllREFE_out", "osc_div_clk"),
348 .type = PLL_REFE,
349 .base_reg = PLLRE_BASE,
350 .misc_reg = PLLRE_MISC,
351 .lock_mask = PLLRE_MISC_LOCK,
352 .lock_enable = PLLRE_MISC_LOCK_ENABLE,
353 .iddq_reg = PLLRE_MISC,
354 .iddq_mask = 1 << PLLRE_IDDQ_BIT,
355 .pdiv_table = pllrefe_map,
356 .mnp_bits = {8, 8, 4, 16},
357 },
358 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */
359 {
360 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),
361 .type = PLL_E,
362 .base_reg = PLLE_BASE,
363 .misc_reg = PLLE_MISC,
364 .lock_mask = PLLE_MISC_LOCK,
365 .lock_enable = PLLE_MISC_LOCK_ENABLE,
366 .mnp_bits = {8, 8, 4, 24},
367 },
368 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */
369 {
370 PLL(0, "pllDP_out0", "pllDP_src"),
371 .type = PLL_DP,
372 .base_reg = PLLDP_BASE,
373 .misc_reg = PLLDP_MISC,
374 .lock_mask = PLL_BASE_LOCK,
375 .lock_enable = PLLSS_MISC_LOCK_ENABLE,
376 .iddq_reg = PLLDP_BASE,
377 .iddq_mask = 1 << PLLSS_IDDQ_BIT,
378 .pdiv_table = pll12g_ssd_esd_map,
379 .mnp_bits = {8, 8, 4, 20},
380 },
381 };
382
383 static int tegra124_pll_init(struct clknode *clk, device_t dev);
384 static int tegra124_pll_set_gate(struct clknode *clk, bool enable);
385 static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq);
386 static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin,
387 uint64_t *fout, int flags, int *stop);
388 struct pll_sc {
389 device_t clkdev;
390 enum pll_type type;
391 uint32_t base_reg;
392 uint32_t misc_reg;
393 uint32_t lock_mask;
394 uint32_t lock_enable;
395 uint32_t iddq_reg;
396 uint32_t iddq_mask;
397 uint32_t flags;
398 struct pdiv_table *pdiv_table;
399 struct mnp_bits mnp_bits;
400 };
401
402 static clknode_method_t tegra124_pll_methods[] = {
403 /* Device interface */
404 CLKNODEMETHOD(clknode_init, tegra124_pll_init),
405 CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate),
406 CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc),
407 CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq),
408 CLKNODEMETHOD_END
409 };
410 DEFINE_CLASS_1(tegra124_pll, tegra124_pll_class, tegra124_pll_methods,
411 sizeof(struct pll_sc), clknode_class);
412
413 static int
pll_enable(struct pll_sc * sc)414 pll_enable(struct pll_sc *sc)
415 {
416 uint32_t reg;
417
418 RD4(sc, sc->base_reg, ®);
419 if (sc->type != PLL_E)
420 reg &= ~PLL_BASE_BYPASS;
421 reg |= PLL_BASE_ENABLE;
422 WR4(sc, sc->base_reg, reg);
423 return (0);
424 }
425
426 static int
pll_disable(struct pll_sc * sc)427 pll_disable(struct pll_sc *sc)
428 {
429 uint32_t reg;
430
431 RD4(sc, sc->base_reg, ®);
432 if (sc->type != PLL_E)
433 reg |= PLL_BASE_BYPASS;
434 reg &= ~PLL_BASE_ENABLE;
435 WR4(sc, sc->base_reg, reg);
436 return (0);
437 }
438
439 static uint32_t
pdiv_to_reg(struct pll_sc * sc,uint32_t p_div)440 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)
441 {
442 struct pdiv_table *tbl;
443
444 tbl = sc->pdiv_table;
445 if (tbl == NULL)
446 return (ffs(p_div) - 1);
447
448 while (tbl->divider != 0) {
449 if (p_div <= tbl->divider)
450 return (tbl->value);
451 tbl++;
452 }
453 return (0xFFFFFFFF);
454 }
455
456 static uint32_t
reg_to_pdiv(struct pll_sc * sc,uint32_t reg)457 reg_to_pdiv(struct pll_sc *sc, uint32_t reg)
458 {
459 struct pdiv_table *tbl;
460
461 tbl = sc->pdiv_table;
462 if (tbl == NULL)
463 return (1 << reg);
464
465 while (tbl->divider) {
466 if (reg == tbl->value)
467 return (tbl->divider);
468 tbl++;
469 }
470 return (0);
471 }
472
473 static uint32_t
get_masked(uint32_t val,uint32_t shift,uint32_t width)474 get_masked(uint32_t val, uint32_t shift, uint32_t width)
475 {
476
477 return ((val >> shift) & ((1 << width) - 1));
478 }
479
480 static uint32_t
set_masked(uint32_t val,uint32_t v,uint32_t shift,uint32_t width)481 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width)
482 {
483
484 val &= ~(((1 << width) - 1) << shift);
485 val |= (v & ((1 << width) - 1)) << shift;
486 return (val);
487 }
488
489 static void
get_divisors(struct pll_sc * sc,uint32_t * m,uint32_t * n,uint32_t * p)490 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)
491 {
492 uint32_t val;
493 struct mnp_bits *mnp_bits;
494
495 mnp_bits = &sc->mnp_bits;
496 RD4(sc, sc->base_reg, &val);
497 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
498 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
499 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
500 }
501
502 static uint32_t
set_divisors(struct pll_sc * sc,uint32_t val,uint32_t m,uint32_t n,uint32_t p)503 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,
504 uint32_t p)
505 {
506 struct mnp_bits *mnp_bits;
507
508 mnp_bits = &sc->mnp_bits;
509 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
510 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
511 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
512 return (val);
513 }
514
515 static bool
is_locked(struct pll_sc * sc)516 is_locked(struct pll_sc *sc)
517 {
518 uint32_t reg;
519
520 switch (sc->type) {
521 case PLL_REFE:
522 RD4(sc, sc->misc_reg, ®);
523 reg &= PLLRE_MISC_LOCK;
524 break;
525
526 case PLL_E:
527 RD4(sc, sc->misc_reg, ®);
528 reg &= PLLE_MISC_LOCK;
529 break;
530
531 default:
532 RD4(sc, sc->base_reg, ®);
533 reg &= PLL_BASE_LOCK;
534 break;
535 }
536 return (reg != 0);
537 }
538
539 static int
wait_for_lock(struct pll_sc * sc)540 wait_for_lock(struct pll_sc *sc)
541 {
542 int i;
543
544 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
545 if (is_locked(sc))
546 break;
547 DELAY(10);
548 }
549 if (i <= 0) {
550 printf("PLL lock timeout\n");
551 return (ETIMEDOUT);
552 }
553 return (0);
554 }
555
556 static int
plle_enable(struct pll_sc * sc)557 plle_enable(struct pll_sc *sc)
558 {
559 uint32_t reg;
560 int rv;
561 struct mnp_bits *mnp_bits;
562 uint32_t pll_m = 1;
563 uint32_t pll_n = 200;
564 uint32_t pll_p = 13;
565 uint32_t pll_cml = 13;
566
567 mnp_bits = &sc->mnp_bits;
568
569 /* Disable lock override. */
570 RD4(sc, sc->base_reg, ®);
571 reg &= ~PLLE_BASE_LOCK_OVERRIDE;
572 WR4(sc, sc->base_reg, reg);
573
574 RD4(sc, PLLE_AUX, ®);
575 reg |= PLLE_AUX_ENABLE_SWCTL;
576 reg &= ~PLLE_AUX_SEQ_ENABLE;
577 WR4(sc, PLLE_AUX, reg);
578 DELAY(10);
579
580 RD4(sc, sc->misc_reg, ®);
581 reg |= PLLE_MISC_LOCK_ENABLE;
582 reg |= PLLE_MISC_IDDQ_SWCTL;
583 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
584 reg |= PLLE_MISC_PTS;
585 reg |= PLLE_MISC_VREG_BG_CTRL_MASK;
586 reg |= PLLE_MISC_VREG_CTRL_MASK;
587 WR4(sc, sc->misc_reg, reg);
588 DELAY(10);
589
590 RD4(sc, PLLE_SS_CNTL, ®);
591 reg |= PLLE_SS_CNTL_DISABLE;
592 WR4(sc, PLLE_SS_CNTL, reg);
593
594 RD4(sc, sc->base_reg, ®);
595 reg = set_divisors(sc, reg, pll_m, pll_n, pll_p);
596 reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
597 reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT;
598 WR4(sc, sc->base_reg, reg);
599 DELAY(10);
600
601 pll_enable(sc);
602 rv = wait_for_lock(sc);
603 if (rv != 0)
604 return (rv);
605
606 RD4(sc, PLLE_SS_CNTL, ®);
607 reg &= ~PLLE_SS_CNTL_SSCCENTER;
608 reg &= ~PLLE_SS_CNTL_SSCINVERT;
609 reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK;
610 reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL;
611 WR4(sc, PLLE_SS_CNTL, reg);
612 reg &= ~PLLE_SS_CNTL_SSCBYP;
613 reg &= ~PLLE_SS_CNTL_BYPASS_SS;
614 WR4(sc, PLLE_SS_CNTL, reg);
615 DELAY(10);
616
617 reg &= ~PLLE_SS_CNTL_INTERP_RESET;
618 WR4(sc, PLLE_SS_CNTL, reg);
619 DELAY(10);
620
621 /* HW control of brick pll. */
622 RD4(sc, sc->misc_reg, ®);
623 reg &= ~PLLE_MISC_IDDQ_SWCTL;
624 WR4(sc, sc->misc_reg, reg);
625
626 RD4(sc, PLLE_AUX, ®);
627 reg |= PLLE_AUX_USE_LOCKDET;
628 reg |= PLLE_AUX_SEQ_START_STATE;
629 reg &= ~PLLE_AUX_ENABLE_SWCTL;
630 reg &= ~PLLE_AUX_SS_SWCTL;
631 WR4(sc, PLLE_AUX, reg);
632 reg |= PLLE_AUX_SEQ_START_STATE;
633 DELAY(10);
634 reg |= PLLE_AUX_SEQ_ENABLE;
635 WR4(sc, PLLE_AUX, reg);
636
637 RD4(sc, XUSBIO_PLL_CFG0, ®);
638 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
639 reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE;
640 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
641 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
642 WR4(sc, XUSBIO_PLL_CFG0, reg);
643 DELAY(10);
644
645 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
646 WR4(sc, XUSBIO_PLL_CFG0, reg);
647
648 /* Enable HW control and unreset SATA PLL. */
649 RD4(sc, SATA_PLL_CFG0, ®);
650 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
651 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;
652 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
653 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;
654 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;
655 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;
656 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;
657 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;
658 reg |= SATA_PLL_CFG0_SEQ_START_STATE;
659 WR4(sc, SATA_PLL_CFG0, reg);
660 DELAY(10);
661 reg |= SATA_PLL_CFG0_SEQ_ENABLE;
662 WR4(sc, SATA_PLL_CFG0, reg);
663
664 /* Enable HW control of PCIe PLL. */
665 RD4(sc, PCIE_PLL_CFG0, ®);
666 reg |= PCIE_PLL_CFG0_SEQ_ENABLE;
667 WR4(sc, PCIE_PLL_CFG0, reg);
668
669 return (0);
670 }
671
672 static int
tegra124_pll_set_gate(struct clknode * clknode,bool enable)673 tegra124_pll_set_gate(struct clknode *clknode, bool enable)
674 {
675 int rv;
676 struct pll_sc *sc;
677
678 sc = clknode_get_softc(clknode);
679 if (enable == 0) {
680 rv = pll_disable(sc);
681 return(rv);
682 }
683
684 if (sc->type == PLL_E)
685 rv = plle_enable(sc);
686 else
687 rv = pll_enable(sc);
688 return (rv);
689 }
690
691 static int
pll_set_std(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags,uint32_t m,uint32_t n,uint32_t p)692 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
693 uint32_t m, uint32_t n, uint32_t p)
694 {
695 uint32_t reg;
696 struct mnp_bits *mnp_bits;
697 int rv;
698
699 mnp_bits = &sc->mnp_bits;
700 if (m >= (1 << mnp_bits->m_width))
701 return (ERANGE);
702 if (n >= (1 << mnp_bits->n_width))
703 return (ERANGE);
704 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
705 return (ERANGE);
706
707 if (flags & CLK_SET_DRYRUN) {
708 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
709 (*fout != (((fin / m) * n) /p)))
710 return (ERANGE);
711
712 *fout = ((fin / m) * n) /p;
713
714 return (0);
715 }
716
717 pll_disable(sc);
718
719 /* take pll out of IDDQ */
720 if (sc->iddq_reg != 0)
721 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);
722
723 RD4(sc, sc->base_reg, ®);
724 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
725 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
726 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
727 mnp_bits->p_width);
728 WR4(sc, sc->base_reg, reg);
729
730 /* Enable PLL. */
731 RD4(sc, sc->base_reg, ®);
732 reg |= PLL_BASE_ENABLE;
733 WR4(sc, sc->base_reg, reg);
734
735 /* Enable lock detection. */
736 RD4(sc, sc->misc_reg, ®);
737 reg |= sc->lock_enable;
738 WR4(sc, sc->misc_reg, reg);
739
740 rv = wait_for_lock(sc);
741 if (rv != 0) {
742 /* Disable PLL */
743 RD4(sc, sc->base_reg, ®);
744 reg &= ~PLL_BASE_ENABLE;
745 WR4(sc, sc->base_reg, reg);
746 return (rv);
747 }
748 RD4(sc, sc->misc_reg, ®);
749
750 pll_enable(sc);
751 *fout = ((fin / m) * n) / p;
752 return 0;
753 }
754
755 static int
plla_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)756 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
757 {
758 uint32_t m, n, p;
759
760 p = 1;
761 m = 5;
762 n = (*fout * p * m + fin / 2)/ fin;
763 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
764 return (pll_set_std(sc, fin, fout, flags, m, n, p));
765 }
766
767 static int
pllc_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)768 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
769 {
770 uint32_t m, n, p;
771
772 p = 2;
773 m = 1;
774 n = (*fout * p * m + fin / 2)/ fin;
775 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
776 return (pll_set_std( sc, fin, fout, flags, m, n, p));
777 }
778
779 /*
780 * PLLD2 is used as source for pixel clock for HDMI.
781 * We must be able to set it frequency very flexibly and
782 * precisely (within 5% tolerance limit allowed by HDMI specs).
783 *
784 * For this reason, it is necessary to search the full state space.
785 * Fortunately, thanks to early cycle terminations, performance
786 * is within acceptable limits.
787 */
788 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */
789 #define PLLD2_PFD_MAX 38000000 /* 38 MHz */
790 #define PLLD2_VCO_MIN 600000000 /* 600 MHz */
791 #define PLLD2_VCO_MAX 1200000000 /* 1.2 GHz */
792
793 static int
plld2_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)794 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
795 {
796 uint32_t m, n, p;
797 uint32_t best_m, best_n, best_p;
798 uint64_t vco, pfd;
799 int64_t err, best_err;
800 struct mnp_bits *mnp_bits;
801 struct pdiv_table *tbl;
802 int p_idx, rv;
803
804 mnp_bits = &sc->mnp_bits;
805 tbl = sc->pdiv_table;
806 best_err = INT64_MAX;
807
808 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) {
809 p = tbl[p_idx].divider;
810
811 /* Check constraints */
812 vco = *fout * p;
813 if (vco < PLLD2_VCO_MIN)
814 continue;
815 if (vco > PLLD2_VCO_MAX)
816 break;
817
818 for (m = 1; m < (1 << mnp_bits->m_width); m++) {
819 n = (*fout * p * m + fin / 2) / fin;
820
821 /* Check constraints */
822 if (n == 0)
823 continue;
824 if (n >= (1 << mnp_bits->n_width))
825 break;
826 vco = (fin * n) / m;
827 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN)
828 continue;
829 pfd = fin / m;
830 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN)
831 continue;
832
833 /* Constraints passed, save best result */
834 err = *fout - vco / p;
835 if (err < 0)
836 err = -err;
837 if (err < best_err) {
838 best_err = err;
839 best_p = p;
840 best_m = m;
841 best_n = n;
842 }
843 if (err == 0)
844 goto done;
845 }
846 }
847 done:
848 /*
849 * HDMI specification allows 5% pixel clock tolerance,
850 * we will by a slightly stricter
851 */
852 if (best_err > ((*fout * 100) / 4))
853 return (ERANGE);
854
855 if (flags & CLK_SET_DRYRUN)
856 return (0);
857 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
858 /* XXXX Panic for rv == ERANGE ? */
859 return (rv);
860 }
861
862 static int
pllrefe_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)863 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
864 {
865 uint32_t m, n, p;
866
867 m = 1;
868 p = 1;
869 n = *fout * p * m / fin;
870 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
871 return (pll_set_std(sc, fin, fout, flags, m, n, p));
872 }
873
874 static int
pllx_set_freq(struct pll_sc * sc,uint64_t fin,uint64_t * fout,int flags)875 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
876 {
877 uint32_t reg;
878 uint32_t m, n, p;
879 struct mnp_bits *mnp_bits;
880 int rv;
881
882 mnp_bits = &sc->mnp_bits;
883
884 p = 1;
885 m = 1;
886 n = (*fout * p * m + fin / 2)/ fin;
887 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
888
889 if (m >= (1 << mnp_bits->m_width))
890 return (ERANGE);
891 if (n >= (1 << mnp_bits->n_width))
892 return (ERANGE);
893 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
894 return (ERANGE);
895
896 if (flags & CLK_SET_DRYRUN) {
897 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
898 (*fout != (((fin / m) * n) /p)))
899 return (ERANGE);
900 *fout = ((fin / m) * n) /p;
901 return (0);
902 }
903
904 /* PLLX doesn't have bypass, disable it first. */
905 RD4(sc, sc->base_reg, ®);
906 reg &= ~PLL_BASE_ENABLE;
907 WR4(sc, sc->base_reg, reg);
908
909 /* Set PLL. */
910 RD4(sc, sc->base_reg, ®);
911 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
912 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
913 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
914 mnp_bits->p_width);
915 WR4(sc, sc->base_reg, reg);
916 RD4(sc, sc->base_reg, ®);
917 DELAY(100);
918
919 /* Enable lock detection. */
920 RD4(sc, sc->misc_reg, ®);
921 reg |= sc->lock_enable;
922 WR4(sc, sc->misc_reg, reg);
923
924 /* Enable PLL. */
925 RD4(sc, sc->base_reg, ®);
926 reg |= PLL_BASE_ENABLE;
927 WR4(sc, sc->base_reg, reg);
928
929 rv = wait_for_lock(sc);
930 if (rv != 0) {
931 /* Disable PLL */
932 RD4(sc, sc->base_reg, ®);
933 reg &= ~PLL_BASE_ENABLE;
934 WR4(sc, sc->base_reg, reg);
935 return (rv);
936 }
937 RD4(sc, sc->misc_reg, ®);
938
939 *fout = ((fin / m) * n) / p;
940 return (0);
941 }
942
943 static int
tegra124_pll_set_freq(struct clknode * clknode,uint64_t fin,uint64_t * fout,int flags,int * stop)944 tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
945 int flags, int *stop)
946 {
947 *stop = 1;
948 int rv;
949 struct pll_sc *sc;
950
951 sc = clknode_get_softc(clknode);
952 dprintf("%s: %s requested freq: %llu, input freq: %llu\n", __func__,
953 clknode_get_name(clknode), *fout, fin);
954 switch (sc->type) {
955 case PLL_A:
956 rv = plla_set_freq(sc, fin, fout, flags);
957 break;
958 case PLL_C:
959 rv = pllc_set_freq(sc, fin, fout, flags);
960 break;
961 case PLL_D2:
962 rv = plld2_set_freq(sc, fin, fout, flags);
963 break;
964
965 case PLL_REFE:
966 rv = pllrefe_set_freq(sc, fin, fout, flags);
967 break;
968
969 case PLL_X:
970 rv = pllx_set_freq(sc, fin, fout, flags);
971 break;
972
973 case PLL_U:
974 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */
975 rv = 0;
976 else
977 rv = ERANGE;
978 break;
979 default:
980 rv = ENXIO;
981 break;
982 }
983
984 return (rv);
985 }
986
987 static int
tegra124_pll_init(struct clknode * clk,device_t dev)988 tegra124_pll_init(struct clknode *clk, device_t dev)
989 {
990 struct pll_sc *sc;
991 uint32_t reg;
992
993 sc = clknode_get_softc(clk);
994
995 /* If PLL is enabled, enable lock detect too. */
996 RD4(sc, sc->base_reg, ®);
997 if (reg & PLL_BASE_ENABLE) {
998 RD4(sc, sc->misc_reg, ®);
999 reg |= sc->lock_enable;
1000 WR4(sc, sc->misc_reg, reg);
1001 }
1002 if (sc->type == PLL_REFE) {
1003 RD4(sc, sc->misc_reg, ®);
1004 reg &= ~(1 << 29); /* Diasble lock override */
1005 WR4(sc, sc->misc_reg, reg);
1006 }
1007
1008 clknode_init_parent_idx(clk, 0);
1009 return(0);
1010 }
1011
1012 static int
tegra124_pll_recalc(struct clknode * clk,uint64_t * freq)1013 tegra124_pll_recalc(struct clknode *clk, uint64_t *freq)
1014 {
1015 struct pll_sc *sc;
1016 uint32_t m, n, p, pr;
1017 uint32_t reg, misc_reg;
1018 int locked;
1019
1020 sc = clknode_get_softc(clk);
1021
1022 RD4(sc, sc->base_reg, ®);
1023 RD4(sc, sc->misc_reg, &misc_reg);
1024
1025 get_divisors(sc, &m, &n, &pr);
1026 if (sc->type != PLL_E)
1027 p = reg_to_pdiv(sc, pr);
1028 else
1029 p = 2 * (pr - 1);
1030 locked = is_locked(sc);
1031
1032 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): "
1033 "e: %d, r: %d, o: %d - %s\n", __func__,
1034 clknode_get_name(clk), reg, misc_reg, m, n, p, pr,
1035 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,
1036 locked ? "locked" : "unlocked");
1037
1038 if ((m == 0) || (n == 0) || (p == 0)) {
1039 *freq = 0;
1040 return (EINVAL);
1041 }
1042 *freq = ((*freq / m) * n) / p;
1043 return (0);
1044 }
1045
1046 static int
pll_register(struct clkdom * clkdom,struct clk_pll_def * clkdef)1047 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef)
1048 {
1049 struct clknode *clk;
1050 struct pll_sc *sc;
1051
1052 clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef);
1053 if (clk == NULL)
1054 return (ENXIO);
1055
1056 sc = clknode_get_softc(clk);
1057 sc->clkdev = clknode_get_device(clk);
1058 sc->type = clkdef->type;
1059 sc->base_reg = clkdef->base_reg;
1060 sc->misc_reg = clkdef->misc_reg;
1061 sc->lock_mask = clkdef->lock_mask;
1062 sc->lock_enable = clkdef->lock_enable;
1063 sc->iddq_reg = clkdef->iddq_reg;
1064 sc->iddq_mask = clkdef->iddq_mask;
1065 sc->flags = clkdef->flags;
1066 sc->pdiv_table = clkdef->pdiv_table;
1067 sc->mnp_bits = clkdef->mnp_bits;
1068 clknode_register(clkdom, clk);
1069 return (0);
1070 }
1071
config_utmi_pll(struct tegra124_car_softc * sc)1072 static void config_utmi_pll(struct tegra124_car_softc *sc)
1073 {
1074 uint32_t reg;
1075 /*
1076 * XXX Simplified UTMIP settings for 12MHz base clock.
1077 */
1078 #define ENABLE_DELAY_COUNT 0x02
1079 #define STABLE_COUNT 0x2F
1080 #define ACTIVE_DELAY_COUNT 0x04
1081 #define XTAL_FREQ_COUNT 0x76
1082
1083 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®);
1084 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1085 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);
1086 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1087 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);
1088 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1089 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1090 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1091 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
1092
1093 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1094 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1095 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);
1096 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1097 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);
1098 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1099 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1100 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1101 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1102 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1103
1104 /* Prepare UTMIP requencer. */
1105 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1106 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1107 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1108 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1109 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1110
1111 /* Powerup UTMIP. */
1112 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®);
1113 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1114 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1115 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
1116 DELAY(10);
1117
1118 /* SW override for UTMIPLL */
1119 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1120 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1121 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1122 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1123 DELAY(10);
1124
1125 /* HW control of UTMIPLL. */
1126 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®);
1127 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1128 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
1129 }
1130
1131 void
tegra124_init_plls(struct tegra124_car_softc * sc)1132 tegra124_init_plls(struct tegra124_car_softc *sc)
1133 {
1134 int i, rv;
1135
1136 for (i = 0; i < nitems(pll_clks); i++) {
1137 rv = pll_register(sc->clkdom, pll_clks + i);
1138 if (rv != 0)
1139 panic("pll_register failed");
1140 }
1141 config_utmi_pll(sc);
1142
1143 }
1144