1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 */
5
6 #ifndef _ENIC_H_
7 #define _ENIC_H_
8
9 #include <rte_vxlan.h>
10 #include <rte_ether.h>
11 #include "vnic_enet.h"
12 #include "vnic_dev.h"
13 #include "vnic_flowman.h"
14 #include "vnic_wq.h"
15 #include "vnic_rq.h"
16 #include "vnic_cq.h"
17 #include "vnic_intr.h"
18 #include "vnic_stats.h"
19 #include "vnic_nic.h"
20 #include "vnic_rss.h"
21 #include "enic_res.h"
22 #include "cq_enet_desc.h"
23 #include <stdbool.h>
24 #include <sys/queue.h>
25 #include <rte_spinlock.h>
26
27 #define DRV_NAME "enic_pmd"
28 #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Poll-mode Driver"
29 #define DRV_COPYRIGHT "Copyright 2008-2015 Cisco Systems, Inc"
30
31 #define VLAN_ETH_HLEN 18
32
33 #define ENICPMD_SETTING(enic, f) ((enic->config.flags & VENETF_##f) ? 1 : 0)
34
35 #define ENICPMD_BDF_LENGTH 13 /* 0000:00:00.0'\0' */
36 #define ENIC_CALC_IP_CKSUM 1
37 #define ENIC_CALC_TCP_UDP_CKSUM 2
38 #define ENIC_MAX_MTU 9000
39 #define ENIC_PAGE_SIZE 4096
40 #define PAGE_ROUND_UP(x) \
41 ((((unsigned long)(x)) + ENIC_PAGE_SIZE-1) & (~(ENIC_PAGE_SIZE-1)))
42
43 #define ENICPMD_VFIO_PATH "/dev/vfio/vfio"
44 /*#define ENIC_DESC_COUNT_MAKE_ODD (x) do{if ((~(x)) & 1) { (x)--; } }while(0)*/
45
46 #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
47 #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
48 /* enet SRIOV Standalone vNic VF */
49 #define PCI_DEVICE_ID_CISCO_VIC_ENET_SN 0x02B7
50
51 /* Special Filter id for non-specific packet flagging. Don't change value */
52 #define ENIC_MAGIC_FILTER_ID 0xffff
53
54 #define ENICPMD_FDIR_MAX 64
55
56 /*
57 * Interrupt 0: LSC and errors
58 * Interrupt 1: rx queue 0
59 * Interrupt 2: rx queue 1
60 * ...
61 */
62 #define ENICPMD_LSC_INTR_OFFSET 0
63 #define ENICPMD_RXQ_INTR_OFFSET 1
64
65 struct enic_fdir_node {
66 struct rte_eth_fdir_filter filter;
67 uint16_t fltr_id;
68 uint16_t rq_index;
69 };
70
71 struct enic_fdir {
72 struct rte_eth_fdir_stats stats;
73 struct rte_hash *hash;
74 struct enic_fdir_node *nodes[ENICPMD_FDIR_MAX];
75 uint32_t modes;
76 uint32_t types_mask;
77 void (*copy_fltr_fn)(struct filter_v2 *filt,
78 const struct rte_eth_fdir_input *input,
79 const struct rte_eth_fdir_masks *masks);
80 };
81
82 struct enic_soft_stats {
83 rte_atomic64_t rx_nombuf;
84 rte_atomic64_t rx_packet_errors;
85 rte_atomic64_t tx_oversized;
86 };
87
88 struct enic_memzone_entry {
89 const struct rte_memzone *rz;
90 LIST_ENTRY(enic_memzone_entry) entries;
91 };
92
93 /* Defined in enic_fm_flow.c */
94 struct enic_flowman;
95 struct enic_fm_flow;
96
97 struct rte_flow {
98 LIST_ENTRY(rte_flow) next;
99 /* Data for filter API based flow (enic_flow.c) */
100 uint16_t enic_filter_id;
101 struct filter_v2 enic_filter;
102 /* Data for flow manager based flow (enic_fm_flow.c) */
103 struct enic_fm_flow *fm;
104 int internal;
105 };
106
107 /* Per-instance private data structure */
108 struct enic {
109 struct rte_pci_device *pdev;
110 struct vnic_enet_config config;
111 struct vnic_dev_bar bar0;
112 struct vnic_dev *vdev;
113
114 /*
115 * mbuf_initializer contains 64 bits of mbuf rearm_data, used by
116 * the avx2 handler at this time.
117 */
118 uint64_t mbuf_initializer;
119 unsigned int port_id;
120 bool overlay_offload;
121 struct rte_eth_dev *rte_dev;
122 struct rte_eth_dev_data *dev_data;
123 struct enic_fdir fdir;
124 char bdf_name[ENICPMD_BDF_LENGTH];
125 int dev_fd;
126 int iommu_group_fd;
127 int iommu_groupid;
128 int eventfd;
129 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
130 pthread_t err_intr_thread;
131 int promisc;
132 int allmulti;
133 uint8_t ig_vlan_strip_en;
134 int link_status;
135 uint8_t hw_ip_checksum;
136 uint16_t max_mtu;
137 uint8_t adv_filters;
138 uint32_t flow_filter_mode;
139 uint8_t filter_actions; /* HW supported actions */
140 bool vxlan;
141 bool disable_overlay; /* devargs disable_overlay=1 */
142 uint8_t enable_avx2_rx; /* devargs enable-avx2-rx=1 */
143 uint8_t geneve_opt_avail; /* Geneve with options offload available */
144 uint8_t geneve_opt_enabled; /* Geneve with options offload enabled */
145 uint8_t geneve_opt_request; /* devargs geneve-opt=1 */
146 bool nic_cfg_chk; /* NIC_CFG_CHK available */
147 bool udp_rss_weak; /* Bodega style UDP RSS */
148 uint8_t ig_vlan_rewrite_mode; /* devargs ig-vlan-rewrite */
149 uint16_t vxlan_port; /* current vxlan port pushed to NIC */
150 int use_simple_tx_handler;
151 int use_noscatter_vec_rx_handler;
152
153 unsigned int flags;
154 unsigned int priv_flags;
155
156 /* work queue (len = conf_wq_count) */
157 struct vnic_wq *wq;
158 unsigned int wq_count; /* equals eth_dev nb_tx_queues */
159
160 /* receive queue (len = conf_rq_count) */
161 struct vnic_rq *rq;
162 unsigned int rq_count; /* equals eth_dev nb_rx_queues */
163
164 /* completion queue (len = conf_cq_count) */
165 struct vnic_cq *cq;
166 unsigned int cq_count; /* equals rq_count + wq_count */
167
168 /* interrupt vectors (len = conf_intr_count) */
169 struct vnic_intr *intr;
170 unsigned int intr_count; /* equals enabled interrupts (lsc + rxqs) */
171
172 /* software counters */
173 struct enic_soft_stats soft_stats;
174
175 /* configured resources on vic */
176 unsigned int conf_rq_count;
177 unsigned int conf_wq_count;
178 unsigned int conf_cq_count;
179 unsigned int conf_intr_count;
180
181 /* linked list storing memory allocations */
182 LIST_HEAD(enic_memzone_list, enic_memzone_entry) memzone_list;
183 rte_spinlock_t memzone_list_lock;
184 rte_spinlock_t mtu_lock;
185
186 LIST_HEAD(enic_flows, rte_flow) flows;
187
188 /* RSS */
189 uint16_t reta_size;
190 uint8_t hash_key_size;
191 uint64_t flow_type_rss_offloads; /* 0 indicates RSS not supported */
192 /*
193 * Keep a copy of current RSS config for queries, as we cannot retrieve
194 * it from the NIC.
195 */
196 uint8_t rss_hash_type; /* NIC_CFG_RSS_HASH_TYPE flags */
197 uint8_t rss_enable;
198 uint64_t rss_hf; /* ETH_RSS flags */
199 union vnic_rss_key rss_key;
200 union vnic_rss_cpu rss_cpu;
201
202 uint64_t rx_offload_capa; /* DEV_RX_OFFLOAD flags */
203 uint64_t tx_offload_capa; /* DEV_TX_OFFLOAD flags */
204 uint64_t tx_queue_offload_capa; /* DEV_TX_OFFLOAD flags */
205 uint64_t tx_offload_mask; /* PKT_TX flags accepted */
206
207 /* Multicast MAC addresses added to the NIC */
208 uint32_t mc_count;
209 struct rte_ether_addr mc_addrs[ENIC_MULTICAST_PERFECT_FILTERS];
210
211 /* Flow manager API */
212 struct enic_flowman *fm;
213 uint64_t fm_vnic_handle;
214 uint32_t fm_vnic_uif;
215 /* switchdev */
216 uint8_t switchdev_mode;
217 uint16_t switch_domain_id;
218 uint16_t max_vf_id;
219 /* Number of queues needed for VF representor paths */
220 uint32_t vf_required_wq;
221 uint32_t vf_required_cq;
222 uint32_t vf_required_rq;
223 /*
224 * Lock to serialize devcmds from PF, VF representors as they all share
225 * the same PF devcmd instance in firmware.
226 */
227 rte_spinlock_t devcmd_lock;
228 };
229
230 struct enic_vf_representor {
231 struct enic enic;
232 struct vnic_enet_config config;
233 struct rte_eth_dev *eth_dev;
234 struct rte_ether_addr mac_addr;
235 struct rte_pci_addr bdf;
236 struct enic *pf;
237 uint16_t switch_domain_id;
238 uint16_t vf_id;
239 int allmulti;
240 int promisc;
241 /* Representor path uses PF queues. These are reserved during init */
242 uint16_t pf_wq_idx; /* WQ dedicated to VF rep */
243 uint16_t pf_wq_cq_idx; /* CQ for WQ */
244 uint16_t pf_rq_sop_idx; /* SOP RQ dedicated to VF rep */
245 uint16_t pf_rq_data_idx; /* Data RQ */
246 /* Representor flows managed by flowman */
247 struct rte_flow *vf2rep_flow[2];
248 struct rte_flow *rep2vf_flow[2];
249 };
250
251 #define VF_ENIC_TO_VF_REP(vf_enic) \
252 container_of(vf_enic, struct enic_vf_representor, enic)
253
enic_is_vf_rep(struct enic * enic)254 static inline int enic_is_vf_rep(struct enic *enic)
255 {
256 return !!(enic->rte_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR);
257 }
258
259 /* Compute ethdev's max packet size from MTU */
enic_mtu_to_max_rx_pktlen(uint32_t mtu)260 static inline uint32_t enic_mtu_to_max_rx_pktlen(uint32_t mtu)
261 {
262 /* ethdev max size includes eth whereas NIC MTU does not */
263 return mtu + RTE_ETHER_HDR_LEN;
264 }
265
266 /* Get the CQ index from a Start of Packet(SOP) RQ index */
enic_sop_rq_idx_to_cq_idx(unsigned int sop_idx)267 static inline unsigned int enic_sop_rq_idx_to_cq_idx(unsigned int sop_idx)
268 {
269 return sop_idx;
270 }
271
272 /* Get the RTE RQ index from a Start of Packet(SOP) RQ index */
enic_sop_rq_idx_to_rte_idx(unsigned int sop_idx)273 static inline unsigned int enic_sop_rq_idx_to_rte_idx(unsigned int sop_idx)
274 {
275 return sop_idx;
276 }
277
278 /* Get the Start of Packet(SOP) RQ index from a RTE RQ index */
enic_rte_rq_idx_to_sop_idx(unsigned int rte_idx)279 static inline unsigned int enic_rte_rq_idx_to_sop_idx(unsigned int rte_idx)
280 {
281 return rte_idx;
282 }
283
284 /* Get the Data RQ index from a RTE RQ index */
enic_rte_rq_idx_to_data_idx(unsigned int rte_idx,struct enic * enic)285 static inline unsigned int enic_rte_rq_idx_to_data_idx(unsigned int rte_idx,
286 struct enic *enic)
287 {
288 return enic->rq_count + rte_idx;
289 }
290
enic_vnic_rq_count(struct enic * enic)291 static inline unsigned int enic_vnic_rq_count(struct enic *enic)
292 {
293 return enic->rq_count * 2;
294 }
295
enic_cq_rq(__rte_unused struct enic * enic,unsigned int rq)296 static inline unsigned int enic_cq_rq(__rte_unused struct enic *enic, unsigned int rq)
297 {
298 return rq;
299 }
300
enic_cq_wq(struct enic * enic,unsigned int wq)301 static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
302 {
303 return enic->rq_count + wq;
304 }
305
306 /*
307 * WQ, RQ, CQ allocation scheme. Firmware gives the driver an array of
308 * WQs, an array of RQs, and an array of CQs. Fow now, these are
309 * statically allocated between PF app send/receive queues and VF
310 * representor app send/receive queues. VF representor supports only 1
311 * send and 1 receive queue. The number of PF app queue is not known
312 * until the queue setup time.
313 *
314 * R = number of receive queues for PF app
315 * S = number of send queues for PF app
316 * V = number of VF representors
317 *
318 * wI = WQ for PF app send queue I
319 * rI = SOP RQ for PF app receive queue I
320 * dI = Data RQ for rI
321 * cwI = CQ for wI
322 * crI = CQ for rI
323 * vwI = WQ for VF representor send queue I
324 * vrI = SOP RQ for VF representor receive queue I
325 * vdI = Data RQ for vrI
326 * vcwI = CQ for vwI
327 * vcrI = CQ for vrI
328 *
329 * WQ array: | w0 |..| wS-1 |..| vwV-1 |..| vw0 |
330 * ^ ^ ^ ^
331 * index 0 S-1 W-V W-1 W=len(WQ array)
332 *
333 * RQ array: | r0 |..| rR-1 |d0 |..|dR-1| ..|vdV-1 |..| vd0 |vrV-1 |..|vr0 |
334 * ^ ^ ^ ^ ^ ^ ^ ^
335 * index 0 R-1 R 2R-1 X-2V X-(V+1) X-V X-1
336 * X=len(RQ array)
337 *
338 * CQ array: | cr0 |..| crR-1 |cw0|..|cwS-1|..|vcwV-1|..| vcw0|vcrV-1|..|vcr0|..
339 * ^ ^ ^ ^ ^ ^ ^ ^
340 * index 0 R-1 R R+S-1 X-2V X-(V+1) X-V X-1
341 * X is not a typo. It really is len(RQ array) to accommodate enic_cq_rq() used
342 * throughout RX handlers. The current scheme requires
343 * len(CQ array) >= len(RQ array).
344 */
345
vf_wq_cq_idx(struct enic_vf_representor * vf)346 static inline unsigned int vf_wq_cq_idx(struct enic_vf_representor *vf)
347 {
348 /* rq is not a typo. index(vcwI) coincides with index(vdI) */
349 return vf->pf->conf_rq_count - (vf->pf->max_vf_id + vf->vf_id + 2);
350 }
351
vf_wq_idx(struct enic_vf_representor * vf)352 static inline unsigned int vf_wq_idx(struct enic_vf_representor *vf)
353 {
354 return vf->pf->conf_wq_count - vf->vf_id - 1;
355 }
356
vf_rq_sop_idx(struct enic_vf_representor * vf)357 static inline unsigned int vf_rq_sop_idx(struct enic_vf_representor *vf)
358 {
359 return vf->pf->conf_rq_count - vf->vf_id - 1;
360 }
361
vf_rq_data_idx(struct enic_vf_representor * vf)362 static inline unsigned int vf_rq_data_idx(struct enic_vf_representor *vf)
363 {
364 return vf->pf->conf_rq_count - (vf->pf->max_vf_id + vf->vf_id + 2);
365 }
366
pmd_priv(struct rte_eth_dev * eth_dev)367 static inline struct enic *pmd_priv(struct rte_eth_dev *eth_dev)
368 {
369 return eth_dev->data->dev_private;
370 }
371
372 static inline uint32_t
enic_ring_add(uint32_t n_descriptors,uint32_t i0,uint32_t i1)373 enic_ring_add(uint32_t n_descriptors, uint32_t i0, uint32_t i1)
374 {
375 uint32_t d = i0 + i1;
376 d -= (d >= n_descriptors) ? n_descriptors : 0;
377 return d;
378 }
379
380 static inline uint32_t
enic_ring_sub(uint32_t n_descriptors,uint32_t i0,uint32_t i1)381 enic_ring_sub(uint32_t n_descriptors, uint32_t i0, uint32_t i1)
382 {
383 int32_t d = i1 - i0;
384 return (uint32_t)((d < 0) ? ((int32_t)n_descriptors + d) : d);
385 }
386
387 static inline uint32_t
enic_ring_incr(uint32_t n_descriptors,uint32_t idx)388 enic_ring_incr(uint32_t n_descriptors, uint32_t idx)
389 {
390 idx++;
391 if (unlikely(idx == n_descriptors))
392 idx = 0;
393 return idx;
394 }
395
396 int dev_is_enic(struct rte_eth_dev *dev);
397 void enic_free_wq(void *txq);
398 int enic_alloc_intr_resources(struct enic *enic);
399 int enic_setup_finish(struct enic *enic);
400 int enic_alloc_wq(struct enic *enic, uint16_t queue_idx,
401 unsigned int socket_id, uint16_t nb_desc);
402 void enic_start_wq(struct enic *enic, uint16_t queue_idx);
403 int enic_stop_wq(struct enic *enic, uint16_t queue_idx);
404 void enic_start_rq(struct enic *enic, uint16_t queue_idx);
405 int enic_stop_rq(struct enic *enic, uint16_t queue_idx);
406 void enic_free_rq(void *rxq);
407 int enic_alloc_rq(struct enic *enic, uint16_t queue_idx,
408 unsigned int socket_id, struct rte_mempool *mp,
409 uint16_t nb_desc, uint16_t free_thresh);
410 int enic_set_vnic_res(struct enic *enic);
411 int enic_init_rss_nic_cfg(struct enic *enic);
412 int enic_set_rss_conf(struct enic *enic,
413 struct rte_eth_rss_conf *rss_conf);
414 int enic_set_rss_reta(struct enic *enic, union vnic_rss_cpu *rss_cpu);
415 int enic_set_vlan_strip(struct enic *enic);
416 int enic_enable(struct enic *enic);
417 int enic_disable(struct enic *enic);
418 void enic_remove(struct enic *enic);
419 int enic_get_link_status(struct enic *enic);
420 int enic_dev_stats_get(struct enic *enic,
421 struct rte_eth_stats *r_stats);
422 int enic_dev_stats_clear(struct enic *enic);
423 int enic_add_packet_filter(struct enic *enic);
424 int enic_set_mac_address(struct enic *enic, uint8_t *mac_addr);
425 int enic_del_mac_address(struct enic *enic, int mac_index);
426 unsigned int enic_cleanup_wq(struct enic *enic, struct vnic_wq *wq);
427 void enic_send_pkt(struct enic *enic, struct vnic_wq *wq,
428 struct rte_mbuf *tx_pkt, unsigned short len,
429 uint8_t sop, uint8_t eop, uint8_t cq_entry,
430 uint16_t ol_flags, uint16_t vlan_tag);
431
432 void enic_post_wq_index(struct vnic_wq *wq);
433 int enic_probe(struct enic *enic);
434 int enic_clsf_init(struct enic *enic);
435 void enic_clsf_destroy(struct enic *enic);
436 int enic_fm_init(struct enic *enic);
437 void enic_fm_destroy(struct enic *enic);
438 void *enic_alloc_consistent(void *priv, size_t size, dma_addr_t *dma_handle,
439 uint8_t *name);
440 void enic_free_consistent(void *priv, size_t size, void *vaddr,
441 dma_addr_t dma_handle);
442 uint16_t enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
443 uint16_t nb_pkts);
444 uint16_t enic_noscatter_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
445 uint16_t nb_pkts);
446 uint16_t enic_dummy_recv_pkts(void *rx_queue,
447 struct rte_mbuf **rx_pkts,
448 uint16_t nb_pkts);
449 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
450 uint16_t nb_pkts);
451 uint16_t enic_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
452 uint16_t nb_pkts);
453 uint16_t enic_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
454 uint16_t nb_pkts);
455 int enic_set_mtu(struct enic *enic, uint16_t new_mtu);
456 int enic_link_update(struct rte_eth_dev *eth_dev);
457 bool enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev);
458 void enic_pick_rx_handler(struct rte_eth_dev *eth_dev);
459 void enic_pick_tx_handler(struct rte_eth_dev *eth_dev);
460 void enic_fdir_info(struct enic *enic);
461 int enic_vf_representor_init(struct rte_eth_dev *eth_dev, void *init_params);
462 int enic_vf_representor_uninit(struct rte_eth_dev *ethdev);
463 int enic_fm_allocate_switch_domain(struct enic *pf);
464 int enic_fm_add_rep2vf_flow(struct enic_vf_representor *vf);
465 int enic_fm_add_vf2rep_flow(struct enic_vf_representor *vf);
466 int enic_alloc_rx_queue_mbufs(struct enic *enic, struct vnic_rq *rq);
467 void enic_rxmbuf_queue_release(struct enic *enic, struct vnic_rq *rq);
468 void enic_free_wq_buf(struct rte_mbuf **buf);
469 void enic_free_rq_buf(struct rte_mbuf **mbuf);
470 extern const struct rte_flow_ops enic_flow_ops;
471 extern const struct rte_flow_ops enic_fm_flow_ops;
472
473 #endif /* _ENIC_H_ */
474