1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_DEFS_H_ 7 #define RTE_PMD_MLX5_DEFS_H_ 8 9 #include <rte_ethdev_driver.h> 10 #include <rte_vxlan.h> 11 12 #include "mlx5_autoconf.h" 13 14 /* Maximum number of simultaneous VLAN filters. */ 15 #define MLX5_MAX_VLAN_IDS 128 16 17 /* 18 * Request TX completion every time descriptors reach this threshold since 19 * the previous request. Must be a power of two for performance reasons. 20 */ 21 #define MLX5_TX_COMP_THRESH 32u 22 23 /* 24 * Request TX completion every time the total number of WQEBBs used for inlining 25 * packets exceeds the size of WQ divided by this divisor. Better to be power of 26 * two for performance. 27 */ 28 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) 29 30 /* 31 * Maximal amount of normal completion CQEs 32 * processed in one call of tx_burst() routine. 33 */ 34 #define MLX5_TX_COMP_MAX_CQE 2u 35 36 37 /* Size of per-queue MR cache array for linear search. */ 38 #define MLX5_MR_CACHE_N 8 39 40 /* Size of MR cache table for binary search. */ 41 #define MLX5_MR_BTREE_CACHE_N 256 42 43 /* 44 * If defined, only use software counters. The PMD will never ask the hardware 45 * for these, and many of them won't be available. 46 */ 47 #ifndef MLX5_PMD_SOFT_COUNTERS 48 #define MLX5_PMD_SOFT_COUNTERS 1 49 #endif 50 51 /* Switch port ID parameters for bonding configurations. */ 52 #define MLX5_PORT_ID_BONDING_PF_MASK 0xf 53 #define MLX5_PORT_ID_BONDING_PF_SHIFT 12 54 55 /* Alarm timeout. */ 56 #define MLX5_ALARM_TIMEOUT_US 100000 57 58 /* Maximum number of extended statistics counters. */ 59 #define MLX5_MAX_XSTATS 32 60 61 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ 62 #define MLX5_MAX_TSO_HEADER (128u + 34u) 63 64 /* Inline data size required by NICs. */ 65 #define MLX5_INLINE_HSIZE_NONE 0 66 #define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \ 67 sizeof(struct rte_vlan_hdr)) 68 #define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \ 69 sizeof(struct rte_ipv6_hdr)) 70 #define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \ 71 sizeof(struct rte_tcp_hdr)) 72 #define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \ 73 sizeof(struct rte_udp_hdr) + \ 74 sizeof(struct rte_vxlan_hdr) + \ 75 sizeof(struct rte_ether_hdr) + \ 76 sizeof(struct rte_vlan_hdr)) 77 #define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \ 78 sizeof(struct rte_ipv6_hdr)) 79 #define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \ 80 sizeof(struct rte_tcp_hdr)) 81 82 /* Threshold of buffer replenishment for vectorized Rx. */ 83 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \ 84 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2)) 85 86 /* Maximum size of burst for vectorized Rx. */ 87 #define MLX5_VPMD_RX_MAX_BURST 64U 88 89 /* Recommended optimal burst size. */ 90 #define MLX5_RX_DEFAULT_BURST 64U 91 #define MLX5_TX_DEFAULT_BURST 64U 92 93 /* Number of packets vectorized Rx can simultaneously process in a loop. */ 94 #define MLX5_VPMD_DESCS_PER_LOOP 4 95 96 /* Mask of RSS on source only or destination only. */ 97 #define MLX5_RSS_SRC_DST_ONLY (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | \ 98 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY) 99 100 /* Supported RSS */ 101 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ 102 MLX5_RSS_SRC_DST_ONLY)) 103 104 /* Timeout in seconds to get a valid link status. */ 105 #define MLX5_LINK_STATUS_TIMEOUT 10 106 107 /* Number of times to retry retrieving the physical link information. */ 108 #define MLX5_GET_LINK_STATUS_RETRY_COUNT 3 109 110 /* Maximum number of UAR pages used by a port, 111 * These are the size and mask for an array of mutexes used to synchronize 112 * the access to port's UARs on platforms that do not support 64 bit writes. 113 * In such systems it is possible to issue the 64 bits DoorBells through two 114 * consecutive writes, each write 32 bits. The access to a UAR page (which can 115 * be accessible by all threads in the process) must be synchronized 116 * (for example, using a semaphore). Such a synchronization is not required 117 * when ringing DoorBells on different UAR pages. 118 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared 119 * among the ports. 120 */ 121 #define MLX5_UAR_PAGE_NUM_MAX 64 122 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) 123 124 /* Fields of memory mapping type in offset parameter of mmap() */ 125 #define MLX5_UAR_MMAP_CMD_SHIFT 8 126 #define MLX5_UAR_MMAP_CMD_MASK 0xff 127 128 /* Environment variable to control the doorbell register mapping. */ 129 #define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" 130 #if defined(RTE_ARCH_ARM64) 131 #define MLX5_SHUT_UP_BF_DEFAULT "0" 132 #else 133 #define MLX5_SHUT_UP_BF_DEFAULT "1" 134 #endif 135 136 #ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD 137 #define MLX5_MMAP_GET_NC_PAGES_CMD 3 138 #endif 139 140 /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ 141 #define MLX5_MPRQ_STRIDE_NUM_N 6U 142 143 /* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */ 144 #define MLX5_MPRQ_STRIDE_SIZE_N 11U 145 146 /* Two-byte shift is disabled for Multi-Packet RQ. */ 147 #define MLX5_MPRQ_TWO_BYTE_SHIFT 0 148 149 /* 150 * Minimum size of packet to be memcpy'd instead of being attached as an 151 * external buffer. 152 */ 153 #define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128 154 155 /* Minimum number Rx queues to enable Multi-Packet RQ. */ 156 #define MLX5_MPRQ_MIN_RXQS 12 157 158 /* Cache size of mempool for Multi-Packet RQ. */ 159 #define MLX5_MPRQ_MP_CACHE_SZ 32U 160 161 /* MLX5_DV_XMETA_EN supported values. */ 162 #define MLX5_XMETA_MODE_LEGACY 0 163 #define MLX5_XMETA_MODE_META16 1 164 #define MLX5_XMETA_MODE_META32 2 165 /* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */ 166 #define MLX5_XMETA_MODE_MISS_INFO 3 167 168 /* MLX5_TX_DB_NC supported values. */ 169 #define MLX5_TXDB_CACHED 0 170 #define MLX5_TXDB_NCACHED 1 171 #define MLX5_TXDB_HEURISTIC 2 172 173 /* Tx accurate scheduling on timestamps parameters. */ 174 #define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ 175 #define MLX5_TXPP_CLKQ_SIZE 1 176 #define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) 177 #define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ 178 MLX5_TXPP_REARM) * 2) 179 #define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2) 180 /* The minimal size test packet to put into one WQE, padded by HW. */ 181 #define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \ 182 sizeof(struct rte_ipv4_hdr)) 183 184 /* Size of the simple hash table for metadata register table. */ 185 #define MLX5_FLOW_MREG_HTABLE_SZ 4096 186 #define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" 187 #define MLX5_DEFAULT_COPY_ID UINT32_MAX 188 189 /* Size of the simple hash table for header modify table. */ 190 #define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 16) 191 192 /* Size of the simple hash table for encap decap table. */ 193 #define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 16) 194 195 /* Hairpin TX/RX queue configuration parameters. */ 196 #define MLX5_HAIRPIN_QUEUE_STRIDE 6 197 #define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) 198 199 /* Maximum number of shared actions supported by rte_flow */ 200 #define MLX5_MAX_SHARED_ACTIONS 2 201 202 /* Definition of static_assert found in /usr/include/assert.h */ 203 #ifndef HAVE_STATIC_ASSERT 204 #define static_assert _Static_assert 205 #endif 206 207 #endif /* RTE_PMD_MLX5_DEFS_H_ */ 208