1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1996 Gardner Buchanan <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Gardner Buchanan.
18 * 4. The name of Gardner Buchanan may not be used to endorse or promote
19 * products derived from this software without specific prior written
20 * permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 /*
38 * This is a driver for SMC's 9000 series of Ethernet adapters.
39 *
40 * This FreeBSD driver is derived from the smc9194 Linux driver by
41 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
42 * This driver also shamelessly borrows from the FreeBSD ep driver
43 * which is Copyright (C) 1994 Herb Peyerl <[email protected]>
44 * All rights reserved.
45 *
46 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
47 * PC. It is adapted from Erik Stahlman's Linux driver which worked
48 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
49 * it will work for the entire SMC 9xxx series. (Ha Ha)
50 *
51 * "Features" of the SMC chip:
52 * 4608 byte packet memory. (for the 91C92. Others have more)
53 * EEPROM for configuration
54 * AUI/TP selection
55 *
56 * Authors:
57 * Erik Stahlman [email protected]
58 * Herb Peyerl [email protected]
59 * Andres Vega Garcia [email protected]
60 * Serge Babkin [email protected]
61 * Gardner Buchanan [email protected]
62 *
63 * Sources:
64 * o SMC databook
65 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman ([email protected])"
66 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
67 *
68 * Known Bugs:
69 * o Setting of the hardware address isn't supported.
70 * o Hardware padding isn't used.
71 */
72
73 /*
74 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
75 *
76 * Copyright (c) 1996 by Tatsumi Hosokawa <[email protected]>
77 * BSD-nomads, Tokyo, Japan.
78 */
79 /*
80 * Multicast support by Kei TANAKA <[email protected]>
81 * Special thanks to [email protected]
82 */
83
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/errno.h>
87 #include <sys/kernel.h>
88 #include <sys/sockio.h>
89 #include <sys/malloc.h>
90 #include <sys/mbuf.h>
91 #include <sys/socket.h>
92 #include <sys/syslog.h>
93
94 #include <sys/module.h>
95 #include <sys/bus.h>
96
97 #include <machine/bus.h>
98 #include <machine/resource.h>
99 #include <sys/rman.h>
100
101 #include <net/ethernet.h>
102 #include <net/if.h>
103 #include <net/if_var.h>
104 #include <net/if_arp.h>
105 #include <net/if_dl.h>
106 #include <net/if_types.h>
107 #include <net/if_mib.h>
108
109 #ifdef INET
110 #include <netinet/in.h>
111 #include <netinet/in_systm.h>
112 #include <netinet/in_var.h>
113 #include <netinet/ip.h>
114 #endif
115
116 #include <net/bpf.h>
117 #include <net/bpfdesc.h>
118
119 #include <dev/sn/if_snreg.h>
120 #include <dev/sn/if_snvar.h>
121
122 /* Exported variables */
123 devclass_t sn_devclass;
124
125 static int snioctl(struct ifnet * ifp, u_long, caddr_t);
126
127 static void snresume(struct ifnet *);
128
129 static void snintr_locked(struct sn_softc *);
130 static void sninit_locked(void *);
131 static void snstart_locked(struct ifnet *);
132
133 static void sninit(void *);
134 static void snread(struct ifnet *);
135 static void snstart(struct ifnet *);
136 static void snstop(struct sn_softc *);
137 static void snwatchdog(void *);
138
139 static void sn_setmcast(struct sn_softc *);
140 static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
141
142 /* I (GB) have been unlucky getting the hardware padding
143 * to work properly.
144 */
145 #define SW_PAD
146
147 static const char *chip_ids[15] = {
148 NULL, NULL, NULL,
149 /* 3 */ "SMC91C90/91C92",
150 /* 4 */ "SMC91C94/91C96",
151 /* 5 */ "SMC91C95",
152 NULL,
153 /* 7 */ "SMC91C100",
154 /* 8 */ "SMC91C100FD",
155 /* 9 */ "SMC91C110",
156 NULL, NULL,
157 NULL, NULL, NULL
158 };
159
160 int
sn_attach(device_t dev)161 sn_attach(device_t dev)
162 {
163 struct sn_softc *sc = device_get_softc(dev);
164 struct ifnet *ifp;
165 uint16_t i;
166 uint8_t *p;
167 int rev;
168 uint16_t address;
169 int err;
170 u_char eaddr[6];
171
172 ifp = sc->ifp = if_alloc(IFT_ETHER);
173 if (ifp == NULL) {
174 device_printf(dev, "can not if_alloc()\n");
175 return (ENOSPC);
176 }
177
178 SN_LOCK_INIT(sc);
179 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
180 snstop(sc);
181 sc->pages_wanted = -1;
182
183 if (bootverbose || 1) {
184 SMC_SELECT_BANK(sc, 3);
185 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
186 if (chip_ids[rev])
187 device_printf(dev, " %s ", chip_ids[rev]);
188 else
189 device_printf(dev, " unsupported chip: rev %d ", rev);
190 SMC_SELECT_BANK(sc, 1);
191 i = CSR_READ_2(sc, CONFIG_REG_W);
192 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
193 }
194
195 /*
196 * Read the station address from the chip. The MAC address is bank 1,
197 * regs 4 - 9
198 */
199 SMC_SELECT_BANK(sc, 1);
200 p = (uint8_t *) eaddr;
201 for (i = 0; i < 6; i += 2) {
202 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
203 p[i + 1] = address >> 8;
204 p[i] = address & 0xFF;
205 }
206 ifp->if_softc = sc;
207 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
208 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
209 ifp->if_start = snstart;
210 ifp->if_ioctl = snioctl;
211 ifp->if_init = sninit;
212 ifp->if_baudrate = 10000000;
213 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
214 ifp->if_snd.ifq_maxlen = ifqmaxlen;
215 IFQ_SET_READY(&ifp->if_snd);
216
217 ether_ifattach(ifp, eaddr);
218
219 /*
220 * Activate the interrupt so we can get card interrupts. This
221 * needs to be done last so that we don't have/hold the lock
222 * during startup to avoid LORs in the network layer.
223 */
224 if ((err = bus_setup_intr(dev, sc->irq_res,
225 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
226 &sc->intrhand)) != 0) {
227 sn_detach(dev);
228 return err;
229 }
230
231 gone_by_fcp101_dev(dev);
232
233 return 0;
234 }
235
236
237 int
sn_detach(device_t dev)238 sn_detach(device_t dev)
239 {
240 struct sn_softc *sc = device_get_softc(dev);
241 struct ifnet *ifp = sc->ifp;
242
243 ether_ifdetach(ifp);
244 SN_LOCK(sc);
245 snstop(sc);
246 SN_UNLOCK(sc);
247 callout_drain(&sc->watchdog);
248 sn_deactivate(dev);
249 if_free(ifp);
250 SN_LOCK_DESTROY(sc);
251 return 0;
252 }
253
254 static void
sninit(void * xsc)255 sninit(void *xsc)
256 {
257 struct sn_softc *sc = xsc;
258 SN_LOCK(sc);
259 sninit_locked(sc);
260 SN_UNLOCK(sc);
261 }
262
263 /*
264 * Reset and initialize the chip
265 */
266 static void
sninit_locked(void * xsc)267 sninit_locked(void *xsc)
268 {
269 struct sn_softc *sc = xsc;
270 struct ifnet *ifp = sc->ifp;
271 int flags;
272 int mask;
273
274 SN_ASSERT_LOCKED(sc);
275
276 /*
277 * This resets the registers mostly to defaults, but doesn't affect
278 * EEPROM. After the reset cycle, we pause briefly for the chip to
279 * be happy.
280 */
281 SMC_SELECT_BANK(sc, 0);
282 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
283 SMC_DELAY(sc);
284 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
285 SMC_DELAY(sc);
286 SMC_DELAY(sc);
287
288 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
289
290 /*
291 * Set the control register to automatically release successfully
292 * transmitted packets (making the best use out of our limited
293 * memory) and to enable the EPH interrupt on certain TX errors.
294 */
295 SMC_SELECT_BANK(sc, 1);
296 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
297 CTR_CR_ENABLE | CTR_LE_ENABLE));
298
299 /* Set squelch level to 240mV (default 480mV) */
300 flags = CSR_READ_2(sc, CONFIG_REG_W);
301 flags |= CR_SET_SQLCH;
302 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
303
304 /*
305 * Reset the MMU and wait for it to be un-busy.
306 */
307 SMC_SELECT_BANK(sc, 2);
308 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
309 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
310 ;
311
312 /*
313 * Disable all interrupts
314 */
315 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
316
317 sn_setmcast(sc);
318
319 /*
320 * Set the transmitter control. We want it enabled.
321 */
322 flags = TCR_ENABLE;
323
324 #ifndef SW_PAD
325 /*
326 * I (GB) have been unlucky getting this to work.
327 */
328 flags |= TCR_PAD_ENABLE;
329 #endif /* SW_PAD */
330
331 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
332
333
334 /*
335 * Now, enable interrupts
336 */
337 SMC_SELECT_BANK(sc, 2);
338
339 mask = IM_EPH_INT |
340 IM_RX_OVRN_INT |
341 IM_RCV_INT |
342 IM_TX_INT;
343
344 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
345 sc->intr_mask = mask;
346 sc->pages_wanted = -1;
347
348
349 /*
350 * Mark the interface running but not active.
351 */
352 ifp->if_drv_flags |= IFF_DRV_RUNNING;
353 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
354 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
355
356 /*
357 * Attempt to push out any waiting packets.
358 */
359 snstart_locked(ifp);
360 }
361
362 static void
snstart(struct ifnet * ifp)363 snstart(struct ifnet *ifp)
364 {
365 struct sn_softc *sc = ifp->if_softc;
366 SN_LOCK(sc);
367 snstart_locked(ifp);
368 SN_UNLOCK(sc);
369 }
370
371
372 static void
snstart_locked(struct ifnet * ifp)373 snstart_locked(struct ifnet *ifp)
374 {
375 struct sn_softc *sc = ifp->if_softc;
376 u_int len;
377 struct mbuf *m;
378 struct mbuf *top;
379 int pad;
380 int mask;
381 uint16_t length;
382 uint16_t numPages;
383 uint8_t packet_no;
384 int time_out;
385 int junk = 0;
386
387 SN_ASSERT_LOCKED(sc);
388
389 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
390 return;
391 if (sc->pages_wanted != -1) {
392 if_printf(ifp, "snstart() while memory allocation pending\n");
393 return;
394 }
395 startagain:
396
397 /*
398 * Sneak a peek at the next packet
399 */
400 m = ifp->if_snd.ifq_head;
401 if (m == NULL)
402 return;
403 /*
404 * Compute the frame length and set pad to give an overall even
405 * number of bytes. Below we assume that the packet length is even.
406 */
407 for (len = 0, top = m; m; m = m->m_next)
408 len += m->m_len;
409
410 pad = (len & 1);
411
412 /*
413 * We drop packets that are too large. Perhaps we should truncate
414 * them instead?
415 */
416 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
417 if_printf(ifp, "large packet discarded (A)\n");
418 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
419 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
420 m_freem(m);
421 goto readcheck;
422 }
423 #ifdef SW_PAD
424
425 /*
426 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
427 */
428 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
429 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
430
431 #endif /* SW_PAD */
432
433 length = pad + len;
434
435 /*
436 * The MMU wants the number of pages to be the number of 256 byte
437 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
438 * include space for the status word, byte count and control bytes in
439 * the allocation request.
440 */
441 numPages = (length + 6) >> 8;
442
443
444 /*
445 * Now, try to allocate the memory
446 */
447 SMC_SELECT_BANK(sc, 2);
448 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
449
450 /*
451 * Wait a short amount of time to see if the allocation request
452 * completes. Otherwise, I enable the interrupt and wait for
453 * completion asynchronously.
454 */
455
456 time_out = MEMORY_WAIT_TIME;
457 do {
458 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
459 break;
460 } while (--time_out);
461
462 if (!time_out || junk > 10) {
463
464 /*
465 * No memory now. Oh well, wait until the chip finds memory
466 * later. Remember how many pages we were asking for and
467 * enable the allocation completion interrupt. Also set a
468 * watchdog in case we miss the interrupt. We mark the
469 * interface active since there is no point in attempting an
470 * snstart() until after the memory is available.
471 */
472 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
473 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
474 sc->intr_mask = mask;
475
476 sc->timer = 1;
477 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
478 sc->pages_wanted = numPages;
479 return;
480 }
481 /*
482 * The memory allocation completed. Check the results.
483 */
484 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
485 if (packet_no & ARR_FAILED) {
486 if (junk++ > 10)
487 if_printf(ifp, "Memory allocation failed\n");
488 goto startagain;
489 }
490 /*
491 * We have a packet number, so tell the card to use it.
492 */
493 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
494
495 /*
496 * Point to the beginning of the packet
497 */
498 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
499
500 /*
501 * Send the packet length (+6 for status, length and control byte)
502 * and the status word (set to zeros)
503 */
504 CSR_WRITE_2(sc, DATA_REG_W, 0);
505 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
506 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
507
508 /*
509 * Get the packet from the kernel. This will include the Ethernet
510 * frame header, MAC Addresses etc.
511 */
512 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
513
514 /*
515 * Push out the data to the card.
516 */
517 for (top = m; m != NULL; m = m->m_next) {
518
519 /*
520 * Push out words.
521 */
522 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
523 m->m_len / 2);
524
525 /*
526 * Push out remaining byte.
527 */
528 if (m->m_len & 1)
529 CSR_WRITE_1(sc, DATA_REG_B,
530 *(mtod(m, caddr_t) + m->m_len - 1));
531 }
532
533 /*
534 * Push out padding.
535 */
536 while (pad > 1) {
537 CSR_WRITE_2(sc, DATA_REG_W, 0);
538 pad -= 2;
539 }
540 if (pad)
541 CSR_WRITE_1(sc, DATA_REG_B, 0);
542
543 /*
544 * Push out control byte and unused packet byte The control byte is 0
545 * meaning the packet is even lengthed and no special CRC handling is
546 * desired.
547 */
548 CSR_WRITE_2(sc, DATA_REG_W, 0);
549
550 /*
551 * Enable the interrupts and let the chipset deal with it Also set a
552 * watchdog in case we miss the interrupt.
553 */
554 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
555 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
556 sc->intr_mask = mask;
557
558 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
559
560 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
561 sc->timer = 1;
562
563 BPF_MTAP(ifp, top);
564
565 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
566 m_freem(top);
567
568
569 readcheck:
570
571 /*
572 * Is another packet coming in? We don't want to overflow the tiny
573 * RX FIFO. If nothing has arrived then attempt to queue another
574 * transmit packet.
575 */
576 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
577 goto startagain;
578 return;
579 }
580
581
582
583 /* Resume a packet transmit operation after a memory allocation
584 * has completed.
585 *
586 * This is basically a hacked up copy of snstart() which handles
587 * a completed memory allocation the same way snstart() does.
588 * It then passes control to snstart to handle any other queued
589 * packets.
590 */
591 static void
snresume(struct ifnet * ifp)592 snresume(struct ifnet *ifp)
593 {
594 struct sn_softc *sc = ifp->if_softc;
595 u_int len;
596 struct mbuf *m;
597 struct mbuf *top;
598 int pad;
599 int mask;
600 uint16_t length;
601 uint16_t numPages;
602 uint16_t pages_wanted;
603 uint8_t packet_no;
604
605 if (sc->pages_wanted < 0)
606 return;
607
608 pages_wanted = sc->pages_wanted;
609 sc->pages_wanted = -1;
610
611 /*
612 * Sneak a peek at the next packet
613 */
614 m = ifp->if_snd.ifq_head;
615 if (m == NULL) {
616 if_printf(ifp, "snresume() with nothing to send\n");
617 return;
618 }
619 /*
620 * Compute the frame length and set pad to give an overall even
621 * number of bytes. Below we assume that the packet length is even.
622 */
623 for (len = 0, top = m; m; m = m->m_next)
624 len += m->m_len;
625
626 pad = (len & 1);
627
628 /*
629 * We drop packets that are too large. Perhaps we should truncate
630 * them instead?
631 */
632 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
633 if_printf(ifp, "large packet discarded (B)\n");
634 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
635 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
636 m_freem(m);
637 return;
638 }
639 #ifdef SW_PAD
640
641 /*
642 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
643 */
644 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
645 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
646
647 #endif /* SW_PAD */
648
649 length = pad + len;
650
651
652 /*
653 * The MMU wants the number of pages to be the number of 256 byte
654 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
655 * include space for the status word, byte count and control bytes in
656 * the allocation request.
657 */
658 numPages = (length + 6) >> 8;
659
660
661 SMC_SELECT_BANK(sc, 2);
662
663 /*
664 * The memory allocation completed. Check the results. If it failed,
665 * we simply set a watchdog timer and hope for the best.
666 */
667 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
668 if (packet_no & ARR_FAILED) {
669 if_printf(ifp, "Memory allocation failed. Weird.\n");
670 sc->timer = 1;
671 goto try_start;
672 }
673 /*
674 * We have a packet number, so tell the card to use it.
675 */
676 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
677
678 /*
679 * Now, numPages should match the pages_wanted recorded when the
680 * memory allocation was initiated.
681 */
682 if (pages_wanted != numPages) {
683 if_printf(ifp, "memory allocation wrong size. Weird.\n");
684 /*
685 * If the allocation was the wrong size we simply release the
686 * memory once it is granted. Wait for the MMU to be un-busy.
687 */
688 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
689 ;
690 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
691
692 return;
693 }
694 /*
695 * Point to the beginning of the packet
696 */
697 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
698
699 /*
700 * Send the packet length (+6 for status, length and control byte)
701 * and the status word (set to zeros)
702 */
703 CSR_WRITE_2(sc, DATA_REG_W, 0);
704 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
705 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
706
707 /*
708 * Get the packet from the kernel. This will include the Ethernet
709 * frame header, MAC Addresses etc.
710 */
711 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
712
713 /*
714 * Push out the data to the card.
715 */
716 for (top = m; m != NULL; m = m->m_next) {
717
718 /*
719 * Push out words.
720 */
721 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
722 m->m_len / 2);
723 /*
724 * Push out remaining byte.
725 */
726 if (m->m_len & 1)
727 CSR_WRITE_1(sc, DATA_REG_B,
728 *(mtod(m, caddr_t) + m->m_len - 1));
729 }
730
731 /*
732 * Push out padding.
733 */
734 while (pad > 1) {
735 CSR_WRITE_2(sc, DATA_REG_W, 0);
736 pad -= 2;
737 }
738 if (pad)
739 CSR_WRITE_1(sc, DATA_REG_B, 0);
740
741 /*
742 * Push out control byte and unused packet byte The control byte is 0
743 * meaning the packet is even lengthed and no special CRC handling is
744 * desired.
745 */
746 CSR_WRITE_2(sc, DATA_REG_W, 0);
747
748 /*
749 * Enable the interrupts and let the chipset deal with it Also set a
750 * watchdog in case we miss the interrupt.
751 */
752 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
753 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
754 sc->intr_mask = mask;
755 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
756
757 BPF_MTAP(ifp, top);
758
759 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
760 m_freem(top);
761
762 try_start:
763
764 /*
765 * Now pass control to snstart() to queue any additional packets
766 */
767 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
768 snstart_locked(ifp);
769
770 /*
771 * We've sent something, so we're active. Set a watchdog in case the
772 * TX_EMPTY interrupt is lost.
773 */
774 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
775 sc->timer = 1;
776
777 return;
778 }
779
780 void
sn_intr(void * arg)781 sn_intr(void *arg)
782 {
783 struct sn_softc *sc = (struct sn_softc *) arg;
784
785 SN_LOCK(sc);
786 snintr_locked(sc);
787 SN_UNLOCK(sc);
788 }
789
790 static void
snintr_locked(struct sn_softc * sc)791 snintr_locked(struct sn_softc *sc)
792 {
793 int status, interrupts;
794 struct ifnet *ifp = sc->ifp;
795
796 /*
797 * Chip state registers
798 */
799 uint8_t mask;
800 uint8_t packet_no;
801 uint16_t tx_status;
802 uint16_t card_stats;
803
804 /*
805 * Clear the watchdog.
806 */
807 sc->timer = 0;
808
809 SMC_SELECT_BANK(sc, 2);
810
811 /*
812 * Obtain the current interrupt mask and clear the hardware mask
813 * while servicing interrupts.
814 */
815 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
816 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
817
818 /*
819 * Get the set of interrupts which occurred and eliminate any which
820 * are masked.
821 */
822 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
823 status = interrupts & mask;
824
825 /*
826 * Now, process each of the interrupt types.
827 */
828
829 /*
830 * Receive Overrun.
831 */
832 if (status & IM_RX_OVRN_INT) {
833 /*
834 * Acknowlege Interrupt
835 */
836 SMC_SELECT_BANK(sc, 2);
837 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
838
839 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
840 }
841 /*
842 * Got a packet.
843 */
844 if (status & IM_RCV_INT) {
845 int packet_number;
846
847 SMC_SELECT_BANK(sc, 2);
848 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
849
850 if (packet_number & FIFO_REMPTY) {
851 /*
852 * we got called , but nothing was on the FIFO
853 */
854 printf("sn: Receive interrupt with nothing on FIFO\n");
855 goto out;
856 }
857 snread(ifp);
858 }
859 /*
860 * An on-card memory allocation came through.
861 */
862 if (status & IM_ALLOC_INT) {
863 /*
864 * Disable this interrupt.
865 */
866 mask &= ~IM_ALLOC_INT;
867 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
868 snresume(ifp);
869 }
870 /*
871 * TX Completion. Handle a transmit error message. This will only be
872 * called when there is an error, because of the AUTO_RELEASE mode.
873 */
874 if (status & IM_TX_INT) {
875 /*
876 * Acknowlege Interrupt
877 */
878 SMC_SELECT_BANK(sc, 2);
879 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
880
881 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
882 packet_no &= FIFO_TX_MASK;
883
884 /*
885 * select this as the packet to read from
886 */
887 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
888
889 /*
890 * Position the pointer to the first word from this packet
891 */
892 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
893
894 /*
895 * Fetch the TX status word. The value found here will be a
896 * copy of the EPH_STATUS_REG_W at the time the transmit
897 * failed.
898 */
899 tx_status = CSR_READ_2(sc, DATA_REG_W);
900
901 if (tx_status & EPHSR_TX_SUC) {
902 device_printf(sc->dev,
903 "Successful packet caused interrupt\n");
904 } else {
905 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
906 }
907
908 if (tx_status & EPHSR_LATCOL)
909 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
910
911 /*
912 * Some of these errors will have disabled transmit.
913 * Re-enable transmit now.
914 */
915 SMC_SELECT_BANK(sc, 0);
916
917 #ifdef SW_PAD
918 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
919 #else
920 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
921 #endif /* SW_PAD */
922
923 /*
924 * kill the failed packet. Wait for the MMU to be un-busy.
925 */
926 SMC_SELECT_BANK(sc, 2);
927 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
928 ;
929 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
930
931 /*
932 * Attempt to queue more transmits.
933 */
934 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
935 snstart_locked(ifp);
936 }
937 /*
938 * Transmit underrun. We use this opportunity to update transmit
939 * statistics from the card.
940 */
941 if (status & IM_TX_EMPTY_INT) {
942
943 /*
944 * Acknowlege Interrupt
945 */
946 SMC_SELECT_BANK(sc, 2);
947 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
948
949 /*
950 * Disable this interrupt.
951 */
952 mask &= ~IM_TX_EMPTY_INT;
953
954 SMC_SELECT_BANK(sc, 0);
955 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
956
957 /*
958 * Single collisions
959 */
960 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, card_stats & ECR_COLN_MASK);
961
962 /*
963 * Multiple collisions
964 */
965 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (card_stats & ECR_MCOLN_MASK) >> 4);
966
967 SMC_SELECT_BANK(sc, 2);
968
969 /*
970 * Attempt to enqueue some more stuff.
971 */
972 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
973 snstart_locked(ifp);
974 }
975 /*
976 * Some other error. Try to fix it by resetting the adapter.
977 */
978 if (status & IM_EPH_INT) {
979 snstop(sc);
980 sninit_locked(sc);
981 }
982
983 out:
984 /*
985 * Handled all interrupt sources.
986 */
987
988 SMC_SELECT_BANK(sc, 2);
989
990 /*
991 * Reestablish interrupts from mask which have not been deselected
992 * during this interrupt. Note that the hardware mask, which was set
993 * to 0x00 at the start of this service routine, may have been
994 * updated by one or more of the interrupt handers and we must let
995 * those new interrupts stay enabled here.
996 */
997 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
998 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
999 sc->intr_mask = mask;
1000 }
1001
1002 static void
snread(struct ifnet * ifp)1003 snread(struct ifnet *ifp)
1004 {
1005 struct sn_softc *sc = ifp->if_softc;
1006 struct ether_header *eh;
1007 struct mbuf *m;
1008 short status;
1009 int packet_number;
1010 uint16_t packet_length;
1011 uint8_t *data;
1012
1013 SMC_SELECT_BANK(sc, 2);
1014 #if 0
1015 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1016
1017 if (packet_number & FIFO_REMPTY) {
1018
1019 /*
1020 * we got called , but nothing was on the FIFO
1021 */
1022 printf("sn: Receive interrupt with nothing on FIFO\n");
1023 return;
1024 }
1025 #endif
1026 read_another:
1027
1028 /*
1029 * Start reading from the start of the packet. Since PTR_RCV is set,
1030 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1031 */
1032 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1033
1034 /*
1035 * First two words are status and packet_length
1036 */
1037 status = CSR_READ_2(sc, DATA_REG_W);
1038 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1039
1040 /*
1041 * The packet length contains 3 extra words: status, length, and a
1042 * extra word with the control byte.
1043 */
1044 packet_length -= 6;
1045
1046 /*
1047 * Account for receive errors and discard.
1048 */
1049 if (status & RS_ERRORS) {
1050 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1051 goto out;
1052 }
1053 /*
1054 * A packet is received.
1055 */
1056
1057 /*
1058 * Adjust for odd-length packet.
1059 */
1060 if (status & RS_ODDFRAME)
1061 packet_length++;
1062
1063 /*
1064 * Allocate a header mbuf from the kernel.
1065 */
1066 MGETHDR(m, M_NOWAIT, MT_DATA);
1067 if (m == NULL)
1068 goto out;
1069
1070 m->m_pkthdr.rcvif = ifp;
1071 m->m_pkthdr.len = m->m_len = packet_length;
1072
1073 /*
1074 * Attach an mbuf cluster.
1075 */
1076 if (!(MCLGET(m, M_NOWAIT))) {
1077 m_freem(m);
1078 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1079 printf("sn: snread() kernel memory allocation problem\n");
1080 goto out;
1081 }
1082 eh = mtod(m, struct ether_header *);
1083
1084 /*
1085 * Get packet, including link layer address, from interface.
1086 */
1087 data = (uint8_t *) eh;
1088 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1089 if (packet_length & 1) {
1090 data += packet_length & ~1;
1091 *data = CSR_READ_1(sc, DATA_REG_B);
1092 }
1093 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1094
1095 /*
1096 * Remove link layer addresses and whatnot.
1097 */
1098 m->m_pkthdr.len = m->m_len = packet_length;
1099
1100 /*
1101 * Drop locks before calling if_input() since it may re-enter
1102 * snstart() in the netisr case. This would result in a
1103 * lock reversal. Better performance might be obtained by
1104 * chaining all packets received, dropping the lock, and then
1105 * calling if_input() on each one.
1106 */
1107 SN_UNLOCK(sc);
1108 (*ifp->if_input)(ifp, m);
1109 SN_LOCK(sc);
1110
1111 out:
1112
1113 /*
1114 * Error or good, tell the card to get rid of this packet Wait for
1115 * the MMU to be un-busy.
1116 */
1117 SMC_SELECT_BANK(sc, 2);
1118 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1119 ;
1120 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1121
1122 /*
1123 * Check whether another packet is ready
1124 */
1125 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1126 if (packet_number & FIFO_REMPTY) {
1127 return;
1128 }
1129 goto read_another;
1130 }
1131
1132
1133 /*
1134 * Handle IOCTLS. This function is completely stolen from if_ep.c
1135 * As with its progenitor, it does not handle hardware address
1136 * changes.
1137 */
1138 static int
snioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1139 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1140 {
1141 struct sn_softc *sc = ifp->if_softc;
1142 int error = 0;
1143
1144 switch (cmd) {
1145 case SIOCSIFFLAGS:
1146 SN_LOCK(sc);
1147 if ((ifp->if_flags & IFF_UP) == 0 &&
1148 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1149 snstop(sc);
1150 } else {
1151 /* reinitialize card on any parameter change */
1152 sninit_locked(sc);
1153 }
1154 SN_UNLOCK(sc);
1155 break;
1156
1157 case SIOCADDMULTI:
1158 case SIOCDELMULTI:
1159 /* update multicast filter list. */
1160 SN_LOCK(sc);
1161 sn_setmcast(sc);
1162 error = 0;
1163 SN_UNLOCK(sc);
1164 break;
1165 default:
1166 error = ether_ioctl(ifp, cmd, data);
1167 break;
1168 }
1169 return (error);
1170 }
1171
1172 static void
snwatchdog(void * arg)1173 snwatchdog(void *arg)
1174 {
1175 struct sn_softc *sc;
1176
1177 sc = arg;
1178 SN_ASSERT_LOCKED(sc);
1179 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1180 if (sc->timer == 0 || --sc->timer > 0)
1181 return;
1182 snintr_locked(sc);
1183 }
1184
1185
1186 /* 1. zero the interrupt mask
1187 * 2. clear the enable receive flag
1188 * 3. clear the enable xmit flags
1189 */
1190 static void
snstop(struct sn_softc * sc)1191 snstop(struct sn_softc *sc)
1192 {
1193
1194 struct ifnet *ifp = sc->ifp;
1195
1196 /*
1197 * Clear interrupt mask; disable all interrupts.
1198 */
1199 SMC_SELECT_BANK(sc, 2);
1200 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1201
1202 /*
1203 * Disable transmitter and Receiver
1204 */
1205 SMC_SELECT_BANK(sc, 0);
1206 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1207 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1208
1209 /*
1210 * Cancel watchdog.
1211 */
1212 sc->timer = 0;
1213 callout_stop(&sc->watchdog);
1214 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1215 }
1216
1217
1218 int
sn_activate(device_t dev)1219 sn_activate(device_t dev)
1220 {
1221 struct sn_softc *sc = device_get_softc(dev);
1222
1223 sc->port_rid = 0;
1224 sc->port_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1225 &sc->port_rid, SMC_IO_EXTENT, RF_ACTIVE);
1226 if (!sc->port_res) {
1227 if (bootverbose)
1228 device_printf(dev, "Cannot allocate ioport\n");
1229 return ENOMEM;
1230 }
1231
1232 sc->irq_rid = 0;
1233 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1234 RF_ACTIVE);
1235 if (!sc->irq_res) {
1236 if (bootverbose)
1237 device_printf(dev, "Cannot allocate irq\n");
1238 sn_deactivate(dev);
1239 return ENOMEM;
1240 }
1241 return (0);
1242 }
1243
1244 void
sn_deactivate(device_t dev)1245 sn_deactivate(device_t dev)
1246 {
1247 struct sn_softc *sc = device_get_softc(dev);
1248
1249 if (sc->intrhand)
1250 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1251 sc->intrhand = 0;
1252 if (sc->port_res)
1253 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1254 sc->port_res);
1255 sc->port_res = 0;
1256 if (sc->modem_res)
1257 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1258 sc->modem_res);
1259 sc->modem_res = 0;
1260 if (sc->irq_res)
1261 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1262 sc->irq_res);
1263 sc->irq_res = 0;
1264 return;
1265 }
1266
1267 /*
1268 * Function: sn_probe(device_t dev)
1269 *
1270 * Purpose:
1271 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1272 * Tries to cause as little damage as possible if it's not a SMC chip.
1273 * Returns a 0 on success
1274 *
1275 * Algorithm:
1276 * (1) see if the high byte of BANK_SELECT is 0x33
1277 * (2) compare the ioaddr with the base register's address
1278 * (3) see if I recognize the chip ID in the appropriate register
1279 *
1280 *
1281 */
1282 int
sn_probe(device_t dev)1283 sn_probe(device_t dev)
1284 {
1285 struct sn_softc *sc = device_get_softc(dev);
1286 uint16_t bank;
1287 uint16_t revision_register;
1288 uint16_t base_address_register;
1289 int err;
1290
1291 if ((err = sn_activate(dev)) != 0)
1292 return err;
1293
1294 /*
1295 * First, see if the high byte is 0x33
1296 */
1297 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1298 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1299 #ifdef SN_DEBUG
1300 device_printf(dev, "test1 failed\n");
1301 #endif
1302 goto error;
1303 }
1304 /*
1305 * The above MIGHT indicate a device, but I need to write to further
1306 * test this. Go to bank 0, then test that the register still
1307 * reports the high byte is 0x33.
1308 */
1309 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1310 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1311 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1312 #ifdef SN_DEBUG
1313 device_printf(dev, "test2 failed\n");
1314 #endif
1315 goto error;
1316 }
1317 /*
1318 * well, we've already written once, so hopefully another time won't
1319 * hurt. This time, I need to switch the bank register to bank 1, so
1320 * I can access the base address register. The contents of the
1321 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1322 * to match the I/O port address where the adapter is being probed.
1323 */
1324 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1325 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1326
1327 if (rman_get_start(sc->port_res) != base_address_register) {
1328
1329 /*
1330 * Well, the base address register didn't match. Must not
1331 * have been a SMC chip after all.
1332 */
1333 #ifdef SN_DEBUG
1334 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1335 "base_address_register = 0x%x\n",
1336 rman_get_start(sc->port_res), base_address_register);
1337 #endif
1338 goto error;
1339 }
1340
1341 /*
1342 * Check if the revision register is something that I recognize.
1343 * These might need to be added to later, as future revisions could
1344 * be added.
1345 */
1346 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1347 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1348 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1349
1350 /*
1351 * I don't regonize this chip, so...
1352 */
1353 #ifdef SN_DEBUG
1354 device_printf(dev, "test4 failed\n");
1355 #endif
1356 goto error;
1357 }
1358
1359 /*
1360 * at this point I'll assume that the chip is an SMC9xxx. It might be
1361 * prudent to check a listing of MAC addresses against the hardware
1362 * address, or do some other tests.
1363 */
1364 sn_deactivate(dev);
1365 return 0;
1366 error:
1367 sn_deactivate(dev);
1368 return ENXIO;
1369 }
1370
1371 #define MCFSZ 8
1372
1373 static void
sn_setmcast(struct sn_softc * sc)1374 sn_setmcast(struct sn_softc *sc)
1375 {
1376 struct ifnet *ifp = sc->ifp;
1377 int flags;
1378 uint8_t mcf[MCFSZ];
1379
1380 SN_ASSERT_LOCKED(sc);
1381
1382 /*
1383 * Set the receiver filter. We want receive enabled and auto strip
1384 * of CRC from received packet. If we are promiscuous then set that
1385 * bit too.
1386 */
1387 flags = RCR_ENABLE | RCR_STRIP_CRC;
1388
1389 if (ifp->if_flags & IFF_PROMISC) {
1390 flags |= RCR_PROMISC | RCR_ALMUL;
1391 } else if (ifp->if_flags & IFF_ALLMULTI) {
1392 flags |= RCR_ALMUL;
1393 } else {
1394 if (sn_getmcf(ifp, mcf)) {
1395 /* set filter */
1396 SMC_SELECT_BANK(sc, 3);
1397 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1398 ((uint16_t)mcf[1] << 8) | mcf[0]);
1399 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1400 ((uint16_t)mcf[3] << 8) | mcf[2]);
1401 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1402 ((uint16_t)mcf[5] << 8) | mcf[4]);
1403 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1404 ((uint16_t)mcf[7] << 8) | mcf[6]);
1405 } else {
1406 flags |= RCR_ALMUL;
1407 }
1408 }
1409 SMC_SELECT_BANK(sc, 0);
1410 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1411 }
1412
1413 static int
sn_getmcf(struct ifnet * ifp,uint8_t * mcf)1414 sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1415 {
1416 int i;
1417 uint32_t index, index2;
1418 uint8_t *af = mcf;
1419 struct ifmultiaddr *ifma;
1420
1421 bzero(mcf, MCFSZ);
1422
1423 if_maddr_rlock(ifp);
1424 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1425 if (ifma->ifma_addr->sa_family != AF_LINK) {
1426 if_maddr_runlock(ifp);
1427 return 0;
1428 }
1429 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1430 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1431 index2 = 0;
1432 for (i = 0; i < 6; i++) {
1433 index2 <<= 1;
1434 index2 |= (index & 0x01);
1435 index >>= 1;
1436 }
1437 af[index2 >> 3] |= 1 << (index2 & 7);
1438 }
1439 if_maddr_runlock(ifp);
1440 return 1; /* use multicast filter */
1441 }
1442