1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 #ifndef _I40E_TYPE_H_
6 #define _I40E_TYPE_H_
7
8 #include "i40e_status.h"
9 #include "i40e_osdep.h"
10 #include "i40e_register.h"
11 #include "i40e_adminq.h"
12 #include "i40e_hmc.h"
13 #include "i40e_lan_hmc.h"
14 #include "i40e_devids.h"
15
16 #define UNREFERENCED_XPARAMETER
17 #define UNREFERENCED_1PARAMETER(_p) (_p);
18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
22
23 #ifndef LINUX_MACROS
24 #ifndef BIT
25 #define BIT(a) (1UL << (a))
26 #endif /* BIT */
27 #ifndef BIT_ULL
28 #define BIT_ULL(a) (1ULL << (a))
29 #endif /* BIT_ULL */
30 #endif /* LINUX_MACROS */
31
32 #ifndef I40E_MASK
33 /* I40E_MASK is a macro used on 32 bit registers */
34 #define I40E_MASK(mask, shift) (mask << shift)
35 #endif
36
37 #define I40E_MAX_PF 16
38 #define I40E_MAX_PF_VSI 64
39 #define I40E_MAX_PF_QP 128
40 #define I40E_MAX_VSI_QP 16
41 #define I40E_MAX_VF_VSI 4
42 #define I40E_MAX_CHAINED_RX_BUFFERS 5
43 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
44
45 /* something less than 1 minute */
46 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
47
48 /* Max default timeout in ms, */
49 #define I40E_MAX_NVM_TIMEOUT 18000
50
51 /* Max timeout in ms for the phy to respond */
52 #define I40E_MAX_PHY_TIMEOUT 500
53
54 /* Check whether address is multicast. */
55 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
56
57 /* Check whether an address is broadcast. */
58 #define I40E_IS_BROADCAST(address) \
59 ((((u8 *)(address))[0] == ((u8)0xff)) && \
60 (((u8 *)(address))[1] == ((u8)0xff)))
61
62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
63 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
64
65 /* forward declaration */
66 struct i40e_hw;
67 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
68
69 #ifndef ETH_ALEN
70 #define ETH_ALEN 6
71 #endif
72 /* Data type manipulation macros. */
73 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
74 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
75
76 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
77 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
78
79 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
80 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
81
82 /* Number of Transmit Descriptors must be a multiple of 32. */
83 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 32
84 /* Number of Receive Descriptors must be a multiple of 32 if
85 * the number of descriptors is greater than 32.
86 */
87 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
88
89 #define I40E_DESC_UNUSED(R) \
90 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
91 (R)->next_to_clean - (R)->next_to_use - 1)
92
93 /* bitfields for Tx queue mapping in QTX_CTL */
94 #define I40E_QTX_CTL_VF_QUEUE 0x0
95 #define I40E_QTX_CTL_VM_QUEUE 0x1
96 #define I40E_QTX_CTL_PF_QUEUE 0x2
97
98 /* debug masks - set these bits in hw->debug_mask to control output */
99 enum i40e_debug_mask {
100 I40E_DEBUG_INIT = 0x00000001,
101 I40E_DEBUG_RELEASE = 0x00000002,
102
103 I40E_DEBUG_LINK = 0x00000010,
104 I40E_DEBUG_PHY = 0x00000020,
105 I40E_DEBUG_HMC = 0x00000040,
106 I40E_DEBUG_NVM = 0x00000080,
107 I40E_DEBUG_LAN = 0x00000100,
108 I40E_DEBUG_FLOW = 0x00000200,
109 I40E_DEBUG_DCB = 0x00000400,
110 I40E_DEBUG_DIAG = 0x00000800,
111 I40E_DEBUG_FD = 0x00001000,
112 I40E_DEBUG_PACKAGE = 0x00002000,
113
114 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
115 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
116 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
117 I40E_DEBUG_AQ_COMMAND = 0x06000000,
118 I40E_DEBUG_AQ = 0x0F000000,
119
120 I40E_DEBUG_USER = 0xF0000000,
121
122 I40E_DEBUG_ALL = 0xFFFFFFFF
123 };
124
125 /* PCI Bus Info */
126 #define I40E_PCI_LINK_STATUS 0xB2
127 #define I40E_PCI_LINK_WIDTH 0x3F0
128 #define I40E_PCI_LINK_WIDTH_1 0x10
129 #define I40E_PCI_LINK_WIDTH_2 0x20
130 #define I40E_PCI_LINK_WIDTH_4 0x40
131 #define I40E_PCI_LINK_WIDTH_8 0x80
132 #define I40E_PCI_LINK_SPEED 0xF
133 #define I40E_PCI_LINK_SPEED_2500 0x1
134 #define I40E_PCI_LINK_SPEED_5000 0x2
135 #define I40E_PCI_LINK_SPEED_8000 0x3
136
137 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
138 I40E_GLGEN_MSCA_STCODE_SHIFT)
139 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
140 I40E_GLGEN_MSCA_OPCODE_SHIFT)
141 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
142 I40E_GLGEN_MSCA_OPCODE_SHIFT)
143
144 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
145 I40E_GLGEN_MSCA_STCODE_SHIFT)
146 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
147 I40E_GLGEN_MSCA_OPCODE_SHIFT)
148 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
149 I40E_GLGEN_MSCA_OPCODE_SHIFT)
150 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
151 I40E_GLGEN_MSCA_OPCODE_SHIFT)
152 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
153 I40E_GLGEN_MSCA_OPCODE_SHIFT)
154
155 #define I40E_PHY_COM_REG_PAGE 0x1E
156 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
157 #define I40E_PHY_LED_MANUAL_ON 0x100
158 #define I40E_PHY_LED_PROV_REG_1 0xC430
159 #define I40E_PHY_LED_MODE_MASK 0xFFFF
160 #define I40E_PHY_LED_MODE_ORIG 0x80000000
161
162 /* Memory types */
163 enum i40e_memset_type {
164 I40E_NONDMA_MEM = 0,
165 I40E_DMA_MEM
166 };
167
168 /* Memcpy types */
169 enum i40e_memcpy_type {
170 I40E_NONDMA_TO_NONDMA = 0,
171 I40E_NONDMA_TO_DMA,
172 I40E_DMA_TO_DMA,
173 I40E_DMA_TO_NONDMA
174 };
175
176 /* These are structs for managing the hardware information and the operations.
177 * The structures of function pointers are filled out at init time when we
178 * know for sure exactly which hardware we're working with. This gives us the
179 * flexibility of using the same main driver code but adapting to slightly
180 * different hardware needs as new parts are developed. For this architecture,
181 * the Firmware and AdminQ are intended to insulate the driver from most of the
182 * future changes, but these structures will also do part of the job.
183 */
184 enum i40e_mac_type {
185 I40E_MAC_UNKNOWN = 0,
186 I40E_MAC_XL710,
187 I40E_MAC_VF,
188 I40E_MAC_X722,
189 I40E_MAC_X722_VF,
190 I40E_MAC_GENERIC,
191 };
192
193 enum i40e_media_type {
194 I40E_MEDIA_TYPE_UNKNOWN = 0,
195 I40E_MEDIA_TYPE_FIBER,
196 I40E_MEDIA_TYPE_BASET,
197 I40E_MEDIA_TYPE_BACKPLANE,
198 I40E_MEDIA_TYPE_CX4,
199 I40E_MEDIA_TYPE_DA,
200 I40E_MEDIA_TYPE_VIRTUAL
201 };
202
203 enum i40e_fc_mode {
204 I40E_FC_NONE = 0,
205 I40E_FC_RX_PAUSE,
206 I40E_FC_TX_PAUSE,
207 I40E_FC_FULL,
208 I40E_FC_PFC,
209 I40E_FC_DEFAULT
210 };
211
212 enum i40e_set_fc_aq_failures {
213 I40E_SET_FC_AQ_FAIL_NONE = 0,
214 I40E_SET_FC_AQ_FAIL_GET = 1,
215 I40E_SET_FC_AQ_FAIL_SET = 2,
216 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
217 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
218 };
219
220 enum i40e_vsi_type {
221 I40E_VSI_MAIN = 0,
222 I40E_VSI_VMDQ1 = 1,
223 I40E_VSI_VMDQ2 = 2,
224 I40E_VSI_CTRL = 3,
225 I40E_VSI_FCOE = 4,
226 I40E_VSI_MIRROR = 5,
227 I40E_VSI_SRIOV = 6,
228 I40E_VSI_FDIR = 7,
229 I40E_VSI_TYPE_UNKNOWN
230 };
231
232 enum i40e_queue_type {
233 I40E_QUEUE_TYPE_RX = 0,
234 I40E_QUEUE_TYPE_TX,
235 I40E_QUEUE_TYPE_PE_CEQ,
236 I40E_QUEUE_TYPE_UNKNOWN
237 };
238
239 enum i40e_prt_mac_link_speed {
240 I40E_PRT_MAC_LINK_SPEED_100MB = 0,
241 I40E_PRT_MAC_LINK_SPEED_1GB,
242 I40E_PRT_MAC_LINK_SPEED_10GB,
243 I40E_PRT_MAC_LINK_SPEED_40GB,
244 I40E_PRT_MAC_LINK_SPEED_20GB
245 };
246
247 struct i40e_link_status {
248 enum i40e_aq_phy_type phy_type;
249 enum i40e_aq_link_speed link_speed;
250 u8 link_info;
251 u8 an_info;
252 u8 req_fec_info;
253 u8 fec_info;
254 u8 ext_info;
255 u8 loopback;
256 /* is Link Status Event notification to SW enabled */
257 bool lse_enable;
258 u16 max_frame_size;
259 bool crc_enable;
260 u8 pacing;
261 u8 requested_speeds;
262 u8 module_type[3];
263 /* 1st byte: module identifier */
264 #define I40E_MODULE_TYPE_SFP 0x03
265 #define I40E_MODULE_TYPE_QSFP 0x0D
266 /* 2nd byte: ethernet compliance codes for 10/40G */
267 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
268 #define I40E_MODULE_TYPE_40G_LR4 0x02
269 #define I40E_MODULE_TYPE_40G_SR4 0x04
270 #define I40E_MODULE_TYPE_40G_CR4 0x08
271 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
272 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
273 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
274 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
275 /* 3rd byte: ethernet compliance codes for 1G */
276 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
277 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
278 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
279 #define I40E_MODULE_TYPE_1000BASE_T 0x08
280 };
281
282 struct i40e_phy_info {
283 struct i40e_link_status link_info;
284 struct i40e_link_status link_info_old;
285 bool get_link_info;
286 enum i40e_media_type media_type;
287 /* all the phy types the NVM is capable of */
288 u64 phy_types;
289 };
290
291 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
292 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
293 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
294 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
295 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
296 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
297 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
298 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
299 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
300 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
301 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
302 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
303 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
304 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
305 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
306 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
307 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
308 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
309 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
310 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
311 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
312 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
313 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
314 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
315 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
316 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
317 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
318 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
319 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
320 /*
321 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
322 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
323 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
324 * a shift is needed to adjust for this with values larger than 31. The
325 * only affected values are I40E_PHY_TYPE_25GBASE_*.
326 */
327 #define I40E_PHY_TYPE_OFFSET 1
328 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
329 I40E_PHY_TYPE_OFFSET)
330 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
331 I40E_PHY_TYPE_OFFSET)
332 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
333 I40E_PHY_TYPE_OFFSET)
334 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
335 I40E_PHY_TYPE_OFFSET)
336 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
337 I40E_PHY_TYPE_OFFSET)
338 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
339 I40E_PHY_TYPE_OFFSET)
340 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
341 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
342 #define I40E_HW_CAP_MAX_GPIO 30
343 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
344 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
345
346 enum i40e_acpi_programming_method {
347 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
348 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
349 };
350
351 #define I40E_WOL_SUPPORT_MASK 0x1
352 #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2
353 #define I40E_PROXY_SUPPORT_MASK 0x4
354
355 /* Capabilities of a PF or a VF or the whole device */
356 struct i40e_hw_capabilities {
357 u32 switch_mode;
358 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
359 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
360 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
361
362 /* Cloud filter modes:
363 * Mode1: Filter on L4 port only
364 * Mode2: Filter for non-tunneled traffic
365 * Mode3: Filter for tunnel traffic
366 */
367 #define I40E_CLOUD_FILTER_MODE1 0x6
368 #define I40E_CLOUD_FILTER_MODE2 0x7
369 #define I40E_CLOUD_FILTER_MODE3 0x8
370 #define I40E_SWITCH_MODE_MASK 0xF
371
372 u32 management_mode;
373 u32 mng_protocols_over_mctp;
374 #define I40E_MNG_PROTOCOL_PLDM 0x2
375 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
376 #define I40E_MNG_PROTOCOL_NCSI 0x8
377 u32 npar_enable;
378 u32 os2bmc;
379 u32 valid_functions;
380 bool sr_iov_1_1;
381 bool vmdq;
382 bool evb_802_1_qbg; /* Edge Virtual Bridging */
383 bool evb_802_1_qbh; /* Bridge Port Extension */
384 bool dcb;
385 bool fcoe;
386 bool iscsi; /* Indicates iSCSI enabled */
387 bool flex10_enable;
388 bool flex10_capable;
389 u32 flex10_mode;
390 #define I40E_FLEX10_MODE_UNKNOWN 0x0
391 #define I40E_FLEX10_MODE_DCC 0x1
392 #define I40E_FLEX10_MODE_DCI 0x2
393
394 u32 flex10_status;
395 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
396 #define I40E_FLEX10_STATUS_VC_MODE 0x2
397
398 bool sec_rev_disabled;
399 bool update_disabled;
400 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
401 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
402
403 bool mgmt_cem;
404 bool ieee_1588;
405 bool iwarp;
406 bool fd;
407 u32 fd_filters_guaranteed;
408 u32 fd_filters_best_effort;
409 bool rss;
410 u32 rss_table_size;
411 u32 rss_table_entry_width;
412 bool led[I40E_HW_CAP_MAX_GPIO];
413 bool sdp[I40E_HW_CAP_MAX_GPIO];
414 u32 nvm_image_type;
415 u32 num_flow_director_filters;
416 u32 num_vfs;
417 u32 vf_base_id;
418 u32 num_vsis;
419 u32 num_rx_qp;
420 u32 num_tx_qp;
421 u32 base_queue;
422 u32 num_msix_vectors;
423 u32 num_msix_vectors_vf;
424 u32 led_pin_num;
425 u32 sdp_pin_num;
426 u32 mdio_port_num;
427 u32 mdio_port_mode;
428 u8 rx_buf_chain_len;
429 u32 enabled_tcmap;
430 u32 maxtc;
431 u64 wr_csr_prot;
432 bool dis_unused_ports;
433 bool apm_wol_support;
434 enum i40e_acpi_programming_method acpi_prog_method;
435 bool proxy_support;
436 };
437
438 struct i40e_mac_info {
439 enum i40e_mac_type type;
440 u8 addr[ETH_ALEN];
441 u8 perm_addr[ETH_ALEN];
442 u8 san_addr[ETH_ALEN];
443 u8 port_addr[ETH_ALEN];
444 u16 max_fcoeq;
445 };
446
447 enum i40e_aq_resources_ids {
448 I40E_NVM_RESOURCE_ID = 1
449 };
450
451 enum i40e_aq_resource_access_type {
452 I40E_RESOURCE_READ = 1,
453 I40E_RESOURCE_WRITE
454 };
455
456 struct i40e_nvm_info {
457 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
458 u32 timeout; /* [ms] */
459 u16 sr_size; /* Shadow RAM size in words */
460 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
461 u16 version; /* NVM package version */
462 u32 eetrack; /* NVM data version */
463 u32 oem_ver; /* OEM version info */
464 };
465
466 /* definitions used in NVM update support */
467
468 enum i40e_nvmupd_cmd {
469 I40E_NVMUPD_INVALID,
470 I40E_NVMUPD_READ_CON,
471 I40E_NVMUPD_READ_SNT,
472 I40E_NVMUPD_READ_LCB,
473 I40E_NVMUPD_READ_SA,
474 I40E_NVMUPD_WRITE_ERA,
475 I40E_NVMUPD_WRITE_CON,
476 I40E_NVMUPD_WRITE_SNT,
477 I40E_NVMUPD_WRITE_LCB,
478 I40E_NVMUPD_WRITE_SA,
479 I40E_NVMUPD_CSUM_CON,
480 I40E_NVMUPD_CSUM_SA,
481 I40E_NVMUPD_CSUM_LCB,
482 I40E_NVMUPD_STATUS,
483 I40E_NVMUPD_EXEC_AQ,
484 I40E_NVMUPD_GET_AQ_RESULT,
485 I40E_NVMUPD_GET_AQ_EVENT,
486 I40E_NVMUPD_FEATURES,
487 };
488
489 enum i40e_nvmupd_state {
490 I40E_NVMUPD_STATE_INIT,
491 I40E_NVMUPD_STATE_READING,
492 I40E_NVMUPD_STATE_WRITING,
493 I40E_NVMUPD_STATE_INIT_WAIT,
494 I40E_NVMUPD_STATE_WRITE_WAIT,
495 I40E_NVMUPD_STATE_ERROR
496 };
497
498 /* nvm_access definition and its masks/shifts need to be accessible to
499 * application, core driver, and shared code. Where is the right file?
500 */
501 #define I40E_NVM_READ 0xB
502 #define I40E_NVM_WRITE 0xC
503
504 #define I40E_NVM_MOD_PNT_MASK 0xFF
505
506 #define I40E_NVM_TRANS_SHIFT 8
507 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
508 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12
509 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
510 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
511 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01
512 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02
513 #define I40E_NVM_CON 0x0
514 #define I40E_NVM_SNT 0x1
515 #define I40E_NVM_LCB 0x2
516 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
517 #define I40E_NVM_ERA 0x4
518 #define I40E_NVM_CSUM 0x8
519 #define I40E_NVM_AQE 0xe
520 #define I40E_NVM_EXEC 0xf
521
522 #define I40E_NVM_EXEC_GET_AQ_RESULT 0x0
523 #define I40E_NVM_EXEC_FEATURES 0xe
524 #define I40E_NVM_EXEC_STATUS 0xf
525
526 #define I40E_NVM_ADAPT_SHIFT 16
527 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
528
529 #define I40E_NVMUPD_MAX_DATA 4096
530 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
531
532 struct i40e_nvm_access {
533 u32 command;
534 u32 config;
535 u32 offset; /* in bytes */
536 u32 data_size; /* in bytes */
537 u8 data[1];
538 };
539
540 /* NVMUpdate features API */
541 #define I40E_NVMUPD_FEATURES_API_VER_MAJOR 0
542 #define I40E_NVMUPD_FEATURES_API_VER_MINOR 14
543 #define I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12
544
545 #define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0)
546
547 struct i40e_nvmupd_features {
548 u8 major;
549 u8 minor;
550 u16 size;
551 u8 features[I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
552 };
553
554 /* (Q)SFP module access definitions */
555 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0
556 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
557 #define I40E_MODULE_TYPE_ADDR 0x00
558 #define I40E_MODULE_REVISION_ADDR 0x01
559 #define I40E_MODULE_SFF_8472_COMP 0x5E
560 #define I40E_MODULE_SFF_8472_SWAP 0x5C
561 #define I40E_MODULE_SFF_ADDR_MODE 0x04
562 #define I40E_MODULE_SFF_DIAG_CAPAB 0x40
563 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
564 #define I40E_MODULE_TYPE_QSFP28 0x11
565 #define I40E_MODULE_QSFP_MAX_LEN 640
566
567 /* PCI bus types */
568 enum i40e_bus_type {
569 i40e_bus_type_unknown = 0,
570 i40e_bus_type_pci,
571 i40e_bus_type_pcix,
572 i40e_bus_type_pci_express,
573 i40e_bus_type_reserved
574 };
575
576 /* PCI bus speeds */
577 enum i40e_bus_speed {
578 i40e_bus_speed_unknown = 0,
579 i40e_bus_speed_33 = 33,
580 i40e_bus_speed_66 = 66,
581 i40e_bus_speed_100 = 100,
582 i40e_bus_speed_120 = 120,
583 i40e_bus_speed_133 = 133,
584 i40e_bus_speed_2500 = 2500,
585 i40e_bus_speed_5000 = 5000,
586 i40e_bus_speed_8000 = 8000,
587 i40e_bus_speed_reserved
588 };
589
590 /* PCI bus widths */
591 enum i40e_bus_width {
592 i40e_bus_width_unknown = 0,
593 i40e_bus_width_pcie_x1 = 1,
594 i40e_bus_width_pcie_x2 = 2,
595 i40e_bus_width_pcie_x4 = 4,
596 i40e_bus_width_pcie_x8 = 8,
597 i40e_bus_width_32 = 32,
598 i40e_bus_width_64 = 64,
599 i40e_bus_width_reserved
600 };
601
602 /* Bus parameters */
603 struct i40e_bus_info {
604 enum i40e_bus_speed speed;
605 enum i40e_bus_width width;
606 enum i40e_bus_type type;
607
608 u16 func;
609 u16 device;
610 u16 lan_id;
611 u16 bus_id;
612 };
613
614 /* Flow control (FC) parameters */
615 struct i40e_fc_info {
616 enum i40e_fc_mode current_mode; /* FC mode in effect */
617 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
618 };
619
620 #define I40E_MAX_TRAFFIC_CLASS 8
621 #define I40E_MAX_USER_PRIORITY 8
622 #define I40E_DCBX_MAX_APPS 32
623 #define I40E_LLDPDU_SIZE 1500
624 #define I40E_TLV_STATUS_OPER 0x1
625 #define I40E_TLV_STATUS_SYNC 0x2
626 #define I40E_TLV_STATUS_ERR 0x4
627 #define I40E_CEE_OPER_MAX_APPS 3
628 #define I40E_APP_PROTOID_FCOE 0x8906
629 #define I40E_APP_PROTOID_ISCSI 0x0cbc
630 #define I40E_APP_PROTOID_FIP 0x8914
631 #define I40E_APP_SEL_ETHTYPE 0x1
632 #define I40E_APP_SEL_TCPIP 0x2
633 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
634 #define I40E_CEE_APP_SEL_TCPIP 0x1
635
636 /* CEE or IEEE 802.1Qaz ETS Configuration data */
637 struct i40e_dcb_ets_config {
638 u8 willing;
639 u8 cbs;
640 u8 maxtcs;
641 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
642 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
643 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
644 };
645
646 /* CEE or IEEE 802.1Qaz PFC Configuration data */
647 struct i40e_dcb_pfc_config {
648 u8 willing;
649 u8 mbc;
650 u8 pfccap;
651 u8 pfcenable;
652 };
653
654 /* CEE or IEEE 802.1Qaz Application Priority data */
655 struct i40e_dcb_app_priority_table {
656 u8 priority;
657 u8 selector;
658 u16 protocolid;
659 };
660
661 struct i40e_dcbx_config {
662 u8 dcbx_mode;
663 #define I40E_DCBX_MODE_CEE 0x1
664 #define I40E_DCBX_MODE_IEEE 0x2
665 u8 app_mode;
666 #define I40E_DCBX_APPS_NON_WILLING 0x1
667 u32 numapps;
668 u32 tlv_status; /* CEE mode TLV status */
669 struct i40e_dcb_ets_config etscfg;
670 struct i40e_dcb_ets_config etsrec;
671 struct i40e_dcb_pfc_config pfc;
672 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
673 };
674
675 /* Port hardware description */
676 struct i40e_hw {
677 u8 *hw_addr;
678 void *back;
679
680 /* subsystem structs */
681 struct i40e_phy_info phy;
682 struct i40e_mac_info mac;
683 struct i40e_bus_info bus;
684 struct i40e_nvm_info nvm;
685 struct i40e_fc_info fc;
686
687 /* switch device is used to get link status when i40e is in ipn3ke */
688 struct rte_eth_dev *switch_dev;
689
690 /* pci info */
691 u16 device_id;
692 u16 vendor_id;
693 u16 subsystem_device_id;
694 u16 subsystem_vendor_id;
695 u8 revision_id;
696 u8 port;
697 bool adapter_stopped;
698 bool adapter_closed;
699
700 /* capabilities for entire device and PCI func */
701 struct i40e_hw_capabilities dev_caps;
702 struct i40e_hw_capabilities func_caps;
703
704 /* Flow Director shared filter space */
705 u16 fdir_shared_filter_count;
706
707 /* device profile info */
708 u8 pf_id;
709 u16 main_vsi_seid;
710
711 /* for multi-function MACs */
712 u16 partition_id;
713 u16 num_partitions;
714 u16 num_ports;
715
716 /* Closest numa node to the device */
717 u16 numa_node;
718
719 /* Admin Queue info */
720 struct i40e_adminq_info aq;
721
722 /* state of nvm update process */
723 enum i40e_nvmupd_state nvmupd_state;
724 struct i40e_aq_desc nvm_wb_desc;
725 struct i40e_aq_desc nvm_aq_event_desc;
726 struct i40e_virt_mem nvm_buff;
727 bool nvm_release_on_done;
728 u16 nvm_wait_opcode;
729
730 /* HMC info */
731 struct i40e_hmc_info hmc; /* HMC info struct */
732
733 /* LLDP/DCBX Status */
734 u16 dcbx_status;
735
736 /* DCBX info */
737 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
738 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
739 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
740
741 /* WoL and proxy support */
742 u16 num_wol_proxy_filters;
743 u16 wol_proxy_vsi_seid;
744
745 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
746 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
747 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
748 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
749 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
750 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
751 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
752 #define I40E_HW_FLAG_DROP_MODE BIT_ULL(7)
753 #define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)
754 u64 flags;
755
756 /* Used in set switch config AQ command */
757 u16 switch_tag;
758 u16 first_tag;
759 u16 second_tag;
760
761 /* NVMUpdate features */
762 struct i40e_nvmupd_features nvmupd_features;
763
764 /* debug mask */
765 u32 debug_mask;
766 char err_str[16];
767 };
768
i40e_is_vf(struct i40e_hw * hw)769 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
770 {
771 return (hw->mac.type == I40E_MAC_VF ||
772 hw->mac.type == I40E_MAC_X722_VF);
773 }
774
775 struct i40e_driver_version {
776 u8 major_version;
777 u8 minor_version;
778 u8 build_version;
779 u8 subbuild_version;
780 u8 driver_string[32];
781 };
782
783 /* RX Descriptors */
784 union i40e_16byte_rx_desc {
785 struct {
786 __le64 pkt_addr; /* Packet buffer address */
787 __le64 hdr_addr; /* Header buffer address */
788 } read;
789 struct {
790 struct {
791 struct {
792 union {
793 __le16 mirroring_status;
794 __le16 fcoe_ctx_id;
795 } mirr_fcoe;
796 __le16 l2tag1;
797 } lo_dword;
798 union {
799 __le32 rss; /* RSS Hash */
800 __le32 fd_id; /* Flow director filter id */
801 __le32 fcoe_param; /* FCoE DDP Context id */
802 } hi_dword;
803 } qword0;
804 struct {
805 /* ext status/error/pktype/length */
806 __le64 status_error_len;
807 } qword1;
808 } wb; /* writeback */
809 };
810
811 union i40e_32byte_rx_desc {
812 struct {
813 __le64 pkt_addr; /* Packet buffer address */
814 __le64 hdr_addr; /* Header buffer address */
815 /* bit 0 of hdr_buffer_addr is DD bit */
816 __le64 rsvd1;
817 __le64 rsvd2;
818 } read;
819 struct {
820 struct i40e_32b_rx_wb_qw0 {
821 struct {
822 union {
823 __le16 mirroring_status;
824 __le16 fcoe_ctx_id;
825 } mirr_fcoe;
826 __le16 l2tag1;
827 } lo_dword;
828 union {
829 __le32 rss; /* RSS Hash */
830 __le32 fcoe_param; /* FCoE DDP Context id */
831 /* Flow director filter id in case of
832 * Programming status desc WB
833 */
834 __le32 fd_id;
835 } hi_dword;
836 } qword0;
837 struct {
838 /* status/error/pktype/length */
839 __le64 status_error_len;
840 } qword1;
841 struct {
842 __le16 ext_status; /* extended status */
843 __le16 rsvd;
844 __le16 l2tag2_1;
845 __le16 l2tag2_2;
846 } qword2;
847 struct {
848 union {
849 __le32 flex_bytes_lo;
850 __le32 pe_status;
851 } lo_dword;
852 union {
853 __le32 flex_bytes_hi;
854 __le32 fd_id;
855 } hi_dword;
856 } qword3;
857 } wb; /* writeback */
858 struct {
859 u64 qword[4];
860 } raw;
861 };
862
863 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
864 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
865 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
866 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
867 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
868 I40E_RXD_QW0_FCOEINDX_SHIFT)
869
870 enum i40e_rx_desc_status_bits {
871 /* Note: These are predefined bit offsets */
872 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
873 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
874 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
875 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
876 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
877 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
878 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
879 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
880
881 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
882 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
883 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
884 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
885 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
886 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
887 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
888 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
889 };
890
891 #define I40E_RXD_QW1_STATUS_SHIFT 0
892 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
893 I40E_RXD_QW1_STATUS_SHIFT)
894
895 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
896 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
897 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
898
899 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
900 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
901
902 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
903 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
904 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
905
906 enum i40e_rx_desc_fltstat_values {
907 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
908 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
909 I40E_RX_DESC_FLTSTAT_RSV = 2,
910 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
911 };
912
913 #define I40E_RXD_PACKET_TYPE_UNICAST 0
914 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
915 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
916 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
917
918 #define I40E_RXD_QW1_ERROR_SHIFT 19
919 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
920
921 enum i40e_rx_desc_error_bits {
922 /* Note: These are predefined bit offsets */
923 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
924 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
925 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
926 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
927 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
928 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
929 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
930 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
931 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
932 };
933
934 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
935 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
936 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
937 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
938 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
939 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
940 };
941
942 #define I40E_RXD_QW1_PTYPE_SHIFT 30
943 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
944
945 /* Packet type non-ip values */
946 enum i40e_rx_l2_ptype {
947 I40E_RX_PTYPE_L2_RESERVED = 0,
948 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
949 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
950 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
951 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
952 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
953 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
954 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
955 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
956 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
957 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
958 I40E_RX_PTYPE_L2_ARP = 11,
959 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
960 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
961 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
962 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
963 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
964 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
965 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
966 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
967 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
968 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
969 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
970 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
971 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
972 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153,
973 I40E_RX_PTYPE_PARSER_ABORTED = 255
974 };
975
976 struct i40e_rx_ptype_decoded {
977 u32 ptype:8;
978 u32 known:1;
979 u32 outer_ip:1;
980 u32 outer_ip_ver:1;
981 u32 outer_frag:1;
982 u32 tunnel_type:3;
983 u32 tunnel_end_prot:2;
984 u32 tunnel_end_frag:1;
985 u32 inner_prot:4;
986 u32 payload_layer:3;
987 };
988
989 enum i40e_rx_ptype_outer_ip {
990 I40E_RX_PTYPE_OUTER_L2 = 0,
991 I40E_RX_PTYPE_OUTER_IP = 1
992 };
993
994 enum i40e_rx_ptype_outer_ip_ver {
995 I40E_RX_PTYPE_OUTER_NONE = 0,
996 I40E_RX_PTYPE_OUTER_IPV4 = 0,
997 I40E_RX_PTYPE_OUTER_IPV6 = 1
998 };
999
1000 enum i40e_rx_ptype_outer_fragmented {
1001 I40E_RX_PTYPE_NOT_FRAG = 0,
1002 I40E_RX_PTYPE_FRAG = 1
1003 };
1004
1005 enum i40e_rx_ptype_tunnel_type {
1006 I40E_RX_PTYPE_TUNNEL_NONE = 0,
1007 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
1008 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
1009 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
1010 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
1011 };
1012
1013 enum i40e_rx_ptype_tunnel_end_prot {
1014 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
1015 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
1016 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
1017 };
1018
1019 enum i40e_rx_ptype_inner_prot {
1020 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
1021 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
1022 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
1023 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
1024 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
1025 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
1026 };
1027
1028 enum i40e_rx_ptype_payload_layer {
1029 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
1030 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
1031 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
1032 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
1033 };
1034
1035 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
1036 #define I40E_RX_PTYPE_SHIFT 56
1037
1038 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
1039 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
1040 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1041
1042 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
1043 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
1044 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1045
1046 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
1047 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1048
1049 #define I40E_RXD_QW1_NEXTP_SHIFT 38
1050 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1051
1052 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
1053 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
1054 I40E_RXD_QW2_EXT_STATUS_SHIFT)
1055
1056 enum i40e_rx_desc_ext_status_bits {
1057 /* Note: These are predefined bit offsets */
1058 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
1059 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
1060 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
1061 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
1062 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1063 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1064 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1065 };
1066
1067 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1068 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1069
1070 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1071 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1072
1073 enum i40e_rx_desc_pe_status_bits {
1074 /* Note: These are predefined bit offsets */
1075 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1076 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1077 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1078 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1079 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1080 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1081 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1082 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1083 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1084 };
1085
1086 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1087 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1088
1089 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1090 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1091 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1092
1093 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1094 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1095 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1096
1097 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1098 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1099 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1100
1101 enum i40e_rx_prog_status_desc_status_bits {
1102 /* Note: These are predefined bit offsets */
1103 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1104 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1105 };
1106
1107 enum i40e_rx_prog_status_desc_prog_id_masks {
1108 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1109 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1110 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1111 };
1112
1113 enum i40e_rx_prog_status_desc_error_bits {
1114 /* Note: These are predefined bit offsets */
1115 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1116 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1117 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1118 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1119 };
1120
1121 #define I40E_TWO_BIT_MASK 0x3
1122 #define I40E_THREE_BIT_MASK 0x7
1123 #define I40E_FOUR_BIT_MASK 0xF
1124 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1125
1126 /* TX Descriptor */
1127 struct i40e_tx_desc {
1128 __le64 buffer_addr; /* Address of descriptor's data buf */
1129 __le64 cmd_type_offset_bsz;
1130 };
1131
1132 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1133 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1134
1135 enum i40e_tx_desc_dtype_value {
1136 I40E_TX_DESC_DTYPE_DATA = 0x0,
1137 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1138 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1139 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1140 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1141 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1142 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1143 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1144 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1145 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1146 };
1147
1148 #define I40E_TXD_QW1_CMD_SHIFT 4
1149 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1150
1151 enum i40e_tx_desc_cmd_bits {
1152 I40E_TX_DESC_CMD_EOP = 0x0001,
1153 I40E_TX_DESC_CMD_RS = 0x0002,
1154 I40E_TX_DESC_CMD_ICRC = 0x0004,
1155 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1156 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1157 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1158 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1159 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1160 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1161 I40E_TX_DESC_CMD_FCOET = 0x0080,
1162 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1163 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1164 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1165 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1166 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1167 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1168 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1169 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1170 };
1171
1172 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1173 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1174 I40E_TXD_QW1_OFFSET_SHIFT)
1175
1176 enum i40e_tx_desc_length_fields {
1177 /* Note: These are predefined bit offsets */
1178 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1179 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1180 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1181 };
1182
1183 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1184 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1185 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1186 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1187
1188 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1189 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1190 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1191
1192 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1193 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1194
1195 /* Context descriptors */
1196 struct i40e_tx_context_desc {
1197 __le32 tunneling_params;
1198 __le16 l2tag2;
1199 __le16 rsvd;
1200 __le64 type_cmd_tso_mss;
1201 };
1202
1203 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1204 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1205
1206 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1207 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1208
1209 enum i40e_tx_ctx_desc_cmd_bits {
1210 I40E_TX_CTX_DESC_TSO = 0x01,
1211 I40E_TX_CTX_DESC_TSYN = 0x02,
1212 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1213 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1214 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1215 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1216 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1217 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1218 I40E_TX_CTX_DESC_SWPE = 0x40
1219 };
1220
1221 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1222 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1223 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1224
1225 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1226 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1227 I40E_TXD_CTX_QW1_MSS_SHIFT)
1228
1229 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1230 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1231
1232 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1233 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1234 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1235
1236 enum i40e_tx_ctx_desc_eipt_offload {
1237 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1238 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1239 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1240 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1241 };
1242
1243 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1244 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1245 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1246
1247 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1248 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1249
1250 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1251 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1252
1253 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1254 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1255
1256 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1257
1258 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1259 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1260 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1261
1262 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1263 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1264 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1265
1266 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1267 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1268 struct i40e_nop_desc {
1269 __le64 rsvd;
1270 __le64 dtype_cmd;
1271 };
1272
1273 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1274 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1275
1276 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1277 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1278
1279 enum i40e_tx_nop_desc_cmd_bits {
1280 /* Note: These are predefined bit offsets */
1281 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1282 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1283 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1284 };
1285
1286 struct i40e_filter_program_desc {
1287 __le32 qindex_flex_ptype_vsi;
1288 __le32 rsvd;
1289 __le32 dtype_cmd_cntindex;
1290 __le32 fd_id;
1291 };
1292 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1293 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1294 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1295 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1296 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1297 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1298 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1299 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1300 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1301
1302 /* Packet Classifier Types for filters */
1303 enum i40e_filter_pctype {
1304 /* Note: Values 0-28 are reserved for future use.
1305 * Value 29, 30, 32 are not supported on XL710 and X710.
1306 */
1307 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1308 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1309 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1310 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1311 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1312 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1313 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1314 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1315 /* Note: Values 37-38 are reserved for future use.
1316 * Value 39, 40, 42 are not supported on XL710 and X710.
1317 */
1318 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1319 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1320 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1321 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1322 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1323 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1324 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1325 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1326 /* Note: Value 47 is reserved for future use */
1327 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1328 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1329 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1330 /* Note: Values 51-62 are reserved for future use */
1331 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1332 };
1333
1334 enum i40e_filter_program_desc_dest {
1335 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1336 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1337 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1338 };
1339
1340 enum i40e_filter_program_desc_fd_status {
1341 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1342 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1343 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1344 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1345 };
1346
1347 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1348 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1349 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1350
1351 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1352 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1353
1354 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1355 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1356 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1357
1358 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1359 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1360
1361 enum i40e_filter_program_desc_pcmd {
1362 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1363 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1364 };
1365
1366 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1367 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1368
1369 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1370 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1371
1372 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1373 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1374 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1375 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1376
1377 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1378 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1379 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1380
1381 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1382 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1383 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1384
1385 enum i40e_filter_type {
1386 I40E_FLOW_DIRECTOR_FLTR = 0,
1387 I40E_PE_QUAD_HASH_FLTR = 1,
1388 I40E_ETHERTYPE_FLTR,
1389 I40E_FCOE_CTX_FLTR,
1390 I40E_MAC_VLAN_FLTR,
1391 I40E_HASH_FLTR
1392 };
1393
1394 struct i40e_vsi_context {
1395 u16 seid;
1396 u16 uplink_seid;
1397 u16 vsi_number;
1398 u16 vsis_allocated;
1399 u16 vsis_unallocated;
1400 u16 flags;
1401 u8 pf_num;
1402 u8 vf_num;
1403 u8 connection_type;
1404 struct i40e_aqc_vsi_properties_data info;
1405 };
1406
1407 struct i40e_veb_context {
1408 u16 seid;
1409 u16 uplink_seid;
1410 u16 veb_number;
1411 u16 vebs_allocated;
1412 u16 vebs_unallocated;
1413 u16 flags;
1414 struct i40e_aqc_get_veb_parameters_completion info;
1415 };
1416
1417 /* Statistics collected by each port, VSI, VEB, and S-channel */
1418 struct i40e_eth_stats {
1419 u64 rx_bytes; /* gorc */
1420 u64 rx_unicast; /* uprc */
1421 u64 rx_multicast; /* mprc */
1422 u64 rx_broadcast; /* bprc */
1423 u64 rx_discards; /* rdpc */
1424 u64 rx_unknown_protocol; /* rupp */
1425 u64 tx_bytes; /* gotc */
1426 u64 tx_unicast; /* uptc */
1427 u64 tx_multicast; /* mptc */
1428 u64 tx_broadcast; /* bptc */
1429 u64 tx_discards; /* tdpc */
1430 u64 tx_errors; /* tepc */
1431 };
1432
1433 /* Statistics collected per VEB per TC */
1434 struct i40e_veb_tc_stats {
1435 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1436 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1437 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1438 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1439 };
1440
1441 /* Statistics collected per function for FCoE */
1442 struct i40e_fcoe_stats {
1443 u64 rx_fcoe_packets; /* fcoeprc */
1444 u64 rx_fcoe_dwords; /* focedwrc */
1445 u64 rx_fcoe_dropped; /* fcoerpdc */
1446 u64 tx_fcoe_packets; /* fcoeptc */
1447 u64 tx_fcoe_dwords; /* focedwtc */
1448 u64 fcoe_bad_fccrc; /* fcoecrc */
1449 u64 fcoe_last_error; /* fcoelast */
1450 u64 fcoe_ddp_count; /* fcoeddpc */
1451 };
1452
1453 /* offset to per function FCoE statistics block */
1454 #define I40E_FCOE_VF_STAT_OFFSET 0
1455 #define I40E_FCOE_PF_STAT_OFFSET 128
1456 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1457
1458 /* Statistics collected by the MAC */
1459 struct i40e_hw_port_stats {
1460 /* eth stats collected by the port */
1461 struct i40e_eth_stats eth;
1462
1463 /* additional port specific stats */
1464 u64 tx_dropped_link_down; /* tdold */
1465 u64 crc_errors; /* crcerrs */
1466 u64 illegal_bytes; /* illerrc */
1467 u64 error_bytes; /* errbc */
1468 u64 mac_local_faults; /* mlfc */
1469 u64 mac_remote_faults; /* mrfc */
1470 u64 rx_length_errors; /* rlec */
1471 u64 link_xon_rx; /* lxonrxc */
1472 u64 link_xoff_rx; /* lxoffrxc */
1473 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1474 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1475 u64 link_xon_tx; /* lxontxc */
1476 u64 link_xoff_tx; /* lxofftxc */
1477 u64 priority_xon_tx[8]; /* pxontxc[8] */
1478 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1479 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1480 u64 rx_size_64; /* prc64 */
1481 u64 rx_size_127; /* prc127 */
1482 u64 rx_size_255; /* prc255 */
1483 u64 rx_size_511; /* prc511 */
1484 u64 rx_size_1023; /* prc1023 */
1485 u64 rx_size_1522; /* prc1522 */
1486 u64 rx_size_big; /* prc9522 */
1487 u64 rx_undersize; /* ruc */
1488 u64 rx_fragments; /* rfc */
1489 u64 rx_oversize; /* roc */
1490 u64 rx_jabber; /* rjc */
1491 u64 tx_size_64; /* ptc64 */
1492 u64 tx_size_127; /* ptc127 */
1493 u64 tx_size_255; /* ptc255 */
1494 u64 tx_size_511; /* ptc511 */
1495 u64 tx_size_1023; /* ptc1023 */
1496 u64 tx_size_1522; /* ptc1522 */
1497 u64 tx_size_big; /* ptc9522 */
1498 u64 mac_short_packet_dropped; /* mspdc */
1499 u64 checksum_error; /* xec */
1500 /* flow director stats */
1501 u64 fd_atr_match;
1502 u64 fd_sb_match;
1503 u64 fd_atr_tunnel_match;
1504 u32 fd_atr_status;
1505 u32 fd_sb_status;
1506 /* EEE LPI */
1507 u32 tx_lpi_status;
1508 u32 rx_lpi_status;
1509 u64 tx_lpi_count; /* etlpic */
1510 u64 rx_lpi_count; /* erlpic */
1511 u64 tx_lpi_duration;
1512 u64 rx_lpi_duration;
1513 };
1514
1515 /* Checksum and Shadow RAM pointers */
1516 #define I40E_SR_NVM_CONTROL_WORD 0x00
1517 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1518 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1519 #define I40E_SR_OPTION_ROM_PTR 0x05
1520 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1521 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1522 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1523 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1524 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1525 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1526 #define I40E_SR_PE_IMAGE_PTR 0x0C
1527 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1528 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1529 #define I40E_EMP_MODULE_PTR 0x0F
1530 #define I40E_SR_EMP_MODULE_PTR 0x48
1531 #define I40E_SR_PBA_FLAGS 0x15
1532 #define I40E_SR_PBA_BLOCK_PTR 0x16
1533 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1534 #define I40E_NVM_OEM_VER_OFF 0x83
1535 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1536 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1537 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1538 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1539 #define I40E_SR_NVM_MAP_VERSION 0x29
1540 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1541 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1542 #define I40E_SR_NVM_EETRACK_LO 0x2D
1543 #define I40E_SR_NVM_EETRACK_HI 0x2E
1544 #define I40E_SR_VPD_PTR 0x2F
1545 #define I40E_SR_PXE_SETUP_PTR 0x30
1546 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1547 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1548 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1549 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1550 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1551 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1552 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1553 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1554 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
1555 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1556 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1557 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1558 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1559 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1560 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1561 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1562 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1563 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1564 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1565 #define I40E_SR_PRESERVATION_RULES_PTR 0x70
1566 #define I40E_X722_SR_5TH_FREE_PROVISION_AREA_PTR 0x71
1567 #define I40E_SR_6TH_FREE_PROVISION_AREA_PTR 0x71
1568
1569 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1570 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1571 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1572 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1573 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1574 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
1575 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
1576 #define I40E_PTR_TYPE BIT(15)
1577 #define I40E_SR_OCP_CFG_WORD0 0x2B
1578 #define I40E_SR_OCP_ENABLED BIT(15)
1579
1580 /* Shadow RAM related */
1581 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1582 #define I40E_SR_BUF_ALIGNMENT 4096
1583 #define I40E_SR_WORDS_IN_1KB 512
1584 /* Checksum should be calculated such that after adding all the words,
1585 * including the checksum word itself, the sum should be 0xBABA.
1586 */
1587 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1588
1589 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1590
1591 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1592
1593 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1594 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1595 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1596 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1597 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1598 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1599 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1600 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1601 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1602 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1603 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1604 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1605 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1606 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1607 };
1608
1609 /* FCoE DIF/DIX Context descriptor */
1610 struct i40e_fcoe_difdix_context_desc {
1611 __le64 flags_buff0_buff1_ref;
1612 __le64 difapp_msk_bias;
1613 };
1614
1615 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1616 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1617 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1618
1619 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1620 /* 2 BITS */
1621 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1622 /* 1 BIT */
1623 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1624 /* 1 BIT */
1625 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1626 /* 2 BITS */
1627 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1628 /* 2 BITS */
1629 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1630 /* 2 BITS */
1631 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1632 /* 2 BITS */
1633 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1634 /* 2 BITS */
1635 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1636 /* 2 BITS */
1637 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1638 /* 2 BITS */
1639 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1640 /* 2 BITS */
1641 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1642 /* 1 BIT */
1643 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1644 /* 1 BIT */
1645 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1646 /* 2 BITS */
1647 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1648 /* 2 BITS */
1649 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1650 /* 2 BITS */
1651 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1652 /* 2 BITS */
1653 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1654 /* 1 BIT */
1655 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1656 /* 1 BIT */
1657 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1658 /* 1 BIT */
1659 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1660 /* 1 BIT */
1661 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1662 };
1663
1664 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1665 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1666 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1667
1668 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1669 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1670 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1671
1672 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1673 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1674 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1675
1676 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1677 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1678 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1679
1680 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1681 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1682 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1683
1684 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1685 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1686 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1687
1688 /* FCoE DIF/DIX Buffers descriptor */
1689 struct i40e_fcoe_difdix_buffers_desc {
1690 __le64 buff_addr0;
1691 __le64 buff_addr1;
1692 };
1693
1694 /* FCoE DDP Context descriptor */
1695 struct i40e_fcoe_ddp_context_desc {
1696 __le64 rsvd;
1697 __le64 type_cmd_foff_lsize;
1698 };
1699
1700 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1701 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1702 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1703
1704 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1705 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1706 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1707
1708 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1709 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1710 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1711 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1712 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1713 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1714 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1715 };
1716
1717 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1718 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1719 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1720
1721 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1722 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1723 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1724
1725 /* FCoE DDP/DWO Queue Context descriptor */
1726 struct i40e_fcoe_queue_context_desc {
1727 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1728 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1729 };
1730
1731 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1732 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1733 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1734
1735 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1736 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1737 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1738
1739 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1740 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1741 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1742
1743 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1744 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1745 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1746
1747 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1748 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1749 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1750 };
1751
1752 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1753 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1754 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1755
1756 /* FCoE DDP/DWO Filter Context descriptor */
1757 struct i40e_fcoe_filter_context_desc {
1758 __le32 param;
1759 __le16 seqn;
1760
1761 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1762 __le16 rsvd_dmaindx;
1763
1764 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1765 __le64 flags_rsvd_lanq;
1766 };
1767
1768 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1769 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1770 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1771
1772 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1773 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1774 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1775 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1776 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1777 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1778 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1779 };
1780
1781 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1782 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1783 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1784
1785 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1786 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1787 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1788
1789 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1790 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1791 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1792
1793 enum i40e_switch_element_types {
1794 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1795 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1796 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1797 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1798 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1799 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1800 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1801 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1802 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1803 };
1804
1805 /* Supported EtherType filters */
1806 enum i40e_ether_type_index {
1807 I40E_ETHER_TYPE_1588 = 0,
1808 I40E_ETHER_TYPE_FIP = 1,
1809 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1810 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1811 I40E_ETHER_TYPE_LLDP = 4,
1812 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1813 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1814 I40E_ETHER_TYPE_QCN_CNM = 7,
1815 I40E_ETHER_TYPE_8021X = 8,
1816 I40E_ETHER_TYPE_ARP = 9,
1817 I40E_ETHER_TYPE_RSV1 = 10,
1818 I40E_ETHER_TYPE_RSV2 = 11,
1819 };
1820
1821 /* Filter context base size is 1K */
1822 #define I40E_HASH_FILTER_BASE_SIZE 1024
1823 /* Supported Hash filter values */
1824 enum i40e_hash_filter_size {
1825 I40E_HASH_FILTER_SIZE_1K = 0,
1826 I40E_HASH_FILTER_SIZE_2K = 1,
1827 I40E_HASH_FILTER_SIZE_4K = 2,
1828 I40E_HASH_FILTER_SIZE_8K = 3,
1829 I40E_HASH_FILTER_SIZE_16K = 4,
1830 I40E_HASH_FILTER_SIZE_32K = 5,
1831 I40E_HASH_FILTER_SIZE_64K = 6,
1832 I40E_HASH_FILTER_SIZE_128K = 7,
1833 I40E_HASH_FILTER_SIZE_256K = 8,
1834 I40E_HASH_FILTER_SIZE_512K = 9,
1835 I40E_HASH_FILTER_SIZE_1M = 10,
1836 };
1837
1838 /* DMA context base size is 0.5K */
1839 #define I40E_DMA_CNTX_BASE_SIZE 512
1840 /* Supported DMA context values */
1841 enum i40e_dma_cntx_size {
1842 I40E_DMA_CNTX_SIZE_512 = 0,
1843 I40E_DMA_CNTX_SIZE_1K = 1,
1844 I40E_DMA_CNTX_SIZE_2K = 2,
1845 I40E_DMA_CNTX_SIZE_4K = 3,
1846 I40E_DMA_CNTX_SIZE_8K = 4,
1847 I40E_DMA_CNTX_SIZE_16K = 5,
1848 I40E_DMA_CNTX_SIZE_32K = 6,
1849 I40E_DMA_CNTX_SIZE_64K = 7,
1850 I40E_DMA_CNTX_SIZE_128K = 8,
1851 I40E_DMA_CNTX_SIZE_256K = 9,
1852 };
1853
1854 /* Supported Hash look up table (LUT) sizes */
1855 enum i40e_hash_lut_size {
1856 I40E_HASH_LUT_SIZE_128 = 0,
1857 I40E_HASH_LUT_SIZE_512 = 1,
1858 };
1859
1860 /* Structure to hold a per PF filter control settings */
1861 struct i40e_filter_control_settings {
1862 /* number of PE Quad Hash filter buckets */
1863 enum i40e_hash_filter_size pe_filt_num;
1864 /* number of PE Quad Hash contexts */
1865 enum i40e_dma_cntx_size pe_cntx_num;
1866 /* number of FCoE filter buckets */
1867 enum i40e_hash_filter_size fcoe_filt_num;
1868 /* number of FCoE DDP contexts */
1869 enum i40e_dma_cntx_size fcoe_cntx_num;
1870 /* size of the Hash LUT */
1871 enum i40e_hash_lut_size hash_lut_size;
1872 /* enable FDIR filters for PF and its VFs */
1873 bool enable_fdir;
1874 /* enable Ethertype filters for PF and its VFs */
1875 bool enable_ethtype;
1876 /* enable MAC/VLAN filters for PF and its VFs */
1877 bool enable_macvlan;
1878 };
1879
1880 /* Structure to hold device level control filter counts */
1881 struct i40e_control_filter_stats {
1882 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1883 u16 etype_used; /* Used perfect EtherType filters */
1884 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1885 u16 etype_free; /* Un-used perfect EtherType filters */
1886 };
1887
1888 enum i40e_reset_type {
1889 I40E_RESET_POR = 0,
1890 I40E_RESET_CORER = 1,
1891 I40E_RESET_GLOBR = 2,
1892 I40E_RESET_EMPR = 3,
1893 };
1894
1895 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1896 #define I40E_NVM_LLDP_CFG_PTR 0x06
1897 #define I40E_SR_LLDP_CFG_PTR 0x31
1898 struct i40e_lldp_variables {
1899 u16 length;
1900 u16 adminstatus;
1901 u16 msgfasttx;
1902 u16 msgtxinterval;
1903 u16 txparams;
1904 u16 timers;
1905 u16 crc8;
1906 };
1907
1908 /* Offsets into Alternate Ram */
1909 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1910 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1911 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1912 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1913 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1914 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1915
1916 /* Alternate Ram Bandwidth Masks */
1917 #define I40E_ALT_BW_VALUE_MASK 0xFF
1918 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1919 #define I40E_ALT_BW_VALID_MASK 0x80000000
1920
1921 /* RSS Hash Table Size */
1922 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1923
1924 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1925 #define I40E_L3_SRC_SHIFT 47
1926 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1927 #define I40E_L3_V6_SRC_SHIFT 43
1928 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1929 #define I40E_L3_DST_SHIFT 35
1930 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1931 #define I40E_L3_V6_DST_SHIFT 35
1932 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1933 #define I40E_L4_SRC_SHIFT 34
1934 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1935 #define I40E_L4_DST_SHIFT 33
1936 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1937 #define I40E_VERIFY_TAG_SHIFT 31
1938 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1939
1940 #define I40E_FLEX_50_SHIFT 13
1941 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1942 #define I40E_FLEX_51_SHIFT 12
1943 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1944 #define I40E_FLEX_52_SHIFT 11
1945 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1946 #define I40E_FLEX_53_SHIFT 10
1947 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1948 #define I40E_FLEX_54_SHIFT 9
1949 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1950 #define I40E_FLEX_55_SHIFT 8
1951 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1952 #define I40E_FLEX_56_SHIFT 7
1953 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1954 #define I40E_FLEX_57_SHIFT 6
1955 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1956
1957 /* Version format for Dynamic Device Personalization(DDP) */
1958 struct i40e_ddp_version {
1959 u8 major;
1960 u8 minor;
1961 u8 update;
1962 u8 draft;
1963 };
1964
1965 #define I40E_DDP_NAME_SIZE 32
1966
1967 /* Package header */
1968 struct i40e_package_header {
1969 struct i40e_ddp_version version;
1970 u32 segment_count;
1971 u32 segment_offset[1];
1972 };
1973
1974 /* Generic segment header */
1975 struct i40e_generic_seg_header {
1976 #define SEGMENT_TYPE_METADATA 0x00000001
1977 #define SEGMENT_TYPE_NOTES 0x00000002
1978 #define SEGMENT_TYPE_I40E 0x00000011
1979 #define SEGMENT_TYPE_X722 0x00000012
1980 u32 type;
1981 struct i40e_ddp_version version;
1982 u32 size;
1983 char name[I40E_DDP_NAME_SIZE];
1984 };
1985
1986 struct i40e_metadata_segment {
1987 struct i40e_generic_seg_header header;
1988 struct i40e_ddp_version version;
1989 #define I40E_DDP_TRACKID_RDONLY 0
1990 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF
1991 #define I40E_DDP_TRACKID_GRP_MSK 0x00FF0000
1992 #define I40E_DDP_TRACKID_GRP_COMP_ALL 0xFF
1993 u32 track_id;
1994 char name[I40E_DDP_NAME_SIZE];
1995 };
1996
1997 struct i40e_device_id_entry {
1998 u32 vendor_dev_id;
1999 u32 sub_vendor_dev_id;
2000 };
2001
2002 struct i40e_profile_segment {
2003 struct i40e_generic_seg_header header;
2004 struct i40e_ddp_version version;
2005 char name[I40E_DDP_NAME_SIZE];
2006 u32 device_table_count;
2007 struct i40e_device_id_entry device_table[1];
2008 };
2009
2010 struct i40e_section_table {
2011 u32 section_count;
2012 u32 section_offset[1];
2013 };
2014
2015 struct i40e_profile_section_header {
2016 u16 tbl_size;
2017 u16 data_end;
2018 struct {
2019 #define SECTION_TYPE_INFO 0x00000010
2020 #define SECTION_TYPE_MMIO 0x00000800
2021 #define SECTION_TYPE_RB_MMIO 0x00001800
2022 #define SECTION_TYPE_AQ 0x00000801
2023 #define SECTION_TYPE_RB_AQ 0x00001801
2024 #define SECTION_TYPE_NOTE 0x80000000
2025 #define SECTION_TYPE_NAME 0x80000001
2026 #define SECTION_TYPE_PROTO 0x80000002
2027 #define SECTION_TYPE_PCTYPE 0x80000003
2028 #define SECTION_TYPE_PTYPE 0x80000004
2029 u32 type;
2030 u32 offset;
2031 u32 size;
2032 } section;
2033 };
2034
2035 struct i40e_profile_tlv_section_record {
2036 u8 rtype;
2037 u8 type;
2038 u16 len;
2039 u8 data[12];
2040 };
2041
2042 /* Generic AQ section in proflie */
2043 struct i40e_profile_aq_section {
2044 u16 opcode;
2045 u16 flags;
2046 u8 param[16];
2047 u16 datalen;
2048 u8 data[1];
2049 };
2050
2051 struct i40e_profile_info {
2052 u32 track_id;
2053 struct i40e_ddp_version version;
2054 u8 op;
2055 #define I40E_DDP_ADD_TRACKID 0x01
2056 #define I40E_DDP_REMOVE_TRACKID 0x02
2057 u8 reserved[7];
2058 u8 name[I40E_DDP_NAME_SIZE];
2059 };
2060
2061 #define I40E_BCM_PHY_PCS_STATUS1_PAGE 0x3
2062 #define I40E_BCM_PHY_PCS_STATUS1_REG 0x0001
2063 #define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8)
2064 #define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9)
2065
2066 #endif /* _I40E_TYPE_H_ */
2067