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39
40
41 /**
42 * cvmx-npei-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon npei.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_NPEI_DEFS_H__
53 #define __CVMX_NPEI_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_BAR1_INDEXX(unsigned long offset)56 static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
57 {
58 if (!(
59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
61 cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
62 return 0x0000000000000000ull + ((offset) & 31) * 16;
63 }
64 #else
65 #define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
66 #endif
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 #define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC()
CVMX_NPEI_BIST_STATUS_FUNC(void)69 static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void)
70 {
71 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
72 cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n");
73 return 0x0000000000000580ull;
74 }
75 #else
76 #define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
77 #endif
78 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
79 #define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC()
CVMX_NPEI_BIST_STATUS2_FUNC(void)80 static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void)
81 {
82 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
83 cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n");
84 return 0x0000000000000680ull;
85 }
86 #else
87 #define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
88 #endif
89 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
90 #define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC()
CVMX_NPEI_CTL_PORT0_FUNC(void)91 static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void)
92 {
93 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
94 cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n");
95 return 0x0000000000000250ull;
96 }
97 #else
98 #define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
99 #endif
100 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
101 #define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC()
CVMX_NPEI_CTL_PORT1_FUNC(void)102 static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void)
103 {
104 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
105 cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n");
106 return 0x0000000000000260ull;
107 }
108 #else
109 #define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
110 #endif
111 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
112 #define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC()
CVMX_NPEI_CTL_STATUS_FUNC(void)113 static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void)
114 {
115 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
116 cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n");
117 return 0x0000000000000570ull;
118 }
119 #else
120 #define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
121 #endif
122 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
123 #define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC()
CVMX_NPEI_CTL_STATUS2_FUNC(void)124 static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void)
125 {
126 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
127 cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n");
128 return 0x0000000000003C00ull;
129 }
130 #else
131 #define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
132 #endif
133 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
134 #define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC()
CVMX_NPEI_DATA_OUT_CNT_FUNC(void)135 static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void)
136 {
137 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
138 cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n");
139 return 0x00000000000005F0ull;
140 }
141 #else
142 #define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
143 #endif
144 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
145 #define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC()
CVMX_NPEI_DBG_DATA_FUNC(void)146 static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void)
147 {
148 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
149 cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n");
150 return 0x0000000000000510ull;
151 }
152 #else
153 #define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
154 #endif
155 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
156 #define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC()
CVMX_NPEI_DBG_SELECT_FUNC(void)157 static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void)
158 {
159 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
160 cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n");
161 return 0x0000000000000500ull;
162 }
163 #else
164 #define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
165 #endif
166 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
167 #define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC()
CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)168 static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)
169 {
170 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
171 cvmx_warn("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
172 return 0x00000000000005C0ull;
173 }
174 #else
175 #define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
176 #endif
177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
178 #define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC()
CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)179 static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)
180 {
181 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
182 cvmx_warn("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
183 return 0x00000000000005D0ull;
184 }
185 #else
186 #define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
187 #endif
188 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_DMAX_COUNTS(unsigned long offset)189 static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset)
190 {
191 if (!(
192 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
193 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
194 cvmx_warn("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
195 return 0x0000000000000450ull + ((offset) & 7) * 16;
196 }
197 #else
198 #define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
199 #endif
200 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_DMAX_DBELL(unsigned long offset)201 static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset)
202 {
203 if (!(
204 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
205 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
206 cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
207 return 0x00000000000003B0ull + ((offset) & 7) * 16;
208 }
209 #else
210 #define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
211 #endif
212 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)213 static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
214 {
215 if (!(
216 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
217 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
218 cvmx_warn("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
219 return 0x0000000000000400ull + ((offset) & 7) * 16;
220 }
221 #else
222 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
223 #endif
224 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_DMAX_NADDR(unsigned long offset)225 static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset)
226 {
227 if (!(
228 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
229 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
230 cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
231 return 0x00000000000004A0ull + ((offset) & 7) * 16;
232 }
233 #else
234 #define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
235 #endif
236 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
237 #define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC()
CVMX_NPEI_DMA_CNTS_FUNC(void)238 static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void)
239 {
240 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
241 cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n");
242 return 0x00000000000005E0ull;
243 }
244 #else
245 #define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
246 #endif
247 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
248 #define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC()
CVMX_NPEI_DMA_CONTROL_FUNC(void)249 static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void)
250 {
251 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
252 cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n");
253 return 0x00000000000003A0ull;
254 }
255 #else
256 #define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
257 #endif
258 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
259 #define CVMX_NPEI_DMA_PCIE_REQ_NUM CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC()
CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)260 static inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
261 {
262 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
263 cvmx_warn("CVMX_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
264 return 0x00000000000005B0ull;
265 }
266 #else
267 #define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
268 #endif
269 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
270 #define CVMX_NPEI_DMA_STATE1 CVMX_NPEI_DMA_STATE1_FUNC()
CVMX_NPEI_DMA_STATE1_FUNC(void)271 static inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void)
272 {
273 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
274 cvmx_warn("CVMX_NPEI_DMA_STATE1 not supported on this chip\n");
275 return 0x00000000000006C0ull;
276 }
277 #else
278 #define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
279 #endif
280 #define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
281 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
282 #define CVMX_NPEI_DMA_STATE2 CVMX_NPEI_DMA_STATE2_FUNC()
CVMX_NPEI_DMA_STATE2_FUNC(void)283 static inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void)
284 {
285 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
286 cvmx_warn("CVMX_NPEI_DMA_STATE2 not supported on this chip\n");
287 return 0x00000000000006D0ull;
288 }
289 #else
290 #define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
291 #endif
292 #define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
293 #define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
294 #define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
295 #define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
296 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
297 #define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC()
CVMX_NPEI_INT_A_ENB_FUNC(void)298 static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void)
299 {
300 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
301 cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n");
302 return 0x0000000000000560ull;
303 }
304 #else
305 #define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
306 #endif
307 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
308 #define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC()
CVMX_NPEI_INT_A_ENB2_FUNC(void)309 static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void)
310 {
311 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
312 cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n");
313 return 0x0000000000003CE0ull;
314 }
315 #else
316 #define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
317 #endif
318 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
319 #define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC()
CVMX_NPEI_INT_A_SUM_FUNC(void)320 static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void)
321 {
322 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
323 cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n");
324 return 0x0000000000000550ull;
325 }
326 #else
327 #define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
328 #endif
329 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
330 #define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC()
CVMX_NPEI_INT_ENB_FUNC(void)331 static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void)
332 {
333 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
334 cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n");
335 return 0x0000000000000540ull;
336 }
337 #else
338 #define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
339 #endif
340 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
341 #define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC()
CVMX_NPEI_INT_ENB2_FUNC(void)342 static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void)
343 {
344 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
345 cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n");
346 return 0x0000000000003CD0ull;
347 }
348 #else
349 #define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
350 #endif
351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
352 #define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC()
CVMX_NPEI_INT_INFO_FUNC(void)353 static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void)
354 {
355 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
356 cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n");
357 return 0x0000000000000590ull;
358 }
359 #else
360 #define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
361 #endif
362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
363 #define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC()
CVMX_NPEI_INT_SUM_FUNC(void)364 static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void)
365 {
366 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
367 cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n");
368 return 0x0000000000000530ull;
369 }
370 #else
371 #define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
372 #endif
373 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
374 #define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC()
CVMX_NPEI_INT_SUM2_FUNC(void)375 static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void)
376 {
377 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
378 cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n");
379 return 0x0000000000003CC0ull;
380 }
381 #else
382 #define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
383 #endif
384 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
385 #define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC()
CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)386 static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)
387 {
388 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
389 cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
390 return 0x0000000000000600ull;
391 }
392 #else
393 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
394 #endif
395 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
396 #define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC()
CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)397 static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)
398 {
399 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
400 cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
401 return 0x0000000000000610ull;
402 }
403 #else
404 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
405 #endif
406 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
407 #define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC()
CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)408 static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)
409 {
410 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
411 cvmx_warn("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
412 return 0x00000000000004F0ull;
413 }
414 #else
415 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
416 #endif
417 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)418 static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
419 {
420 if (!(
421 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
422 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
423 cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
424 return 0x0000000000000280ull + ((offset) & 31) * 16 - 16*12;
425 }
426 #else
427 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
428 #endif
429 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
430 #define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC()
CVMX_NPEI_MSI_ENB0_FUNC(void)431 static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void)
432 {
433 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
434 cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n");
435 return 0x0000000000003C50ull;
436 }
437 #else
438 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
439 #endif
440 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
441 #define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC()
CVMX_NPEI_MSI_ENB1_FUNC(void)442 static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void)
443 {
444 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
445 cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n");
446 return 0x0000000000003C60ull;
447 }
448 #else
449 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
450 #endif
451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
452 #define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC()
CVMX_NPEI_MSI_ENB2_FUNC(void)453 static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void)
454 {
455 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
456 cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n");
457 return 0x0000000000003C70ull;
458 }
459 #else
460 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
461 #endif
462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
463 #define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC()
CVMX_NPEI_MSI_ENB3_FUNC(void)464 static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void)
465 {
466 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
467 cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n");
468 return 0x0000000000003C80ull;
469 }
470 #else
471 #define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
472 #endif
473 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
474 #define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC()
CVMX_NPEI_MSI_RCV0_FUNC(void)475 static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void)
476 {
477 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
478 cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n");
479 return 0x0000000000003C10ull;
480 }
481 #else
482 #define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
483 #endif
484 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
485 #define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC()
CVMX_NPEI_MSI_RCV1_FUNC(void)486 static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void)
487 {
488 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
489 cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n");
490 return 0x0000000000003C20ull;
491 }
492 #else
493 #define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
494 #endif
495 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
496 #define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC()
CVMX_NPEI_MSI_RCV2_FUNC(void)497 static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void)
498 {
499 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
500 cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n");
501 return 0x0000000000003C30ull;
502 }
503 #else
504 #define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
505 #endif
506 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
507 #define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC()
CVMX_NPEI_MSI_RCV3_FUNC(void)508 static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void)
509 {
510 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
511 cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n");
512 return 0x0000000000003C40ull;
513 }
514 #else
515 #define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
516 #endif
517 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
518 #define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC()
CVMX_NPEI_MSI_RD_MAP_FUNC(void)519 static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void)
520 {
521 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
522 cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n");
523 return 0x0000000000003CA0ull;
524 }
525 #else
526 #define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
527 #endif
528 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
529 #define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC()
CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)530 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)
531 {
532 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
533 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
534 return 0x0000000000003CF0ull;
535 }
536 #else
537 #define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
538 #endif
539 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
540 #define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC()
CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)541 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)
542 {
543 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
544 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
545 return 0x0000000000003D00ull;
546 }
547 #else
548 #define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
549 #endif
550 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
551 #define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC()
CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)552 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)
553 {
554 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
555 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
556 return 0x0000000000003D10ull;
557 }
558 #else
559 #define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
560 #endif
561 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
562 #define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC()
CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)563 static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)
564 {
565 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
566 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
567 return 0x0000000000003D20ull;
568 }
569 #else
570 #define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
571 #endif
572 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
573 #define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC()
CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)574 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)
575 {
576 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
577 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
578 return 0x0000000000003D30ull;
579 }
580 #else
581 #define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
582 #endif
583 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
584 #define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC()
CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)585 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)
586 {
587 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
588 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
589 return 0x0000000000003D40ull;
590 }
591 #else
592 #define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
593 #endif
594 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
595 #define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC()
CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)596 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)
597 {
598 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
599 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
600 return 0x0000000000003D50ull;
601 }
602 #else
603 #define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
604 #endif
605 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
606 #define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC()
CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)607 static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)
608 {
609 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
610 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
611 return 0x0000000000003D60ull;
612 }
613 #else
614 #define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
615 #endif
616 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
617 #define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC()
CVMX_NPEI_MSI_WR_MAP_FUNC(void)618 static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void)
619 {
620 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
621 cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n");
622 return 0x0000000000003C90ull;
623 }
624 #else
625 #define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
626 #endif
627 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
628 #define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC()
CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)629 static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)
630 {
631 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
632 cvmx_warn("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
633 return 0x0000000000003D70ull;
634 }
635 #else
636 #define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
637 #endif
638 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
639 #define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC()
CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)640 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)
641 {
642 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
643 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n");
644 return 0x0000000000003CB0ull;
645 }
646 #else
647 #define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
648 #endif
649 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
650 #define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC()
CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)651 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
652 {
653 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
654 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
655 return 0x0000000000000650ull;
656 }
657 #else
658 #define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
659 #endif
660 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
661 #define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC()
CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)662 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
663 {
664 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
665 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
666 return 0x0000000000000660ull;
667 }
668 #else
669 #define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
670 #endif
671 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
672 #define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC()
CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)673 static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
674 {
675 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
676 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
677 return 0x0000000000000670ull;
678 }
679 #else
680 #define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
681 #endif
682 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_CNTS(unsigned long offset)683 static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset)
684 {
685 if (!(
686 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
687 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
688 cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
689 return 0x0000000000002400ull + ((offset) & 31) * 16;
690 }
691 #else
692 #define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
693 #endif
694 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)695 static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
696 {
697 if (!(
698 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
699 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
700 cvmx_warn("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
701 return 0x0000000000002800ull + ((offset) & 31) * 16;
702 }
703 #else
704 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
705 #endif
706 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)707 static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
708 {
709 if (!(
710 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
711 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
712 cvmx_warn("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
713 return 0x0000000000002C00ull + ((offset) & 31) * 16;
714 }
715 #else
716 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
717 #endif
718 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)719 static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
720 {
721 if (!(
722 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
723 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
724 cvmx_warn("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
725 return 0x0000000000003000ull + ((offset) & 31) * 16;
726 }
727 #else
728 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
729 #endif
730 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)731 static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
732 {
733 if (!(
734 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
735 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
736 cvmx_warn("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
737 return 0x0000000000003400ull + ((offset) & 31) * 16;
738 }
739 #else
740 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
741 #endif
742 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_IN_BP(unsigned long offset)743 static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset)
744 {
745 if (!(
746 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
747 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
748 cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
749 return 0x0000000000003800ull + ((offset) & 31) * 16;
750 }
751 #else
752 #define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
753 #endif
754 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)755 static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
756 {
757 if (!(
758 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
759 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
760 cvmx_warn("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
761 return 0x0000000000001400ull + ((offset) & 31) * 16;
762 }
763 #else
764 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
765 #endif
766 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)767 static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
768 {
769 if (!(
770 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
771 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
772 cvmx_warn("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
773 return 0x0000000000001800ull + ((offset) & 31) * 16;
774 }
775 #else
776 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
777 #endif
778 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)779 static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
780 {
781 if (!(
782 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
783 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
784 cvmx_warn("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
785 return 0x0000000000001C00ull + ((offset) & 31) * 16;
786 }
787 #else
788 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
789 #endif
790 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
791 #define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC()
CVMX_NPEI_PKT_CNT_INT_FUNC(void)792 static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void)
793 {
794 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
795 cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n");
796 return 0x0000000000001110ull;
797 }
798 #else
799 #define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
800 #endif
801 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
802 #define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC()
CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)803 static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)
804 {
805 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
806 cvmx_warn("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
807 return 0x0000000000001130ull;
808 }
809 #else
810 #define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
811 #endif
812 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
813 #define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC()
CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)814 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)
815 {
816 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
817 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
818 return 0x00000000000010B0ull;
819 }
820 #else
821 #define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
822 #endif
823 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
824 #define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC()
CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)825 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)
826 {
827 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
828 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
829 return 0x00000000000010A0ull;
830 }
831 #else
832 #define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
833 #endif
834 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
835 #define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC()
CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)836 static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
837 {
838 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
839 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
840 return 0x0000000000001090ull;
841 }
842 #else
843 #define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
844 #endif
845 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
846 #define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC()
CVMX_NPEI_PKT_DPADDR_FUNC(void)847 static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void)
848 {
849 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
850 cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n");
851 return 0x0000000000001080ull;
852 }
853 #else
854 #define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
855 #endif
856 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
857 #define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC()
CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)858 static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)
859 {
860 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
861 cvmx_warn("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
862 return 0x0000000000001150ull;
863 }
864 #else
865 #define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
866 #endif
867 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
868 #define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC()
CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)869 static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)
870 {
871 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
872 cvmx_warn("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n");
873 return 0x0000000000001000ull;
874 }
875 #else
876 #define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
877 #endif
878 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
879 #define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC()
CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)880 static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
881 {
882 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
883 cvmx_warn("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
884 return 0x0000000000001190ull;
885 }
886 #else
887 #define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
888 #endif
889 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
890 #define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC()
CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)891 static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)
892 {
893 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
894 cvmx_warn("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
895 return 0x0000000000001020ull;
896 }
897 #else
898 #define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
899 #endif
900 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
901 #define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC()
CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)902 static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)
903 {
904 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
905 cvmx_warn("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n");
906 return 0x0000000000001100ull;
907 }
908 #else
909 #define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
910 #endif
911 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
912 #define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC()
CVMX_NPEI_PKT_IN_BP_FUNC(void)913 static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void)
914 {
915 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
916 cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n");
917 return 0x00000000000006B0ull;
918 }
919 #else
920 #define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
921 #endif
922 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)923 static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
924 {
925 if (!(
926 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
927 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
928 cvmx_warn("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
929 return 0x0000000000002000ull + ((offset) & 31) * 16;
930 }
931 #else
932 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
933 #endif
934 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
935 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)936 static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
937 {
938 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
939 cvmx_warn("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
940 return 0x00000000000006A0ull;
941 }
942 #else
943 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
944 #endif
945 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
946 #define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC()
CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)947 static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
948 {
949 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
950 cvmx_warn("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
951 return 0x00000000000011A0ull;
952 }
953 #else
954 #define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
955 #endif
956 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
957 #define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC()
CVMX_NPEI_PKT_IPTR_FUNC(void)958 static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void)
959 {
960 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
961 cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n");
962 return 0x0000000000001070ull;
963 }
964 #else
965 #define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
966 #endif
967 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
968 #define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC()
CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)969 static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
970 {
971 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
972 cvmx_warn("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
973 return 0x0000000000001160ull;
974 }
975 #else
976 #define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
977 #endif
978 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
979 #define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC()
CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)980 static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)
981 {
982 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
983 cvmx_warn("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n");
984 return 0x00000000000010D0ull;
985 }
986 #else
987 #define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
988 #endif
989 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
990 #define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC()
CVMX_NPEI_PKT_OUT_ENB_FUNC(void)991 static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void)
992 {
993 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
994 cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n");
995 return 0x0000000000001010ull;
996 }
997 #else
998 #define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
999 #endif
1000 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1001 #define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC()
CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)1002 static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)
1003 {
1004 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1005 cvmx_warn("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n");
1006 return 0x00000000000010E0ull;
1007 }
1008 #else
1009 #define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
1010 #endif
1011 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1012 #define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC()
CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)1013 static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)
1014 {
1015 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1016 cvmx_warn("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
1017 return 0x0000000000000690ull;
1018 }
1019 #else
1020 #define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
1021 #endif
1022 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1023 #define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC()
CVMX_NPEI_PKT_SLIST_ES_FUNC(void)1024 static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void)
1025 {
1026 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1027 cvmx_warn("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n");
1028 return 0x0000000000001050ull;
1029 }
1030 #else
1031 #define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
1032 #endif
1033 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1034 #define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC()
CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)1035 static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
1036 {
1037 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1038 cvmx_warn("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
1039 return 0x0000000000001180ull;
1040 }
1041 #else
1042 #define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
1043 #endif
1044 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1045 #define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC()
CVMX_NPEI_PKT_SLIST_NS_FUNC(void)1046 static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void)
1047 {
1048 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1049 cvmx_warn("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n");
1050 return 0x0000000000001040ull;
1051 }
1052 #else
1053 #define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
1054 #endif
1055 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1056 #define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC()
CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)1057 static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)
1058 {
1059 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1060 cvmx_warn("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n");
1061 return 0x0000000000001030ull;
1062 }
1063 #else
1064 #define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
1065 #endif
1066 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1067 #define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC()
CVMX_NPEI_PKT_TIME_INT_FUNC(void)1068 static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void)
1069 {
1070 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1071 cvmx_warn("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n");
1072 return 0x0000000000001120ull;
1073 }
1074 #else
1075 #define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
1076 #endif
1077 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1078 #define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC()
CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)1079 static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)
1080 {
1081 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1082 cvmx_warn("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
1083 return 0x0000000000001140ull;
1084 }
1085 #else
1086 #define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
1087 #endif
1088 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1089 #define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC()
CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)1090 static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)
1091 {
1092 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1093 cvmx_warn("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
1094 return 0x0000000000000520ull;
1095 }
1096 #else
1097 #define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
1098 #endif
1099 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1100 #define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC()
CVMX_NPEI_SCRATCH_1_FUNC(void)1101 static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void)
1102 {
1103 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1104 cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n");
1105 return 0x0000000000000270ull;
1106 }
1107 #else
1108 #define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
1109 #endif
1110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1111 #define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC()
CVMX_NPEI_STATE1_FUNC(void)1112 static inline uint64_t CVMX_NPEI_STATE1_FUNC(void)
1113 {
1114 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1115 cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n");
1116 return 0x0000000000000620ull;
1117 }
1118 #else
1119 #define CVMX_NPEI_STATE1 (0x0000000000000620ull)
1120 #endif
1121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1122 #define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC()
CVMX_NPEI_STATE2_FUNC(void)1123 static inline uint64_t CVMX_NPEI_STATE2_FUNC(void)
1124 {
1125 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1126 cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n");
1127 return 0x0000000000000630ull;
1128 }
1129 #else
1130 #define CVMX_NPEI_STATE2 (0x0000000000000630ull)
1131 #endif
1132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1133 #define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC()
CVMX_NPEI_STATE3_FUNC(void)1134 static inline uint64_t CVMX_NPEI_STATE3_FUNC(void)
1135 {
1136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1137 cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n");
1138 return 0x0000000000000640ull;
1139 }
1140 #else
1141 #define CVMX_NPEI_STATE3 (0x0000000000000640ull)
1142 #endif
1143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1144 #define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC()
CVMX_NPEI_WINDOW_CTL_FUNC(void)1145 static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void)
1146 {
1147 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1148 cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n");
1149 return 0x0000000000000380ull;
1150 }
1151 #else
1152 #define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
1153 #endif
1154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1155 #define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC()
CVMX_NPEI_WIN_RD_ADDR_FUNC(void)1156 static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void)
1157 {
1158 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1159 cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n");
1160 return 0x0000000000000210ull;
1161 }
1162 #else
1163 #define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
1164 #endif
1165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1166 #define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC()
CVMX_NPEI_WIN_RD_DATA_FUNC(void)1167 static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void)
1168 {
1169 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1170 cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n");
1171 return 0x0000000000000240ull;
1172 }
1173 #else
1174 #define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
1175 #endif
1176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1177 #define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC()
CVMX_NPEI_WIN_WR_ADDR_FUNC(void)1178 static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void)
1179 {
1180 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1181 cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n");
1182 return 0x0000000000000200ull;
1183 }
1184 #else
1185 #define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
1186 #endif
1187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1188 #define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC()
CVMX_NPEI_WIN_WR_DATA_FUNC(void)1189 static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void)
1190 {
1191 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1192 cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n");
1193 return 0x0000000000000220ull;
1194 }
1195 #else
1196 #define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
1197 #endif
1198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1199 #define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC()
CVMX_NPEI_WIN_WR_MASK_FUNC(void)1200 static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
1201 {
1202 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1203 cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n");
1204 return 0x0000000000000230ull;
1205 }
1206 #else
1207 #define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
1208 #endif
1209
1210 /**
1211 * cvmx_npei_bar1_index#
1212 *
1213 * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B)
1214 *
1215 * General 5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General)
1216 * PktMem 10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet)
1217 * Rsvd 1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode)
1218 * == NPEI_PKT_CNT_INT_ENB[PORT]
1219 * == NPEI_PKT_TIME_INT_ENB[PORT]
1220 * == NPEI_PKT_CNT_INT[PORT]
1221 * == NPEI_PKT_TIME_INT[PORT]
1222 * == NPEI_PKT_PCIE_PORT[PP]
1223 * == NPEI_PKT_SLIST_ROR[ROR]
1224 * == NPEI_PKT_SLIST_ROR[NSR] ?
1225 * == NPEI_PKT_SLIST_ES[ES]
1226 * == NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
1227 * == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
1228 * == NPEI_PKTn_CNTS[CNT]
1229 * NPEI_CTL_STATUS[OUTn_ENB] == NPEI_PKT_OUT_ENB[ENB]
1230 * NPEI_BASE_ADDRESS_OUTPUTn[BADDR] == NPEI_PKTn_SLIST_BADDR[ADDR]
1231 * NPEI_DESC_OUTPUTn[SIZE] == NPEI_PKTn_SLIST_FIFO_RSIZE[RSIZE]
1232 * NPEI_Pn_DBPAIR_ADDR[NADDR] == NPEI_PKTn_SLIST_BADDR[ADDR] + NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
1233 * NPEI_PKT_CREDITSn[PTR_CNT] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
1234 * NPEI_P0_PAIR_CNTS[AVAIL] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
1235 * NPEI_P0_PAIR_CNTS[FCNT] ==
1236 * NPEI_PKTS_SENTn[PKT_CNT] == NPEI_PKTn_CNTS[CNT]
1237 * NPEI_OUTPUT_CONTROL[Pn_BMODE] == NPEI_PKT_OUT_BMODE[BMODE]
1238 * NPEI_PKT_CREDITSn[PKT_CNT] == NPEI_PKTn_CNTS[CNT]
1239 * NPEI_BUFF_SIZE_OUTPUTn[BSIZE] == NPEI_PKT_SLIST_ID_SIZE[BSIZE]
1240 * NPEI_BUFF_SIZE_OUTPUTn[ISIZE] == NPEI_PKT_SLIST_ID_SIZE[ISIZE]
1241 * NPEI_OUTPUT_CONTROL[On_CSRM] == NPEI_PKT_DPADDR[DPTR] & NPEI_PKT_OUT_USE_IPTR[PORT]
1242 * NPEI_OUTPUT_CONTROL[On_ES] == NPEI_PKT_DATA_OUT_ES[ES]
1243 * NPEI_OUTPUT_CONTROL[On_NS] == NPEI_PKT_DATA_OUT_NS[NSR] ?
1244 * NPEI_OUTPUT_CONTROL[On_RO] == NPEI_PKT_DATA_OUT_ROR[ROR]
1245 * NPEI_PKTS_SENT_INT_LEVn[PKT_CNT] == NPEI_PKT_INT_LEVELS[CNT]
1246 * NPEI_PKTS_SENT_TIMEn[PKT_TIME] == NPEI_PKT_INT_LEVELS[TIME]
1247 * NPEI_OUTPUT_CONTROL[IPTR_On] == NPEI_PKT_IPTR[IPTR]
1248 * NPEI_PCIE_PORT_OUTPUT[] == NPEI_PKT_PCIE_PORT[PP]
1249 *
1250 * NPEI_BAR1_INDEXX = NPEI BAR1 IndexX Register
1251 *
1252 * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
1253 * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16
1254 * through NPEI_BAR1_INDEX31 is used for transactions originating with PCIE-PORT1.
1255 */
1256 union cvmx_npei_bar1_indexx {
1257 uint32_t u32;
1258 struct cvmx_npei_bar1_indexx_s {
1259 #ifdef __BIG_ENDIAN_BITFIELD
1260 uint32_t reserved_18_31 : 14;
1261 uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */
1262 uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */
1263 uint32_t end_swp : 2; /**< Endian Swap Mode */
1264 uint32_t addr_v : 1; /**< Set '1' when the selected address range is valid. */
1265 #else
1266 uint32_t addr_v : 1;
1267 uint32_t end_swp : 2;
1268 uint32_t ca : 1;
1269 uint32_t addr_idx : 14;
1270 uint32_t reserved_18_31 : 14;
1271 #endif
1272 } s;
1273 struct cvmx_npei_bar1_indexx_s cn52xx;
1274 struct cvmx_npei_bar1_indexx_s cn52xxp1;
1275 struct cvmx_npei_bar1_indexx_s cn56xx;
1276 struct cvmx_npei_bar1_indexx_s cn56xxp1;
1277 };
1278 typedef union cvmx_npei_bar1_indexx cvmx_npei_bar1_indexx_t;
1279
1280 /**
1281 * cvmx_npei_bist_status
1282 *
1283 * NPEI_BIST_STATUS = NPI's BIST Status Register
1284 *
1285 * Results from BIST runs of NPEI's memories.
1286 */
1287 union cvmx_npei_bist_status {
1288 uint64_t u64;
1289 struct cvmx_npei_bist_status_s {
1290 #ifdef __BIG_ENDIAN_BITFIELD
1291 uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */
1292 uint64_t reserved_60_62 : 3;
1293 uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */
1294 uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */
1295 uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */
1296 uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */
1297 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */
1298 uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */
1299 uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */
1300 uint64_t reserved_50_52 : 3;
1301 uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */
1302 uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */
1303 uint64_t reserved_36_47 : 12;
1304 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1305 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1306 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1307 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1308 uint64_t reserved_31_31 : 1;
1309 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1310 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1311 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1312 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1313 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1314 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1315 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1316 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1317 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1318 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1319 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1320 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1321 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1322 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1323 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1324 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1325 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1326 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1327 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1328 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1329 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1330 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1331 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1332 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1333 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1334 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1335 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1336 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1337 uint64_t reserved_2_2 : 1;
1338 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1339 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1340 #else
1341 uint64_t ncb_cmd : 1;
1342 uint64_t msi : 1;
1343 uint64_t reserved_2_2 : 1;
1344 uint64_t dif3 : 1;
1345 uint64_t dif2 : 1;
1346 uint64_t dif1 : 1;
1347 uint64_t dif0 : 1;
1348 uint64_t csm1 : 1;
1349 uint64_t csm0 : 1;
1350 uint64_t p2n1_p1 : 1;
1351 uint64_t p2n1_p0 : 1;
1352 uint64_t p2n1_n : 1;
1353 uint64_t p2n1_c1 : 1;
1354 uint64_t p2n1_c0 : 1;
1355 uint64_t p2n0_p1 : 1;
1356 uint64_t p2n0_p0 : 1;
1357 uint64_t p2n0_n : 1;
1358 uint64_t p2n0_c1 : 1;
1359 uint64_t p2n0_c0 : 1;
1360 uint64_t p2n0_co : 1;
1361 uint64_t p2n0_no : 1;
1362 uint64_t p2n0_po : 1;
1363 uint64_t p2n1_co : 1;
1364 uint64_t p2n1_no : 1;
1365 uint64_t p2n1_po : 1;
1366 uint64_t cpl_p1 : 1;
1367 uint64_t cpl_p0 : 1;
1368 uint64_t n2p1_o : 1;
1369 uint64_t n2p1_c : 1;
1370 uint64_t n2p0_o : 1;
1371 uint64_t n2p0_c : 1;
1372 uint64_t reserved_31_31 : 1;
1373 uint64_t d3_pst : 1;
1374 uint64_t d2_pst : 1;
1375 uint64_t d1_pst : 1;
1376 uint64_t d0_pst : 1;
1377 uint64_t reserved_36_47 : 12;
1378 uint64_t pkt_slm : 1;
1379 uint64_t pkt_ind : 1;
1380 uint64_t reserved_50_52 : 3;
1381 uint64_t pcsr_sl : 1;
1382 uint64_t pcsr_id : 1;
1383 uint64_t pcsr_cnt : 1;
1384 uint64_t pcsr_im : 1;
1385 uint64_t pcsr_int : 1;
1386 uint64_t pkt_pif : 1;
1387 uint64_t pcr_gim : 1;
1388 uint64_t reserved_60_62 : 3;
1389 uint64_t pkt_rdf : 1;
1390 #endif
1391 } s;
1392 struct cvmx_npei_bist_status_cn52xx {
1393 #ifdef __BIG_ENDIAN_BITFIELD
1394 uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */
1395 uint64_t reserved_60_62 : 3;
1396 uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */
1397 uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */
1398 uint64_t pcsr_int : 1; /**< BIST Status for PKT OUTB Interrupt MEM */
1399 uint64_t pcsr_im : 1; /**< BIST Status for PKT CSR Instr MEM */
1400 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT INB Count MEM */
1401 uint64_t pcsr_id : 1; /**< BIST Status for PKT INB Instr Done MEM */
1402 uint64_t pcsr_sl : 1; /**< BIST Status for PKT OUTB SLIST MEM */
1403 uint64_t pkt_imem : 1; /**< BIST Status for PKT OUTB IFIFO */
1404 uint64_t pkt_pfm : 1; /**< BIST Status for PKT Front MEM */
1405 uint64_t pkt_pof : 1; /**< BIST Status for PKT OUTB FIFO */
1406 uint64_t reserved_48_49 : 2;
1407 uint64_t pkt_pop0 : 1; /**< BIST Status for PKT OUTB Slist0 */
1408 uint64_t pkt_pop1 : 1; /**< BIST Status for PKT OUTB Slist1 */
1409 uint64_t d0_mem : 1; /**< BIST Status for DMA MEM 0 */
1410 uint64_t d1_mem : 1; /**< BIST Status for DMA MEM 1 */
1411 uint64_t d2_mem : 1; /**< BIST Status for DMA MEM 2 */
1412 uint64_t d3_mem : 1; /**< BIST Status for DMA MEM 3 */
1413 uint64_t d4_mem : 1; /**< BIST Status for DMA MEM 4 */
1414 uint64_t ds_mem : 1; /**< BIST Status for DMA Memory */
1415 uint64_t reserved_36_39 : 4;
1416 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1417 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1418 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1419 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1420 uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */
1421 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1422 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1423 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1424 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1425 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1426 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1427 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1428 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1429 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1430 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1431 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1432 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1433 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1434 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1435 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1436 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1437 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1438 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1439 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1440 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1441 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1442 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1443 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1444 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1445 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1446 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1447 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1448 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1449 uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */
1450 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1451 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1452 #else
1453 uint64_t ncb_cmd : 1;
1454 uint64_t msi : 1;
1455 uint64_t dif4 : 1;
1456 uint64_t dif3 : 1;
1457 uint64_t dif2 : 1;
1458 uint64_t dif1 : 1;
1459 uint64_t dif0 : 1;
1460 uint64_t csm1 : 1;
1461 uint64_t csm0 : 1;
1462 uint64_t p2n1_p1 : 1;
1463 uint64_t p2n1_p0 : 1;
1464 uint64_t p2n1_n : 1;
1465 uint64_t p2n1_c1 : 1;
1466 uint64_t p2n1_c0 : 1;
1467 uint64_t p2n0_p1 : 1;
1468 uint64_t p2n0_p0 : 1;
1469 uint64_t p2n0_n : 1;
1470 uint64_t p2n0_c1 : 1;
1471 uint64_t p2n0_c0 : 1;
1472 uint64_t p2n0_co : 1;
1473 uint64_t p2n0_no : 1;
1474 uint64_t p2n0_po : 1;
1475 uint64_t p2n1_co : 1;
1476 uint64_t p2n1_no : 1;
1477 uint64_t p2n1_po : 1;
1478 uint64_t cpl_p1 : 1;
1479 uint64_t cpl_p0 : 1;
1480 uint64_t n2p1_o : 1;
1481 uint64_t n2p1_c : 1;
1482 uint64_t n2p0_o : 1;
1483 uint64_t n2p0_c : 1;
1484 uint64_t d4_pst : 1;
1485 uint64_t d3_pst : 1;
1486 uint64_t d2_pst : 1;
1487 uint64_t d1_pst : 1;
1488 uint64_t d0_pst : 1;
1489 uint64_t reserved_36_39 : 4;
1490 uint64_t ds_mem : 1;
1491 uint64_t d4_mem : 1;
1492 uint64_t d3_mem : 1;
1493 uint64_t d2_mem : 1;
1494 uint64_t d1_mem : 1;
1495 uint64_t d0_mem : 1;
1496 uint64_t pkt_pop1 : 1;
1497 uint64_t pkt_pop0 : 1;
1498 uint64_t reserved_48_49 : 2;
1499 uint64_t pkt_pof : 1;
1500 uint64_t pkt_pfm : 1;
1501 uint64_t pkt_imem : 1;
1502 uint64_t pcsr_sl : 1;
1503 uint64_t pcsr_id : 1;
1504 uint64_t pcsr_cnt : 1;
1505 uint64_t pcsr_im : 1;
1506 uint64_t pcsr_int : 1;
1507 uint64_t pkt_pif : 1;
1508 uint64_t pcr_gim : 1;
1509 uint64_t reserved_60_62 : 3;
1510 uint64_t pkt_rdf : 1;
1511 #endif
1512 } cn52xx;
1513 struct cvmx_npei_bist_status_cn52xxp1 {
1514 #ifdef __BIG_ENDIAN_BITFIELD
1515 uint64_t reserved_46_63 : 18;
1516 uint64_t d0_mem0 : 1; /**< BIST Status for DMA0 Memory */
1517 uint64_t d1_mem1 : 1; /**< BIST Status for DMA1 Memory */
1518 uint64_t d2_mem2 : 1; /**< BIST Status for DMA2 Memory */
1519 uint64_t d3_mem3 : 1; /**< BIST Status for DMA3 Memory */
1520 uint64_t dr0_mem : 1; /**< BIST Status for DMA0 Store */
1521 uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */
1522 uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */
1523 uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */
1524 uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */
1525 uint64_t dr1_mem : 1; /**< BIST Status for DMA1 Store */
1526 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1527 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1528 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1529 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1530 uint64_t dr2_mem : 1; /**< BIST Status for DMA2 Store */
1531 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1532 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1533 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1534 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1535 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1536 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1537 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1538 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1539 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1540 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1541 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1542 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1543 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1544 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1545 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1546 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1547 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1548 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1549 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1550 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1551 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1552 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1553 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1554 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1555 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1556 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1557 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1558 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1559 uint64_t dr3_mem : 1; /**< BIST Status for DMA3 Store */
1560 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1561 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1562 #else
1563 uint64_t ncb_cmd : 1;
1564 uint64_t msi : 1;
1565 uint64_t dr3_mem : 1;
1566 uint64_t dif3 : 1;
1567 uint64_t dif2 : 1;
1568 uint64_t dif1 : 1;
1569 uint64_t dif0 : 1;
1570 uint64_t csm1 : 1;
1571 uint64_t csm0 : 1;
1572 uint64_t p2n1_p1 : 1;
1573 uint64_t p2n1_p0 : 1;
1574 uint64_t p2n1_n : 1;
1575 uint64_t p2n1_c1 : 1;
1576 uint64_t p2n1_c0 : 1;
1577 uint64_t p2n0_p1 : 1;
1578 uint64_t p2n0_p0 : 1;
1579 uint64_t p2n0_n : 1;
1580 uint64_t p2n0_c1 : 1;
1581 uint64_t p2n0_c0 : 1;
1582 uint64_t p2n0_co : 1;
1583 uint64_t p2n0_no : 1;
1584 uint64_t p2n0_po : 1;
1585 uint64_t p2n1_co : 1;
1586 uint64_t p2n1_no : 1;
1587 uint64_t p2n1_po : 1;
1588 uint64_t cpl_p1 : 1;
1589 uint64_t cpl_p0 : 1;
1590 uint64_t n2p1_o : 1;
1591 uint64_t n2p1_c : 1;
1592 uint64_t n2p0_o : 1;
1593 uint64_t n2p0_c : 1;
1594 uint64_t dr2_mem : 1;
1595 uint64_t d3_pst : 1;
1596 uint64_t d2_pst : 1;
1597 uint64_t d1_pst : 1;
1598 uint64_t d0_pst : 1;
1599 uint64_t dr1_mem : 1;
1600 uint64_t d3_mem : 1;
1601 uint64_t d2_mem : 1;
1602 uint64_t d1_mem : 1;
1603 uint64_t d0_mem : 1;
1604 uint64_t dr0_mem : 1;
1605 uint64_t d3_mem3 : 1;
1606 uint64_t d2_mem2 : 1;
1607 uint64_t d1_mem1 : 1;
1608 uint64_t d0_mem0 : 1;
1609 uint64_t reserved_46_63 : 18;
1610 #endif
1611 } cn52xxp1;
1612 struct cvmx_npei_bist_status_cn52xx cn56xx;
1613 struct cvmx_npei_bist_status_cn56xxp1 {
1614 #ifdef __BIG_ENDIAN_BITFIELD
1615 uint64_t reserved_58_63 : 6;
1616 uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */
1617 uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */
1618 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */
1619 uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */
1620 uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */
1621 uint64_t pkt_pout : 1; /**< BIST Status for PKT OUT Count MEM */
1622 uint64_t pkt_imem : 1; /**< BIST Status for PKT Instruction MEM */
1623 uint64_t pkt_cntm : 1; /**< BIST Status for PKT Count MEM */
1624 uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */
1625 uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */
1626 uint64_t pkt_odf : 1; /**< BIST Status for PKT Output Data FIFO */
1627 uint64_t pkt_oif : 1; /**< BIST Status for PKT Output INFO FIFO */
1628 uint64_t pkt_out : 1; /**< BIST Status for PKT Output FIFO */
1629 uint64_t pkt_i0 : 1; /**< BIST Status for PKT Instr0 */
1630 uint64_t pkt_i1 : 1; /**< BIST Status for PKT Instr1 */
1631 uint64_t pkt_s0 : 1; /**< BIST Status for PKT Slist0 */
1632 uint64_t pkt_s1 : 1; /**< BIST Status for PKT Slist1 */
1633 uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */
1634 uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */
1635 uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */
1636 uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */
1637 uint64_t d4_mem : 1; /**< BIST Status for DMA4 Memory */
1638 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */
1639 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */
1640 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */
1641 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */
1642 uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */
1643 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
1644 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
1645 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
1646 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
1647 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
1648 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
1649 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */
1650 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */
1651 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */
1652 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */
1653 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */
1654 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */
1655 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
1656 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
1657 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
1658 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
1659 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
1660 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
1661 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
1662 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
1663 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
1664 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
1665 uint64_t csm0 : 1; /**< BIST Status for CSM0 */
1666 uint64_t csm1 : 1; /**< BIST Status for CSM1 */
1667 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */
1668 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */
1669 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */
1670 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */
1671 uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */
1672 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
1673 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
1674 #else
1675 uint64_t ncb_cmd : 1;
1676 uint64_t msi : 1;
1677 uint64_t dif4 : 1;
1678 uint64_t dif3 : 1;
1679 uint64_t dif2 : 1;
1680 uint64_t dif1 : 1;
1681 uint64_t dif0 : 1;
1682 uint64_t csm1 : 1;
1683 uint64_t csm0 : 1;
1684 uint64_t p2n1_p1 : 1;
1685 uint64_t p2n1_p0 : 1;
1686 uint64_t p2n1_n : 1;
1687 uint64_t p2n1_c1 : 1;
1688 uint64_t p2n1_c0 : 1;
1689 uint64_t p2n0_p1 : 1;
1690 uint64_t p2n0_p0 : 1;
1691 uint64_t p2n0_n : 1;
1692 uint64_t p2n0_c1 : 1;
1693 uint64_t p2n0_c0 : 1;
1694 uint64_t p2n0_co : 1;
1695 uint64_t p2n0_no : 1;
1696 uint64_t p2n0_po : 1;
1697 uint64_t p2n1_co : 1;
1698 uint64_t p2n1_no : 1;
1699 uint64_t p2n1_po : 1;
1700 uint64_t cpl_p1 : 1;
1701 uint64_t cpl_p0 : 1;
1702 uint64_t n2p1_o : 1;
1703 uint64_t n2p1_c : 1;
1704 uint64_t n2p0_o : 1;
1705 uint64_t n2p0_c : 1;
1706 uint64_t d4_pst : 1;
1707 uint64_t d3_pst : 1;
1708 uint64_t d2_pst : 1;
1709 uint64_t d1_pst : 1;
1710 uint64_t d0_pst : 1;
1711 uint64_t d4_mem : 1;
1712 uint64_t d3_mem : 1;
1713 uint64_t d2_mem : 1;
1714 uint64_t d1_mem : 1;
1715 uint64_t d0_mem : 1;
1716 uint64_t pkt_s1 : 1;
1717 uint64_t pkt_s0 : 1;
1718 uint64_t pkt_i1 : 1;
1719 uint64_t pkt_i0 : 1;
1720 uint64_t pkt_out : 1;
1721 uint64_t pkt_oif : 1;
1722 uint64_t pkt_odf : 1;
1723 uint64_t pkt_slm : 1;
1724 uint64_t pkt_ind : 1;
1725 uint64_t pkt_cntm : 1;
1726 uint64_t pkt_imem : 1;
1727 uint64_t pkt_pout : 1;
1728 uint64_t pcsr_sl : 1;
1729 uint64_t pcsr_id : 1;
1730 uint64_t pcsr_cnt : 1;
1731 uint64_t pcsr_im : 1;
1732 uint64_t pcsr_int : 1;
1733 uint64_t reserved_58_63 : 6;
1734 #endif
1735 } cn56xxp1;
1736 };
1737 typedef union cvmx_npei_bist_status cvmx_npei_bist_status_t;
1738
1739 /**
1740 * cvmx_npei_bist_status2
1741 *
1742 * NPEI_BIST_STATUS2 = NPI's BIST Status Register2
1743 *
1744 * Results from BIST runs of NPEI's memories.
1745 */
1746 union cvmx_npei_bist_status2 {
1747 uint64_t u64;
1748 struct cvmx_npei_bist_status2_s {
1749 #ifdef __BIG_ENDIAN_BITFIELD
1750 uint64_t reserved_14_63 : 50;
1751 uint64_t prd_tag : 1; /**< BIST Status for DMA PCIE RD Tag MEM */
1752 uint64_t prd_st0 : 1; /**< BIST Status for DMA PCIE RD state MEM 0 */
1753 uint64_t prd_st1 : 1; /**< BIST Status for DMA PCIE RD state MEM 1 */
1754 uint64_t prd_err : 1; /**< BIST Status for DMA PCIE RD ERR state MEM */
1755 uint64_t nrd_st : 1; /**< BIST Status for DMA L2C RD state MEM */
1756 uint64_t nwe_st : 1; /**< BIST Status for DMA L2C WR state MEM */
1757 uint64_t nwe_wr0 : 1; /**< BIST Status for DMA L2C WR MEM 0 */
1758 uint64_t nwe_wr1 : 1; /**< BIST Status for DMA L2C WR MEM 1 */
1759 uint64_t pkt_rd : 1; /**< BIST Status for Inbound PKT MEM */
1760 uint64_t psc_p0 : 1; /**< BIST Status for PSC TLP 0 MEM */
1761 uint64_t psc_p1 : 1; /**< BIST Status for PSC TLP 1 MEM */
1762 uint64_t pkt_gd : 1; /**< BIST Status for PKT OUTB Gather Data FIFO */
1763 uint64_t pkt_gl : 1; /**< BIST Status for PKT_OUTB Gather List FIFO */
1764 uint64_t pkt_blk : 1; /**< BIST Status for PKT OUTB Blocked FIFO */
1765 #else
1766 uint64_t pkt_blk : 1;
1767 uint64_t pkt_gl : 1;
1768 uint64_t pkt_gd : 1;
1769 uint64_t psc_p1 : 1;
1770 uint64_t psc_p0 : 1;
1771 uint64_t pkt_rd : 1;
1772 uint64_t nwe_wr1 : 1;
1773 uint64_t nwe_wr0 : 1;
1774 uint64_t nwe_st : 1;
1775 uint64_t nrd_st : 1;
1776 uint64_t prd_err : 1;
1777 uint64_t prd_st1 : 1;
1778 uint64_t prd_st0 : 1;
1779 uint64_t prd_tag : 1;
1780 uint64_t reserved_14_63 : 50;
1781 #endif
1782 } s;
1783 struct cvmx_npei_bist_status2_s cn52xx;
1784 struct cvmx_npei_bist_status2_s cn56xx;
1785 };
1786 typedef union cvmx_npei_bist_status2 cvmx_npei_bist_status2_t;
1787
1788 /**
1789 * cvmx_npei_ctl_port0
1790 *
1791 * NPEI_CTL_PORT0 = NPEI's Control Port 0
1792 *
1793 * Contains control for access for Port0
1794 */
1795 union cvmx_npei_ctl_port0 {
1796 uint64_t u64;
1797 struct cvmx_npei_ctl_port0_s {
1798 #ifdef __BIG_ENDIAN_BITFIELD
1799 uint64_t reserved_21_63 : 43;
1800 uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit
1801 from the L2C before sending additional completions
1802 to the L2C from the PCIe.
1803 Set this for more conservative behavior. Clear
1804 this for more aggressive, higher-performance
1805 behavior */
1806 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */
1807 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */
1808 uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */
1809 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */
1810 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
1811 INTD (11). */
1812 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
1813 INTD (11). */
1814 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
1815 INTD (11). */
1816 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
1817 INTD (11). */
1818 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */
1819 uint64_t reserved_6_6 : 1;
1820 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */
1821 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when
1822 clear '0' BAR2 access will cause UR responses. */
1823 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to
1824 determine the endian swap mode. */
1825 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to
1826 determine the L2 cache attribute.
1827 Not cached in L2 if XOR result is 1 */
1828 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1829 from the L2C before sending additional stores to
1830 the L2C from the PCIe.
1831 Most applications will not notice a difference, so
1832 should not set this bit. Setting the bit is more
1833 conservative on ordering, lower performance */
1834 #else
1835 uint64_t wait_com : 1;
1836 uint64_t bar2_cax : 1;
1837 uint64_t bar2_esx : 2;
1838 uint64_t bar2_enb : 1;
1839 uint64_t ptlp_ro : 1;
1840 uint64_t reserved_6_6 : 1;
1841 uint64_t ctlp_ro : 1;
1842 uint64_t inta_map : 2;
1843 uint64_t intb_map : 2;
1844 uint64_t intc_map : 2;
1845 uint64_t intd_map : 2;
1846 uint64_t inta : 1;
1847 uint64_t intb : 1;
1848 uint64_t intc : 1;
1849 uint64_t intd : 1;
1850 uint64_t waitl_com : 1;
1851 uint64_t reserved_21_63 : 43;
1852 #endif
1853 } s;
1854 struct cvmx_npei_ctl_port0_s cn52xx;
1855 struct cvmx_npei_ctl_port0_s cn52xxp1;
1856 struct cvmx_npei_ctl_port0_s cn56xx;
1857 struct cvmx_npei_ctl_port0_s cn56xxp1;
1858 };
1859 typedef union cvmx_npei_ctl_port0 cvmx_npei_ctl_port0_t;
1860
1861 /**
1862 * cvmx_npei_ctl_port1
1863 *
1864 * NPEI_CTL_PORT1 = NPEI's Control Port1
1865 *
1866 * Contains control for access for Port1
1867 */
1868 union cvmx_npei_ctl_port1 {
1869 uint64_t u64;
1870 struct cvmx_npei_ctl_port1_s {
1871 #ifdef __BIG_ENDIAN_BITFIELD
1872 uint64_t reserved_21_63 : 43;
1873 uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit
1874 from the L2C before sending additional completions
1875 to the L2C from the PCIe.
1876 Set this for more conservative behavior. Clear
1877 this for more aggressive, higher-performance */
1878 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */
1879 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */
1880 uint64_t intb : 1; /**< When '0' Intv wire asserted. Before mapping. */
1881 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */
1882 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
1883 INTD (11). */
1884 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
1885 INTD (11). */
1886 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
1887 INTD (11). */
1888 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
1889 INTD (11). */
1890 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */
1891 uint64_t reserved_6_6 : 1;
1892 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */
1893 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when
1894 clear '0' BAR2 access will cause UR responses. */
1895 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to
1896 determine the endian swap mode. */
1897 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to
1898 determine the L2 cache attribute.
1899 Not cached in L2 if XOR result is 1 */
1900 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit
1901 from the L2C before sending additional stores to
1902 the L2C from the PCIe.
1903 Most applications will not notice a difference, so
1904 should not set this bit. Setting the bit is more
1905 conservative on ordering, lower performance */
1906 #else
1907 uint64_t wait_com : 1;
1908 uint64_t bar2_cax : 1;
1909 uint64_t bar2_esx : 2;
1910 uint64_t bar2_enb : 1;
1911 uint64_t ptlp_ro : 1;
1912 uint64_t reserved_6_6 : 1;
1913 uint64_t ctlp_ro : 1;
1914 uint64_t inta_map : 2;
1915 uint64_t intb_map : 2;
1916 uint64_t intc_map : 2;
1917 uint64_t intd_map : 2;
1918 uint64_t inta : 1;
1919 uint64_t intb : 1;
1920 uint64_t intc : 1;
1921 uint64_t intd : 1;
1922 uint64_t waitl_com : 1;
1923 uint64_t reserved_21_63 : 43;
1924 #endif
1925 } s;
1926 struct cvmx_npei_ctl_port1_s cn52xx;
1927 struct cvmx_npei_ctl_port1_s cn52xxp1;
1928 struct cvmx_npei_ctl_port1_s cn56xx;
1929 struct cvmx_npei_ctl_port1_s cn56xxp1;
1930 };
1931 typedef union cvmx_npei_ctl_port1 cvmx_npei_ctl_port1_t;
1932
1933 /**
1934 * cvmx_npei_ctl_status
1935 *
1936 * NPEI_CTL_STATUS = NPEI Control Status Register
1937 *
1938 * Contains control and status for NPEI. Writes to this register are not oSrdered with writes/reads to the PCIe Memory space.
1939 * To ensure that a write has completed the user must read the register before making an access(i.e. PCIe memory space)
1940 * that requires the value of this register to be updated.
1941 */
1942 union cvmx_npei_ctl_status {
1943 uint64_t u64;
1944 struct cvmx_npei_ctl_status_s {
1945 #ifdef __BIG_ENDIAN_BITFIELD
1946 uint64_t reserved_44_63 : 20;
1947 uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1.
1948 In RC mode 1 tag is needed for each outbound TLP
1949 that requires a CPL TLP. In Endpoint mode the
1950 number of tags required for a TLP request is
1951 1 per 64-bytes of CPL data + 1.
1952 This field should only be written as part of
1953 reset sequence, before issuing any reads, CFGs, or
1954 IO transactions from the core(s). */
1955 uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0.
1956 In RC mode 1 tag is needed for each outbound TLP
1957 that requires a CPL TLP. In Endpoint mode the
1958 number of tags required for a TLP request is
1959 1 per 64-bytes of CPL data + 1.
1960 This field should only be written as part of
1961 reset sequence, before issuing any reads, CFGs, or
1962 IO transactions from the core(s). */
1963 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a
1964 CPL to a CFG RD that does not carry a Retry Status.
1965 Until such time that the timeout occurs and Retry
1966 Status is received for a CFG RD, the Read CFG Read
1967 will be resent. A value of 0 disables retries and
1968 treats a CPL Retry as a CPL UR. */
1969 uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received
1970 from PKO to be zero, and replicates the back-
1971 pressure indication for the first ring attached
1972 to a PKO port across all the rings attached to a
1973 PKO port. When '1' backpressure is on a per
1974 port/ring. */
1975 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to
1976 link down state. This bit is only reset on raw
1977 reset so it can be read for state to determine if
1978 a reset occured. Bit is cleared when a '1' is
1979 written to this field. */
1980 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority
1981 NPEI, PCIe0, then PCIe1. '1' == round robin. */
1982 uint64_t pkt_bp : 4; /**< Unused */
1983 uint64_t host_mode : 1; /**< Host mode */
1984 uint64_t chip_rev : 8; /**< The chip revision. */
1985 #else
1986 uint64_t chip_rev : 8;
1987 uint64_t host_mode : 1;
1988 uint64_t pkt_bp : 4;
1989 uint64_t arb : 1;
1990 uint64_t lnk_rst : 1;
1991 uint64_t ring_en : 1;
1992 uint64_t cfg_rtry : 16;
1993 uint64_t p0_ntags : 6;
1994 uint64_t p1_ntags : 6;
1995 uint64_t reserved_44_63 : 20;
1996 #endif
1997 } s;
1998 struct cvmx_npei_ctl_status_s cn52xx;
1999 struct cvmx_npei_ctl_status_cn52xxp1 {
2000 #ifdef __BIG_ENDIAN_BITFIELD
2001 uint64_t reserved_44_63 : 20;
2002 uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1.
2003 In RC mode 1 tag is needed for each outbound TLP
2004 that requires a CPL TLP. In Endpoint mode the
2005 number of tags required for a TLP request is
2006 1 per 64-bytes of CPL data + 1.
2007 This field should only be written as part of
2008 reset sequence, before issuing any reads, CFGs, or
2009 IO transactions from the core(s). */
2010 uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0.
2011 In RC mode 1 tag is needed for each outbound TLP
2012 that requires a CPL TLP. In Endpoint mode the
2013 number of tags required for a TLP request is
2014 1 per 64-bytes of CPL data + 1.
2015 This field should only be written as part of
2016 reset sequence, before issuing any reads, CFGs, or
2017 IO transactions from the core(s). */
2018 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a
2019 CPL to a CFG RD that does not carry a Retry Status.
2020 Until such time that the timeout occurs and Retry
2021 Status is received for a CFG RD, the Read CFG Read
2022 will be resent. A value of 0 disables retries and
2023 treats a CPL Retry as a CPL UR. */
2024 uint64_t reserved_15_15 : 1;
2025 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to
2026 link down state. This bit is only reset on raw
2027 reset so it can be read for state to determine if
2028 a reset occured. Bit is cleared when a '1' is
2029 written to this field. */
2030 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority
2031 NPEI, PCIe0, then PCIe1. '1' == round robin. */
2032 uint64_t reserved_9_12 : 4;
2033 uint64_t host_mode : 1; /**< Host mode */
2034 uint64_t chip_rev : 8; /**< The chip revision. */
2035 #else
2036 uint64_t chip_rev : 8;
2037 uint64_t host_mode : 1;
2038 uint64_t reserved_9_12 : 4;
2039 uint64_t arb : 1;
2040 uint64_t lnk_rst : 1;
2041 uint64_t reserved_15_15 : 1;
2042 uint64_t cfg_rtry : 16;
2043 uint64_t p0_ntags : 6;
2044 uint64_t p1_ntags : 6;
2045 uint64_t reserved_44_63 : 20;
2046 #endif
2047 } cn52xxp1;
2048 struct cvmx_npei_ctl_status_s cn56xx;
2049 struct cvmx_npei_ctl_status_cn56xxp1 {
2050 #ifdef __BIG_ENDIAN_BITFIELD
2051 uint64_t reserved_15_63 : 49;
2052 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to
2053 link down state. This bit is only reset on raw
2054 reset so it can be read for state to determine if
2055 a reset occured. Bit is cleared when a '1' is
2056 written to this field. */
2057 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority
2058 NPEI, PCIe0, then PCIe1. '1' == round robin. */
2059 uint64_t pkt_bp : 4; /**< Unused */
2060 uint64_t host_mode : 1; /**< Host mode */
2061 uint64_t chip_rev : 8; /**< The chip revision. */
2062 #else
2063 uint64_t chip_rev : 8;
2064 uint64_t host_mode : 1;
2065 uint64_t pkt_bp : 4;
2066 uint64_t arb : 1;
2067 uint64_t lnk_rst : 1;
2068 uint64_t reserved_15_63 : 49;
2069 #endif
2070 } cn56xxp1;
2071 };
2072 typedef union cvmx_npei_ctl_status cvmx_npei_ctl_status_t;
2073
2074 /**
2075 * cvmx_npei_ctl_status2
2076 *
2077 * NPEI_CTL_STATUS2 = NPEI's Control Status2 Register
2078 *
2079 * Contains control and status for NPEI.
2080 * Writes to this register are not ordered with writes/reads to the PCI Memory space.
2081 * To ensure that a write has completed the user must read the register before
2082 * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
2083 */
2084 union cvmx_npei_ctl_status2 {
2085 uint64_t u64;
2086 struct cvmx_npei_ctl_status2_s {
2087 #ifdef __BIG_ENDIAN_BITFIELD
2088 uint64_t reserved_16_63 : 48;
2089 uint64_t mps : 1; /**< Max Payload Size
2090 0 = 128B
2091 1 = 256B
2092 Note: PCIE*_CFG030[MPS] must be set to the same
2093 value for proper function. */
2094 uint64_t mrrs : 3; /**< Max Read Request Size
2095 0 = 128B
2096 1 = 256B
2097 2 = 512B
2098 3 = 1024B
2099 4 = 2048B
2100 5 = 4096B
2101 Note: This field must not exceed the desired
2102 max read request size. This means this field
2103 should not exceed PCIE*_CFG030[MRRS]. */
2104 uint64_t c1_w_flt : 1; /**< When '1' enables the window filter for reads and
2105 writes using the window registers.
2106 PCIE-Port1.
2107 Unfilter writes are:
2108 MIO, SubId0
2109 MIO, SubId7
2110 NPEI, SubId0
2111 NPEI, SubId7
2112 POW, SubId7
2113 IPD, SubId7
2114 USBN0, SubId7
2115 Unfiltered Reads are:
2116 MIO, SubId0
2117 MIO, SubId7
2118 NPEI, SubId0
2119 NPEI, SubId7
2120 POW, SubId1
2121 POW, SubId2
2122 POW, SubId3
2123 POW, SubId7
2124 IPD, SubId7
2125 USBN0, SubId7 */
2126 uint64_t c0_w_flt : 1; /**< When '1' enables the window filter for reads and
2127 writes using the window registers.
2128 PCIE-Port0.
2129 Unfilter writes are:
2130 MIO, SubId0
2131 MIO, SubId7
2132 NPEI, SubId0
2133 NPEI, SubId7
2134 POW, SubId7
2135 IPD, SubId7
2136 USBN0, SubId7
2137 Unfiltered Reads are:
2138 MIO, SubId0
2139 MIO, SubId7
2140 NPEI, SubId0
2141 NPEI, SubId7
2142 POW, SubId1
2143 POW, SubId2
2144 POW, SubId3
2145 POW, SubId7
2146 IPD, SubId7
2147 USBN0, SubId7 */
2148 uint64_t c1_b1_s : 3; /**< Pcie-Port1, Bar1 Size. 1 == 64MB, 2 == 128MB,
2149 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
2150 0 and 7 are reserved. */
2151 uint64_t c0_b1_s : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
2152 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
2153 0 and 7 are reserved. */
2154 uint64_t c1_wi_d : 1; /**< When set '1' disables access to the Window
2155 Registers from the PCIe-Port1. */
2156 uint64_t c1_b0_d : 1; /**< When set '1' disables access from PCIe-Port1 to
2157 BAR-0 address offsets: Less Than 0x270,
2158 Greater than 0x270 AND less than 0x0520, 0x3BC0,
2159 0x3CD0. */
2160 uint64_t c0_wi_d : 1; /**< When set '1' disables access to the Window
2161 Registers from the PCIe-Port0. */
2162 uint64_t c0_b0_d : 1; /**< When set '1' disables access from PCIe-Port0 to
2163 BAR-0 address offsets: Less Than 0x270,
2164 Greater than 0x270 AND less than 0x0520, 0x3BC0,
2165 0x3CD0. */
2166 #else
2167 uint64_t c0_b0_d : 1;
2168 uint64_t c0_wi_d : 1;
2169 uint64_t c1_b0_d : 1;
2170 uint64_t c1_wi_d : 1;
2171 uint64_t c0_b1_s : 3;
2172 uint64_t c1_b1_s : 3;
2173 uint64_t c0_w_flt : 1;
2174 uint64_t c1_w_flt : 1;
2175 uint64_t mrrs : 3;
2176 uint64_t mps : 1;
2177 uint64_t reserved_16_63 : 48;
2178 #endif
2179 } s;
2180 struct cvmx_npei_ctl_status2_s cn52xx;
2181 struct cvmx_npei_ctl_status2_s cn52xxp1;
2182 struct cvmx_npei_ctl_status2_s cn56xx;
2183 struct cvmx_npei_ctl_status2_s cn56xxp1;
2184 };
2185 typedef union cvmx_npei_ctl_status2 cvmx_npei_ctl_status2_t;
2186
2187 /**
2188 * cvmx_npei_data_out_cnt
2189 *
2190 * NPEI_DATA_OUT_CNT = NPEI DATA OUT COUNT
2191 *
2192 * The EXEC data out fifo-count and the data unload counter.
2193 */
2194 union cvmx_npei_data_out_cnt {
2195 uint64_t u64;
2196 struct cvmx_npei_data_out_cnt_s {
2197 #ifdef __BIG_ENDIAN_BITFIELD
2198 uint64_t reserved_44_63 : 20;
2199 uint64_t p1_ucnt : 16; /**< PCIE-Port1 Fifo Unload Count. This counter is
2200 incremented by '1' every time a word is removed
2201 from the Data Out FIFO, whose count is shown in
2202 P0_FCNT. */
2203 uint64_t p1_fcnt : 6; /**< PCIE-Port1 Data Out Fifo Count. Number of address
2204 data words to be sent out the PCIe port presently
2205 buffered in the FIFO. */
2206 uint64_t p0_ucnt : 16; /**< PCIE-Port0 Fifo Unload Count. This counter is
2207 incremented by '1' every time a word is removed
2208 from the Data Out FIFO, whose count is shown in
2209 P0_FCNT. */
2210 uint64_t p0_fcnt : 6; /**< PCIE-Port0 Data Out Fifo Count. Number of address
2211 data words to be sent out the PCIe port presently
2212 buffered in the FIFO. */
2213 #else
2214 uint64_t p0_fcnt : 6;
2215 uint64_t p0_ucnt : 16;
2216 uint64_t p1_fcnt : 6;
2217 uint64_t p1_ucnt : 16;
2218 uint64_t reserved_44_63 : 20;
2219 #endif
2220 } s;
2221 struct cvmx_npei_data_out_cnt_s cn52xx;
2222 struct cvmx_npei_data_out_cnt_s cn52xxp1;
2223 struct cvmx_npei_data_out_cnt_s cn56xx;
2224 struct cvmx_npei_data_out_cnt_s cn56xxp1;
2225 };
2226 typedef union cvmx_npei_data_out_cnt cvmx_npei_data_out_cnt_t;
2227
2228 /**
2229 * cvmx_npei_dbg_data
2230 *
2231 * NPEI_DBG_DATA = NPEI Debug Data Register
2232 *
2233 * Value returned on the debug-data lines from the RSLs
2234 */
2235 union cvmx_npei_dbg_data {
2236 uint64_t u64;
2237 struct cvmx_npei_dbg_data_s {
2238 #ifdef __BIG_ENDIAN_BITFIELD
2239 uint64_t reserved_28_63 : 36;
2240 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */
2241 uint64_t reserved_25_26 : 2;
2242 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency
2243 0=1.25 Gbaud
2244 1=2.5 Gbaud
2245 2=3.125 Gbaud
2246 3=3.75 Gbaud */
2247 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion
2248 Core frequency = 50MHz*C_MUL */
2249 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
2250 debug select value. */
2251 uint64_t data : 17; /**< Value on the debug data lines. */
2252 #else
2253 uint64_t data : 17;
2254 uint64_t dsel_ext : 1;
2255 uint64_t c_mul : 5;
2256 uint64_t qlm1_spd : 2;
2257 uint64_t reserved_25_26 : 2;
2258 uint64_t qlm0_rev_lanes : 1;
2259 uint64_t reserved_28_63 : 36;
2260 #endif
2261 } s;
2262 struct cvmx_npei_dbg_data_cn52xx {
2263 #ifdef __BIG_ENDIAN_BITFIELD
2264 uint64_t reserved_29_63 : 35;
2265 uint64_t qlm0_link_width : 1; /**< Link width of PCIe port 0
2266 0 = PCIe port 0 is 2 lanes,
2267 2 lane PCIe port 1 exists
2268 1 = PCIe port 0 is 4 lanes,
2269 PCIe port 1 does not exist */
2270 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */
2271 uint64_t qlm1_mode : 2; /**< Sets the QLM1 Mode
2272 0=Reserved
2273 1=XAUI
2274 2=SGMII
2275 3=PICMG */
2276 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency
2277 0=1.25 Gbaud
2278 1=2.5 Gbaud
2279 2=3.125 Gbaud
2280 3=3.75 Gbaud */
2281 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion
2282 Core frequency = 50MHz*C_MUL */
2283 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
2284 debug select value. */
2285 uint64_t data : 17; /**< Value on the debug data lines. */
2286 #else
2287 uint64_t data : 17;
2288 uint64_t dsel_ext : 1;
2289 uint64_t c_mul : 5;
2290 uint64_t qlm1_spd : 2;
2291 uint64_t qlm1_mode : 2;
2292 uint64_t qlm0_rev_lanes : 1;
2293 uint64_t qlm0_link_width : 1;
2294 uint64_t reserved_29_63 : 35;
2295 #endif
2296 } cn52xx;
2297 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
2298 struct cvmx_npei_dbg_data_cn56xx {
2299 #ifdef __BIG_ENDIAN_BITFIELD
2300 uint64_t reserved_29_63 : 35;
2301 uint64_t qlm2_rev_lanes : 1; /**< Lane reversal for PCIe port 1 */
2302 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */
2303 uint64_t qlm3_spd : 2; /**< Sets the QLM3 frequency
2304 0=1.25 Gbaud
2305 1=2.5 Gbaud
2306 2=3.125 Gbaud
2307 3=3.75 Gbaud */
2308 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency
2309 0=1.25 Gbaud
2310 1=2.5 Gbaud
2311 2=3.125 Gbaud
2312 3=3.75 Gbaud */
2313 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion
2314 Core frequency = 50MHz*C_MUL */
2315 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
2316 debug select value. */
2317 uint64_t data : 17; /**< Value on the debug data lines. */
2318 #else
2319 uint64_t data : 17;
2320 uint64_t dsel_ext : 1;
2321 uint64_t c_mul : 5;
2322 uint64_t qlm1_spd : 2;
2323 uint64_t qlm3_spd : 2;
2324 uint64_t qlm0_rev_lanes : 1;
2325 uint64_t qlm2_rev_lanes : 1;
2326 uint64_t reserved_29_63 : 35;
2327 #endif
2328 } cn56xx;
2329 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
2330 };
2331 typedef union cvmx_npei_dbg_data cvmx_npei_dbg_data_t;
2332
2333 /**
2334 * cvmx_npei_dbg_select
2335 *
2336 * NPEI_DBG_SELECT = Debug Select Register
2337 *
2338 * Contains the debug select value last written to the RSLs.
2339 */
2340 union cvmx_npei_dbg_select {
2341 uint64_t u64;
2342 struct cvmx_npei_dbg_select_s {
2343 #ifdef __BIG_ENDIAN_BITFIELD
2344 uint64_t reserved_16_63 : 48;
2345 uint64_t dbg_sel : 16; /**< When this register is written its value is sent to
2346 all RSLs. */
2347 #else
2348 uint64_t dbg_sel : 16;
2349 uint64_t reserved_16_63 : 48;
2350 #endif
2351 } s;
2352 struct cvmx_npei_dbg_select_s cn52xx;
2353 struct cvmx_npei_dbg_select_s cn52xxp1;
2354 struct cvmx_npei_dbg_select_s cn56xx;
2355 struct cvmx_npei_dbg_select_s cn56xxp1;
2356 };
2357 typedef union cvmx_npei_dbg_select cvmx_npei_dbg_select_t;
2358
2359 /**
2360 * cvmx_npei_dma#_counts
2361 *
2362 * NPEI_DMA[0..4]_COUNTS = DMA Instruction Counts
2363 *
2364 * Values for determing the number of instructions for DMA[0..4] in the NPEI.
2365 */
2366 union cvmx_npei_dmax_counts {
2367 uint64_t u64;
2368 struct cvmx_npei_dmax_counts_s {
2369 #ifdef __BIG_ENDIAN_BITFIELD
2370 uint64_t reserved_39_63 : 25;
2371 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */
2372 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */
2373 #else
2374 uint64_t dbell : 32;
2375 uint64_t fcnt : 7;
2376 uint64_t reserved_39_63 : 25;
2377 #endif
2378 } s;
2379 struct cvmx_npei_dmax_counts_s cn52xx;
2380 struct cvmx_npei_dmax_counts_s cn52xxp1;
2381 struct cvmx_npei_dmax_counts_s cn56xx;
2382 struct cvmx_npei_dmax_counts_s cn56xxp1;
2383 };
2384 typedef union cvmx_npei_dmax_counts cvmx_npei_dmax_counts_t;
2385
2386 /**
2387 * cvmx_npei_dma#_dbell
2388 *
2389 * NPEI_DMA_DBELL[0..4] = DMA Door Bell
2390 *
2391 * The door bell register for DMA[0..4] queue.
2392 */
2393 union cvmx_npei_dmax_dbell {
2394 uint32_t u32;
2395 struct cvmx_npei_dmax_dbell_s {
2396 #ifdef __BIG_ENDIAN_BITFIELD
2397 uint32_t reserved_16_31 : 16;
2398 uint32_t dbell : 16; /**< The value written to this register is added to the
2399 number of 8byte words to be read and processes for
2400 the low priority dma queue. */
2401 #else
2402 uint32_t dbell : 16;
2403 uint32_t reserved_16_31 : 16;
2404 #endif
2405 } s;
2406 struct cvmx_npei_dmax_dbell_s cn52xx;
2407 struct cvmx_npei_dmax_dbell_s cn52xxp1;
2408 struct cvmx_npei_dmax_dbell_s cn56xx;
2409 struct cvmx_npei_dmax_dbell_s cn56xxp1;
2410 };
2411 typedef union cvmx_npei_dmax_dbell cvmx_npei_dmax_dbell_t;
2412
2413 /**
2414 * cvmx_npei_dma#_ibuff_saddr
2415 *
2416 * NPEI_DMA[0..4]_IBUFF_SADDR = DMA Instruction Buffer Starting Address
2417 *
2418 * The address to start reading Instructions from for DMA[0..4].
2419 */
2420 union cvmx_npei_dmax_ibuff_saddr {
2421 uint64_t u64;
2422 struct cvmx_npei_dmax_ibuff_saddr_s {
2423 #ifdef __BIG_ENDIAN_BITFIELD
2424 uint64_t reserved_37_63 : 27;
2425 uint64_t idle : 1; /**< DMA Engine IDLE state */
2426 uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the
2427 first instruction. SADDR is address bit 35:7 of the
2428 first instructions address. */
2429 uint64_t reserved_0_6 : 7;
2430 #else
2431 uint64_t reserved_0_6 : 7;
2432 uint64_t saddr : 29;
2433 uint64_t idle : 1;
2434 uint64_t reserved_37_63 : 27;
2435 #endif
2436 } s;
2437 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
2438 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
2439 #ifdef __BIG_ENDIAN_BITFIELD
2440 uint64_t reserved_36_63 : 28;
2441 uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the
2442 first instruction. SADDR is address bit 35:7 of the
2443 first instructions address. */
2444 uint64_t reserved_0_6 : 7;
2445 #else
2446 uint64_t reserved_0_6 : 7;
2447 uint64_t saddr : 29;
2448 uint64_t reserved_36_63 : 28;
2449 #endif
2450 } cn52xxp1;
2451 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
2452 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
2453 };
2454 typedef union cvmx_npei_dmax_ibuff_saddr cvmx_npei_dmax_ibuff_saddr_t;
2455
2456 /**
2457 * cvmx_npei_dma#_naddr
2458 *
2459 * NPEI_DMA[0..4]_NADDR = DMA Next Ichunk Address
2460 *
2461 * Place NPEI will read the next Ichunk data from. This is valid when state is 0
2462 */
2463 union cvmx_npei_dmax_naddr {
2464 uint64_t u64;
2465 struct cvmx_npei_dmax_naddr_s {
2466 #ifdef __BIG_ENDIAN_BITFIELD
2467 uint64_t reserved_36_63 : 28;
2468 uint64_t addr : 36; /**< The next L2C address to read DMA# instructions
2469 from. */
2470 #else
2471 uint64_t addr : 36;
2472 uint64_t reserved_36_63 : 28;
2473 #endif
2474 } s;
2475 struct cvmx_npei_dmax_naddr_s cn52xx;
2476 struct cvmx_npei_dmax_naddr_s cn52xxp1;
2477 struct cvmx_npei_dmax_naddr_s cn56xx;
2478 struct cvmx_npei_dmax_naddr_s cn56xxp1;
2479 };
2480 typedef union cvmx_npei_dmax_naddr cvmx_npei_dmax_naddr_t;
2481
2482 /**
2483 * cvmx_npei_dma0_int_level
2484 *
2485 * NPEI_DMA0_INT_LEVEL = NPEI DMA0 Interrupt Level
2486 *
2487 * Thresholds for DMA count and timer interrupts for DMA0.
2488 */
2489 union cvmx_npei_dma0_int_level {
2490 uint64_t u64;
2491 struct cvmx_npei_dma0_int_level_s {
2492 #ifdef __BIG_ENDIAN_BITFIELD
2493 uint64_t time : 32; /**< Whenever the DMA_CNT0 timer exceeds
2494 this value, NPEI_INT_SUM[DTIME0] is set.
2495 The DMA_CNT0 timer increments every core clock
2496 whenever NPEI_DMA_CNTS[DMA0]!=0, and is cleared
2497 when NPEI_INT_SUM[DTIME0] is written with one. */
2498 uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA0] exceeds this value,
2499 NPEI_INT_SUM[DCNT0] is set. */
2500 #else
2501 uint64_t cnt : 32;
2502 uint64_t time : 32;
2503 #endif
2504 } s;
2505 struct cvmx_npei_dma0_int_level_s cn52xx;
2506 struct cvmx_npei_dma0_int_level_s cn52xxp1;
2507 struct cvmx_npei_dma0_int_level_s cn56xx;
2508 struct cvmx_npei_dma0_int_level_s cn56xxp1;
2509 };
2510 typedef union cvmx_npei_dma0_int_level cvmx_npei_dma0_int_level_t;
2511
2512 /**
2513 * cvmx_npei_dma1_int_level
2514 *
2515 * NPEI_DMA1_INT_LEVEL = NPEI DMA1 Interrupt Level
2516 *
2517 * Thresholds for DMA count and timer interrupts for DMA1.
2518 */
2519 union cvmx_npei_dma1_int_level {
2520 uint64_t u64;
2521 struct cvmx_npei_dma1_int_level_s {
2522 #ifdef __BIG_ENDIAN_BITFIELD
2523 uint64_t time : 32; /**< Whenever the DMA_CNT1 timer exceeds
2524 this value, NPEI_INT_SUM[DTIME1] is set.
2525 The DMA_CNT1 timer increments every core clock
2526 whenever NPEI_DMA_CNTS[DMA1]!=0, and is cleared
2527 when NPEI_INT_SUM[DTIME1] is written with one. */
2528 uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA1] exceeds this value,
2529 NPEI_INT_SUM[DCNT1] is set. */
2530 #else
2531 uint64_t cnt : 32;
2532 uint64_t time : 32;
2533 #endif
2534 } s;
2535 struct cvmx_npei_dma1_int_level_s cn52xx;
2536 struct cvmx_npei_dma1_int_level_s cn52xxp1;
2537 struct cvmx_npei_dma1_int_level_s cn56xx;
2538 struct cvmx_npei_dma1_int_level_s cn56xxp1;
2539 };
2540 typedef union cvmx_npei_dma1_int_level cvmx_npei_dma1_int_level_t;
2541
2542 /**
2543 * cvmx_npei_dma_cnts
2544 *
2545 * NPEI_DMA_CNTS = NPEI DMA Count
2546 *
2547 * The DMA Count values for DMA0 and DMA1.
2548 */
2549 union cvmx_npei_dma_cnts {
2550 uint64_t u64;
2551 struct cvmx_npei_dma_cnts_s {
2552 #ifdef __BIG_ENDIAN_BITFIELD
2553 uint64_t dma1 : 32; /**< The DMA counter 1.
2554 Writing this field will cause the written value to
2555 be subtracted from DMA1. SW should use a 4-byte
2556 write to access this field so as not to change the
2557 value of other fields in this register.
2558 HW will optionally increment this field after
2559 it completes an OUTBOUND or EXTERNAL-ONLY DMA
2560 instruction. These increments may cause interrupts.
2561 Refer to NPEI_DMA1_INT_LEVEL and
2562 NPEI_INT_SUM[DCNT1,DTIME1]. */
2563 uint64_t dma0 : 32; /**< The DMA counter 0.
2564 Writing this field will cause the written value to
2565 be subtracted from DMA0. SW should use a 4-byte
2566 write to access this field so as not to change the
2567 value of other fields in this register.
2568 HW will optionally increment this field after
2569 it completes an OUTBOUND or EXTERNAL-ONLY DMA
2570 instruction. These increments may cause interrupts.
2571 Refer to NPEI_DMA0_INT_LEVEL and
2572 NPEI_INT_SUM[DCNT0,DTIME0]. */
2573 #else
2574 uint64_t dma0 : 32;
2575 uint64_t dma1 : 32;
2576 #endif
2577 } s;
2578 struct cvmx_npei_dma_cnts_s cn52xx;
2579 struct cvmx_npei_dma_cnts_s cn52xxp1;
2580 struct cvmx_npei_dma_cnts_s cn56xx;
2581 struct cvmx_npei_dma_cnts_s cn56xxp1;
2582 };
2583 typedef union cvmx_npei_dma_cnts cvmx_npei_dma_cnts_t;
2584
2585 /**
2586 * cvmx_npei_dma_control
2587 *
2588 * NPEI_DMA_CONTROL = DMA Control Register
2589 *
2590 * Controls operation of the DMA IN/OUT.
2591 */
2592 union cvmx_npei_dma_control {
2593 uint64_t u64;
2594 struct cvmx_npei_dma_control_s {
2595 #ifdef __BIG_ENDIAN_BITFIELD
2596 uint64_t reserved_40_63 : 24;
2597 uint64_t p_32b_m : 1; /**< DMA PCIE 32-bit word read disable bit
2598 When 0, enable the feature */
2599 uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2600 engine. After being enabled a DMA engine should not
2601 be dis-abled while processing instructions. */
2602 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2603 engine. After being enabled a DMA engine should not
2604 be dis-abled while processing instructions. */
2605 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2606 engine. After being enabled a DMA engine should not
2607 be dis-abled while processing instructions. */
2608 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2609 engine. After being enabled a DMA engine should not
2610 be dis-abled while processing instructions. */
2611 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2612 engine. After being enabled a DMA engine should not
2613 be dis-abled while processing instructions. */
2614 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write
2615 0 to L2C memory when a DMA is done, the address
2616 to be written to will be treated as a Little
2617 Endian address. */
2618 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB
2619 field for a free page operation for the memory
2620 that contained the data. */
2621 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
2622 this value is used for the DWB field of the
2623 operation. */
2624 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
2625 be returned to when used. */
2626 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
2627 if '0' then the number of bytes in the dma transfer
2628 will be added to the count register. */
2629 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
2630 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
2631 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
2632 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
2633 '1' use pointer values for address and register
2634 values for RO, ES, and NS, '0' use register
2635 values for address and pointer values for
2636 RO, ES, and NS. */
2637 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
2638 This value should only be written once. After
2639 writing this value a new value will not be
2640 recognized until the end of the DMA I-Chunk is
2641 reached. */
2642 #else
2643 uint64_t csize : 14;
2644 uint64_t o_mode : 1;
2645 uint64_t o_es : 2;
2646 uint64_t o_ns : 1;
2647 uint64_t o_ro : 1;
2648 uint64_t o_add1 : 1;
2649 uint64_t fpa_que : 3;
2650 uint64_t dwb_ichk : 9;
2651 uint64_t dwb_denb : 1;
2652 uint64_t b0_lend : 1;
2653 uint64_t dma0_enb : 1;
2654 uint64_t dma1_enb : 1;
2655 uint64_t dma2_enb : 1;
2656 uint64_t dma3_enb : 1;
2657 uint64_t dma4_enb : 1;
2658 uint64_t p_32b_m : 1;
2659 uint64_t reserved_40_63 : 24;
2660 #endif
2661 } s;
2662 struct cvmx_npei_dma_control_s cn52xx;
2663 struct cvmx_npei_dma_control_cn52xxp1 {
2664 #ifdef __BIG_ENDIAN_BITFIELD
2665 uint64_t reserved_38_63 : 26;
2666 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2667 engine. After being enabled a DMA engine should not
2668 be dis-abled while processing instructions. */
2669 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2670 engine. After being enabled a DMA engine should not
2671 be dis-abled while processing instructions. */
2672 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2673 engine. After being enabled a DMA engine should not
2674 be dis-abled while processing instructions. */
2675 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2676 engine. After being enabled a DMA engine should not
2677 be dis-abled while processing instructions. */
2678 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write
2679 0 to L2C memory when a DMA is done, the address
2680 to be written to will be treated as a Little
2681 Endian address. */
2682 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB
2683 field for a free page operation for the memory
2684 that contained the data. */
2685 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
2686 this value is used for the DWB field of the
2687 operation. */
2688 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
2689 be returned to when used. */
2690 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
2691 if '0' then the number of bytes in the dma transfer
2692 will be added to the count register. */
2693 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
2694 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
2695 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
2696 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
2697 '1' use pointer values for address and register
2698 values for RO, ES, and NS, '0' use register
2699 values for address and pointer values for
2700 RO, ES, and NS. */
2701 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
2702 This value should only be written once. After
2703 writing this value a new value will not be
2704 recognized until the end of the DMA I-Chunk is
2705 reached. */
2706 #else
2707 uint64_t csize : 14;
2708 uint64_t o_mode : 1;
2709 uint64_t o_es : 2;
2710 uint64_t o_ns : 1;
2711 uint64_t o_ro : 1;
2712 uint64_t o_add1 : 1;
2713 uint64_t fpa_que : 3;
2714 uint64_t dwb_ichk : 9;
2715 uint64_t dwb_denb : 1;
2716 uint64_t b0_lend : 1;
2717 uint64_t dma0_enb : 1;
2718 uint64_t dma1_enb : 1;
2719 uint64_t dma2_enb : 1;
2720 uint64_t dma3_enb : 1;
2721 uint64_t reserved_38_63 : 26;
2722 #endif
2723 } cn52xxp1;
2724 struct cvmx_npei_dma_control_s cn56xx;
2725 struct cvmx_npei_dma_control_cn56xxp1 {
2726 #ifdef __BIG_ENDIAN_BITFIELD
2727 uint64_t reserved_39_63 : 25;
2728 uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2729 engine. After being enabled a DMA engine should not
2730 be dis-abled while processing instructions. */
2731 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2732 engine. After being enabled a DMA engine should not
2733 be dis-abled while processing instructions. */
2734 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2735 engine. After being enabled a DMA engine should not
2736 be dis-abled while processing instructions. */
2737 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2738 engine. After being enabled a DMA engine should not
2739 be dis-abled while processing instructions. */
2740 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA
2741 engine. After being enabled a DMA engine should not
2742 be dis-abled while processing instructions. */
2743 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write
2744 0 to L2C memory when a DMA is done, the address
2745 to be written to will be treated as a Little
2746 Endian address. */
2747 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB
2748 field for a free page operation for the memory
2749 that contained the data. */
2750 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed
2751 this value is used for the DWB field of the
2752 operation. */
2753 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will
2754 be returned to when used. */
2755 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters,
2756 if '0' then the number of bytes in the dma transfer
2757 will be added to the count register. */
2758 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */
2759 uint64_t o_ns : 1; /**< Nosnoop For DMA. */
2760 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */
2761 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used.
2762 '1' use pointer values for address and register
2763 values for RO, ES, and NS, '0' use register
2764 values for address and pointer values for
2765 RO, ES, and NS. */
2766 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk.
2767 This value should only be written once. After
2768 writing this value a new value will not be
2769 recognized until the end of the DMA I-Chunk is
2770 reached. */
2771 #else
2772 uint64_t csize : 14;
2773 uint64_t o_mode : 1;
2774 uint64_t o_es : 2;
2775 uint64_t o_ns : 1;
2776 uint64_t o_ro : 1;
2777 uint64_t o_add1 : 1;
2778 uint64_t fpa_que : 3;
2779 uint64_t dwb_ichk : 9;
2780 uint64_t dwb_denb : 1;
2781 uint64_t b0_lend : 1;
2782 uint64_t dma0_enb : 1;
2783 uint64_t dma1_enb : 1;
2784 uint64_t dma2_enb : 1;
2785 uint64_t dma3_enb : 1;
2786 uint64_t dma4_enb : 1;
2787 uint64_t reserved_39_63 : 25;
2788 #endif
2789 } cn56xxp1;
2790 };
2791 typedef union cvmx_npei_dma_control cvmx_npei_dma_control_t;
2792
2793 /**
2794 * cvmx_npei_dma_pcie_req_num
2795 *
2796 * NPEI_DMA_PCIE_REQ_NUM = NPEI DMA PCIE Outstanding Read Request Number
2797 *
2798 * Outstanding PCIE read request number for DMAs and Packet, maximum number is 16
2799 */
2800 union cvmx_npei_dma_pcie_req_num {
2801 uint64_t u64;
2802 struct cvmx_npei_dma_pcie_req_num_s {
2803 #ifdef __BIG_ENDIAN_BITFIELD
2804 uint64_t dma_arb : 1; /**< DMA_PKT Read Request Arbitration
2805 - 1: DMA0-4 and PKT are round robin. i.e.
2806 DMA0-DMA1-DMA2-DMA3-DMA4-PKT...
2807 - 0: DMA0-4 are round robin, pkt gets selected
2808 half the time. i.e.
2809 DMA0-PKT-DMA1-PKT-DMA2-PKT-DMA3-PKT-DMA4-PKT... */
2810 uint64_t reserved_53_62 : 10;
2811 uint64_t pkt_cnt : 5; /**< PKT outstanding PCIE Read Request Number for each
2812 PCIe port
2813 When PKT_CNT=x, for each PCIe port, the number
2814 of outstanding PCIe memory space reads by the PCIe
2815 packet input/output will not exceed x.
2816 Valid Number is between 1 and 16 */
2817 uint64_t reserved_45_47 : 3;
2818 uint64_t dma4_cnt : 5; /**< DMA4 outstanding PCIE Read Request Number
2819 When DMA4_CNT=x, the number of outstanding PCIe
2820 memory space reads by the PCIe DMA engine 4
2821 will not exceed x.
2822 Valid Number is between 1 and 16 */
2823 uint64_t reserved_37_39 : 3;
2824 uint64_t dma3_cnt : 5; /**< DMA3 outstanding PCIE Read Request Number
2825 When DMA3_CNT=x, the number of outstanding PCIe
2826 memory space reads by the PCIe DMA engine 3
2827 will not exceed x.
2828 Valid Number is between 1 and 16 */
2829 uint64_t reserved_29_31 : 3;
2830 uint64_t dma2_cnt : 5; /**< DMA2 outstanding PCIE Read Request Number
2831 When DMA2_CNT=x, the number of outstanding PCIe
2832 memory space reads by the PCIe DMA engine 2
2833 will not exceed x.
2834 Valid Number is between 1 and 16 */
2835 uint64_t reserved_21_23 : 3;
2836 uint64_t dma1_cnt : 5; /**< DMA1 outstanding PCIE Read Request Number
2837 When DMA1_CNT=x, the number of outstanding PCIe
2838 memory space reads by the PCIe DMA engine 1
2839 will not exceed x.
2840 Valid Number is between 1 and 16 */
2841 uint64_t reserved_13_15 : 3;
2842 uint64_t dma0_cnt : 5; /**< DMA0 outstanding PCIE Read Request Number
2843 When DMA0_CNT=x, the number of outstanding PCIe
2844 memory space reads by the PCIe DMA engine 0
2845 will not exceed x.
2846 Valid Number is between 1 and 16 */
2847 uint64_t reserved_5_7 : 3;
2848 uint64_t dma_cnt : 5; /**< Total outstanding PCIE Read Request Number for each
2849 PCIe port
2850 When DMA_CNT=x, for each PCIe port, the total
2851 number of outstanding PCIe memory space reads
2852 by the PCIe DMA engines and packet input/output
2853 will not exceed x.
2854 Valid Number is between 1 and 16 */
2855 #else
2856 uint64_t dma_cnt : 5;
2857 uint64_t reserved_5_7 : 3;
2858 uint64_t dma0_cnt : 5;
2859 uint64_t reserved_13_15 : 3;
2860 uint64_t dma1_cnt : 5;
2861 uint64_t reserved_21_23 : 3;
2862 uint64_t dma2_cnt : 5;
2863 uint64_t reserved_29_31 : 3;
2864 uint64_t dma3_cnt : 5;
2865 uint64_t reserved_37_39 : 3;
2866 uint64_t dma4_cnt : 5;
2867 uint64_t reserved_45_47 : 3;
2868 uint64_t pkt_cnt : 5;
2869 uint64_t reserved_53_62 : 10;
2870 uint64_t dma_arb : 1;
2871 #endif
2872 } s;
2873 struct cvmx_npei_dma_pcie_req_num_s cn52xx;
2874 struct cvmx_npei_dma_pcie_req_num_s cn56xx;
2875 };
2876 typedef union cvmx_npei_dma_pcie_req_num cvmx_npei_dma_pcie_req_num_t;
2877
2878 /**
2879 * cvmx_npei_dma_state1
2880 *
2881 * NPEI_DMA_STATE1 = NPI's DMA State 1
2882 *
2883 * Results from DMA state register 1
2884 */
2885 union cvmx_npei_dma_state1 {
2886 uint64_t u64;
2887 struct cvmx_npei_dma_state1_s {
2888 #ifdef __BIG_ENDIAN_BITFIELD
2889 uint64_t reserved_40_63 : 24;
2890 uint64_t d4_dwe : 8; /**< DMA4 PICe Write State */
2891 uint64_t d3_dwe : 8; /**< DMA3 PICe Write State */
2892 uint64_t d2_dwe : 8; /**< DMA2 PICe Write State */
2893 uint64_t d1_dwe : 8; /**< DMA1 PICe Write State */
2894 uint64_t d0_dwe : 8; /**< DMA0 PICe Write State */
2895 #else
2896 uint64_t d0_dwe : 8;
2897 uint64_t d1_dwe : 8;
2898 uint64_t d2_dwe : 8;
2899 uint64_t d3_dwe : 8;
2900 uint64_t d4_dwe : 8;
2901 uint64_t reserved_40_63 : 24;
2902 #endif
2903 } s;
2904 struct cvmx_npei_dma_state1_s cn52xx;
2905 };
2906 typedef union cvmx_npei_dma_state1 cvmx_npei_dma_state1_t;
2907
2908 /**
2909 * cvmx_npei_dma_state1_p1
2910 *
2911 * NPEI_DMA_STATE1_P1 = NPEI DMA Request and Instruction State
2912 *
2913 * DMA engine Debug information.
2914 */
2915 union cvmx_npei_dma_state1_p1 {
2916 uint64_t u64;
2917 struct cvmx_npei_dma_state1_p1_s {
2918 #ifdef __BIG_ENDIAN_BITFIELD
2919 uint64_t reserved_60_63 : 4;
2920 uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */
2921 uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */
2922 uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */
2923 uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */
2924 uint64_t d4_difst : 7; /**< DMA engine 4 dif instruction read state */
2925 uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */
2926 uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */
2927 uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */
2928 uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */
2929 uint64_t d4_reqst : 5; /**< DMA engine 4 request data state */
2930 #else
2931 uint64_t d4_reqst : 5;
2932 uint64_t d3_reqst : 5;
2933 uint64_t d2_reqst : 5;
2934 uint64_t d1_reqst : 5;
2935 uint64_t d0_reqst : 5;
2936 uint64_t d4_difst : 7;
2937 uint64_t d3_difst : 7;
2938 uint64_t d2_difst : 7;
2939 uint64_t d1_difst : 7;
2940 uint64_t d0_difst : 7;
2941 uint64_t reserved_60_63 : 4;
2942 #endif
2943 } s;
2944 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
2945 #ifdef __BIG_ENDIAN_BITFIELD
2946 uint64_t reserved_60_63 : 4;
2947 uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */
2948 uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */
2949 uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */
2950 uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */
2951 uint64_t reserved_25_31 : 7;
2952 uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */
2953 uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */
2954 uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */
2955 uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */
2956 uint64_t reserved_0_4 : 5;
2957 #else
2958 uint64_t reserved_0_4 : 5;
2959 uint64_t d3_reqst : 5;
2960 uint64_t d2_reqst : 5;
2961 uint64_t d1_reqst : 5;
2962 uint64_t d0_reqst : 5;
2963 uint64_t reserved_25_31 : 7;
2964 uint64_t d3_difst : 7;
2965 uint64_t d2_difst : 7;
2966 uint64_t d1_difst : 7;
2967 uint64_t d0_difst : 7;
2968 uint64_t reserved_60_63 : 4;
2969 #endif
2970 } cn52xxp1;
2971 struct cvmx_npei_dma_state1_p1_s cn56xxp1;
2972 };
2973 typedef union cvmx_npei_dma_state1_p1 cvmx_npei_dma_state1_p1_t;
2974
2975 /**
2976 * cvmx_npei_dma_state2
2977 *
2978 * NPEI_DMA_STATE2 = NPI's DMA State 2
2979 *
2980 * Results from DMA state register 2
2981 */
2982 union cvmx_npei_dma_state2 {
2983 uint64_t u64;
2984 struct cvmx_npei_dma_state2_s {
2985 #ifdef __BIG_ENDIAN_BITFIELD
2986 uint64_t reserved_28_63 : 36;
2987 uint64_t ndwe : 4; /**< DMA L2C Write State */
2988 uint64_t reserved_21_23 : 3;
2989 uint64_t ndre : 5; /**< DMA L2C Read State */
2990 uint64_t reserved_10_15 : 6;
2991 uint64_t prd : 10; /**< DMA PICe Read State */
2992 #else
2993 uint64_t prd : 10;
2994 uint64_t reserved_10_15 : 6;
2995 uint64_t ndre : 5;
2996 uint64_t reserved_21_23 : 3;
2997 uint64_t ndwe : 4;
2998 uint64_t reserved_28_63 : 36;
2999 #endif
3000 } s;
3001 struct cvmx_npei_dma_state2_s cn52xx;
3002 };
3003 typedef union cvmx_npei_dma_state2 cvmx_npei_dma_state2_t;
3004
3005 /**
3006 * cvmx_npei_dma_state2_p1
3007 *
3008 * NPEI_DMA_STATE2_P1 = NPEI DMA Instruction Fetch State
3009 *
3010 * DMA engine Debug information.
3011 */
3012 union cvmx_npei_dma_state2_p1 {
3013 uint64_t u64;
3014 struct cvmx_npei_dma_state2_p1_s {
3015 #ifdef __BIG_ENDIAN_BITFIELD
3016 uint64_t reserved_45_63 : 19;
3017 uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */
3018 uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */
3019 uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */
3020 uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */
3021 uint64_t d4_dffst : 9; /**< DMA engine 4 dif instruction fetch state */
3022 #else
3023 uint64_t d4_dffst : 9;
3024 uint64_t d3_dffst : 9;
3025 uint64_t d2_dffst : 9;
3026 uint64_t d1_dffst : 9;
3027 uint64_t d0_dffst : 9;
3028 uint64_t reserved_45_63 : 19;
3029 #endif
3030 } s;
3031 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
3032 #ifdef __BIG_ENDIAN_BITFIELD
3033 uint64_t reserved_45_63 : 19;
3034 uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */
3035 uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */
3036 uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */
3037 uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */
3038 uint64_t reserved_0_8 : 9;
3039 #else
3040 uint64_t reserved_0_8 : 9;
3041 uint64_t d3_dffst : 9;
3042 uint64_t d2_dffst : 9;
3043 uint64_t d1_dffst : 9;
3044 uint64_t d0_dffst : 9;
3045 uint64_t reserved_45_63 : 19;
3046 #endif
3047 } cn52xxp1;
3048 struct cvmx_npei_dma_state2_p1_s cn56xxp1;
3049 };
3050 typedef union cvmx_npei_dma_state2_p1 cvmx_npei_dma_state2_p1_t;
3051
3052 /**
3053 * cvmx_npei_dma_state3_p1
3054 *
3055 * NPEI_DMA_STATE3_P1 = NPEI DMA DRE State
3056 *
3057 * DMA engine Debug information.
3058 */
3059 union cvmx_npei_dma_state3_p1 {
3060 uint64_t u64;
3061 struct cvmx_npei_dma_state3_p1_s {
3062 #ifdef __BIG_ENDIAN_BITFIELD
3063 uint64_t reserved_60_63 : 4;
3064 uint64_t d0_drest : 15; /**< DMA engine 0 dre state */
3065 uint64_t d1_drest : 15; /**< DMA engine 1 dre state */
3066 uint64_t d2_drest : 15; /**< DMA engine 2 dre state */
3067 uint64_t d3_drest : 15; /**< DMA engine 3 dre state */
3068 #else
3069 uint64_t d3_drest : 15;
3070 uint64_t d2_drest : 15;
3071 uint64_t d1_drest : 15;
3072 uint64_t d0_drest : 15;
3073 uint64_t reserved_60_63 : 4;
3074 #endif
3075 } s;
3076 struct cvmx_npei_dma_state3_p1_s cn52xxp1;
3077 struct cvmx_npei_dma_state3_p1_s cn56xxp1;
3078 };
3079 typedef union cvmx_npei_dma_state3_p1 cvmx_npei_dma_state3_p1_t;
3080
3081 /**
3082 * cvmx_npei_dma_state4_p1
3083 *
3084 * NPEI_DMA_STATE4_P1 = NPEI DMA DWE State
3085 *
3086 * DMA engine Debug information.
3087 */
3088 union cvmx_npei_dma_state4_p1 {
3089 uint64_t u64;
3090 struct cvmx_npei_dma_state4_p1_s {
3091 #ifdef __BIG_ENDIAN_BITFIELD
3092 uint64_t reserved_52_63 : 12;
3093 uint64_t d0_dwest : 13; /**< DMA engine 0 dwe state */
3094 uint64_t d1_dwest : 13; /**< DMA engine 1 dwe state */
3095 uint64_t d2_dwest : 13; /**< DMA engine 2 dwe state */
3096 uint64_t d3_dwest : 13; /**< DMA engine 3 dwe state */
3097 #else
3098 uint64_t d3_dwest : 13;
3099 uint64_t d2_dwest : 13;
3100 uint64_t d1_dwest : 13;
3101 uint64_t d0_dwest : 13;
3102 uint64_t reserved_52_63 : 12;
3103 #endif
3104 } s;
3105 struct cvmx_npei_dma_state4_p1_s cn52xxp1;
3106 struct cvmx_npei_dma_state4_p1_s cn56xxp1;
3107 };
3108 typedef union cvmx_npei_dma_state4_p1 cvmx_npei_dma_state4_p1_t;
3109
3110 /**
3111 * cvmx_npei_dma_state5_p1
3112 *
3113 * NPEI_DMA_STATE5_P1 = NPEI DMA DWE and DRE State
3114 *
3115 * DMA engine Debug information.
3116 */
3117 union cvmx_npei_dma_state5_p1 {
3118 uint64_t u64;
3119 struct cvmx_npei_dma_state5_p1_s {
3120 #ifdef __BIG_ENDIAN_BITFIELD
3121 uint64_t reserved_28_63 : 36;
3122 uint64_t d4_drest : 15; /**< DMA engine 4 dre state */
3123 uint64_t d4_dwest : 13; /**< DMA engine 4 dwe state */
3124 #else
3125 uint64_t d4_dwest : 13;
3126 uint64_t d4_drest : 15;
3127 uint64_t reserved_28_63 : 36;
3128 #endif
3129 } s;
3130 struct cvmx_npei_dma_state5_p1_s cn56xxp1;
3131 };
3132 typedef union cvmx_npei_dma_state5_p1 cvmx_npei_dma_state5_p1_t;
3133
3134 /**
3135 * cvmx_npei_int_a_enb
3136 *
3137 * NPEI_INTERRUPT_A_ENB = NPI's Interrupt A Enable Register
3138 *
3139 * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPEI
3140 */
3141 union cvmx_npei_int_a_enb {
3142 uint64_t u64;
3143 struct cvmx_npei_int_a_enb_s {
3144 #ifdef __BIG_ENDIAN_BITFIELD
3145 uint64_t reserved_10_63 : 54;
3146 uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an
3147 interrupt to the PCIE core for MSI/inta. */
3148 uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an
3149 interrupt to the PCIE core for MSI/inta. */
3150 uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an
3151 interrupt to the PCIE core for MSI/inta. */
3152 uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an
3153 interrupt to the PCIE core for MSI/inta. */
3154 uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an
3155 interrupt to the PCIE core for MSI/inta. */
3156 uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an
3157 interrupt to the PCIE core for MSI/inta. */
3158 uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an
3159 interrupt to the PCIE core for MSI/inta. */
3160 uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an
3161 interrupt to the PCIE core for MSI/inta. */
3162 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3163 interrupt to the PCIE core for MSI/inta. */
3164 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3165 interrupt to the PCIE core for MSI/inta. */
3166 #else
3167 uint64_t dma0_cpl : 1;
3168 uint64_t dma1_cpl : 1;
3169 uint64_t pins_err : 1;
3170 uint64_t pop_err : 1;
3171 uint64_t pdi_err : 1;
3172 uint64_t pgl_err : 1;
3173 uint64_t p0_rdlk : 1;
3174 uint64_t p1_rdlk : 1;
3175 uint64_t pin_bp : 1;
3176 uint64_t pout_err : 1;
3177 uint64_t reserved_10_63 : 54;
3178 #endif
3179 } s;
3180 struct cvmx_npei_int_a_enb_s cn52xx;
3181 struct cvmx_npei_int_a_enb_cn52xxp1 {
3182 #ifdef __BIG_ENDIAN_BITFIELD
3183 uint64_t reserved_2_63 : 62;
3184 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3185 interrupt to the PCIE core for MSI/inta. */
3186 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3187 interrupt to the PCIE core for MSI/inta. */
3188 #else
3189 uint64_t dma0_cpl : 1;
3190 uint64_t dma1_cpl : 1;
3191 uint64_t reserved_2_63 : 62;
3192 #endif
3193 } cn52xxp1;
3194 struct cvmx_npei_int_a_enb_s cn56xx;
3195 };
3196 typedef union cvmx_npei_int_a_enb cvmx_npei_int_a_enb_t;
3197
3198 /**
3199 * cvmx_npei_int_a_enb2
3200 *
3201 * NPEI_INTERRUPT_A_ENB2 = NPEI's Interrupt A Enable2 Register
3202 *
3203 * Used to enable the various interrupting conditions of NPEI
3204 */
3205 union cvmx_npei_int_a_enb2 {
3206 uint64_t u64;
3207 struct cvmx_npei_int_a_enb2_s {
3208 #ifdef __BIG_ENDIAN_BITFIELD
3209 uint64_t reserved_10_63 : 54;
3210 uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an
3211 interrupt on the RSL. */
3212 uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an
3213 interrupt on the RSL. */
3214 uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an
3215 interrupt on the RSL. */
3216 uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an
3217 interrupt on the RSL. */
3218 uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an
3219 interrupt on the RSL. */
3220 uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an
3221 interrupt on the RSL. */
3222 uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an
3223 interrupt on the RSL. */
3224 uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an
3225 interrupt on the RSL. */
3226 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3227 interrupt to the PCIE core for MSI/inta. */
3228 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3229 interrupt to the PCIE core for MSI/inta. */
3230 #else
3231 uint64_t dma0_cpl : 1;
3232 uint64_t dma1_cpl : 1;
3233 uint64_t pins_err : 1;
3234 uint64_t pop_err : 1;
3235 uint64_t pdi_err : 1;
3236 uint64_t pgl_err : 1;
3237 uint64_t p0_rdlk : 1;
3238 uint64_t p1_rdlk : 1;
3239 uint64_t pin_bp : 1;
3240 uint64_t pout_err : 1;
3241 uint64_t reserved_10_63 : 54;
3242 #endif
3243 } s;
3244 struct cvmx_npei_int_a_enb2_s cn52xx;
3245 struct cvmx_npei_int_a_enb2_cn52xxp1 {
3246 #ifdef __BIG_ENDIAN_BITFIELD
3247 uint64_t reserved_2_63 : 62;
3248 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an
3249 interrupt to the PCIE core for MSI/inta. */
3250 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an
3251 interrupt to the PCIE core for MSI/inta. */
3252 #else
3253 uint64_t dma0_cpl : 1;
3254 uint64_t dma1_cpl : 1;
3255 uint64_t reserved_2_63 : 62;
3256 #endif
3257 } cn52xxp1;
3258 struct cvmx_npei_int_a_enb2_s cn56xx;
3259 };
3260 typedef union cvmx_npei_int_a_enb2 cvmx_npei_int_a_enb2_t;
3261
3262 /**
3263 * cvmx_npei_int_a_sum
3264 *
3265 * NPEI_INTERRUPT_A_SUM = NPI Interrupt A Summary Register
3266 *
3267 * Set when an interrupt condition occurs, write '1' to clear. When an interrupt bitin this register is set and
3268 * the cooresponding bit in the NPEI_INT_A_ENB register is set, then NPEI_INT_SUM[61] will be set.
3269 */
3270 union cvmx_npei_int_a_sum {
3271 uint64_t u64;
3272 struct cvmx_npei_int_a_sum_s {
3273 #ifdef __BIG_ENDIAN_BITFIELD
3274 uint64_t reserved_10_63 : 54;
3275 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit
3276 set. */
3277 uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK.
3278 See NPEI_PKT_IN_BP */
3279 uint64_t p1_rdlk : 1; /**< PCIe port 1 received a read lock. */
3280 uint64_t p0_rdlk : 1; /**< PCIe port 0 received a read lock. */
3281 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list
3282 read this bit is set. */
3283 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read
3284 this bit is set. */
3285 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter
3286 pointer pair this bit is set. */
3287 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction
3288 this bit is set. */
3289 uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3290 response from PCIe Port 1 */
3291 uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3292 response from PCIe Port 0 */
3293 #else
3294 uint64_t dma0_cpl : 1;
3295 uint64_t dma1_cpl : 1;
3296 uint64_t pins_err : 1;
3297 uint64_t pop_err : 1;
3298 uint64_t pdi_err : 1;
3299 uint64_t pgl_err : 1;
3300 uint64_t p0_rdlk : 1;
3301 uint64_t p1_rdlk : 1;
3302 uint64_t pin_bp : 1;
3303 uint64_t pout_err : 1;
3304 uint64_t reserved_10_63 : 54;
3305 #endif
3306 } s;
3307 struct cvmx_npei_int_a_sum_s cn52xx;
3308 struct cvmx_npei_int_a_sum_cn52xxp1 {
3309 #ifdef __BIG_ENDIAN_BITFIELD
3310 uint64_t reserved_2_63 : 62;
3311 uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3312 response from PCIe Port 1 */
3313 uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA
3314 response from PCIe Port 0 */
3315 #else
3316 uint64_t dma0_cpl : 1;
3317 uint64_t dma1_cpl : 1;
3318 uint64_t reserved_2_63 : 62;
3319 #endif
3320 } cn52xxp1;
3321 struct cvmx_npei_int_a_sum_s cn56xx;
3322 };
3323 typedef union cvmx_npei_int_a_sum cvmx_npei_int_a_sum_t;
3324
3325 /**
3326 * cvmx_npei_int_enb
3327 *
3328 * NPEI_INTERRUPT_ENB = NPI's Interrupt Enable Register
3329 *
3330 * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPI
3331 */
3332 union cvmx_npei_int_enb {
3333 uint64_t u64;
3334 struct cvmx_npei_int_enb_s {
3335 #ifdef __BIG_ENDIAN_BITFIELD
3336 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an
3337 interrupt to the PCIE core for MSI/inta. */
3338 uint64_t reserved_62_62 : 1;
3339 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an
3340 interrupt to the PCIE core for MSI/inta. */
3341 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3342 interrupt to the PCIE core for MSI/inta. */
3343 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3344 interrupt to the PCIE core for MSI/inta. */
3345 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3346 interrupt to the PCIE core for MSI/inta. */
3347 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3348 interrupt to the PCIE core for MSI/inta. */
3349 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3350 interrupt to the PCIE core for MSI/inta. */
3351 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3352 interrupt to the PCIE core for MSI/inta. */
3353 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3354 interrupt to the PCIE core for MSI/inta. */
3355 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3356 interrupt to the PCIE core for MSI/inta. */
3357 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3358 interrupt to the PCIE core for MSI/inta. */
3359 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3360 interrupt to the PCIE core for MSI/inta. */
3361 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3362 interrupt to the PCIE core for MSI/inta. */
3363 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3364 interrupt to the PCIE core for MSI/inta. */
3365 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3366 interrupt to the PCIE core for MSI/inta. */
3367 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3368 interrupt to the PCIE core for MSI/inta. */
3369 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3370 interrupt to the PCIE core for MSI/inta. */
3371 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3372 interrupt to the PCIE core for MSI/inta. */
3373 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3374 interrupt to the PCIE core for MSI/inta. */
3375 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3376 interrupt to the PCIE core for MSI/inta. */
3377 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3378 interrupt to the PCIE core for MSI/inta. */
3379 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3380 interrupt to the PCIE core for MSI/inta. */
3381 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3382 interrupt to the PCIE core for MSI/inta. */
3383 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3384 interrupt to the PCIE core for MSI/inta. */
3385 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3386 interrupt to the PCIE core for MSI/inta. */
3387 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3388 interrupt to the PCIE core for MSI/inta. */
3389 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3390 interrupt to the PCIE core for MSI/inta. */
3391 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3392 interrupt to the PCIE core for MSI/inta. */
3393 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3394 interrupt to the PCIE core for MSI/inta. */
3395 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3396 interrupt to the PCIE core for MSI/inta. */
3397 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3398 interrupt to the PCIE core for MSI/inta. */
3399 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3400 interrupt to the PCIE core for MSI/inta. */
3401 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3402 interrupt to the PCIE core for MSI/inta. */
3403 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an
3404 interrupt to the PCIE core for MSI/inta. */
3405 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3406 interrupt to the PCIE core for MSI/inta. */
3407 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an
3408 interrupt to the PCIE core for MSI/inta. */
3409 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
3410 interrupt to the PCIE core for MSI/inta. */
3411 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
3412 interrupt to the PCIE core for MSI/inta. */
3413 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
3414 interrupt to the PCIE core for MSI/inta. */
3415 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
3416 interrupt to the PCIE core for MSI/inta. */
3417 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an
3418 interrupt to the PCIE core for MSI/inta. */
3419 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
3420 interrupt to the PCIE core for MSI/inta. */
3421 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an
3422 interrupt to the PCIE core for MSI/inta. */
3423 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
3424 interrupt to the PCIE core for MSI/inta. */
3425 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
3426 interrupt to the PCIE core for MSI/inta. */
3427 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
3428 interrupt to the PCIE core for MSI/inta. */
3429 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
3430 interrupt to the PCIE core for MSI/inta. */
3431 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
3432 interrupt to the PCIE core for MSI/inta. */
3433 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
3434 interrupt to the PCIE core for MSI/inta. */
3435 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
3436 interrupt to the PCIE core for MSI/inta. */
3437 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
3438 interrupt to the PCIE core for MSI/inta. */
3439 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
3440 interrupt to the PCIE core for MSI/inta. */
3441 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
3442 interrupt to the PCIE core for MSI/inta. */
3443 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
3444 interrupt to the PCIE core for MSI/inta. */
3445 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
3446 interrupt to the PCIE core for MSI/inta. */
3447 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
3448 interrupt to the PCIE core for MSI/inta. */
3449 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
3450 interrupt to the PCIE core for MSI/inta. */
3451 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
3452 interrupt to the PCIE core for MSI/inta. */
3453 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
3454 interrupt to the PCIE core for MSI/inta. */
3455 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
3456 interrupt to the PCIE core for MSI/inta. */
3457 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
3458 interrupt to the PCIE core for MSI/inta. */
3459 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
3460 interrupt to the PCIE core for MSI/inta. */
3461 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an
3462 interrupt to the PCIE core for MSI/inta. */
3463 #else
3464 uint64_t rml_rto : 1;
3465 uint64_t rml_wto : 1;
3466 uint64_t bar0_to : 1;
3467 uint64_t iob2big : 1;
3468 uint64_t dma0dbo : 1;
3469 uint64_t dma1dbo : 1;
3470 uint64_t dma2dbo : 1;
3471 uint64_t dma3dbo : 1;
3472 uint64_t dma4dbo : 1;
3473 uint64_t dma0fi : 1;
3474 uint64_t dma1fi : 1;
3475 uint64_t dcnt0 : 1;
3476 uint64_t dcnt1 : 1;
3477 uint64_t dtime0 : 1;
3478 uint64_t dtime1 : 1;
3479 uint64_t psldbof : 1;
3480 uint64_t pidbof : 1;
3481 uint64_t pcnt : 1;
3482 uint64_t ptime : 1;
3483 uint64_t c0_aeri : 1;
3484 uint64_t crs0_er : 1;
3485 uint64_t c0_se : 1;
3486 uint64_t crs0_dr : 1;
3487 uint64_t c0_wake : 1;
3488 uint64_t c0_pmei : 1;
3489 uint64_t c0_hpint : 1;
3490 uint64_t c1_aeri : 1;
3491 uint64_t crs1_er : 1;
3492 uint64_t c1_se : 1;
3493 uint64_t crs1_dr : 1;
3494 uint64_t c1_wake : 1;
3495 uint64_t c1_pmei : 1;
3496 uint64_t c1_hpint : 1;
3497 uint64_t c0_up_b0 : 1;
3498 uint64_t c0_up_b1 : 1;
3499 uint64_t c0_up_b2 : 1;
3500 uint64_t c0_up_wi : 1;
3501 uint64_t c0_up_bx : 1;
3502 uint64_t c0_un_b0 : 1;
3503 uint64_t c0_un_b1 : 1;
3504 uint64_t c0_un_b2 : 1;
3505 uint64_t c0_un_wi : 1;
3506 uint64_t c0_un_bx : 1;
3507 uint64_t c1_up_b0 : 1;
3508 uint64_t c1_up_b1 : 1;
3509 uint64_t c1_up_b2 : 1;
3510 uint64_t c1_up_wi : 1;
3511 uint64_t c1_up_bx : 1;
3512 uint64_t c1_un_b0 : 1;
3513 uint64_t c1_un_b1 : 1;
3514 uint64_t c1_un_b2 : 1;
3515 uint64_t c1_un_wi : 1;
3516 uint64_t c1_un_bx : 1;
3517 uint64_t c0_un_wf : 1;
3518 uint64_t c1_un_wf : 1;
3519 uint64_t c0_up_wf : 1;
3520 uint64_t c1_up_wf : 1;
3521 uint64_t c0_exc : 1;
3522 uint64_t c1_exc : 1;
3523 uint64_t c0_ldwn : 1;
3524 uint64_t c1_ldwn : 1;
3525 uint64_t int_a : 1;
3526 uint64_t reserved_62_62 : 1;
3527 uint64_t mio_inta : 1;
3528 #endif
3529 } s;
3530 struct cvmx_npei_int_enb_s cn52xx;
3531 struct cvmx_npei_int_enb_cn52xxp1 {
3532 #ifdef __BIG_ENDIAN_BITFIELD
3533 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an
3534 interrupt to the PCIE core for MSI/inta. */
3535 uint64_t reserved_62_62 : 1;
3536 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an
3537 interrupt to the PCIE core for MSI/inta. */
3538 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3539 interrupt to the PCIE core for MSI/inta. */
3540 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3541 interrupt to the PCIE core for MSI/inta. */
3542 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3543 interrupt to the PCIE core for MSI/inta. */
3544 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3545 interrupt to the PCIE core for MSI/inta. */
3546 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3547 interrupt to the PCIE core for MSI/inta. */
3548 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3549 interrupt to the PCIE core for MSI/inta. */
3550 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3551 interrupt to the PCIE core for MSI/inta. */
3552 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3553 interrupt to the PCIE core for MSI/inta. */
3554 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3555 interrupt to the PCIE core for MSI/inta. */
3556 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3557 interrupt to the PCIE core for MSI/inta. */
3558 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3559 interrupt to the PCIE core for MSI/inta. */
3560 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3561 interrupt to the PCIE core for MSI/inta. */
3562 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3563 interrupt to the PCIE core for MSI/inta. */
3564 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3565 interrupt to the PCIE core for MSI/inta. */
3566 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3567 interrupt to the PCIE core for MSI/inta. */
3568 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3569 interrupt to the PCIE core for MSI/inta. */
3570 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3571 interrupt to the PCIE core for MSI/inta. */
3572 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3573 interrupt to the PCIE core for MSI/inta. */
3574 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3575 interrupt to the PCIE core for MSI/inta. */
3576 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3577 interrupt to the PCIE core for MSI/inta. */
3578 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3579 interrupt to the PCIE core for MSI/inta. */
3580 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3581 interrupt to the PCIE core for MSI/inta. */
3582 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3583 interrupt to the PCIE core for MSI/inta. */
3584 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3585 interrupt to the PCIE core for MSI/inta. */
3586 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3587 interrupt to the PCIE core for MSI/inta. */
3588 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3589 interrupt to the PCIE core for MSI/inta. */
3590 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3591 interrupt to the PCIE core for MSI/inta. */
3592 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3593 interrupt to the PCIE core for MSI/inta. */
3594 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3595 interrupt to the PCIE core for MSI/inta. */
3596 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3597 interrupt to the PCIE core for MSI/inta. */
3598 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3599 interrupt to the PCIE core for MSI/inta. */
3600 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an
3601 interrupt to the PCIE core for MSI/inta. */
3602 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3603 interrupt to the PCIE core for MSI/inta. */
3604 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an
3605 interrupt to the PCIE core for MSI/inta. */
3606 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
3607 interrupt to the PCIE core for MSI/inta. */
3608 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
3609 interrupt to the PCIE core for MSI/inta. */
3610 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
3611 interrupt to the PCIE core for MSI/inta. */
3612 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
3613 interrupt to the PCIE core for MSI/inta. */
3614 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an
3615 interrupt to the PCIE core for MSI/inta. */
3616 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
3617 interrupt to the PCIE core for MSI/inta. */
3618 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an
3619 interrupt to the PCIE core for MSI/inta. */
3620 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
3621 interrupt to the PCIE core for MSI/inta. */
3622 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
3623 interrupt to the PCIE core for MSI/inta. */
3624 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
3625 interrupt to the PCIE core for MSI/inta. */
3626 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
3627 interrupt to the PCIE core for MSI/inta. */
3628 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
3629 interrupt to the PCIE core for MSI/inta. */
3630 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
3631 interrupt to the PCIE core for MSI/inta. */
3632 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
3633 interrupt to the PCIE core for MSI/inta. */
3634 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
3635 interrupt to the PCIE core for MSI/inta. */
3636 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
3637 interrupt to the PCIE core for MSI/inta. */
3638 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
3639 interrupt to the PCIE core for MSI/inta. */
3640 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
3641 interrupt to the PCIE core for MSI/inta. */
3642 uint64_t reserved_8_8 : 1;
3643 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
3644 interrupt to the PCIE core for MSI/inta. */
3645 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
3646 interrupt to the PCIE core for MSI/inta. */
3647 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
3648 interrupt to the PCIE core for MSI/inta. */
3649 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
3650 interrupt to the PCIE core for MSI/inta. */
3651 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
3652 interrupt to the PCIE core for MSI/inta. */
3653 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
3654 interrupt to the PCIE core for MSI/inta. */
3655 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
3656 interrupt to the PCIE core for MSI/inta. */
3657 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an
3658 interrupt to the PCIE core for MSI/inta. */
3659 #else
3660 uint64_t rml_rto : 1;
3661 uint64_t rml_wto : 1;
3662 uint64_t bar0_to : 1;
3663 uint64_t iob2big : 1;
3664 uint64_t dma0dbo : 1;
3665 uint64_t dma1dbo : 1;
3666 uint64_t dma2dbo : 1;
3667 uint64_t dma3dbo : 1;
3668 uint64_t reserved_8_8 : 1;
3669 uint64_t dma0fi : 1;
3670 uint64_t dma1fi : 1;
3671 uint64_t dcnt0 : 1;
3672 uint64_t dcnt1 : 1;
3673 uint64_t dtime0 : 1;
3674 uint64_t dtime1 : 1;
3675 uint64_t psldbof : 1;
3676 uint64_t pidbof : 1;
3677 uint64_t pcnt : 1;
3678 uint64_t ptime : 1;
3679 uint64_t c0_aeri : 1;
3680 uint64_t crs0_er : 1;
3681 uint64_t c0_se : 1;
3682 uint64_t crs0_dr : 1;
3683 uint64_t c0_wake : 1;
3684 uint64_t c0_pmei : 1;
3685 uint64_t c0_hpint : 1;
3686 uint64_t c1_aeri : 1;
3687 uint64_t crs1_er : 1;
3688 uint64_t c1_se : 1;
3689 uint64_t crs1_dr : 1;
3690 uint64_t c1_wake : 1;
3691 uint64_t c1_pmei : 1;
3692 uint64_t c1_hpint : 1;
3693 uint64_t c0_up_b0 : 1;
3694 uint64_t c0_up_b1 : 1;
3695 uint64_t c0_up_b2 : 1;
3696 uint64_t c0_up_wi : 1;
3697 uint64_t c0_up_bx : 1;
3698 uint64_t c0_un_b0 : 1;
3699 uint64_t c0_un_b1 : 1;
3700 uint64_t c0_un_b2 : 1;
3701 uint64_t c0_un_wi : 1;
3702 uint64_t c0_un_bx : 1;
3703 uint64_t c1_up_b0 : 1;
3704 uint64_t c1_up_b1 : 1;
3705 uint64_t c1_up_b2 : 1;
3706 uint64_t c1_up_wi : 1;
3707 uint64_t c1_up_bx : 1;
3708 uint64_t c1_un_b0 : 1;
3709 uint64_t c1_un_b1 : 1;
3710 uint64_t c1_un_b2 : 1;
3711 uint64_t c1_un_wi : 1;
3712 uint64_t c1_un_bx : 1;
3713 uint64_t c0_un_wf : 1;
3714 uint64_t c1_un_wf : 1;
3715 uint64_t c0_up_wf : 1;
3716 uint64_t c1_up_wf : 1;
3717 uint64_t c0_exc : 1;
3718 uint64_t c1_exc : 1;
3719 uint64_t c0_ldwn : 1;
3720 uint64_t c1_ldwn : 1;
3721 uint64_t int_a : 1;
3722 uint64_t reserved_62_62 : 1;
3723 uint64_t mio_inta : 1;
3724 #endif
3725 } cn52xxp1;
3726 struct cvmx_npei_int_enb_s cn56xx;
3727 struct cvmx_npei_int_enb_cn56xxp1 {
3728 #ifdef __BIG_ENDIAN_BITFIELD
3729 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an
3730 interrupt to the PCIE core for MSI/inta. */
3731 uint64_t reserved_61_62 : 2;
3732 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3733 interrupt to the PCIE core for MSI/inta. */
3734 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3735 interrupt to the PCIE core for MSI/inta. */
3736 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3737 interrupt to the PCIE core for MSI/inta. */
3738 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3739 interrupt to the PCIE core for MSI/inta. */
3740 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3741 interrupt to the PCIE core for MSI/inta. */
3742 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3743 interrupt to the PCIE core for MSI/inta. */
3744 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3745 interrupt to the PCIE core for MSI/inta. */
3746 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3747 interrupt to the PCIE core for MSI/inta. */
3748 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3749 interrupt to the PCIE core for MSI/inta. */
3750 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3751 interrupt to the PCIE core for MSI/inta. */
3752 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3753 interrupt to the PCIE core for MSI/inta. */
3754 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3755 interrupt to the PCIE core for MSI/inta. */
3756 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3757 interrupt to the PCIE core for MSI/inta. */
3758 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3759 interrupt to the PCIE core for MSI/inta. */
3760 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3761 interrupt to the PCIE core for MSI/inta. */
3762 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3763 interrupt to the PCIE core for MSI/inta. */
3764 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3765 interrupt to the PCIE core for MSI/inta. */
3766 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3767 interrupt to the PCIE core for MSI/inta. */
3768 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3769 interrupt to the PCIE core for MSI/inta. */
3770 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3771 interrupt to the PCIE core for MSI/inta. */
3772 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3773 interrupt to the PCIE core for MSI/inta. */
3774 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3775 interrupt to the PCIE core for MSI/inta. */
3776 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3777 interrupt to the PCIE core for MSI/inta. */
3778 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3779 interrupt to the PCIE core for MSI/inta. */
3780 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3781 interrupt to the PCIE core for MSI/inta. */
3782 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3783 interrupt to the PCIE core for MSI/inta. */
3784 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3785 interrupt to the PCIE core for MSI/inta. */
3786 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3787 interrupt to the PCIE core for MSI/inta. */
3788 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3789 interrupt to the PCIE core for MSI/inta. */
3790 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3791 interrupt to the PCIE core for MSI/inta. */
3792 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3793 interrupt to the PCIE core for MSI/inta. */
3794 uint64_t reserved_29_29 : 1;
3795 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3796 interrupt to the PCIE core for MSI/inta. */
3797 uint64_t reserved_27_27 : 1;
3798 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
3799 interrupt to the PCIE core for MSI/inta. */
3800 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
3801 interrupt to the PCIE core for MSI/inta. */
3802 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
3803 interrupt to the PCIE core for MSI/inta. */
3804 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
3805 interrupt to the PCIE core for MSI/inta. */
3806 uint64_t reserved_22_22 : 1;
3807 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
3808 interrupt to the PCIE core for MSI/inta. */
3809 uint64_t reserved_20_20 : 1;
3810 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
3811 interrupt to the PCIE core for MSI/inta. */
3812 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
3813 interrupt to the PCIE core for MSI/inta. */
3814 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
3815 interrupt to the PCIE core for MSI/inta. */
3816 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
3817 interrupt to the PCIE core for MSI/inta. */
3818 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
3819 interrupt to the PCIE core for MSI/inta. */
3820 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
3821 interrupt to the PCIE core for MSI/inta. */
3822 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
3823 interrupt to the PCIE core for MSI/inta. */
3824 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
3825 interrupt to the PCIE core for MSI/inta. */
3826 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
3827 interrupt to the PCIE core for MSI/inta. */
3828 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
3829 interrupt to the PCIE core for MSI/inta. */
3830 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
3831 interrupt to the PCIE core for MSI/inta. */
3832 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
3833 interrupt to the PCIE core for MSI/inta. */
3834 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
3835 interrupt to the PCIE core for MSI/inta. */
3836 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
3837 interrupt to the PCIE core for MSI/inta. */
3838 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
3839 interrupt to the PCIE core for MSI/inta. */
3840 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
3841 interrupt to the PCIE core for MSI/inta. */
3842 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
3843 interrupt to the PCIE core for MSI/inta. */
3844 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
3845 interrupt to the PCIE core for MSI/inta. */
3846 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
3847 interrupt to the PCIE core for MSI/inta. */
3848 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an
3849 interrupt to the PCIE core for MSI/inta. */
3850 #else
3851 uint64_t rml_rto : 1;
3852 uint64_t rml_wto : 1;
3853 uint64_t bar0_to : 1;
3854 uint64_t iob2big : 1;
3855 uint64_t dma0dbo : 1;
3856 uint64_t dma1dbo : 1;
3857 uint64_t dma2dbo : 1;
3858 uint64_t dma3dbo : 1;
3859 uint64_t dma4dbo : 1;
3860 uint64_t dma0fi : 1;
3861 uint64_t dma1fi : 1;
3862 uint64_t dcnt0 : 1;
3863 uint64_t dcnt1 : 1;
3864 uint64_t dtime0 : 1;
3865 uint64_t dtime1 : 1;
3866 uint64_t psldbof : 1;
3867 uint64_t pidbof : 1;
3868 uint64_t pcnt : 1;
3869 uint64_t ptime : 1;
3870 uint64_t c0_aeri : 1;
3871 uint64_t reserved_20_20 : 1;
3872 uint64_t c0_se : 1;
3873 uint64_t reserved_22_22 : 1;
3874 uint64_t c0_wake : 1;
3875 uint64_t c0_pmei : 1;
3876 uint64_t c0_hpint : 1;
3877 uint64_t c1_aeri : 1;
3878 uint64_t reserved_27_27 : 1;
3879 uint64_t c1_se : 1;
3880 uint64_t reserved_29_29 : 1;
3881 uint64_t c1_wake : 1;
3882 uint64_t c1_pmei : 1;
3883 uint64_t c1_hpint : 1;
3884 uint64_t c0_up_b0 : 1;
3885 uint64_t c0_up_b1 : 1;
3886 uint64_t c0_up_b2 : 1;
3887 uint64_t c0_up_wi : 1;
3888 uint64_t c0_up_bx : 1;
3889 uint64_t c0_un_b0 : 1;
3890 uint64_t c0_un_b1 : 1;
3891 uint64_t c0_un_b2 : 1;
3892 uint64_t c0_un_wi : 1;
3893 uint64_t c0_un_bx : 1;
3894 uint64_t c1_up_b0 : 1;
3895 uint64_t c1_up_b1 : 1;
3896 uint64_t c1_up_b2 : 1;
3897 uint64_t c1_up_wi : 1;
3898 uint64_t c1_up_bx : 1;
3899 uint64_t c1_un_b0 : 1;
3900 uint64_t c1_un_b1 : 1;
3901 uint64_t c1_un_b2 : 1;
3902 uint64_t c1_un_wi : 1;
3903 uint64_t c1_un_bx : 1;
3904 uint64_t c0_un_wf : 1;
3905 uint64_t c1_un_wf : 1;
3906 uint64_t c0_up_wf : 1;
3907 uint64_t c1_up_wf : 1;
3908 uint64_t c0_exc : 1;
3909 uint64_t c1_exc : 1;
3910 uint64_t c0_ldwn : 1;
3911 uint64_t c1_ldwn : 1;
3912 uint64_t reserved_61_62 : 2;
3913 uint64_t mio_inta : 1;
3914 #endif
3915 } cn56xxp1;
3916 };
3917 typedef union cvmx_npei_int_enb cvmx_npei_int_enb_t;
3918
3919 /**
3920 * cvmx_npei_int_enb2
3921 *
3922 * NPEI_INTERRUPT_ENB2 = NPI's Interrupt Enable2 Register
3923 *
3924 * Used to enable the various interrupting conditions of NPI
3925 */
3926 union cvmx_npei_int_enb2 {
3927 uint64_t u64;
3928 struct cvmx_npei_int_enb2_s {
3929 #ifdef __BIG_ENDIAN_BITFIELD
3930 uint64_t reserved_62_63 : 2;
3931 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an
3932 interrupt on the RSL. */
3933 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
3934 interrupt on the RSL. */
3935 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
3936 interrupt on the RSL. */
3937 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
3938 interrupt on the RSL. */
3939 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
3940 interrupt on the RSL. */
3941 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
3942 interrupt on the RSL. */
3943 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
3944 interrupt on the RSL. */
3945 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
3946 interrupt on the RSL. */
3947 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
3948 interrupt on the RSL. */
3949 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
3950 interrupt on the RSL. */
3951 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
3952 interrupt on the RSL. */
3953 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
3954 interrupt on the RSL. */
3955 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
3956 interrupt on the RSL. */
3957 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
3958 interrupt on the RSL. */
3959 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
3960 interrupt on the RSL. */
3961 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
3962 interrupt on the RSL. */
3963 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
3964 interrupt on the RSL. */
3965 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
3966 interrupt on the RSL. */
3967 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
3968 interrupt on the RSL. */
3969 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
3970 interrupt on the RSL. */
3971 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
3972 interrupt on the RSL. */
3973 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
3974 interrupt on the RSL. */
3975 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
3976 interrupt on the RSL. */
3977 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
3978 interrupt on the RSL. */
3979 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
3980 interrupt on the RSL. */
3981 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
3982 interrupt on the RSL. */
3983 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
3984 interrupt on the RSL. */
3985 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
3986 interrupt on the RSL. */
3987 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
3988 interrupt on the RSL. */
3989 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
3990 interrupt on the RSL. */
3991 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
3992 interrupt on the RSL. */
3993 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
3994 interrupt on the RSL. */
3995 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an
3996 interrupt on the RSL. */
3997 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
3998 interrupt on the RSL. */
3999 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an
4000 interrupt on the RSL. */
4001 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
4002 interrupt on the RSL. */
4003 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
4004 interrupt on the RSL. */
4005 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
4006 interrupt on the RSL. */
4007 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
4008 interrupt on the RSL. */
4009 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an
4010 interrupt on the RSL. */
4011 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
4012 interrupt on the RSL. */
4013 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an
4014 interrupt on the RSL. */
4015 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
4016 interrupt on the RSL. */
4017 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
4018 interrupt on the RSL. */
4019 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
4020 interrupt on the RSL. */
4021 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
4022 interrupt on the RSL. */
4023 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
4024 interrupt on the RSL. */
4025 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
4026 interrupt on the RSL. */
4027 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
4028 interrupt on the RSL. */
4029 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
4030 interrupt on the RSL. */
4031 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
4032 interrupt on the RSL. */
4033 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
4034 interrupt on the RSL. */
4035 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
4036 interrupt on the RSL. */
4037 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
4038 interrupt on the RSL. */
4039 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
4040 interrupt on the RSL. */
4041 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
4042 interrupt on the RSL. */
4043 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
4044 interrupt on the RSL. */
4045 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
4046 interrupt on the RSL. */
4047 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
4048 interrupt on the RSL. */
4049 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
4050 interrupt on the RSL. */
4051 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
4052 interrupt on the RSL. */
4053 uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an
4054 interrupt on the RSL. */
4055 #else
4056 uint64_t rml_rto : 1;
4057 uint64_t rml_wto : 1;
4058 uint64_t bar0_to : 1;
4059 uint64_t iob2big : 1;
4060 uint64_t dma0dbo : 1;
4061 uint64_t dma1dbo : 1;
4062 uint64_t dma2dbo : 1;
4063 uint64_t dma3dbo : 1;
4064 uint64_t dma4dbo : 1;
4065 uint64_t dma0fi : 1;
4066 uint64_t dma1fi : 1;
4067 uint64_t dcnt0 : 1;
4068 uint64_t dcnt1 : 1;
4069 uint64_t dtime0 : 1;
4070 uint64_t dtime1 : 1;
4071 uint64_t psldbof : 1;
4072 uint64_t pidbof : 1;
4073 uint64_t pcnt : 1;
4074 uint64_t ptime : 1;
4075 uint64_t c0_aeri : 1;
4076 uint64_t crs0_er : 1;
4077 uint64_t c0_se : 1;
4078 uint64_t crs0_dr : 1;
4079 uint64_t c0_wake : 1;
4080 uint64_t c0_pmei : 1;
4081 uint64_t c0_hpint : 1;
4082 uint64_t c1_aeri : 1;
4083 uint64_t crs1_er : 1;
4084 uint64_t c1_se : 1;
4085 uint64_t crs1_dr : 1;
4086 uint64_t c1_wake : 1;
4087 uint64_t c1_pmei : 1;
4088 uint64_t c1_hpint : 1;
4089 uint64_t c0_up_b0 : 1;
4090 uint64_t c0_up_b1 : 1;
4091 uint64_t c0_up_b2 : 1;
4092 uint64_t c0_up_wi : 1;
4093 uint64_t c0_up_bx : 1;
4094 uint64_t c0_un_b0 : 1;
4095 uint64_t c0_un_b1 : 1;
4096 uint64_t c0_un_b2 : 1;
4097 uint64_t c0_un_wi : 1;
4098 uint64_t c0_un_bx : 1;
4099 uint64_t c1_up_b0 : 1;
4100 uint64_t c1_up_b1 : 1;
4101 uint64_t c1_up_b2 : 1;
4102 uint64_t c1_up_wi : 1;
4103 uint64_t c1_up_bx : 1;
4104 uint64_t c1_un_b0 : 1;
4105 uint64_t c1_un_b1 : 1;
4106 uint64_t c1_un_b2 : 1;
4107 uint64_t c1_un_wi : 1;
4108 uint64_t c1_un_bx : 1;
4109 uint64_t c0_un_wf : 1;
4110 uint64_t c1_un_wf : 1;
4111 uint64_t c0_up_wf : 1;
4112 uint64_t c1_up_wf : 1;
4113 uint64_t c0_exc : 1;
4114 uint64_t c1_exc : 1;
4115 uint64_t c0_ldwn : 1;
4116 uint64_t c1_ldwn : 1;
4117 uint64_t int_a : 1;
4118 uint64_t reserved_62_63 : 2;
4119 #endif
4120 } s;
4121 struct cvmx_npei_int_enb2_s cn52xx;
4122 struct cvmx_npei_int_enb2_cn52xxp1 {
4123 #ifdef __BIG_ENDIAN_BITFIELD
4124 uint64_t reserved_62_63 : 2;
4125 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an
4126 interrupt on the RSL. */
4127 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM2[60] to generate an
4128 interrupt on the RSL. */
4129 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM2[59] to generate an
4130 interrupt on the RSL. */
4131 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM2[58] to generate an
4132 interrupt on the RSL. */
4133 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM2[57] to generate an
4134 interrupt on the RSL. */
4135 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM2[56] to generate an
4136 interrupt on the RSL. */
4137 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM2[55] to generate an
4138 interrupt on the RSL. */
4139 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM2[54] to generate an
4140 interrupt on the RSL. */
4141 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM2[53] to generate an
4142 interrupt on the RSL. */
4143 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM2[52] to generate an
4144 interrupt on the RSL. */
4145 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM2[51] to generate an
4146 interrupt on the RSL. */
4147 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM2[50] to generate an
4148 interrupt on the RSL. */
4149 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM2[49] to generate an
4150 interrupt on the RSL. */
4151 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM2[48] to generate an
4152 interrupt on the RSL. */
4153 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM2[47] to generate an
4154 interrupt on the RSL. */
4155 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM2[46] to generate an
4156 interrupt on the RSL. */
4157 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM2[45] to generate an
4158 interrupt on the RSL. */
4159 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM2[44] to generate an
4160 interrupt on the RSL. */
4161 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM2[43] to generate an
4162 interrupt on the RSL. */
4163 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM2[42] to generate an
4164 interrupt on the RSL. */
4165 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM2[41] to generate an
4166 interrupt on the RSL. */
4167 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM2[40] to generate an
4168 interrupt on the RSL. */
4169 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM2[39] to generate an
4170 interrupt on the RSL. */
4171 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM2[38] to generate an
4172 interrupt on the RSL. */
4173 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM2[37] to generate an
4174 interrupt on the RSL. */
4175 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM2[36] to generate an
4176 interrupt on the RSL. */
4177 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM2[35] to generate an
4178 interrupt on the RSL. */
4179 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM2[34] to generate an
4180 interrupt on the RSL. */
4181 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM2[33] to generate an
4182 interrupt on the RSL. */
4183 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM2[32] to generate an
4184 interrupt on the RSL. */
4185 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM2[31] to generate an
4186 interrupt on the RSL. */
4187 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM2[30] to generate an
4188 interrupt on the RSL. */
4189 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an
4190 interrupt on the RSL. */
4191 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM2[28] to generate an
4192 interrupt on the RSL. */
4193 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an
4194 interrupt on the RSL. */
4195 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM2[26] to generate an
4196 interrupt on the RSL. */
4197 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM2[25] to generate an
4198 interrupt on the RSL. */
4199 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM2[24] to generate an
4200 interrupt on the RSL. */
4201 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM2[23] to generate an
4202 interrupt on the RSL. */
4203 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an
4204 interrupt on the RSL. */
4205 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM2[21] to generate an
4206 interrupt on the RSL. */
4207 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an
4208 interrupt on the RSL. */
4209 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM2[19] to generate an
4210 interrupt on the RSL. */
4211 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM2[18] to generate an
4212 interrupt on the RSL. */
4213 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM2[17] to generate an
4214 interrupt on the RSL. */
4215 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM2[16] to generate an
4216 interrupt on the RSL. */
4217 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM2[15] to generate an
4218 interrupt on the RSL. */
4219 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM2[14] to generate an
4220 interrupt on the RSL. */
4221 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM2[13] to generate an
4222 interrupt on the RSL. */
4223 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM2[12] to generate an
4224 interrupt on the RSL. */
4225 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM2[11] to generate an
4226 interrupt on the RSL. */
4227 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM2[10] to generate an
4228 interrupt on the RSL. */
4229 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM2[9] to generate an
4230 interrupt on the RSL. */
4231 uint64_t reserved_8_8 : 1;
4232 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM2[7] to generate an
4233 interrupt on the RSL. */
4234 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM2[6] to generate an
4235 interrupt on the RSL. */
4236 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM2[5] to generate an
4237 interrupt on the RSL. */
4238 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM2[4] to generate an
4239 interrupt on the RSL. */
4240 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM2[3] to generate an
4241 interrupt on the RSL. */
4242 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM2[2] to generate an
4243 interrupt on the RSL. */
4244 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM2[1] to generate an
4245 interrupt on the RSL. */
4246 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM2[0] to generate an
4247 interrupt on the RSL. */
4248 #else
4249 uint64_t rml_rto : 1;
4250 uint64_t rml_wto : 1;
4251 uint64_t bar0_to : 1;
4252 uint64_t iob2big : 1;
4253 uint64_t dma0dbo : 1;
4254 uint64_t dma1dbo : 1;
4255 uint64_t dma2dbo : 1;
4256 uint64_t dma3dbo : 1;
4257 uint64_t reserved_8_8 : 1;
4258 uint64_t dma0fi : 1;
4259 uint64_t dma1fi : 1;
4260 uint64_t dcnt0 : 1;
4261 uint64_t dcnt1 : 1;
4262 uint64_t dtime0 : 1;
4263 uint64_t dtime1 : 1;
4264 uint64_t psldbof : 1;
4265 uint64_t pidbof : 1;
4266 uint64_t pcnt : 1;
4267 uint64_t ptime : 1;
4268 uint64_t c0_aeri : 1;
4269 uint64_t crs0_er : 1;
4270 uint64_t c0_se : 1;
4271 uint64_t crs0_dr : 1;
4272 uint64_t c0_wake : 1;
4273 uint64_t c0_pmei : 1;
4274 uint64_t c0_hpint : 1;
4275 uint64_t c1_aeri : 1;
4276 uint64_t crs1_er : 1;
4277 uint64_t c1_se : 1;
4278 uint64_t crs1_dr : 1;
4279 uint64_t c1_wake : 1;
4280 uint64_t c1_pmei : 1;
4281 uint64_t c1_hpint : 1;
4282 uint64_t c0_up_b0 : 1;
4283 uint64_t c0_up_b1 : 1;
4284 uint64_t c0_up_b2 : 1;
4285 uint64_t c0_up_wi : 1;
4286 uint64_t c0_up_bx : 1;
4287 uint64_t c0_un_b0 : 1;
4288 uint64_t c0_un_b1 : 1;
4289 uint64_t c0_un_b2 : 1;
4290 uint64_t c0_un_wi : 1;
4291 uint64_t c0_un_bx : 1;
4292 uint64_t c1_up_b0 : 1;
4293 uint64_t c1_up_b1 : 1;
4294 uint64_t c1_up_b2 : 1;
4295 uint64_t c1_up_wi : 1;
4296 uint64_t c1_up_bx : 1;
4297 uint64_t c1_un_b0 : 1;
4298 uint64_t c1_un_b1 : 1;
4299 uint64_t c1_un_b2 : 1;
4300 uint64_t c1_un_wi : 1;
4301 uint64_t c1_un_bx : 1;
4302 uint64_t c0_un_wf : 1;
4303 uint64_t c1_un_wf : 1;
4304 uint64_t c0_up_wf : 1;
4305 uint64_t c1_up_wf : 1;
4306 uint64_t c0_exc : 1;
4307 uint64_t c1_exc : 1;
4308 uint64_t c0_ldwn : 1;
4309 uint64_t c1_ldwn : 1;
4310 uint64_t int_a : 1;
4311 uint64_t reserved_62_63 : 2;
4312 #endif
4313 } cn52xxp1;
4314 struct cvmx_npei_int_enb2_s cn56xx;
4315 struct cvmx_npei_int_enb2_cn56xxp1 {
4316 #ifdef __BIG_ENDIAN_BITFIELD
4317 uint64_t reserved_61_63 : 3;
4318 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an
4319 interrupt on the RSL. */
4320 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an
4321 interrupt on the RSL. */
4322 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an
4323 interrupt on the RSL. */
4324 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an
4325 interrupt on the RSL. */
4326 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an
4327 interrupt on the RSL. */
4328 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an
4329 interrupt on the RSL. */
4330 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an
4331 interrupt on the RSL. */
4332 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an
4333 interrupt on the RSL. */
4334 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an
4335 interrupt on the RSL. */
4336 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an
4337 interrupt on the RSL. */
4338 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an
4339 interrupt on the RSL. */
4340 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an
4341 interrupt on the RSL. */
4342 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an
4343 interrupt on the RSL. */
4344 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an
4345 interrupt on the RSL. */
4346 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an
4347 interrupt on the RSL. */
4348 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an
4349 interrupt on the RSL. */
4350 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an
4351 interrupt on the RSL. */
4352 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an
4353 interrupt on the RSL. */
4354 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an
4355 interrupt on the RSL. */
4356 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an
4357 interrupt on the RSL. */
4358 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an
4359 interrupt on the RSL. */
4360 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an
4361 interrupt on the RSL. */
4362 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an
4363 interrupt on the RSL. */
4364 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an
4365 interrupt on the RSL. */
4366 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an
4367 interrupt on the RSL. */
4368 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an
4369 interrupt on the RSL. */
4370 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an
4371 interrupt on the RSL. */
4372 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an
4373 interrupt on the RSL. */
4374 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an
4375 interrupt on the RSL. */
4376 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an
4377 interrupt on the RSL. */
4378 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an
4379 interrupt on the RSL. */
4380 uint64_t reserved_29_29 : 1;
4381 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an
4382 interrupt on the RSL. */
4383 uint64_t reserved_27_27 : 1;
4384 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an
4385 interrupt on the RSL. */
4386 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an
4387 interrupt on the RSL. */
4388 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an
4389 interrupt on the RSL. */
4390 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an
4391 interrupt on the RSL. */
4392 uint64_t reserved_22_22 : 1;
4393 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an
4394 interrupt on the RSL. */
4395 uint64_t reserved_20_20 : 1;
4396 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an
4397 interrupt on the RSL. */
4398 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an
4399 interrupt on the RSL. */
4400 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an
4401 interrupt on the RSL. */
4402 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an
4403 interrupt on the RSL. */
4404 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an
4405 interrupt on the RSL. */
4406 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an
4407 interrupt on the RSL. */
4408 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an
4409 interrupt on the RSL. */
4410 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an
4411 interrupt on the RSL. */
4412 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an
4413 interrupt on the RSL. */
4414 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an
4415 interrupt on the RSL. */
4416 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an
4417 interrupt on the RSL. */
4418 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an
4419 interrupt on the RSL. */
4420 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an
4421 interrupt on the RSL. */
4422 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an
4423 interrupt on the RSL. */
4424 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an
4425 interrupt on the RSL. */
4426 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an
4427 interrupt on the RSL. */
4428 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an
4429 interrupt on the RSL. */
4430 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an
4431 interrupt on the RSL. */
4432 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an
4433 interrupt on the RSL. */
4434 uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an
4435 interrupt on the RSL. */
4436 #else
4437 uint64_t rml_rto : 1;
4438 uint64_t rml_wto : 1;
4439 uint64_t bar0_to : 1;
4440 uint64_t iob2big : 1;
4441 uint64_t dma0dbo : 1;
4442 uint64_t dma1dbo : 1;
4443 uint64_t dma2dbo : 1;
4444 uint64_t dma3dbo : 1;
4445 uint64_t dma4dbo : 1;
4446 uint64_t dma0fi : 1;
4447 uint64_t dma1fi : 1;
4448 uint64_t dcnt0 : 1;
4449 uint64_t dcnt1 : 1;
4450 uint64_t dtime0 : 1;
4451 uint64_t dtime1 : 1;
4452 uint64_t psldbof : 1;
4453 uint64_t pidbof : 1;
4454 uint64_t pcnt : 1;
4455 uint64_t ptime : 1;
4456 uint64_t c0_aeri : 1;
4457 uint64_t reserved_20_20 : 1;
4458 uint64_t c0_se : 1;
4459 uint64_t reserved_22_22 : 1;
4460 uint64_t c0_wake : 1;
4461 uint64_t c0_pmei : 1;
4462 uint64_t c0_hpint : 1;
4463 uint64_t c1_aeri : 1;
4464 uint64_t reserved_27_27 : 1;
4465 uint64_t c1_se : 1;
4466 uint64_t reserved_29_29 : 1;
4467 uint64_t c1_wake : 1;
4468 uint64_t c1_pmei : 1;
4469 uint64_t c1_hpint : 1;
4470 uint64_t c0_up_b0 : 1;
4471 uint64_t c0_up_b1 : 1;
4472 uint64_t c0_up_b2 : 1;
4473 uint64_t c0_up_wi : 1;
4474 uint64_t c0_up_bx : 1;
4475 uint64_t c0_un_b0 : 1;
4476 uint64_t c0_un_b1 : 1;
4477 uint64_t c0_un_b2 : 1;
4478 uint64_t c0_un_wi : 1;
4479 uint64_t c0_un_bx : 1;
4480 uint64_t c1_up_b0 : 1;
4481 uint64_t c1_up_b1 : 1;
4482 uint64_t c1_up_b2 : 1;
4483 uint64_t c1_up_wi : 1;
4484 uint64_t c1_up_bx : 1;
4485 uint64_t c1_un_b0 : 1;
4486 uint64_t c1_un_b1 : 1;
4487 uint64_t c1_un_b2 : 1;
4488 uint64_t c1_un_wi : 1;
4489 uint64_t c1_un_bx : 1;
4490 uint64_t c0_un_wf : 1;
4491 uint64_t c1_un_wf : 1;
4492 uint64_t c0_up_wf : 1;
4493 uint64_t c1_up_wf : 1;
4494 uint64_t c0_exc : 1;
4495 uint64_t c1_exc : 1;
4496 uint64_t c0_ldwn : 1;
4497 uint64_t c1_ldwn : 1;
4498 uint64_t reserved_61_63 : 3;
4499 #endif
4500 } cn56xxp1;
4501 };
4502 typedef union cvmx_npei_int_enb2 cvmx_npei_int_enb2_t;
4503
4504 /**
4505 * cvmx_npei_int_info
4506 *
4507 * NPEI_INT_INFO = NPI Interrupt Information
4508 *
4509 * Contains information about some of the interrupt condition that can occur in the NPEI_INTERRUPT_SUM register.
4510 */
4511 union cvmx_npei_int_info {
4512 uint64_t u64;
4513 struct cvmx_npei_int_info_s {
4514 #ifdef __BIG_ENDIAN_BITFIELD
4515 uint64_t reserved_12_63 : 52;
4516 uint64_t pidbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit
4517 is set. This field when set will not change again
4518 unitl NPEI_INTERRUPT_SUM[PIDBOF] is cleared. */
4519 uint64_t psldbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PSLDBOF] bit
4520 is set. This field when set will not change again
4521 unitl NPEI_INTERRUPT_SUM[PSLDBOF] is cleared. */
4522 #else
4523 uint64_t psldbof : 6;
4524 uint64_t pidbof : 6;
4525 uint64_t reserved_12_63 : 52;
4526 #endif
4527 } s;
4528 struct cvmx_npei_int_info_s cn52xx;
4529 struct cvmx_npei_int_info_s cn56xx;
4530 struct cvmx_npei_int_info_s cn56xxp1;
4531 };
4532 typedef union cvmx_npei_int_info cvmx_npei_int_info_t;
4533
4534 /**
4535 * cvmx_npei_int_sum
4536 *
4537 * NPEI_INTERRUPT_SUM = NPI Interrupt Summary Register
4538 *
4539 * Set when an interrupt condition occurs, write '1' to clear.
4540 *
4541 * HACK: These used to exist, how are TO handled?
4542 * <3> PO0_2SML R/W1C 0x0 0 The packet being sent out on Port0 is smaller $R NS
4543 * than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.
4544 * <7> I0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS
4545 * read instructions.
4546 * <15> P0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS
4547 * read packet data.
4548 * <23> G0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS
4549 * read a gather list.
4550 * <31> P0_PTOUT R/W1C 0x0 0 Port-0 output had a read timeout on a DATA/INFO $R NS
4551 * pair.
4552 */
4553 union cvmx_npei_int_sum {
4554 uint64_t u64;
4555 struct cvmx_npei_int_sum_s {
4556 #ifdef __BIG_ENDIAN_BITFIELD
4557 uint64_t mio_inta : 1; /**< Interrupt from MIO. */
4558 uint64_t reserved_62_62 : 1;
4559 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and
4560 the cooresponding bit in the NPEI_INT_A_ENB
4561 register is set. */
4562 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */
4563 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */
4564 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit
4565 set and its cooresponding PESC1_DBG_INFO_EN bit
4566 is set. */
4567 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit
4568 set and its cooresponding PESC0_DBG_INFO_EN bit
4569 is set. */
4570 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4571 register. Core1. */
4572 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4573 register. Core0. */
4574 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4575 register. Core1. */
4576 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4577 register. Core0. */
4578 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4579 Core 1. */
4580 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4581 Core 1. */
4582 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4583 Core 1. */
4584 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4585 Core 1. */
4586 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4587 Core 1. */
4588 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4589 Core 1. */
4590 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4591 Core 1. */
4592 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4593 Core 1. */
4594 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4595 Core 1. */
4596 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4597 Core 1. */
4598 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4599 Core 0. */
4600 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4601 Core 0. */
4602 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4603 Core 0. */
4604 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4605 Core 0. */
4606 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4607 Core 0. */
4608 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4609 Core 0. */
4610 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4611 Core 0. */
4612 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4613 Core 0. */
4614 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4615 Core 0. */
4616 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4617 Core 0. */
4618 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt.
4619 Pcie Core 1 (hp_int).
4620 This interrupt will only be generated when
4621 PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
4622 not supported. */
4623 uint64_t c1_pmei : 1; /**< PME Interrupt.
4624 Pcie Core 1. (cfg_pme_int) */
4625 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit.
4626 Pcie Core 1. (wake_n)
4627 Octeon will never generate this interrupt. */
4628 uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */
4629 uint64_t c1_se : 1; /**< System Error, RC Mode Only.
4630 Pcie Core 1. (cfg_sys_err_rc) */
4631 uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4632 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4633 Pcie Core 1. */
4634 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt.
4635 Pcie Core 0 (hp_int).
4636 This interrupt will only be generated when
4637 PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
4638 not supported. */
4639 uint64_t c0_pmei : 1; /**< PME Interrupt.
4640 Pcie Core 0. (cfg_pme_int) */
4641 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit.
4642 Pcie Core 0. (wake_n)
4643 Octeon will never generate this interrupt. */
4644 uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */
4645 uint64_t c0_se : 1; /**< System Error, RC Mode Only.
4646 Pcie Core 0. (cfg_sys_err_rc) */
4647 uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4648 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4649 Pcie Core 0 (cfg_aer_rc_err_int). */
4650 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can
4651 be found in NPEI_PKT_TIME_INT. */
4652 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can
4653 be found in NPEI_PKT_CNT_INT. */
4654 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which
4655 doorbell can be found in NPEI_INT_INFO[PIDBOF] */
4656 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which
4657 doorbell can be found in NPEI_INT_INFO[PSLDBOF] */
4658 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
4659 DMA_CNT1 timer increments every core clock. When
4660 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
4661 this bit is set. Writing a '1' to this bit also
4662 clears the DMA_CNT1 timer. */
4663 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
4664 DMA_CNT0 timer increments every core clock. When
4665 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
4666 this bit is set. Writing a '1' to this bit also
4667 clears the DMA_CNT0 timer. */
4668 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
4669 greater than NPEI_DMA1_INT_LEVEL[CNT]. */
4670 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
4671 greater than NPEI_DMA0_INT_LEVEL[CNT]. */
4672 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */
4673 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */
4674 uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow.
4675 Bit[32] of the doorbell count was set. */
4676 uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow.
4677 Bit[32] of the doorbell count was set. */
4678 uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow.
4679 Bit[32] of the doorbell count was set. */
4680 uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow.
4681 Bit[32] of the doorbell count was set. */
4682 uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow.
4683 Bit[32] of the doorbell count was set. */
4684 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
4685 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
4686 read-data/commit in 0xffff core clocks. */
4687 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */
4688 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */
4689 #else
4690 uint64_t rml_rto : 1;
4691 uint64_t rml_wto : 1;
4692 uint64_t bar0_to : 1;
4693 uint64_t iob2big : 1;
4694 uint64_t dma0dbo : 1;
4695 uint64_t dma1dbo : 1;
4696 uint64_t dma2dbo : 1;
4697 uint64_t dma3dbo : 1;
4698 uint64_t dma4dbo : 1;
4699 uint64_t dma0fi : 1;
4700 uint64_t dma1fi : 1;
4701 uint64_t dcnt0 : 1;
4702 uint64_t dcnt1 : 1;
4703 uint64_t dtime0 : 1;
4704 uint64_t dtime1 : 1;
4705 uint64_t psldbof : 1;
4706 uint64_t pidbof : 1;
4707 uint64_t pcnt : 1;
4708 uint64_t ptime : 1;
4709 uint64_t c0_aeri : 1;
4710 uint64_t crs0_er : 1;
4711 uint64_t c0_se : 1;
4712 uint64_t crs0_dr : 1;
4713 uint64_t c0_wake : 1;
4714 uint64_t c0_pmei : 1;
4715 uint64_t c0_hpint : 1;
4716 uint64_t c1_aeri : 1;
4717 uint64_t crs1_er : 1;
4718 uint64_t c1_se : 1;
4719 uint64_t crs1_dr : 1;
4720 uint64_t c1_wake : 1;
4721 uint64_t c1_pmei : 1;
4722 uint64_t c1_hpint : 1;
4723 uint64_t c0_up_b0 : 1;
4724 uint64_t c0_up_b1 : 1;
4725 uint64_t c0_up_b2 : 1;
4726 uint64_t c0_up_wi : 1;
4727 uint64_t c0_up_bx : 1;
4728 uint64_t c0_un_b0 : 1;
4729 uint64_t c0_un_b1 : 1;
4730 uint64_t c0_un_b2 : 1;
4731 uint64_t c0_un_wi : 1;
4732 uint64_t c0_un_bx : 1;
4733 uint64_t c1_up_b0 : 1;
4734 uint64_t c1_up_b1 : 1;
4735 uint64_t c1_up_b2 : 1;
4736 uint64_t c1_up_wi : 1;
4737 uint64_t c1_up_bx : 1;
4738 uint64_t c1_un_b0 : 1;
4739 uint64_t c1_un_b1 : 1;
4740 uint64_t c1_un_b2 : 1;
4741 uint64_t c1_un_wi : 1;
4742 uint64_t c1_un_bx : 1;
4743 uint64_t c0_un_wf : 1;
4744 uint64_t c1_un_wf : 1;
4745 uint64_t c0_up_wf : 1;
4746 uint64_t c1_up_wf : 1;
4747 uint64_t c0_exc : 1;
4748 uint64_t c1_exc : 1;
4749 uint64_t c0_ldwn : 1;
4750 uint64_t c1_ldwn : 1;
4751 uint64_t int_a : 1;
4752 uint64_t reserved_62_62 : 1;
4753 uint64_t mio_inta : 1;
4754 #endif
4755 } s;
4756 struct cvmx_npei_int_sum_s cn52xx;
4757 struct cvmx_npei_int_sum_cn52xxp1 {
4758 #ifdef __BIG_ENDIAN_BITFIELD
4759 uint64_t mio_inta : 1; /**< Interrupt from MIO. */
4760 uint64_t reserved_62_62 : 1;
4761 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and
4762 the cooresponding bit in the NPEI_INT_A_ENB
4763 register is set. */
4764 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */
4765 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */
4766 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit
4767 set and its cooresponding PESC1_DBG_INFO_EN bit
4768 is set. */
4769 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit
4770 set and its cooresponding PESC0_DBG_INFO_EN bit
4771 is set. */
4772 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4773 register. Core1. */
4774 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4775 register. Core0. */
4776 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4777 register. Core1. */
4778 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4779 register. Core0. */
4780 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4781 Core 1. */
4782 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4783 Core 1. */
4784 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4785 Core 1. */
4786 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4787 Core 1. */
4788 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4789 Core 1. */
4790 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4791 Core 1. */
4792 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4793 Core 1. */
4794 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4795 Core 1. */
4796 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4797 Core 1. */
4798 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4799 Core 1. */
4800 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4801 Core 0. */
4802 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4803 Core 0. */
4804 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4805 Core 0. */
4806 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4807 Core 0. */
4808 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4809 Core 0. */
4810 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4811 Core 0. */
4812 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4813 Core 0. */
4814 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4815 Core 0. */
4816 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4817 Core 0. */
4818 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4819 Core 0. */
4820 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt.
4821 Pcie Core 1 (hp_int).
4822 This interrupt will only be generated when
4823 PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
4824 not supported. */
4825 uint64_t c1_pmei : 1; /**< PME Interrupt.
4826 Pcie Core 1. (cfg_pme_int) */
4827 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit.
4828 Pcie Core 1. (wake_n)
4829 Octeon will never generate this interrupt. */
4830 uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */
4831 uint64_t c1_se : 1; /**< System Error, RC Mode Only.
4832 Pcie Core 1. (cfg_sys_err_rc) */
4833 uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4834 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4835 Pcie Core 1. */
4836 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt.
4837 Pcie Core 0 (hp_int).
4838 This interrupt will only be generated when
4839 PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
4840 not supported. */
4841 uint64_t c0_pmei : 1; /**< PME Interrupt.
4842 Pcie Core 0. (cfg_pme_int) */
4843 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit.
4844 Pcie Core 0. (wake_n)
4845 Octeon will never generate this interrupt. */
4846 uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */
4847 uint64_t c0_se : 1; /**< System Error, RC Mode Only.
4848 Pcie Core 0. (cfg_sys_err_rc) */
4849 uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
4850 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
4851 Pcie Core 0 (cfg_aer_rc_err_int). */
4852 uint64_t reserved_15_18 : 4;
4853 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
4854 DMA_CNT1 timer increments every core clock. When
4855 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
4856 this bit is set. Writing a '1' to this bit also
4857 clears the DMA_CNT1 timer. */
4858 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
4859 DMA_CNT0 timer increments every core clock. When
4860 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
4861 this bit is set. Writing a '1' to this bit also
4862 clears the DMA_CNT0 timer. */
4863 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
4864 greater than NPEI_DMA1_INT_LEVEL[CNT]. */
4865 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
4866 greater than NPEI_DMA0_INT_LEVEL[CNT]. */
4867 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */
4868 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */
4869 uint64_t reserved_8_8 : 1;
4870 uint64_t dma3dbo : 1; /**< DMA3 doorbell count overflow.
4871 Bit[32] of the doorbell count was set. */
4872 uint64_t dma2dbo : 1; /**< DMA2 doorbell count overflow.
4873 Bit[32] of the doorbell count was set. */
4874 uint64_t dma1dbo : 1; /**< DMA1 doorbell count overflow.
4875 Bit[32] of the doorbell count was set. */
4876 uint64_t dma0dbo : 1; /**< DMA0 doorbell count overflow.
4877 Bit[32] of the doorbell count was set. */
4878 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
4879 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
4880 read-data/commit in 0xffff core clocks. */
4881 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */
4882 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */
4883 #else
4884 uint64_t rml_rto : 1;
4885 uint64_t rml_wto : 1;
4886 uint64_t bar0_to : 1;
4887 uint64_t iob2big : 1;
4888 uint64_t dma0dbo : 1;
4889 uint64_t dma1dbo : 1;
4890 uint64_t dma2dbo : 1;
4891 uint64_t dma3dbo : 1;
4892 uint64_t reserved_8_8 : 1;
4893 uint64_t dma0fi : 1;
4894 uint64_t dma1fi : 1;
4895 uint64_t dcnt0 : 1;
4896 uint64_t dcnt1 : 1;
4897 uint64_t dtime0 : 1;
4898 uint64_t dtime1 : 1;
4899 uint64_t reserved_15_18 : 4;
4900 uint64_t c0_aeri : 1;
4901 uint64_t crs0_er : 1;
4902 uint64_t c0_se : 1;
4903 uint64_t crs0_dr : 1;
4904 uint64_t c0_wake : 1;
4905 uint64_t c0_pmei : 1;
4906 uint64_t c0_hpint : 1;
4907 uint64_t c1_aeri : 1;
4908 uint64_t crs1_er : 1;
4909 uint64_t c1_se : 1;
4910 uint64_t crs1_dr : 1;
4911 uint64_t c1_wake : 1;
4912 uint64_t c1_pmei : 1;
4913 uint64_t c1_hpint : 1;
4914 uint64_t c0_up_b0 : 1;
4915 uint64_t c0_up_b1 : 1;
4916 uint64_t c0_up_b2 : 1;
4917 uint64_t c0_up_wi : 1;
4918 uint64_t c0_up_bx : 1;
4919 uint64_t c0_un_b0 : 1;
4920 uint64_t c0_un_b1 : 1;
4921 uint64_t c0_un_b2 : 1;
4922 uint64_t c0_un_wi : 1;
4923 uint64_t c0_un_bx : 1;
4924 uint64_t c1_up_b0 : 1;
4925 uint64_t c1_up_b1 : 1;
4926 uint64_t c1_up_b2 : 1;
4927 uint64_t c1_up_wi : 1;
4928 uint64_t c1_up_bx : 1;
4929 uint64_t c1_un_b0 : 1;
4930 uint64_t c1_un_b1 : 1;
4931 uint64_t c1_un_b2 : 1;
4932 uint64_t c1_un_wi : 1;
4933 uint64_t c1_un_bx : 1;
4934 uint64_t c0_un_wf : 1;
4935 uint64_t c1_un_wf : 1;
4936 uint64_t c0_up_wf : 1;
4937 uint64_t c1_up_wf : 1;
4938 uint64_t c0_exc : 1;
4939 uint64_t c1_exc : 1;
4940 uint64_t c0_ldwn : 1;
4941 uint64_t c1_ldwn : 1;
4942 uint64_t int_a : 1;
4943 uint64_t reserved_62_62 : 1;
4944 uint64_t mio_inta : 1;
4945 #endif
4946 } cn52xxp1;
4947 struct cvmx_npei_int_sum_s cn56xx;
4948 struct cvmx_npei_int_sum_cn56xxp1 {
4949 #ifdef __BIG_ENDIAN_BITFIELD
4950 uint64_t mio_inta : 1; /**< Interrupt from MIO. */
4951 uint64_t reserved_61_62 : 2;
4952 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */
4953 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */
4954 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit
4955 set and its cooresponding PESC1_DBG_INFO_EN bit
4956 is set. */
4957 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit
4958 set and its cooresponding PESC0_DBG_INFO_EN bit
4959 is set. */
4960 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4961 register. Core1. */
4962 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window
4963 register. Core0. */
4964 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4965 register. Core1. */
4966 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window
4967 register. Core0. */
4968 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4969 Core 1. */
4970 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4971 Core 1. */
4972 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4973 Core 1. */
4974 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4975 Core 1. */
4976 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4977 Core 1. */
4978 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4979 Core 1. */
4980 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
4981 Core 1. */
4982 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
4983 Core 1. */
4984 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
4985 Core 1. */
4986 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
4987 Core 1. */
4988 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar.
4989 Core 0. */
4990 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register.
4991 Core 0. */
4992 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2.
4993 Core 0. */
4994 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1.
4995 Core 0. */
4996 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0.
4997 Core 0. */
4998 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar.
4999 Core 0. */
5000 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register.
5001 Core 0. */
5002 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2.
5003 Core 0. */
5004 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1.
5005 Core 0. */
5006 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0.
5007 Core 0. */
5008 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt.
5009 Pcie Core 1 (hp_int).
5010 This interrupt will only be generated when
5011 PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
5012 not supported. */
5013 uint64_t c1_pmei : 1; /**< PME Interrupt.
5014 Pcie Core 1. (cfg_pme_int) */
5015 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit.
5016 Pcie Core 1. (wake_n)
5017 Octeon will never generate this interrupt. */
5018 uint64_t reserved_29_29 : 1;
5019 uint64_t c1_se : 1; /**< System Error, RC Mode Only.
5020 Pcie Core 1. (cfg_sys_err_rc) */
5021 uint64_t reserved_27_27 : 1;
5022 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
5023 Pcie Core 1. */
5024 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt.
5025 Pcie Core 0 (hp_int).
5026 This interrupt will only be generated when
5027 PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
5028 not supported. */
5029 uint64_t c0_pmei : 1; /**< PME Interrupt.
5030 Pcie Core 0. (cfg_pme_int) */
5031 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit.
5032 Pcie Core 0. (wake_n)
5033 Octeon will never generate this interrupt. */
5034 uint64_t reserved_22_22 : 1;
5035 uint64_t c0_se : 1; /**< System Error, RC Mode Only.
5036 Pcie Core 0. (cfg_sys_err_rc) */
5037 uint64_t reserved_20_20 : 1;
5038 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
5039 Pcie Core 0 (cfg_aer_rc_err_int). */
5040 uint64_t reserved_15_18 : 4;
5041 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
5042 DMA_CNT1 timer increments every core clock. When
5043 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
5044 this bit is set. Writing a '1' to this bit also
5045 clears the DMA_CNT1 timer. */
5046 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
5047 DMA_CNT0 timer increments every core clock. When
5048 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
5049 this bit is set. Writing a '1' to this bit also
5050 clears the DMA_CNT0 timer. */
5051 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
5052 greater than NPEI_DMA1_INT_LEVEL[CNT]. */
5053 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
5054 greater than NPEI_DMA0_INT_LEVEL[CNT]. */
5055 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */
5056 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */
5057 uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow.
5058 Bit[32] of the doorbell count was set. */
5059 uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow.
5060 Bit[32] of the doorbell count was set. */
5061 uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow.
5062 Bit[32] of the doorbell count was set. */
5063 uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow.
5064 Bit[32] of the doorbell count was set. */
5065 uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow.
5066 Bit[32] of the doorbell count was set. */
5067 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
5068 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
5069 read-data/commit in 0xffff core clocks. */
5070 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */
5071 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */
5072 #else
5073 uint64_t rml_rto : 1;
5074 uint64_t rml_wto : 1;
5075 uint64_t bar0_to : 1;
5076 uint64_t iob2big : 1;
5077 uint64_t dma0dbo : 1;
5078 uint64_t dma1dbo : 1;
5079 uint64_t dma2dbo : 1;
5080 uint64_t dma3dbo : 1;
5081 uint64_t dma4dbo : 1;
5082 uint64_t dma0fi : 1;
5083 uint64_t dma1fi : 1;
5084 uint64_t dcnt0 : 1;
5085 uint64_t dcnt1 : 1;
5086 uint64_t dtime0 : 1;
5087 uint64_t dtime1 : 1;
5088 uint64_t reserved_15_18 : 4;
5089 uint64_t c0_aeri : 1;
5090 uint64_t reserved_20_20 : 1;
5091 uint64_t c0_se : 1;
5092 uint64_t reserved_22_22 : 1;
5093 uint64_t c0_wake : 1;
5094 uint64_t c0_pmei : 1;
5095 uint64_t c0_hpint : 1;
5096 uint64_t c1_aeri : 1;
5097 uint64_t reserved_27_27 : 1;
5098 uint64_t c1_se : 1;
5099 uint64_t reserved_29_29 : 1;
5100 uint64_t c1_wake : 1;
5101 uint64_t c1_pmei : 1;
5102 uint64_t c1_hpint : 1;
5103 uint64_t c0_up_b0 : 1;
5104 uint64_t c0_up_b1 : 1;
5105 uint64_t c0_up_b2 : 1;
5106 uint64_t c0_up_wi : 1;
5107 uint64_t c0_up_bx : 1;
5108 uint64_t c0_un_b0 : 1;
5109 uint64_t c0_un_b1 : 1;
5110 uint64_t c0_un_b2 : 1;
5111 uint64_t c0_un_wi : 1;
5112 uint64_t c0_un_bx : 1;
5113 uint64_t c1_up_b0 : 1;
5114 uint64_t c1_up_b1 : 1;
5115 uint64_t c1_up_b2 : 1;
5116 uint64_t c1_up_wi : 1;
5117 uint64_t c1_up_bx : 1;
5118 uint64_t c1_un_b0 : 1;
5119 uint64_t c1_un_b1 : 1;
5120 uint64_t c1_un_b2 : 1;
5121 uint64_t c1_un_wi : 1;
5122 uint64_t c1_un_bx : 1;
5123 uint64_t c0_un_wf : 1;
5124 uint64_t c1_un_wf : 1;
5125 uint64_t c0_up_wf : 1;
5126 uint64_t c1_up_wf : 1;
5127 uint64_t c0_exc : 1;
5128 uint64_t c1_exc : 1;
5129 uint64_t c0_ldwn : 1;
5130 uint64_t c1_ldwn : 1;
5131 uint64_t reserved_61_62 : 2;
5132 uint64_t mio_inta : 1;
5133 #endif
5134 } cn56xxp1;
5135 };
5136 typedef union cvmx_npei_int_sum cvmx_npei_int_sum_t;
5137
5138 /**
5139 * cvmx_npei_int_sum2
5140 *
5141 * NPEI_INTERRUPT_SUM2 = NPI Interrupt Summary2 Register
5142 *
5143 * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit variances.
5144 */
5145 union cvmx_npei_int_sum2 {
5146 uint64_t u64;
5147 struct cvmx_npei_int_sum2_s {
5148 #ifdef __BIG_ENDIAN_BITFIELD
5149 uint64_t mio_inta : 1; /**< Equal to the cooresponding bit if the
5150 NPEI_INT_SUM register. */
5151 uint64_t reserved_62_62 : 1;
5152 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and
5153 the cooresponding bit in the NPEI_INT_A_ENB2
5154 register is set. */
5155 uint64_t c1_ldwn : 1; /**< Equal to the cooresponding bit if the
5156 NPEI_INT_SUM register. */
5157 uint64_t c0_ldwn : 1; /**< Equal to the cooresponding bit if the
5158 NPEI_INT_SUM register. */
5159 uint64_t c1_exc : 1; /**< Equal to the cooresponding bit if the
5160 NPEI_INT_SUM register. */
5161 uint64_t c0_exc : 1; /**< Equal to the cooresponding bit if the
5162 NPEI_INT_SUM register. */
5163 uint64_t c1_up_wf : 1; /**< Equal to the cooresponding bit if the
5164 NPEI_INT_SUM register. */
5165 uint64_t c0_up_wf : 1; /**< Equal to the cooresponding bit if the
5166 NPEI_INT_SUM register. */
5167 uint64_t c1_un_wf : 1; /**< Equal to the cooresponding bit if the
5168 NPEI_INT_SUM register. */
5169 uint64_t c0_un_wf : 1; /**< Equal to the cooresponding bit if the
5170 NPEI_INT_SUM register. */
5171 uint64_t c1_un_bx : 1; /**< Equal to the cooresponding bit if the
5172 NPEI_INT_SUM register. */
5173 uint64_t c1_un_wi : 1; /**< Equal to the cooresponding bit if the
5174 NPEI_INT_SUM register. */
5175 uint64_t c1_un_b2 : 1; /**< Equal to the cooresponding bit if the
5176 NPEI_INT_SUM register. */
5177 uint64_t c1_un_b1 : 1; /**< Equal to the cooresponding bit if the
5178 NPEI_INT_SUM register. */
5179 uint64_t c1_un_b0 : 1; /**< Equal to the cooresponding bit if the
5180 NPEI_INT_SUM register. */
5181 uint64_t c1_up_bx : 1; /**< Equal to the cooresponding bit if the
5182 NPEI_INT_SUM register. */
5183 uint64_t c1_up_wi : 1; /**< Equal to the cooresponding bit if the
5184 NPEI_INT_SUM register. */
5185 uint64_t c1_up_b2 : 1; /**< Equal to the cooresponding bit if the
5186 NPEI_INT_SUM register. */
5187 uint64_t c1_up_b1 : 1; /**< Equal to the cooresponding bit if the
5188 NPEI_INT_SUM register. */
5189 uint64_t c1_up_b0 : 1; /**< Equal to the cooresponding bit if the
5190 NPEI_INT_SUM register. */
5191 uint64_t c0_un_bx : 1; /**< Equal to the cooresponding bit if the
5192 NPEI_INT_SUM register. */
5193 uint64_t c0_un_wi : 1; /**< Equal to the cooresponding bit if the
5194 NPEI_INT_SUM register. */
5195 uint64_t c0_un_b2 : 1; /**< Equal to the cooresponding bit if the
5196 NPEI_INT_SUM register. */
5197 uint64_t c0_un_b1 : 1; /**< Equal to the cooresponding bit if the
5198 NPEI_INT_SUM register. */
5199 uint64_t c0_un_b0 : 1; /**< Equal to the cooresponding bit if the
5200 NPEI_INT_SUM register. */
5201 uint64_t c0_up_bx : 1; /**< Equal to the cooresponding bit if the
5202 NPEI_INT_SUM register. */
5203 uint64_t c0_up_wi : 1; /**< Equal to the cooresponding bit if the
5204 NPEI_INT_SUM register. */
5205 uint64_t c0_up_b2 : 1; /**< Equal to the cooresponding bit if the
5206 NPEI_INT_SUM register. */
5207 uint64_t c0_up_b1 : 1; /**< Equal to the cooresponding bit if the
5208 NPEI_INT_SUM register. */
5209 uint64_t c0_up_b0 : 1; /**< Equal to the cooresponding bit if the
5210 NPEI_INT_SUM register. */
5211 uint64_t c1_hpint : 1; /**< Equal to the cooresponding bit if the
5212 NPEI_INT_SUM register. */
5213 uint64_t c1_pmei : 1; /**< Equal to the cooresponding bit if the
5214 NPEI_INT_SUM register. */
5215 uint64_t c1_wake : 1; /**< Equal to the cooresponding bit if the
5216 NPEI_INT_SUM register. */
5217 uint64_t crs1_dr : 1; /**< Equal to the cooresponding bit if the
5218 NPEI_INT_SUM register. */
5219 uint64_t c1_se : 1; /**< Equal to the cooresponding bit if the
5220 NPEI_INT_SUM register. */
5221 uint64_t crs1_er : 1; /**< Equal to the cooresponding bit if the
5222 NPEI_INT_SUM register. */
5223 uint64_t c1_aeri : 1; /**< Equal to the cooresponding bit if the
5224 NPEI_INT_SUM register. */
5225 uint64_t c0_hpint : 1; /**< Equal to the cooresponding bit if the
5226 NPEI_INT_SUM register. */
5227 uint64_t c0_pmei : 1; /**< Equal to the cooresponding bit if the
5228 NPEI_INT_SUM register. */
5229 uint64_t c0_wake : 1; /**< Equal to the cooresponding bit if the
5230 NPEI_INT_SUM register. */
5231 uint64_t crs0_dr : 1; /**< Equal to the cooresponding bit if the
5232 NPEI_INT_SUM register. */
5233 uint64_t c0_se : 1; /**< Equal to the cooresponding bit if the
5234 NPEI_INT_SUM register. */
5235 uint64_t crs0_er : 1; /**< Equal to the cooresponding bit if the
5236 NPEI_INT_SUM register. */
5237 uint64_t c0_aeri : 1; /**< Equal to the cooresponding bit if the
5238 NPEI_INT_SUM register. */
5239 uint64_t reserved_15_18 : 4;
5240 uint64_t dtime1 : 1; /**< Equal to the cooresponding bit if the
5241 NPEI_INT_SUM register. */
5242 uint64_t dtime0 : 1; /**< Equal to the cooresponding bit if the
5243 NPEI_INT_SUM register. */
5244 uint64_t dcnt1 : 1; /**< Equal to the cooresponding bit if the
5245 NPEI_INT_SUM register. */
5246 uint64_t dcnt0 : 1; /**< Equal to the cooresponding bit if the
5247 NPEI_INT_SUM register. */
5248 uint64_t dma1fi : 1; /**< Equal to the cooresponding bit if the
5249 NPEI_INT_SUM register. */
5250 uint64_t dma0fi : 1; /**< Equal to the cooresponding bit if the
5251 NPEI_INT_SUM register. */
5252 uint64_t reserved_8_8 : 1;
5253 uint64_t dma3dbo : 1; /**< Equal to the cooresponding bit if the
5254 NPEI_INT_SUM register. */
5255 uint64_t dma2dbo : 1; /**< Equal to the cooresponding bit if the
5256 NPEI_INT_SUM register. */
5257 uint64_t dma1dbo : 1; /**< Equal to the cooresponding bit if the
5258 NPEI_INT_SUM register. */
5259 uint64_t dma0dbo : 1; /**< Equal to the cooresponding bit if the
5260 NPEI_INT_SUM register. */
5261 uint64_t iob2big : 1; /**< Equal to the cooresponding bit if the
5262 NPEI_INT_SUM register. */
5263 uint64_t bar0_to : 1; /**< Equal to the cooresponding bit if the
5264 NPEI_INT_SUM register. */
5265 uint64_t rml_wto : 1; /**< Equal to the cooresponding bit if the
5266 NPEI_INT_SUM register. */
5267 uint64_t rml_rto : 1; /**< Equal to the cooresponding bit if the
5268 NPEI_INT_SUM register. */
5269 #else
5270 uint64_t rml_rto : 1;
5271 uint64_t rml_wto : 1;
5272 uint64_t bar0_to : 1;
5273 uint64_t iob2big : 1;
5274 uint64_t dma0dbo : 1;
5275 uint64_t dma1dbo : 1;
5276 uint64_t dma2dbo : 1;
5277 uint64_t dma3dbo : 1;
5278 uint64_t reserved_8_8 : 1;
5279 uint64_t dma0fi : 1;
5280 uint64_t dma1fi : 1;
5281 uint64_t dcnt0 : 1;
5282 uint64_t dcnt1 : 1;
5283 uint64_t dtime0 : 1;
5284 uint64_t dtime1 : 1;
5285 uint64_t reserved_15_18 : 4;
5286 uint64_t c0_aeri : 1;
5287 uint64_t crs0_er : 1;
5288 uint64_t c0_se : 1;
5289 uint64_t crs0_dr : 1;
5290 uint64_t c0_wake : 1;
5291 uint64_t c0_pmei : 1;
5292 uint64_t c0_hpint : 1;
5293 uint64_t c1_aeri : 1;
5294 uint64_t crs1_er : 1;
5295 uint64_t c1_se : 1;
5296 uint64_t crs1_dr : 1;
5297 uint64_t c1_wake : 1;
5298 uint64_t c1_pmei : 1;
5299 uint64_t c1_hpint : 1;
5300 uint64_t c0_up_b0 : 1;
5301 uint64_t c0_up_b1 : 1;
5302 uint64_t c0_up_b2 : 1;
5303 uint64_t c0_up_wi : 1;
5304 uint64_t c0_up_bx : 1;
5305 uint64_t c0_un_b0 : 1;
5306 uint64_t c0_un_b1 : 1;
5307 uint64_t c0_un_b2 : 1;
5308 uint64_t c0_un_wi : 1;
5309 uint64_t c0_un_bx : 1;
5310 uint64_t c1_up_b0 : 1;
5311 uint64_t c1_up_b1 : 1;
5312 uint64_t c1_up_b2 : 1;
5313 uint64_t c1_up_wi : 1;
5314 uint64_t c1_up_bx : 1;
5315 uint64_t c1_un_b0 : 1;
5316 uint64_t c1_un_b1 : 1;
5317 uint64_t c1_un_b2 : 1;
5318 uint64_t c1_un_wi : 1;
5319 uint64_t c1_un_bx : 1;
5320 uint64_t c0_un_wf : 1;
5321 uint64_t c1_un_wf : 1;
5322 uint64_t c0_up_wf : 1;
5323 uint64_t c1_up_wf : 1;
5324 uint64_t c0_exc : 1;
5325 uint64_t c1_exc : 1;
5326 uint64_t c0_ldwn : 1;
5327 uint64_t c1_ldwn : 1;
5328 uint64_t int_a : 1;
5329 uint64_t reserved_62_62 : 1;
5330 uint64_t mio_inta : 1;
5331 #endif
5332 } s;
5333 struct cvmx_npei_int_sum2_s cn52xx;
5334 struct cvmx_npei_int_sum2_s cn52xxp1;
5335 struct cvmx_npei_int_sum2_s cn56xx;
5336 };
5337 typedef union cvmx_npei_int_sum2 cvmx_npei_int_sum2_t;
5338
5339 /**
5340 * cvmx_npei_last_win_rdata0
5341 *
5342 * NPEI_LAST_WIN_RDATA0 = NPEI Last Window Read Data Port0
5343 *
5344 * The data from the last initiated window read.
5345 */
5346 union cvmx_npei_last_win_rdata0 {
5347 uint64_t u64;
5348 struct cvmx_npei_last_win_rdata0_s {
5349 #ifdef __BIG_ENDIAN_BITFIELD
5350 uint64_t data : 64; /**< Last window read data. */
5351 #else
5352 uint64_t data : 64;
5353 #endif
5354 } s;
5355 struct cvmx_npei_last_win_rdata0_s cn52xx;
5356 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
5357 struct cvmx_npei_last_win_rdata0_s cn56xx;
5358 struct cvmx_npei_last_win_rdata0_s cn56xxp1;
5359 };
5360 typedef union cvmx_npei_last_win_rdata0 cvmx_npei_last_win_rdata0_t;
5361
5362 /**
5363 * cvmx_npei_last_win_rdata1
5364 *
5365 * NPEI_LAST_WIN_RDATA1 = NPEI Last Window Read Data Port1
5366 *
5367 * The data from the last initiated window read.
5368 */
5369 union cvmx_npei_last_win_rdata1 {
5370 uint64_t u64;
5371 struct cvmx_npei_last_win_rdata1_s {
5372 #ifdef __BIG_ENDIAN_BITFIELD
5373 uint64_t data : 64; /**< Last window read data. */
5374 #else
5375 uint64_t data : 64;
5376 #endif
5377 } s;
5378 struct cvmx_npei_last_win_rdata1_s cn52xx;
5379 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
5380 struct cvmx_npei_last_win_rdata1_s cn56xx;
5381 struct cvmx_npei_last_win_rdata1_s cn56xxp1;
5382 };
5383 typedef union cvmx_npei_last_win_rdata1 cvmx_npei_last_win_rdata1_t;
5384
5385 /**
5386 * cvmx_npei_mem_access_ctl
5387 *
5388 * NPEI_MEM_ACCESS_CTL = NPEI's Memory Access Control
5389 *
5390 * Contains control for access to the PCIe address space.
5391 */
5392 union cvmx_npei_mem_access_ctl {
5393 uint64_t u64;
5394 struct cvmx_npei_mem_access_ctl_s {
5395 #ifdef __BIG_ENDIAN_BITFIELD
5396 uint64_t reserved_14_63 : 50;
5397 uint64_t max_word : 4; /**< The maximum number of words to merge into a single
5398 write operation from the PPs to the PCIe. Legal
5399 values are 1 to 16, where a '0' is treated as 16. */
5400 uint64_t timer : 10; /**< When the NPEI starts a PP to PCIe write it waits
5401 no longer than the value of TIMER in eclks to
5402 merge additional writes from the PPs into 1
5403 large write. The values for this field is 1 to
5404 1024 where a value of '0' is treated as 1024. */
5405 #else
5406 uint64_t timer : 10;
5407 uint64_t max_word : 4;
5408 uint64_t reserved_14_63 : 50;
5409 #endif
5410 } s;
5411 struct cvmx_npei_mem_access_ctl_s cn52xx;
5412 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
5413 struct cvmx_npei_mem_access_ctl_s cn56xx;
5414 struct cvmx_npei_mem_access_ctl_s cn56xxp1;
5415 };
5416 typedef union cvmx_npei_mem_access_ctl cvmx_npei_mem_access_ctl_t;
5417
5418 /**
5419 * cvmx_npei_mem_access_subid#
5420 *
5421 * NPEI_MEM_ACCESS_SUBIDX = NPEI Memory Access SubidX Register
5422 *
5423 * Contains address index and control bits for access to memory from Core PPs.
5424 */
5425 union cvmx_npei_mem_access_subidx {
5426 uint64_t u64;
5427 struct cvmx_npei_mem_access_subidx_s {
5428 #ifdef __BIG_ENDIAN_BITFIELD
5429 uint64_t reserved_42_63 : 22;
5430 uint64_t zero : 1; /**< Causes all byte reads to be zero length reads.
5431 Returns to the EXEC a zero for all read data. */
5432 uint64_t port : 2; /**< Port the request is sent to. */
5433 uint64_t nmerge : 1; /**< No merging is allowed in this window. */
5434 uint64_t esr : 2; /**< Endian-swap for Reads. */
5435 uint64_t esw : 2; /**< Endian-swap for Writes. */
5436 uint64_t nsr : 1; /**< No Snoop for Reads. */
5437 uint64_t nsw : 1; /**< No Snoop for Writes. */
5438 uint64_t ror : 1; /**< Relaxed Ordering for Reads. */
5439 uint64_t row : 1; /**< Relaxed Ordering for Writes. */
5440 uint64_t ba : 30; /**< PCIe Adddress Bits <63:34>. */
5441 #else
5442 uint64_t ba : 30;
5443 uint64_t row : 1;
5444 uint64_t ror : 1;
5445 uint64_t nsw : 1;
5446 uint64_t nsr : 1;
5447 uint64_t esw : 2;
5448 uint64_t esr : 2;
5449 uint64_t nmerge : 1;
5450 uint64_t port : 2;
5451 uint64_t zero : 1;
5452 uint64_t reserved_42_63 : 22;
5453 #endif
5454 } s;
5455 struct cvmx_npei_mem_access_subidx_s cn52xx;
5456 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
5457 struct cvmx_npei_mem_access_subidx_s cn56xx;
5458 struct cvmx_npei_mem_access_subidx_s cn56xxp1;
5459 };
5460 typedef union cvmx_npei_mem_access_subidx cvmx_npei_mem_access_subidx_t;
5461
5462 /**
5463 * cvmx_npei_msi_enb0
5464 *
5465 * NPEI_MSI_ENB0 = NPEI MSI Enable0
5466 *
5467 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0.
5468 */
5469 union cvmx_npei_msi_enb0 {
5470 uint64_t u64;
5471 struct cvmx_npei_msi_enb0_s {
5472 #ifdef __BIG_ENDIAN_BITFIELD
5473 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV0. */
5474 #else
5475 uint64_t enb : 64;
5476 #endif
5477 } s;
5478 struct cvmx_npei_msi_enb0_s cn52xx;
5479 struct cvmx_npei_msi_enb0_s cn52xxp1;
5480 struct cvmx_npei_msi_enb0_s cn56xx;
5481 struct cvmx_npei_msi_enb0_s cn56xxp1;
5482 };
5483 typedef union cvmx_npei_msi_enb0 cvmx_npei_msi_enb0_t;
5484
5485 /**
5486 * cvmx_npei_msi_enb1
5487 *
5488 * NPEI_MSI_ENB1 = NPEI MSI Enable1
5489 *
5490 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1.
5491 */
5492 union cvmx_npei_msi_enb1 {
5493 uint64_t u64;
5494 struct cvmx_npei_msi_enb1_s {
5495 #ifdef __BIG_ENDIAN_BITFIELD
5496 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV1. */
5497 #else
5498 uint64_t enb : 64;
5499 #endif
5500 } s;
5501 struct cvmx_npei_msi_enb1_s cn52xx;
5502 struct cvmx_npei_msi_enb1_s cn52xxp1;
5503 struct cvmx_npei_msi_enb1_s cn56xx;
5504 struct cvmx_npei_msi_enb1_s cn56xxp1;
5505 };
5506 typedef union cvmx_npei_msi_enb1 cvmx_npei_msi_enb1_t;
5507
5508 /**
5509 * cvmx_npei_msi_enb2
5510 *
5511 * NPEI_MSI_ENB2 = NPEI MSI Enable2
5512 *
5513 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2.
5514 */
5515 union cvmx_npei_msi_enb2 {
5516 uint64_t u64;
5517 struct cvmx_npei_msi_enb2_s {
5518 #ifdef __BIG_ENDIAN_BITFIELD
5519 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV2. */
5520 #else
5521 uint64_t enb : 64;
5522 #endif
5523 } s;
5524 struct cvmx_npei_msi_enb2_s cn52xx;
5525 struct cvmx_npei_msi_enb2_s cn52xxp1;
5526 struct cvmx_npei_msi_enb2_s cn56xx;
5527 struct cvmx_npei_msi_enb2_s cn56xxp1;
5528 };
5529 typedef union cvmx_npei_msi_enb2 cvmx_npei_msi_enb2_t;
5530
5531 /**
5532 * cvmx_npei_msi_enb3
5533 *
5534 * NPEI_MSI_ENB3 = NPEI MSI Enable3
5535 *
5536 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3.
5537 */
5538 union cvmx_npei_msi_enb3 {
5539 uint64_t u64;
5540 struct cvmx_npei_msi_enb3_s {
5541 #ifdef __BIG_ENDIAN_BITFIELD
5542 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV3. */
5543 #else
5544 uint64_t enb : 64;
5545 #endif
5546 } s;
5547 struct cvmx_npei_msi_enb3_s cn52xx;
5548 struct cvmx_npei_msi_enb3_s cn52xxp1;
5549 struct cvmx_npei_msi_enb3_s cn56xx;
5550 struct cvmx_npei_msi_enb3_s cn56xxp1;
5551 };
5552 typedef union cvmx_npei_msi_enb3 cvmx_npei_msi_enb3_t;
5553
5554 /**
5555 * cvmx_npei_msi_rcv0
5556 *
5557 * NPEI_MSI_RCV0 = NPEI MSI Receive0
5558 *
5559 * Contains bits [63:0] of the 256 bits oof MSI interrupts.
5560 */
5561 union cvmx_npei_msi_rcv0 {
5562 uint64_t u64;
5563 struct cvmx_npei_msi_rcv0_s {
5564 #ifdef __BIG_ENDIAN_BITFIELD
5565 uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
5566 #else
5567 uint64_t intr : 64;
5568 #endif
5569 } s;
5570 struct cvmx_npei_msi_rcv0_s cn52xx;
5571 struct cvmx_npei_msi_rcv0_s cn52xxp1;
5572 struct cvmx_npei_msi_rcv0_s cn56xx;
5573 struct cvmx_npei_msi_rcv0_s cn56xxp1;
5574 };
5575 typedef union cvmx_npei_msi_rcv0 cvmx_npei_msi_rcv0_t;
5576
5577 /**
5578 * cvmx_npei_msi_rcv1
5579 *
5580 * NPEI_MSI_RCV1 = NPEI MSI Receive1
5581 *
5582 * Contains bits [127:64] of the 256 bits oof MSI interrupts.
5583 */
5584 union cvmx_npei_msi_rcv1 {
5585 uint64_t u64;
5586 struct cvmx_npei_msi_rcv1_s {
5587 #ifdef __BIG_ENDIAN_BITFIELD
5588 uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
5589 #else
5590 uint64_t intr : 64;
5591 #endif
5592 } s;
5593 struct cvmx_npei_msi_rcv1_s cn52xx;
5594 struct cvmx_npei_msi_rcv1_s cn52xxp1;
5595 struct cvmx_npei_msi_rcv1_s cn56xx;
5596 struct cvmx_npei_msi_rcv1_s cn56xxp1;
5597 };
5598 typedef union cvmx_npei_msi_rcv1 cvmx_npei_msi_rcv1_t;
5599
5600 /**
5601 * cvmx_npei_msi_rcv2
5602 *
5603 * NPEI_MSI_RCV2 = NPEI MSI Receive2
5604 *
5605 * Contains bits [191:128] of the 256 bits oof MSI interrupts.
5606 */
5607 union cvmx_npei_msi_rcv2 {
5608 uint64_t u64;
5609 struct cvmx_npei_msi_rcv2_s {
5610 #ifdef __BIG_ENDIAN_BITFIELD
5611 uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
5612 #else
5613 uint64_t intr : 64;
5614 #endif
5615 } s;
5616 struct cvmx_npei_msi_rcv2_s cn52xx;
5617 struct cvmx_npei_msi_rcv2_s cn52xxp1;
5618 struct cvmx_npei_msi_rcv2_s cn56xx;
5619 struct cvmx_npei_msi_rcv2_s cn56xxp1;
5620 };
5621 typedef union cvmx_npei_msi_rcv2 cvmx_npei_msi_rcv2_t;
5622
5623 /**
5624 * cvmx_npei_msi_rcv3
5625 *
5626 * NPEI_MSI_RCV3 = NPEI MSI Receive3
5627 *
5628 * Contains bits [255:192] of the 256 bits oof MSI interrupts.
5629 */
5630 union cvmx_npei_msi_rcv3 {
5631 uint64_t u64;
5632 struct cvmx_npei_msi_rcv3_s {
5633 #ifdef __BIG_ENDIAN_BITFIELD
5634 uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
5635 #else
5636 uint64_t intr : 64;
5637 #endif
5638 } s;
5639 struct cvmx_npei_msi_rcv3_s cn52xx;
5640 struct cvmx_npei_msi_rcv3_s cn52xxp1;
5641 struct cvmx_npei_msi_rcv3_s cn56xx;
5642 struct cvmx_npei_msi_rcv3_s cn56xxp1;
5643 };
5644 typedef union cvmx_npei_msi_rcv3 cvmx_npei_msi_rcv3_t;
5645
5646 /**
5647 * cvmx_npei_msi_rd_map
5648 *
5649 * NPEI_MSI_RD_MAP = NPEI MSI Read MAP
5650 *
5651 * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
5652 */
5653 union cvmx_npei_msi_rd_map {
5654 uint64_t u64;
5655 struct cvmx_npei_msi_rd_map_s {
5656 #ifdef __BIG_ENDIAN_BITFIELD
5657 uint64_t reserved_16_63 : 48;
5658 uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY
5659 written to the MSI_INT field of this register. */
5660 uint64_t msi_int : 8; /**< Selects the value that would be received when the
5661 NPEI_PCIE_MSI_RCV register is written. */
5662 #else
5663 uint64_t msi_int : 8;
5664 uint64_t rd_int : 8;
5665 uint64_t reserved_16_63 : 48;
5666 #endif
5667 } s;
5668 struct cvmx_npei_msi_rd_map_s cn52xx;
5669 struct cvmx_npei_msi_rd_map_s cn52xxp1;
5670 struct cvmx_npei_msi_rd_map_s cn56xx;
5671 struct cvmx_npei_msi_rd_map_s cn56xxp1;
5672 };
5673 typedef union cvmx_npei_msi_rd_map cvmx_npei_msi_rd_map_t;
5674
5675 /**
5676 * cvmx_npei_msi_w1c_enb0
5677 *
5678 * NPEI_MSI_W1C_ENB0 = NPEI MSI Write 1 To Clear Enable0
5679 *
5680 * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register.
5681 */
5682 union cvmx_npei_msi_w1c_enb0 {
5683 uint64_t u64;
5684 struct cvmx_npei_msi_w1c_enb0_s {
5685 #ifdef __BIG_ENDIAN_BITFIELD
5686 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5687 cooresponding bit in NPEI_MSI_ENB0.
5688 A read to this address will return 0. */
5689 #else
5690 uint64_t clr : 64;
5691 #endif
5692 } s;
5693 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
5694 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
5695 };
5696 typedef union cvmx_npei_msi_w1c_enb0 cvmx_npei_msi_w1c_enb0_t;
5697
5698 /**
5699 * cvmx_npei_msi_w1c_enb1
5700 *
5701 * NPEI_MSI_W1C_ENB1 = NPEI MSI Write 1 To Clear Enable1
5702 *
5703 * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register.
5704 */
5705 union cvmx_npei_msi_w1c_enb1 {
5706 uint64_t u64;
5707 struct cvmx_npei_msi_w1c_enb1_s {
5708 #ifdef __BIG_ENDIAN_BITFIELD
5709 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5710 cooresponding bit in NPEI_MSI_ENB1.
5711 A read to this address will return 0. */
5712 #else
5713 uint64_t clr : 64;
5714 #endif
5715 } s;
5716 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
5717 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
5718 };
5719 typedef union cvmx_npei_msi_w1c_enb1 cvmx_npei_msi_w1c_enb1_t;
5720
5721 /**
5722 * cvmx_npei_msi_w1c_enb2
5723 *
5724 * NPEI_MSI_W1C_ENB2 = NPEI MSI Write 1 To Clear Enable2
5725 *
5726 * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register.
5727 */
5728 union cvmx_npei_msi_w1c_enb2 {
5729 uint64_t u64;
5730 struct cvmx_npei_msi_w1c_enb2_s {
5731 #ifdef __BIG_ENDIAN_BITFIELD
5732 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5733 cooresponding bit in NPEI_MSI_ENB2.
5734 A read to this address will return 0. */
5735 #else
5736 uint64_t clr : 64;
5737 #endif
5738 } s;
5739 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
5740 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
5741 };
5742 typedef union cvmx_npei_msi_w1c_enb2 cvmx_npei_msi_w1c_enb2_t;
5743
5744 /**
5745 * cvmx_npei_msi_w1c_enb3
5746 *
5747 * NPEI_MSI_W1C_ENB3 = NPEI MSI Write 1 To Clear Enable3
5748 *
5749 * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register.
5750 */
5751 union cvmx_npei_msi_w1c_enb3 {
5752 uint64_t u64;
5753 struct cvmx_npei_msi_w1c_enb3_s {
5754 #ifdef __BIG_ENDIAN_BITFIELD
5755 uint64_t clr : 64; /**< A write of '1' to a vector will clear the
5756 cooresponding bit in NPEI_MSI_ENB3.
5757 A read to this address will return 0. */
5758 #else
5759 uint64_t clr : 64;
5760 #endif
5761 } s;
5762 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
5763 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
5764 };
5765 typedef union cvmx_npei_msi_w1c_enb3 cvmx_npei_msi_w1c_enb3_t;
5766
5767 /**
5768 * cvmx_npei_msi_w1s_enb0
5769 *
5770 * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable0
5771 *
5772 * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register.
5773 */
5774 union cvmx_npei_msi_w1s_enb0 {
5775 uint64_t u64;
5776 struct cvmx_npei_msi_w1s_enb0_s {
5777 #ifdef __BIG_ENDIAN_BITFIELD
5778 uint64_t set : 64; /**< A write of '1' to a vector will set the
5779 cooresponding bit in NPEI_MSI_ENB0.
5780 A read to this address will return 0. */
5781 #else
5782 uint64_t set : 64;
5783 #endif
5784 } s;
5785 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
5786 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
5787 };
5788 typedef union cvmx_npei_msi_w1s_enb0 cvmx_npei_msi_w1s_enb0_t;
5789
5790 /**
5791 * cvmx_npei_msi_w1s_enb1
5792 *
5793 * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable1
5794 *
5795 * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register.
5796 */
5797 union cvmx_npei_msi_w1s_enb1 {
5798 uint64_t u64;
5799 struct cvmx_npei_msi_w1s_enb1_s {
5800 #ifdef __BIG_ENDIAN_BITFIELD
5801 uint64_t set : 64; /**< A write of '1' to a vector will set the
5802 cooresponding bit in NPEI_MSI_ENB1.
5803 A read to this address will return 0. */
5804 #else
5805 uint64_t set : 64;
5806 #endif
5807 } s;
5808 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
5809 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
5810 };
5811 typedef union cvmx_npei_msi_w1s_enb1 cvmx_npei_msi_w1s_enb1_t;
5812
5813 /**
5814 * cvmx_npei_msi_w1s_enb2
5815 *
5816 * NPEI_MSI_W1S_ENB2 = NPEI MSI Write 1 To Set Enable2
5817 *
5818 * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register.
5819 */
5820 union cvmx_npei_msi_w1s_enb2 {
5821 uint64_t u64;
5822 struct cvmx_npei_msi_w1s_enb2_s {
5823 #ifdef __BIG_ENDIAN_BITFIELD
5824 uint64_t set : 64; /**< A write of '1' to a vector will set the
5825 cooresponding bit in NPEI_MSI_ENB2.
5826 A read to this address will return 0. */
5827 #else
5828 uint64_t set : 64;
5829 #endif
5830 } s;
5831 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
5832 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
5833 };
5834 typedef union cvmx_npei_msi_w1s_enb2 cvmx_npei_msi_w1s_enb2_t;
5835
5836 /**
5837 * cvmx_npei_msi_w1s_enb3
5838 *
5839 * NPEI_MSI_W1S_ENB3 = NPEI MSI Write 1 To Set Enable3
5840 *
5841 * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register.
5842 */
5843 union cvmx_npei_msi_w1s_enb3 {
5844 uint64_t u64;
5845 struct cvmx_npei_msi_w1s_enb3_s {
5846 #ifdef __BIG_ENDIAN_BITFIELD
5847 uint64_t set : 64; /**< A write of '1' to a vector will set the
5848 cooresponding bit in NPEI_MSI_ENB3.
5849 A read to this address will return 0. */
5850 #else
5851 uint64_t set : 64;
5852 #endif
5853 } s;
5854 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
5855 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
5856 };
5857 typedef union cvmx_npei_msi_w1s_enb3 cvmx_npei_msi_w1s_enb3_t;
5858
5859 /**
5860 * cvmx_npei_msi_wr_map
5861 *
5862 * NPEI_MSI_WR_MAP = NPEI MSI Write MAP
5863 *
5864 * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
5865 */
5866 union cvmx_npei_msi_wr_map {
5867 uint64_t u64;
5868 struct cvmx_npei_msi_wr_map_s {
5869 #ifdef __BIG_ENDIAN_BITFIELD
5870 uint64_t reserved_16_63 : 48;
5871 uint64_t ciu_int : 8; /**< Selects which bit in the NPEI_MSI_RCV# (0-255)
5872 will be set when the value specified in the
5873 MSI_INT of this register is recevied during a
5874 write to the NPEI_PCIE_MSI_RCV register. */
5875 uint64_t msi_int : 8; /**< Selects the value that would be received when the
5876 NPEI_PCIE_MSI_RCV register is written. */
5877 #else
5878 uint64_t msi_int : 8;
5879 uint64_t ciu_int : 8;
5880 uint64_t reserved_16_63 : 48;
5881 #endif
5882 } s;
5883 struct cvmx_npei_msi_wr_map_s cn52xx;
5884 struct cvmx_npei_msi_wr_map_s cn52xxp1;
5885 struct cvmx_npei_msi_wr_map_s cn56xx;
5886 struct cvmx_npei_msi_wr_map_s cn56xxp1;
5887 };
5888 typedef union cvmx_npei_msi_wr_map cvmx_npei_msi_wr_map_t;
5889
5890 /**
5891 * cvmx_npei_pcie_credit_cnt
5892 *
5893 * NPEI_PCIE_CREDIT_CNT = NPEI PCIE Credit Count
5894 *
5895 * Contains the number of credits for the pcie port FIFOs used by the NPEI. This value needs to be set BEFORE PCIe traffic
5896 * flow from NPEI to PCIE Ports starts. A write to this register will cause the credit counts in the NPEI for the two
5897 * PCIE ports to be reset to the value in this register.
5898 */
5899 union cvmx_npei_pcie_credit_cnt {
5900 uint64_t u64;
5901 struct cvmx_npei_pcie_credit_cnt_s {
5902 #ifdef __BIG_ENDIAN_BITFIELD
5903 uint64_t reserved_48_63 : 16;
5904 uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits.
5905 Legal values are 0x25 to 0x80. */
5906 uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits.
5907 Legal values are 0x5 to 0x10. */
5908 uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits.
5909 Legal values are 0x25 to 0x80. */
5910 uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits.
5911 Legal values are 0x25 to 0x80. */
5912 uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits.
5913 Legal values are 0x5 to 0x10. */
5914 uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits.
5915 Legal values are 0x25 to 0x80. */
5916 #else
5917 uint64_t p0_pcnt : 8;
5918 uint64_t p0_ncnt : 8;
5919 uint64_t p0_ccnt : 8;
5920 uint64_t p1_pcnt : 8;
5921 uint64_t p1_ncnt : 8;
5922 uint64_t p1_ccnt : 8;
5923 uint64_t reserved_48_63 : 16;
5924 #endif
5925 } s;
5926 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
5927 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
5928 };
5929 typedef union cvmx_npei_pcie_credit_cnt cvmx_npei_pcie_credit_cnt_t;
5930
5931 /**
5932 * cvmx_npei_pcie_msi_rcv
5933 *
5934 * NPEI_PCIE_MSI_RCV = NPEI PCIe MSI Receive
5935 *
5936 * Register where MSI writes are directed from the PCIe.
5937 */
5938 union cvmx_npei_pcie_msi_rcv {
5939 uint64_t u64;
5940 struct cvmx_npei_pcie_msi_rcv_s {
5941 #ifdef __BIG_ENDIAN_BITFIELD
5942 uint64_t reserved_8_63 : 56;
5943 uint64_t intr : 8; /**< A write to this register will result in a bit in
5944 one of the NPEI_MSI_RCV# registers being set.
5945 Which bit is set is dependent on the previously
5946 written using the NPEI_MSI_WR_MAP register or if
5947 not previously written the reset value of the MAP. */
5948 #else
5949 uint64_t intr : 8;
5950 uint64_t reserved_8_63 : 56;
5951 #endif
5952 } s;
5953 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
5954 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
5955 struct cvmx_npei_pcie_msi_rcv_s cn56xx;
5956 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
5957 };
5958 typedef union cvmx_npei_pcie_msi_rcv cvmx_npei_pcie_msi_rcv_t;
5959
5960 /**
5961 * cvmx_npei_pcie_msi_rcv_b1
5962 *
5963 * NPEI_PCIE_MSI_RCV_B1 = NPEI PCIe MSI Receive Byte 1
5964 *
5965 * Register where MSI writes are directed from the PCIe.
5966 */
5967 union cvmx_npei_pcie_msi_rcv_b1 {
5968 uint64_t u64;
5969 struct cvmx_npei_pcie_msi_rcv_b1_s {
5970 #ifdef __BIG_ENDIAN_BITFIELD
5971 uint64_t reserved_16_63 : 48;
5972 uint64_t intr : 8; /**< A write to this register will result in a bit in
5973 one of the NPEI_MSI_RCV# registers being set.
5974 Which bit is set is dependent on the previously
5975 written using the NPEI_MSI_WR_MAP register or if
5976 not previously written the reset value of the MAP. */
5977 uint64_t reserved_0_7 : 8;
5978 #else
5979 uint64_t reserved_0_7 : 8;
5980 uint64_t intr : 8;
5981 uint64_t reserved_16_63 : 48;
5982 #endif
5983 } s;
5984 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
5985 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
5986 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
5987 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
5988 };
5989 typedef union cvmx_npei_pcie_msi_rcv_b1 cvmx_npei_pcie_msi_rcv_b1_t;
5990
5991 /**
5992 * cvmx_npei_pcie_msi_rcv_b2
5993 *
5994 * NPEI_PCIE_MSI_RCV_B2 = NPEI PCIe MSI Receive Byte 2
5995 *
5996 * Register where MSI writes are directed from the PCIe.
5997 */
5998 union cvmx_npei_pcie_msi_rcv_b2 {
5999 uint64_t u64;
6000 struct cvmx_npei_pcie_msi_rcv_b2_s {
6001 #ifdef __BIG_ENDIAN_BITFIELD
6002 uint64_t reserved_24_63 : 40;
6003 uint64_t intr : 8; /**< A write to this register will result in a bit in
6004 one of the NPEI_MSI_RCV# registers being set.
6005 Which bit is set is dependent on the previously
6006 written using the NPEI_MSI_WR_MAP register or if
6007 not previously written the reset value of the MAP. */
6008 uint64_t reserved_0_15 : 16;
6009 #else
6010 uint64_t reserved_0_15 : 16;
6011 uint64_t intr : 8;
6012 uint64_t reserved_24_63 : 40;
6013 #endif
6014 } s;
6015 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
6016 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
6017 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
6018 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
6019 };
6020 typedef union cvmx_npei_pcie_msi_rcv_b2 cvmx_npei_pcie_msi_rcv_b2_t;
6021
6022 /**
6023 * cvmx_npei_pcie_msi_rcv_b3
6024 *
6025 * NPEI_PCIE_MSI_RCV_B3 = NPEI PCIe MSI Receive Byte 3
6026 *
6027 * Register where MSI writes are directed from the PCIe.
6028 */
6029 union cvmx_npei_pcie_msi_rcv_b3 {
6030 uint64_t u64;
6031 struct cvmx_npei_pcie_msi_rcv_b3_s {
6032 #ifdef __BIG_ENDIAN_BITFIELD
6033 uint64_t reserved_32_63 : 32;
6034 uint64_t intr : 8; /**< A write to this register will result in a bit in
6035 one of the NPEI_MSI_RCV# registers being set.
6036 Which bit is set is dependent on the previously
6037 written using the NPEI_MSI_WR_MAP register or if
6038 not previously written the reset value of the MAP. */
6039 uint64_t reserved_0_23 : 24;
6040 #else
6041 uint64_t reserved_0_23 : 24;
6042 uint64_t intr : 8;
6043 uint64_t reserved_32_63 : 32;
6044 #endif
6045 } s;
6046 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
6047 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
6048 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
6049 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
6050 };
6051 typedef union cvmx_npei_pcie_msi_rcv_b3 cvmx_npei_pcie_msi_rcv_b3_t;
6052
6053 /**
6054 * cvmx_npei_pkt#_cnts
6055 *
6056 * NPEI_PKT[0..31]_CNTS = NPEI Packet ring# Counts
6057 *
6058 * The counters for output rings.
6059 */
6060 union cvmx_npei_pktx_cnts {
6061 uint64_t u64;
6062 struct cvmx_npei_pktx_cnts_s {
6063 #ifdef __BIG_ENDIAN_BITFIELD
6064 uint64_t reserved_54_63 : 10;
6065 uint64_t timer : 22; /**< Timer incremented every 1024 core clocks
6066 when NPEI_PKTS#_CNTS[CNT] is non zero. Field
6067 cleared when NPEI_PKTS#_CNTS[CNT] goes to 0.
6068 Field is also cleared when NPEI_PKT_TIME_INT is
6069 cleared.
6070 The first increment of this count can occur
6071 between 0 to 1023 core clocks. */
6072 uint64_t cnt : 32; /**< ring counter. This field is incremented as
6073 packets are sent out and decremented in response to
6074 writes to this field.
6075 When NPEI_PKT_OUT_BMODE is '0' a value of 1 is
6076 added to the register for each packet, when '1'
6077 and the info-pointer is NOT used the length of the
6078 packet plus 8 is added, when '1' and info-pointer
6079 mode IS used the packet length is added to this
6080 field. */
6081 #else
6082 uint64_t cnt : 32;
6083 uint64_t timer : 22;
6084 uint64_t reserved_54_63 : 10;
6085 #endif
6086 } s;
6087 struct cvmx_npei_pktx_cnts_s cn52xx;
6088 struct cvmx_npei_pktx_cnts_s cn56xx;
6089 };
6090 typedef union cvmx_npei_pktx_cnts cvmx_npei_pktx_cnts_t;
6091
6092 /**
6093 * cvmx_npei_pkt#_in_bp
6094 *
6095 * NPEI_PKT[0..31]_IN_BP = NPEI Packet ring# Input Backpressure
6096 *
6097 * The counters and thresholds for input packets to apply backpressure to processing of the packets.
6098 */
6099 union cvmx_npei_pktx_in_bp {
6100 uint64_t u64;
6101 struct cvmx_npei_pktx_in_bp_s {
6102 #ifdef __BIG_ENDIAN_BITFIELD
6103 uint64_t wmark : 32; /**< When CNT is greater than this threshold no more
6104 packets will be processed for this ring.
6105 When writing this field of the NPEI_PKT#_IN_BP
6106 register, use a 4-byte write so as to not write
6107 any other field of this register. */
6108 uint64_t cnt : 32; /**< ring counter. This field is incremented by one
6109 whenever OCTEON receives, buffers, and creates a
6110 work queue entry for a packet that arrives by the
6111 cooresponding input ring. A write to this field
6112 will be subtracted from the field value.
6113 When writing this field of the NPEI_PKT#_IN_BP
6114 register, use a 4-byte write so as to not write
6115 any other field of this register. */
6116 #else
6117 uint64_t cnt : 32;
6118 uint64_t wmark : 32;
6119 #endif
6120 } s;
6121 struct cvmx_npei_pktx_in_bp_s cn52xx;
6122 struct cvmx_npei_pktx_in_bp_s cn56xx;
6123 };
6124 typedef union cvmx_npei_pktx_in_bp cvmx_npei_pktx_in_bp_t;
6125
6126 /**
6127 * cvmx_npei_pkt#_instr_baddr
6128 *
6129 * NPEI_PKT[0..31]_INSTR_BADDR = NPEI Packet ring# Instruction Base Address
6130 *
6131 * Start of Instruction for input packets.
6132 */
6133 union cvmx_npei_pktx_instr_baddr {
6134 uint64_t u64;
6135 struct cvmx_npei_pktx_instr_baddr_s {
6136 #ifdef __BIG_ENDIAN_BITFIELD
6137 uint64_t addr : 61; /**< Base address for Instructions. */
6138 uint64_t reserved_0_2 : 3;
6139 #else
6140 uint64_t reserved_0_2 : 3;
6141 uint64_t addr : 61;
6142 #endif
6143 } s;
6144 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
6145 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
6146 };
6147 typedef union cvmx_npei_pktx_instr_baddr cvmx_npei_pktx_instr_baddr_t;
6148
6149 /**
6150 * cvmx_npei_pkt#_instr_baoff_dbell
6151 *
6152 * NPEI_PKT[0..31]_INSTR_BAOFF_DBELL = NPEI Packet ring# Instruction Base Address Offset and Doorbell
6153 *
6154 * The doorbell and base address offset for next read.
6155 */
6156 union cvmx_npei_pktx_instr_baoff_dbell {
6157 uint64_t u64;
6158 struct cvmx_npei_pktx_instr_baoff_dbell_s {
6159 #ifdef __BIG_ENDIAN_BITFIELD
6160 uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR
6161 where the next instruction will be read. */
6162 uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field
6163 will increment the value here. Reads will return
6164 present value. A write of 0xffffffff will set the
6165 DBELL and AOFF fields to '0'. */
6166 #else
6167 uint64_t dbell : 32;
6168 uint64_t aoff : 32;
6169 #endif
6170 } s;
6171 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
6172 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
6173 };
6174 typedef union cvmx_npei_pktx_instr_baoff_dbell cvmx_npei_pktx_instr_baoff_dbell_t;
6175
6176 /**
6177 * cvmx_npei_pkt#_instr_fifo_rsize
6178 *
6179 * NPEI_PKT[0..31]_INSTR_FIFO_RSIZE = NPEI Packet ring# Instruction FIFO and Ring Size.
6180 *
6181 * Fifo field and ring size for Instructions.
6182 */
6183 union cvmx_npei_pktx_instr_fifo_rsize {
6184 uint64_t u64;
6185 struct cvmx_npei_pktx_instr_fifo_rsize_s {
6186 #ifdef __BIG_ENDIAN_BITFIELD
6187 uint64_t max : 9; /**< Max Fifo Size. */
6188 uint64_t rrp : 9; /**< Fifo read pointer. */
6189 uint64_t wrp : 9; /**< Fifo write pointer. */
6190 uint64_t fcnt : 5; /**< Fifo count. */
6191 uint64_t rsize : 32; /**< Instruction ring size. */
6192 #else
6193 uint64_t rsize : 32;
6194 uint64_t fcnt : 5;
6195 uint64_t wrp : 9;
6196 uint64_t rrp : 9;
6197 uint64_t max : 9;
6198 #endif
6199 } s;
6200 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
6201 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
6202 };
6203 typedef union cvmx_npei_pktx_instr_fifo_rsize cvmx_npei_pktx_instr_fifo_rsize_t;
6204
6205 /**
6206 * cvmx_npei_pkt#_instr_header
6207 *
6208 * NPEI_PKT[0..31]_INSTR_HEADER = NPEI Packet ring# Instruction Header.
6209 *
6210 * VAlues used to build input packet header.
6211 */
6212 union cvmx_npei_pktx_instr_header {
6213 uint64_t u64;
6214 struct cvmx_npei_pktx_instr_header_s {
6215 #ifdef __BIG_ENDIAN_BITFIELD
6216 uint64_t reserved_44_63 : 20;
6217 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
6218 uint64_t reserved_38_42 : 5;
6219 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
6220 uint64_t reserved_35_35 : 1;
6221 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
6222 uint64_t reserved_22_27 : 6;
6223 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
6224 as part of the packet data, regardless of the
6225 value of bit [63] of the instruction header.
6226 USE_IHDR must be set whenever PBP is set. */
6227 uint64_t reserved_16_20 : 5;
6228 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
6229 is not raw and PBP is not set. */
6230 uint64_t reserved_13_13 : 1;
6231 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
6232 is not raw and PBP is not set. */
6233 uint64_t reserved_0_5 : 6;
6234 #else
6235 uint64_t reserved_0_5 : 6;
6236 uint64_t skp_len : 7;
6237 uint64_t reserved_13_13 : 1;
6238 uint64_t par_mode : 2;
6239 uint64_t reserved_16_20 : 5;
6240 uint64_t use_ihdr : 1;
6241 uint64_t reserved_22_27 : 6;
6242 uint64_t rskp_len : 7;
6243 uint64_t reserved_35_35 : 1;
6244 uint64_t rparmode : 2;
6245 uint64_t reserved_38_42 : 5;
6246 uint64_t pbp : 1;
6247 uint64_t reserved_44_63 : 20;
6248 #endif
6249 } s;
6250 struct cvmx_npei_pktx_instr_header_s cn52xx;
6251 struct cvmx_npei_pktx_instr_header_s cn56xx;
6252 };
6253 typedef union cvmx_npei_pktx_instr_header cvmx_npei_pktx_instr_header_t;
6254
6255 /**
6256 * cvmx_npei_pkt#_slist_baddr
6257 *
6258 * NPEI_PKT[0..31]_SLIST_BADDR = NPEI Packet ring# Scatter List Base Address
6259 *
6260 * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
6261 */
6262 union cvmx_npei_pktx_slist_baddr {
6263 uint64_t u64;
6264 struct cvmx_npei_pktx_slist_baddr_s {
6265 #ifdef __BIG_ENDIAN_BITFIELD
6266 uint64_t addr : 60; /**< Base address for scatter list pointers. */
6267 uint64_t reserved_0_3 : 4;
6268 #else
6269 uint64_t reserved_0_3 : 4;
6270 uint64_t addr : 60;
6271 #endif
6272 } s;
6273 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
6274 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
6275 };
6276 typedef union cvmx_npei_pktx_slist_baddr cvmx_npei_pktx_slist_baddr_t;
6277
6278 /**
6279 * cvmx_npei_pkt#_slist_baoff_dbell
6280 *
6281 * NPEI_PKT[0..31]_SLIST_BAOFF_DBELL = NPEI Packet ring# Scatter List Base Address Offset and Doorbell
6282 *
6283 * The doorbell and base address offset for next read.
6284 */
6285 union cvmx_npei_pktx_slist_baoff_dbell {
6286 uint64_t u64;
6287 struct cvmx_npei_pktx_slist_baoff_dbell_s {
6288 #ifdef __BIG_ENDIAN_BITFIELD
6289 uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR
6290 where the next SList pointer will be read.
6291 A write of 0xFFFFFFFF to the DBELL field will
6292 clear DBELL and AOFF */
6293 uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field
6294 will increment the value here. Reads will return
6295 present value. The value of this field is
6296 decremented as read operations are ISSUED for
6297 scatter pointers.
6298 A write of 0xFFFFFFFF will clear DBELL and AOFF */
6299 #else
6300 uint64_t dbell : 32;
6301 uint64_t aoff : 32;
6302 #endif
6303 } s;
6304 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
6305 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
6306 };
6307 typedef union cvmx_npei_pktx_slist_baoff_dbell cvmx_npei_pktx_slist_baoff_dbell_t;
6308
6309 /**
6310 * cvmx_npei_pkt#_slist_fifo_rsize
6311 *
6312 * NPEI_PKT[0..31]_SLIST_FIFO_RSIZE = NPEI Packet ring# Scatter List FIFO and Ring Size.
6313 *
6314 * The number of scatter pointer pairs in the scatter list.
6315 */
6316 union cvmx_npei_pktx_slist_fifo_rsize {
6317 uint64_t u64;
6318 struct cvmx_npei_pktx_slist_fifo_rsize_s {
6319 #ifdef __BIG_ENDIAN_BITFIELD
6320 uint64_t reserved_32_63 : 32;
6321 uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in
6322 the scatter list ring. */
6323 #else
6324 uint64_t rsize : 32;
6325 uint64_t reserved_32_63 : 32;
6326 #endif
6327 } s;
6328 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
6329 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
6330 };
6331 typedef union cvmx_npei_pktx_slist_fifo_rsize cvmx_npei_pktx_slist_fifo_rsize_t;
6332
6333 /**
6334 * cvmx_npei_pkt_cnt_int
6335 *
6336 * NPEI_PKT_CNT_INT = NPI Packet Counter Interrupt
6337 *
6338 * The packets rings that are interrupting because of Packet Counters.
6339 */
6340 union cvmx_npei_pkt_cnt_int {
6341 uint64_t u64;
6342 struct cvmx_npei_pkt_cnt_int_s {
6343 #ifdef __BIG_ENDIAN_BITFIELD
6344 uint64_t reserved_32_63 : 32;
6345 uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when
6346 NPEI_PKT#_CNTS[CNT] is greater
6347 than NPEI_PKT_INT_LEVELS[CNT]. */
6348 #else
6349 uint64_t port : 32;
6350 uint64_t reserved_32_63 : 32;
6351 #endif
6352 } s;
6353 struct cvmx_npei_pkt_cnt_int_s cn52xx;
6354 struct cvmx_npei_pkt_cnt_int_s cn56xx;
6355 };
6356 typedef union cvmx_npei_pkt_cnt_int cvmx_npei_pkt_cnt_int_t;
6357
6358 /**
6359 * cvmx_npei_pkt_cnt_int_enb
6360 *
6361 * NPEI_PKT_CNT_INT_ENB = NPI Packet Counter Interrupt Enable
6362 *
6363 * Enable for the packets rings that are interrupting because of Packet Counters.
6364 */
6365 union cvmx_npei_pkt_cnt_int_enb {
6366 uint64_t u64;
6367 struct cvmx_npei_pkt_cnt_int_enb_s {
6368 #ifdef __BIG_ENDIAN_BITFIELD
6369 uint64_t reserved_32_63 : 32;
6370 uint64_t port : 32; /**< Bit vector cooresponding to ring number when set
6371 allows NPEI_PKT_CNT_INT to generate an interrupt. */
6372 #else
6373 uint64_t port : 32;
6374 uint64_t reserved_32_63 : 32;
6375 #endif
6376 } s;
6377 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
6378 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
6379 };
6380 typedef union cvmx_npei_pkt_cnt_int_enb cvmx_npei_pkt_cnt_int_enb_t;
6381
6382 /**
6383 * cvmx_npei_pkt_data_out_es
6384 *
6385 * NPEI_PKT_DATA_OUT_ES = NPEI's Packet Data Out Endian Swap
6386 *
6387 * The Endian Swap for writing Data Out.
6388 */
6389 union cvmx_npei_pkt_data_out_es {
6390 uint64_t u64;
6391 struct cvmx_npei_pkt_data_out_es_s {
6392 #ifdef __BIG_ENDIAN_BITFIELD
6393 uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31.
6394 Two bits are used per ring (i.e. ring 0 [1:0],
6395 ring 1 [3:2], ....). */
6396 #else
6397 uint64_t es : 64;
6398 #endif
6399 } s;
6400 struct cvmx_npei_pkt_data_out_es_s cn52xx;
6401 struct cvmx_npei_pkt_data_out_es_s cn56xx;
6402 };
6403 typedef union cvmx_npei_pkt_data_out_es cvmx_npei_pkt_data_out_es_t;
6404
6405 /**
6406 * cvmx_npei_pkt_data_out_ns
6407 *
6408 * NPEI_PKT_DATA_OUT_NS = NPEI's Packet Data Out No Snoop
6409 *
6410 * The NS field for the TLP when writing packet data.
6411 */
6412 union cvmx_npei_pkt_data_out_ns {
6413 uint64_t u64;
6414 struct cvmx_npei_pkt_data_out_ns_s {
6415 #ifdef __BIG_ENDIAN_BITFIELD
6416 uint64_t reserved_32_63 : 32;
6417 uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding
6418 to the Packet-ring will enable NS in TLP header. */
6419 #else
6420 uint64_t nsr : 32;
6421 uint64_t reserved_32_63 : 32;
6422 #endif
6423 } s;
6424 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
6425 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
6426 };
6427 typedef union cvmx_npei_pkt_data_out_ns cvmx_npei_pkt_data_out_ns_t;
6428
6429 /**
6430 * cvmx_npei_pkt_data_out_ror
6431 *
6432 * NPEI_PKT_DATA_OUT_ROR = NPEI's Packet Data Out Relaxed Ordering
6433 *
6434 * The ROR field for the TLP when writing Packet Data.
6435 */
6436 union cvmx_npei_pkt_data_out_ror {
6437 uint64_t u64;
6438 struct cvmx_npei_pkt_data_out_ror_s {
6439 #ifdef __BIG_ENDIAN_BITFIELD
6440 uint64_t reserved_32_63 : 32;
6441 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding
6442 to the Packet-ring will enable ROR in TLP header. */
6443 #else
6444 uint64_t ror : 32;
6445 uint64_t reserved_32_63 : 32;
6446 #endif
6447 } s;
6448 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
6449 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
6450 };
6451 typedef union cvmx_npei_pkt_data_out_ror cvmx_npei_pkt_data_out_ror_t;
6452
6453 /**
6454 * cvmx_npei_pkt_dpaddr
6455 *
6456 * NPEI_PKT_DPADDR = NPEI's Packet Data Pointer Addr
6457 *
6458 * Used to detemine address and attributes for packet data writes.
6459 */
6460 union cvmx_npei_pkt_dpaddr {
6461 uint64_t u64;
6462 struct cvmx_npei_pkt_dpaddr_s {
6463 #ifdef __BIG_ENDIAN_BITFIELD
6464 uint64_t reserved_32_63 : 32;
6465 uint64_t dptr : 32; /**< When asserted '1' the vector bit cooresponding
6466 to the Packet-ring will use:
6467 the address[63:60] to write packet data
6468 comes from the DPTR[63:60] in the scatter-list
6469 pair and the RO, NS, ES values come from the O0_ES,
6470 O0_NS, O0_RO. When '0' the RO == DPTR[60],
6471 NS == DPTR[61], ES == DPTR[63:62], the address the
6472 packet will be written to is ADDR[63:60] ==
6473 O0_ES[1:0], O0_NS, O0_RO. */
6474 #else
6475 uint64_t dptr : 32;
6476 uint64_t reserved_32_63 : 32;
6477 #endif
6478 } s;
6479 struct cvmx_npei_pkt_dpaddr_s cn52xx;
6480 struct cvmx_npei_pkt_dpaddr_s cn56xx;
6481 };
6482 typedef union cvmx_npei_pkt_dpaddr cvmx_npei_pkt_dpaddr_t;
6483
6484 /**
6485 * cvmx_npei_pkt_in_bp
6486 *
6487 * NPEI_PKT_IN_BP = NPEI Packet Input Backpressure
6488 *
6489 * Which input rings have backpressure applied.
6490 */
6491 union cvmx_npei_pkt_in_bp {
6492 uint64_t u64;
6493 struct cvmx_npei_pkt_in_bp_s {
6494 #ifdef __BIG_ENDIAN_BITFIELD
6495 uint64_t reserved_32_63 : 32;
6496 uint64_t bp : 32; /**< A packet input ring that has its count greater
6497 than its WMARK will have backpressure applied.
6498 Each of the 32 bits coorespond to an input ring.
6499 When '1' that ring has backpressure applied an
6500 will fetch no more instructions, but will process
6501 any previously fetched instructions. */
6502 #else
6503 uint64_t bp : 32;
6504 uint64_t reserved_32_63 : 32;
6505 #endif
6506 } s;
6507 struct cvmx_npei_pkt_in_bp_s cn52xx;
6508 struct cvmx_npei_pkt_in_bp_s cn56xx;
6509 };
6510 typedef union cvmx_npei_pkt_in_bp cvmx_npei_pkt_in_bp_t;
6511
6512 /**
6513 * cvmx_npei_pkt_in_done#_cnts
6514 *
6515 * NPEI_PKT_IN_DONE[0..31]_CNTS = NPEI Instruction Done ring# Counts
6516 *
6517 * Counters for instructions completed on Input rings.
6518 */
6519 union cvmx_npei_pkt_in_donex_cnts {
6520 uint64_t u64;
6521 struct cvmx_npei_pkt_in_donex_cnts_s {
6522 #ifdef __BIG_ENDIAN_BITFIELD
6523 uint64_t reserved_32_63 : 32;
6524 uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction
6525 is completed. This field is incremented as the
6526 last of the data is read from the PCIe. */
6527 #else
6528 uint64_t cnt : 32;
6529 uint64_t reserved_32_63 : 32;
6530 #endif
6531 } s;
6532 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
6533 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
6534 };
6535 typedef union cvmx_npei_pkt_in_donex_cnts cvmx_npei_pkt_in_donex_cnts_t;
6536
6537 /**
6538 * cvmx_npei_pkt_in_instr_counts
6539 *
6540 * NPEI_PKT_IN_INSTR_COUNTS = NPEI Packet Input Instrutction Counts
6541 *
6542 * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
6543 */
6544 union cvmx_npei_pkt_in_instr_counts {
6545 uint64_t u64;
6546 struct cvmx_npei_pkt_in_instr_counts_s {
6547 #ifdef __BIG_ENDIAN_BITFIELD
6548 uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */
6549 uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads
6550 issued for them.
6551 to the Packet-ring is in reset. */
6552 #else
6553 uint64_t rd_cnt : 32;
6554 uint64_t wr_cnt : 32;
6555 #endif
6556 } s;
6557 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
6558 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
6559 };
6560 typedef union cvmx_npei_pkt_in_instr_counts cvmx_npei_pkt_in_instr_counts_t;
6561
6562 /**
6563 * cvmx_npei_pkt_in_pcie_port
6564 *
6565 * NPEI_PKT_IN_PCIE_PORT = NPEI's Packet In To PCIe Port Assignment
6566 *
6567 * Assigns Packet Input rings to PCIe ports.
6568 */
6569 union cvmx_npei_pkt_in_pcie_port {
6570 uint64_t u64;
6571 struct cvmx_npei_pkt_in_pcie_port_s {
6572 #ifdef __BIG_ENDIAN_BITFIELD
6573 uint64_t pp : 64; /**< The PCIe port that the Packet ring number is
6574 assigned. Two bits are used per ring (i.e. ring 0
6575 [1:0], ring 1 [3:2], ....). A value of '0 means
6576 that the Packetring is assign to PCIe Port 0, a '1'
6577 PCIe Port 1, '2' and '3' are reserved. */
6578 #else
6579 uint64_t pp : 64;
6580 #endif
6581 } s;
6582 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
6583 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
6584 };
6585 typedef union cvmx_npei_pkt_in_pcie_port cvmx_npei_pkt_in_pcie_port_t;
6586
6587 /**
6588 * cvmx_npei_pkt_input_control
6589 *
6590 * NPEI_PKT_INPUT_CONTROL = NPEI's Packet Input Control
6591 *
6592 * Control for reads for gather list and instructions.
6593 */
6594 union cvmx_npei_pkt_input_control {
6595 uint64_t u64;
6596 struct cvmx_npei_pkt_input_control_s {
6597 #ifdef __BIG_ENDIAN_BITFIELD
6598 uint64_t reserved_23_63 : 41;
6599 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be
6600 made with a Round Robin arbitration. When '0'
6601 the input packet ring is fixed in priority,
6602 where the lower ring number has higher priority. */
6603 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in
6604 calculating a DPTR. */
6605 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of
6606 gather data. */
6607 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of
6608 gather data. */
6609 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of
6610 gather data. */
6611 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
6612 ROR, ESR, and NSR. When clear '0' the value in
6613 DPTR will be used. In turn the bits not used for
6614 ROR, ESR, and NSR, will be used for bits [63:60]
6615 of the address used to fetch packet data. */
6616 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of
6617 gather list and gather instruction. */
6618 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of
6619 gather list and gather instruction. */
6620 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of
6621 gather list and gather instruction. */
6622 #else
6623 uint64_t ror : 1;
6624 uint64_t esr : 2;
6625 uint64_t nsr : 1;
6626 uint64_t use_csr : 1;
6627 uint64_t d_ror : 1;
6628 uint64_t d_esr : 2;
6629 uint64_t d_nsr : 1;
6630 uint64_t pbp_dhi : 13;
6631 uint64_t pkt_rr : 1;
6632 uint64_t reserved_23_63 : 41;
6633 #endif
6634 } s;
6635 struct cvmx_npei_pkt_input_control_s cn52xx;
6636 struct cvmx_npei_pkt_input_control_s cn56xx;
6637 };
6638 typedef union cvmx_npei_pkt_input_control cvmx_npei_pkt_input_control_t;
6639
6640 /**
6641 * cvmx_npei_pkt_instr_enb
6642 *
6643 * NPEI_PKT_INSTR_ENB = NPEI's Packet Instruction Enable
6644 *
6645 * Enables the instruction fetch for a Packet-ring.
6646 */
6647 union cvmx_npei_pkt_instr_enb {
6648 uint64_t u64;
6649 struct cvmx_npei_pkt_instr_enb_s {
6650 #ifdef __BIG_ENDIAN_BITFIELD
6651 uint64_t reserved_32_63 : 32;
6652 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding
6653 to the Packet-ring is enabled. */
6654 #else
6655 uint64_t enb : 32;
6656 uint64_t reserved_32_63 : 32;
6657 #endif
6658 } s;
6659 struct cvmx_npei_pkt_instr_enb_s cn52xx;
6660 struct cvmx_npei_pkt_instr_enb_s cn56xx;
6661 };
6662 typedef union cvmx_npei_pkt_instr_enb cvmx_npei_pkt_instr_enb_t;
6663
6664 /**
6665 * cvmx_npei_pkt_instr_rd_size
6666 *
6667 * NPEI_PKT_INSTR_RD_SIZE = NPEI Instruction Read Size
6668 *
6669 * The number of instruction allowed to be read at one time.
6670 */
6671 union cvmx_npei_pkt_instr_rd_size {
6672 uint64_t u64;
6673 struct cvmx_npei_pkt_instr_rd_size_s {
6674 #ifdef __BIG_ENDIAN_BITFIELD
6675 uint64_t rdsize : 64; /**< Number of instructions to be read in one PCIe read
6676 request for the 4 PKOport - 8 rings. Every two bits
6677 (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
6678 combinations.
6679 - 15:0 PKOPort0,Ring 7..0 31:16 PKOPort1,Ring 7..0
6680 - 47:32 PKOPort2,Ring 7..0 63:48 PKOPort3,Ring 7..0
6681 Two bit value are:
6682 0 - 1 Instruction
6683 1 - 2 Instructions
6684 2 - 3 Instructions
6685 3 - 4 Instructions */
6686 #else
6687 uint64_t rdsize : 64;
6688 #endif
6689 } s;
6690 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
6691 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
6692 };
6693 typedef union cvmx_npei_pkt_instr_rd_size cvmx_npei_pkt_instr_rd_size_t;
6694
6695 /**
6696 * cvmx_npei_pkt_instr_size
6697 *
6698 * NPEI_PKT_INSTR_SIZE = NPEI's Packet Instruction Size
6699 *
6700 * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
6701 */
6702 union cvmx_npei_pkt_instr_size {
6703 uint64_t u64;
6704 struct cvmx_npei_pkt_instr_size_s {
6705 #ifdef __BIG_ENDIAN_BITFIELD
6706 uint64_t reserved_32_63 : 32;
6707 uint64_t is_64b : 32; /**< When asserted '1' the vector bit cooresponding
6708 to the Packet-ring is a 64-byte instruction. */
6709 #else
6710 uint64_t is_64b : 32;
6711 uint64_t reserved_32_63 : 32;
6712 #endif
6713 } s;
6714 struct cvmx_npei_pkt_instr_size_s cn52xx;
6715 struct cvmx_npei_pkt_instr_size_s cn56xx;
6716 };
6717 typedef union cvmx_npei_pkt_instr_size cvmx_npei_pkt_instr_size_t;
6718
6719 /**
6720 * cvmx_npei_pkt_int_levels
6721 *
6722 * 0x90F0 reserved NPEI_PKT_PCIE_PORT2
6723 *
6724 *
6725 * NPEI_PKT_INT_LEVELS = NPEI's Packet Interrupt Levels
6726 *
6727 * Output packet interrupt levels.
6728 */
6729 union cvmx_npei_pkt_int_levels {
6730 uint64_t u64;
6731 struct cvmx_npei_pkt_int_levels_s {
6732 #ifdef __BIG_ENDIAN_BITFIELD
6733 uint64_t reserved_54_63 : 10;
6734 uint64_t time : 22; /**< When NPEI_PKT#_CNTS[TIMER] is greater than this
6735 value an interrupt is generated. */
6736 uint64_t cnt : 32; /**< When NPEI_PKT#_CNTS[CNT] becomes
6737 greater than this value an interrupt is generated. */
6738 #else
6739 uint64_t cnt : 32;
6740 uint64_t time : 22;
6741 uint64_t reserved_54_63 : 10;
6742 #endif
6743 } s;
6744 struct cvmx_npei_pkt_int_levels_s cn52xx;
6745 struct cvmx_npei_pkt_int_levels_s cn56xx;
6746 };
6747 typedef union cvmx_npei_pkt_int_levels cvmx_npei_pkt_int_levels_t;
6748
6749 /**
6750 * cvmx_npei_pkt_iptr
6751 *
6752 * NPEI_PKT_IPTR = NPEI's Packet Info Poitner
6753 *
6754 * Controls using the Info-Pointer to store length and data.
6755 */
6756 union cvmx_npei_pkt_iptr {
6757 uint64_t u64;
6758 struct cvmx_npei_pkt_iptr_s {
6759 #ifdef __BIG_ENDIAN_BITFIELD
6760 uint64_t reserved_32_63 : 32;
6761 uint64_t iptr : 32; /**< When asserted '1' the vector bit cooresponding
6762 to the Packet-ring will use the Info-Pointer to
6763 store length and data. */
6764 #else
6765 uint64_t iptr : 32;
6766 uint64_t reserved_32_63 : 32;
6767 #endif
6768 } s;
6769 struct cvmx_npei_pkt_iptr_s cn52xx;
6770 struct cvmx_npei_pkt_iptr_s cn56xx;
6771 };
6772 typedef union cvmx_npei_pkt_iptr cvmx_npei_pkt_iptr_t;
6773
6774 /**
6775 * cvmx_npei_pkt_out_bmode
6776 *
6777 * NPEI_PKT_OUT_BMODE = NPEI's Packet Out Byte Mode
6778 *
6779 * Control the updating of the NPEI_PKT#_CNT register.
6780 */
6781 union cvmx_npei_pkt_out_bmode {
6782 uint64_t u64;
6783 struct cvmx_npei_pkt_out_bmode_s {
6784 #ifdef __BIG_ENDIAN_BITFIELD
6785 uint64_t reserved_32_63 : 32;
6786 uint64_t bmode : 32; /**< When asserted '1' the vector bit cooresponding
6787 to the Packet-ring will have its NPEI_PKT#_CNT
6788 register updated with the number of bytes in the
6789 packet sent, when '0' the register will have a
6790 value of '1' added. */
6791 #else
6792 uint64_t bmode : 32;
6793 uint64_t reserved_32_63 : 32;
6794 #endif
6795 } s;
6796 struct cvmx_npei_pkt_out_bmode_s cn52xx;
6797 struct cvmx_npei_pkt_out_bmode_s cn56xx;
6798 };
6799 typedef union cvmx_npei_pkt_out_bmode cvmx_npei_pkt_out_bmode_t;
6800
6801 /**
6802 * cvmx_npei_pkt_out_enb
6803 *
6804 * NPEI_PKT_OUT_ENB = NPEI's Packet Output Enable
6805 *
6806 * Enables the output packet engines.
6807 */
6808 union cvmx_npei_pkt_out_enb {
6809 uint64_t u64;
6810 struct cvmx_npei_pkt_out_enb_s {
6811 #ifdef __BIG_ENDIAN_BITFIELD
6812 uint64_t reserved_32_63 : 32;
6813 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding
6814 to the Packet-ring is enabled.
6815 If an error occurs on reading pointers for an
6816 output ring, the ring will be disabled by clearing
6817 the bit associated with the ring to '0'. */
6818 #else
6819 uint64_t enb : 32;
6820 uint64_t reserved_32_63 : 32;
6821 #endif
6822 } s;
6823 struct cvmx_npei_pkt_out_enb_s cn52xx;
6824 struct cvmx_npei_pkt_out_enb_s cn56xx;
6825 };
6826 typedef union cvmx_npei_pkt_out_enb cvmx_npei_pkt_out_enb_t;
6827
6828 /**
6829 * cvmx_npei_pkt_output_wmark
6830 *
6831 * NPEI_PKT_OUTPUT_WMARK = NPEI's Packet Output Water Mark
6832 *
6833 * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
6834 */
6835 union cvmx_npei_pkt_output_wmark {
6836 uint64_t u64;
6837 struct cvmx_npei_pkt_output_wmark_s {
6838 #ifdef __BIG_ENDIAN_BITFIELD
6839 uint64_t reserved_32_63 : 32;
6840 uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure
6841 for the ring will be applied to the PKO. */
6842 #else
6843 uint64_t wmark : 32;
6844 uint64_t reserved_32_63 : 32;
6845 #endif
6846 } s;
6847 struct cvmx_npei_pkt_output_wmark_s cn52xx;
6848 struct cvmx_npei_pkt_output_wmark_s cn56xx;
6849 };
6850 typedef union cvmx_npei_pkt_output_wmark cvmx_npei_pkt_output_wmark_t;
6851
6852 /**
6853 * cvmx_npei_pkt_pcie_port
6854 *
6855 * NPEI_PKT_PCIE_PORT = NPEI's Packet To PCIe Port Assignment
6856 *
6857 * Assigns Packet Ports to PCIe ports.
6858 */
6859 union cvmx_npei_pkt_pcie_port {
6860 uint64_t u64;
6861 struct cvmx_npei_pkt_pcie_port_s {
6862 #ifdef __BIG_ENDIAN_BITFIELD
6863 uint64_t pp : 64; /**< The PCIe port that the Packet ring number is
6864 assigned. Two bits are used per ring (i.e. ring 0
6865 [1:0], ring 1 [3:2], ....). A value of '0 means
6866 that the Packetring is assign to PCIe Port 0, a '1'
6867 PCIe Port 1, '2' and '3' are reserved. */
6868 #else
6869 uint64_t pp : 64;
6870 #endif
6871 } s;
6872 struct cvmx_npei_pkt_pcie_port_s cn52xx;
6873 struct cvmx_npei_pkt_pcie_port_s cn56xx;
6874 };
6875 typedef union cvmx_npei_pkt_pcie_port cvmx_npei_pkt_pcie_port_t;
6876
6877 /**
6878 * cvmx_npei_pkt_port_in_rst
6879 *
6880 * NPEI_PKT_PORT_IN_RST = NPEI Packet Port In Reset
6881 *
6882 * Vector bits related to ring-port for ones that are reset.
6883 */
6884 union cvmx_npei_pkt_port_in_rst {
6885 uint64_t u64;
6886 struct cvmx_npei_pkt_port_in_rst_s {
6887 #ifdef __BIG_ENDIAN_BITFIELD
6888 uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding
6889 to the inbound Packet-ring is in reset. */
6890 uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding
6891 to the outbound Packet-ring is in reset. */
6892 #else
6893 uint64_t out_rst : 32;
6894 uint64_t in_rst : 32;
6895 #endif
6896 } s;
6897 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
6898 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
6899 };
6900 typedef union cvmx_npei_pkt_port_in_rst cvmx_npei_pkt_port_in_rst_t;
6901
6902 /**
6903 * cvmx_npei_pkt_slist_es
6904 *
6905 * NPEI_PKT_SLIST_ES = NPEI's Packet Scatter List Endian Swap
6906 *
6907 * The Endian Swap for Scatter List Read.
6908 */
6909 union cvmx_npei_pkt_slist_es {
6910 uint64_t u64;
6911 struct cvmx_npei_pkt_slist_es_s {
6912 #ifdef __BIG_ENDIAN_BITFIELD
6913 uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31.
6914 Two bits are used per ring (i.e. ring 0 [1:0],
6915 ring 1 [3:2], ....). */
6916 #else
6917 uint64_t es : 64;
6918 #endif
6919 } s;
6920 struct cvmx_npei_pkt_slist_es_s cn52xx;
6921 struct cvmx_npei_pkt_slist_es_s cn56xx;
6922 };
6923 typedef union cvmx_npei_pkt_slist_es cvmx_npei_pkt_slist_es_t;
6924
6925 /**
6926 * cvmx_npei_pkt_slist_id_size
6927 *
6928 * NPEI_PKT_SLIST_ID_SIZE = NPEI Packet Scatter List Info and Data Size
6929 *
6930 * The Size of the information and data fields pointed to by Scatter List pointers.
6931 */
6932 union cvmx_npei_pkt_slist_id_size {
6933 uint64_t u64;
6934 struct cvmx_npei_pkt_slist_id_size_s {
6935 #ifdef __BIG_ENDIAN_BITFIELD
6936 uint64_t reserved_23_63 : 41;
6937 uint64_t isize : 7; /**< Information size. Legal sizes are 0 to 120. */
6938 uint64_t bsize : 16; /**< Data size. */
6939 #else
6940 uint64_t bsize : 16;
6941 uint64_t isize : 7;
6942 uint64_t reserved_23_63 : 41;
6943 #endif
6944 } s;
6945 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
6946 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
6947 };
6948 typedef union cvmx_npei_pkt_slist_id_size cvmx_npei_pkt_slist_id_size_t;
6949
6950 /**
6951 * cvmx_npei_pkt_slist_ns
6952 *
6953 * NPEI_PKT_SLIST_NS = NPEI's Packet Scatter List No Snoop
6954 *
6955 * The NS field for the TLP when fetching Scatter List.
6956 */
6957 union cvmx_npei_pkt_slist_ns {
6958 uint64_t u64;
6959 struct cvmx_npei_pkt_slist_ns_s {
6960 #ifdef __BIG_ENDIAN_BITFIELD
6961 uint64_t reserved_32_63 : 32;
6962 uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding
6963 to the Packet-ring will enable NS in TLP header. */
6964 #else
6965 uint64_t nsr : 32;
6966 uint64_t reserved_32_63 : 32;
6967 #endif
6968 } s;
6969 struct cvmx_npei_pkt_slist_ns_s cn52xx;
6970 struct cvmx_npei_pkt_slist_ns_s cn56xx;
6971 };
6972 typedef union cvmx_npei_pkt_slist_ns cvmx_npei_pkt_slist_ns_t;
6973
6974 /**
6975 * cvmx_npei_pkt_slist_ror
6976 *
6977 * NPEI_PKT_SLIST_ROR = NPEI's Packet Scatter List Relaxed Ordering
6978 *
6979 * The ROR field for the TLP when fetching Scatter List.
6980 */
6981 union cvmx_npei_pkt_slist_ror {
6982 uint64_t u64;
6983 struct cvmx_npei_pkt_slist_ror_s {
6984 #ifdef __BIG_ENDIAN_BITFIELD
6985 uint64_t reserved_32_63 : 32;
6986 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding
6987 to the Packet-ring will enable ROR in TLP header. */
6988 #else
6989 uint64_t ror : 32;
6990 uint64_t reserved_32_63 : 32;
6991 #endif
6992 } s;
6993 struct cvmx_npei_pkt_slist_ror_s cn52xx;
6994 struct cvmx_npei_pkt_slist_ror_s cn56xx;
6995 };
6996 typedef union cvmx_npei_pkt_slist_ror cvmx_npei_pkt_slist_ror_t;
6997
6998 /**
6999 * cvmx_npei_pkt_time_int
7000 *
7001 * NPEI_PKT_TIME_INT = NPEI Packet Timer Interrupt
7002 *
7003 * The packets rings that are interrupting because of Packet Timers.
7004 */
7005 union cvmx_npei_pkt_time_int {
7006 uint64_t u64;
7007 struct cvmx_npei_pkt_time_int_s {
7008 #ifdef __BIG_ENDIAN_BITFIELD
7009 uint64_t reserved_32_63 : 32;
7010 uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when
7011 NPEI_PKT#_CNTS[TIMER] is greater than
7012 NPEI_PKT_INT_LEVELS[TIME]. */
7013 #else
7014 uint64_t port : 32;
7015 uint64_t reserved_32_63 : 32;
7016 #endif
7017 } s;
7018 struct cvmx_npei_pkt_time_int_s cn52xx;
7019 struct cvmx_npei_pkt_time_int_s cn56xx;
7020 };
7021 typedef union cvmx_npei_pkt_time_int cvmx_npei_pkt_time_int_t;
7022
7023 /**
7024 * cvmx_npei_pkt_time_int_enb
7025 *
7026 * NPEI_PKT_TIME_INT_ENB = NPEI Packet Timer Interrupt Enable
7027 *
7028 * The packets rings that are interrupting because of Packet Timers.
7029 */
7030 union cvmx_npei_pkt_time_int_enb {
7031 uint64_t u64;
7032 struct cvmx_npei_pkt_time_int_enb_s {
7033 #ifdef __BIG_ENDIAN_BITFIELD
7034 uint64_t reserved_32_63 : 32;
7035 uint64_t port : 32; /**< Bit vector cooresponding to ring number when set
7036 allows NPEI_PKT_TIME_INT to generate an interrupt. */
7037 #else
7038 uint64_t port : 32;
7039 uint64_t reserved_32_63 : 32;
7040 #endif
7041 } s;
7042 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
7043 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
7044 };
7045 typedef union cvmx_npei_pkt_time_int_enb cvmx_npei_pkt_time_int_enb_t;
7046
7047 /**
7048 * cvmx_npei_rsl_int_blocks
7049 *
7050 * NPEI_RSL_INT_BLOCKS = NPEI RSL Interrupt Blocks Register
7051 *
7052 * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
7053 * that presently has an interrupt pending. The Field Description below supplies the name of the
7054 * register that software should read to find out why that intterupt bit is set.
7055 */
7056 union cvmx_npei_rsl_int_blocks {
7057 uint64_t u64;
7058 struct cvmx_npei_rsl_int_blocks_s {
7059 #ifdef __BIG_ENDIAN_BITFIELD
7060 uint64_t reserved_31_63 : 33;
7061 uint64_t iob : 1; /**< IOB_INT_SUM */
7062 uint64_t lmc1 : 1; /**< LMC1_MEM_CFG0 */
7063 uint64_t agl : 1; /**< AGL_GMX_RX0_INT_REG & AGL_GMX_TX_INT_REG */
7064 uint64_t reserved_24_27 : 4;
7065 uint64_t asxpcs1 : 1; /**< PCS1_INT*_REG */
7066 uint64_t asxpcs0 : 1; /**< PCS0_INT*_REG */
7067 uint64_t reserved_21_21 : 1;
7068 uint64_t pip : 1; /**< PIP_INT_REG. */
7069 uint64_t spx1 : 1; /**< Always reads as zero */
7070 uint64_t spx0 : 1; /**< Always reads as zero */
7071 uint64_t lmc0 : 1; /**< LMC0_MEM_CFG0 */
7072 uint64_t l2c : 1; /**< L2C_INT_STAT */
7073 uint64_t usb1 : 1; /**< Always reads as zero */
7074 uint64_t rad : 1; /**< RAD_REG_ERROR */
7075 uint64_t usb : 1; /**< USBN0_INT_SUM */
7076 uint64_t pow : 1; /**< POW_ECC_ERR */
7077 uint64_t tim : 1; /**< TIM_REG_ERROR */
7078 uint64_t pko : 1; /**< PKO_REG_ERROR */
7079 uint64_t ipd : 1; /**< IPD_INT_SUM */
7080 uint64_t reserved_8_8 : 1;
7081 uint64_t zip : 1; /**< ZIP_ERROR */
7082 uint64_t dfa : 1; /**< Always reads as zero */
7083 uint64_t fpa : 1; /**< FPA_INT_SUM */
7084 uint64_t key : 1; /**< KEY_INT_SUM */
7085 uint64_t npei : 1; /**< NPEI_INT_SUM */
7086 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
7087 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
7088 uint64_t mio : 1; /**< MIO_BOOT_ERR */
7089 #else
7090 uint64_t mio : 1;
7091 uint64_t gmx0 : 1;
7092 uint64_t gmx1 : 1;
7093 uint64_t npei : 1;
7094 uint64_t key : 1;
7095 uint64_t fpa : 1;
7096 uint64_t dfa : 1;
7097 uint64_t zip : 1;
7098 uint64_t reserved_8_8 : 1;
7099 uint64_t ipd : 1;
7100 uint64_t pko : 1;
7101 uint64_t tim : 1;
7102 uint64_t pow : 1;
7103 uint64_t usb : 1;
7104 uint64_t rad : 1;
7105 uint64_t usb1 : 1;
7106 uint64_t l2c : 1;
7107 uint64_t lmc0 : 1;
7108 uint64_t spx0 : 1;
7109 uint64_t spx1 : 1;
7110 uint64_t pip : 1;
7111 uint64_t reserved_21_21 : 1;
7112 uint64_t asxpcs0 : 1;
7113 uint64_t asxpcs1 : 1;
7114 uint64_t reserved_24_27 : 4;
7115 uint64_t agl : 1;
7116 uint64_t lmc1 : 1;
7117 uint64_t iob : 1;
7118 uint64_t reserved_31_63 : 33;
7119 #endif
7120 } s;
7121 struct cvmx_npei_rsl_int_blocks_s cn52xx;
7122 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
7123 struct cvmx_npei_rsl_int_blocks_s cn56xx;
7124 struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
7125 };
7126 typedef union cvmx_npei_rsl_int_blocks cvmx_npei_rsl_int_blocks_t;
7127
7128 /**
7129 * cvmx_npei_scratch_1
7130 *
7131 * NPEI_SCRATCH_1 = NPEI's Scratch 1
7132 *
7133 * A general purpose 64 bit register for SW use.
7134 */
7135 union cvmx_npei_scratch_1 {
7136 uint64_t u64;
7137 struct cvmx_npei_scratch_1_s {
7138 #ifdef __BIG_ENDIAN_BITFIELD
7139 uint64_t data : 64; /**< The value in this register is totaly SW dependent. */
7140 #else
7141 uint64_t data : 64;
7142 #endif
7143 } s;
7144 struct cvmx_npei_scratch_1_s cn52xx;
7145 struct cvmx_npei_scratch_1_s cn52xxp1;
7146 struct cvmx_npei_scratch_1_s cn56xx;
7147 struct cvmx_npei_scratch_1_s cn56xxp1;
7148 };
7149 typedef union cvmx_npei_scratch_1 cvmx_npei_scratch_1_t;
7150
7151 /**
7152 * cvmx_npei_state1
7153 *
7154 * NPEI_STATE1 = NPEI State 1
7155 *
7156 * State machines in NPEI. For debug.
7157 */
7158 union cvmx_npei_state1 {
7159 uint64_t u64;
7160 struct cvmx_npei_state1_s {
7161 #ifdef __BIG_ENDIAN_BITFIELD
7162 uint64_t cpl1 : 12; /**< CPL1 State */
7163 uint64_t cpl0 : 12; /**< CPL0 State */
7164 uint64_t arb : 1; /**< ARB State */
7165 uint64_t csr : 39; /**< CSR State */
7166 #else
7167 uint64_t csr : 39;
7168 uint64_t arb : 1;
7169 uint64_t cpl0 : 12;
7170 uint64_t cpl1 : 12;
7171 #endif
7172 } s;
7173 struct cvmx_npei_state1_s cn52xx;
7174 struct cvmx_npei_state1_s cn52xxp1;
7175 struct cvmx_npei_state1_s cn56xx;
7176 struct cvmx_npei_state1_s cn56xxp1;
7177 };
7178 typedef union cvmx_npei_state1 cvmx_npei_state1_t;
7179
7180 /**
7181 * cvmx_npei_state2
7182 *
7183 * NPEI_STATE2 = NPEI State 2
7184 *
7185 * State machines in NPEI. For debug.
7186 */
7187 union cvmx_npei_state2 {
7188 uint64_t u64;
7189 struct cvmx_npei_state2_s {
7190 #ifdef __BIG_ENDIAN_BITFIELD
7191 uint64_t reserved_48_63 : 16;
7192 uint64_t npei : 1; /**< NPEI State */
7193 uint64_t rac : 1; /**< RAC State */
7194 uint64_t csm1 : 15; /**< CSM1 State */
7195 uint64_t csm0 : 15; /**< CSM0 State */
7196 uint64_t nnp0 : 8; /**< NNP0 State */
7197 uint64_t nnd : 8; /**< NND State */
7198 #else
7199 uint64_t nnd : 8;
7200 uint64_t nnp0 : 8;
7201 uint64_t csm0 : 15;
7202 uint64_t csm1 : 15;
7203 uint64_t rac : 1;
7204 uint64_t npei : 1;
7205 uint64_t reserved_48_63 : 16;
7206 #endif
7207 } s;
7208 struct cvmx_npei_state2_s cn52xx;
7209 struct cvmx_npei_state2_s cn52xxp1;
7210 struct cvmx_npei_state2_s cn56xx;
7211 struct cvmx_npei_state2_s cn56xxp1;
7212 };
7213 typedef union cvmx_npei_state2 cvmx_npei_state2_t;
7214
7215 /**
7216 * cvmx_npei_state3
7217 *
7218 * NPEI_STATE3 = NPEI State 3
7219 *
7220 * State machines in NPEI. For debug.
7221 */
7222 union cvmx_npei_state3 {
7223 uint64_t u64;
7224 struct cvmx_npei_state3_s {
7225 #ifdef __BIG_ENDIAN_BITFIELD
7226 uint64_t reserved_56_63 : 8;
7227 uint64_t psm1 : 15; /**< PSM1 State */
7228 uint64_t psm0 : 15; /**< PSM0 State */
7229 uint64_t nsm1 : 13; /**< NSM1 State */
7230 uint64_t nsm0 : 13; /**< NSM0 State */
7231 #else
7232 uint64_t nsm0 : 13;
7233 uint64_t nsm1 : 13;
7234 uint64_t psm0 : 15;
7235 uint64_t psm1 : 15;
7236 uint64_t reserved_56_63 : 8;
7237 #endif
7238 } s;
7239 struct cvmx_npei_state3_s cn52xx;
7240 struct cvmx_npei_state3_s cn52xxp1;
7241 struct cvmx_npei_state3_s cn56xx;
7242 struct cvmx_npei_state3_s cn56xxp1;
7243 };
7244 typedef union cvmx_npei_state3 cvmx_npei_state3_t;
7245
7246 /**
7247 * cvmx_npei_win_rd_addr
7248 *
7249 * NPEI_WIN_RD_ADDR = NPEI Window Read Address Register
7250 *
7251 * The address to be read when the NPEI_WIN_RD_DATA register is read.
7252 */
7253 union cvmx_npei_win_rd_addr {
7254 uint64_t u64;
7255 struct cvmx_npei_win_rd_addr_s {
7256 #ifdef __BIG_ENDIAN_BITFIELD
7257 uint64_t reserved_51_63 : 13;
7258 uint64_t ld_cmd : 2; /**< The load command sent wit hthe read.
7259 0x0 == Load 8-bytes, 0x1 == Load 4-bytes,
7260 0x2 == Load 2-bytes, 0x3 == Load 1-bytes, */
7261 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
7262 read as '0'. */
7263 uint64_t rd_addr : 48; /**< The address to be read from. Whenever the LSB of
7264 this register is written, the Read Operation will
7265 take place.
7266 [47:40] = NCB_ID
7267 [39:0] = Address
7268 When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
7269 [39:32] == x, Not Used
7270 [31:27] == RSL_ID
7271 [12:0] == RSL Register Offset */
7272 #else
7273 uint64_t rd_addr : 48;
7274 uint64_t iobit : 1;
7275 uint64_t ld_cmd : 2;
7276 uint64_t reserved_51_63 : 13;
7277 #endif
7278 } s;
7279 struct cvmx_npei_win_rd_addr_s cn52xx;
7280 struct cvmx_npei_win_rd_addr_s cn52xxp1;
7281 struct cvmx_npei_win_rd_addr_s cn56xx;
7282 struct cvmx_npei_win_rd_addr_s cn56xxp1;
7283 };
7284 typedef union cvmx_npei_win_rd_addr cvmx_npei_win_rd_addr_t;
7285
7286 /**
7287 * cvmx_npei_win_rd_data
7288 *
7289 * NPEI_WIN_RD_DATA = NPEI Window Read Data Register
7290 *
7291 * Reading this register causes a window read operation to take place. Address read is taht contained in the NPEI_WIN_RD_ADDR
7292 * register.
7293 */
7294 union cvmx_npei_win_rd_data {
7295 uint64_t u64;
7296 struct cvmx_npei_win_rd_data_s {
7297 #ifdef __BIG_ENDIAN_BITFIELD
7298 uint64_t rd_data : 64; /**< The read data. */
7299 #else
7300 uint64_t rd_data : 64;
7301 #endif
7302 } s;
7303 struct cvmx_npei_win_rd_data_s cn52xx;
7304 struct cvmx_npei_win_rd_data_s cn52xxp1;
7305 struct cvmx_npei_win_rd_data_s cn56xx;
7306 struct cvmx_npei_win_rd_data_s cn56xxp1;
7307 };
7308 typedef union cvmx_npei_win_rd_data cvmx_npei_win_rd_data_t;
7309
7310 /**
7311 * cvmx_npei_win_wr_addr
7312 *
7313 * NPEI_WIN_WR_ADDR = NPEI Window Write Address Register
7314 *
7315 * Contains the address to be writen to when a write operation is started by writing the
7316 * NPEI_WIN_WR_DATA register (see below).
7317 *
7318 * Notes:
7319 * Even though address bit [2] can be set, it should always be kept to '0'.
7320 *
7321 */
7322 union cvmx_npei_win_wr_addr {
7323 uint64_t u64;
7324 struct cvmx_npei_win_wr_addr_s {
7325 #ifdef __BIG_ENDIAN_BITFIELD
7326 uint64_t reserved_49_63 : 15;
7327 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
7328 read as '0'. */
7329 uint64_t wr_addr : 46; /**< The address that will be written to when the
7330 NPEI_WIN_WR_DATA register is written.
7331 [47:40] = NCB_ID
7332 [39:3] = Address
7333 When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
7334 [39:32] == x, Not Used
7335 [31:27] == RSL_ID
7336 [12:2] == RSL Register Offset
7337 [1:0] == x, Not Used */
7338 uint64_t reserved_0_1 : 2;
7339 #else
7340 uint64_t reserved_0_1 : 2;
7341 uint64_t wr_addr : 46;
7342 uint64_t iobit : 1;
7343 uint64_t reserved_49_63 : 15;
7344 #endif
7345 } s;
7346 struct cvmx_npei_win_wr_addr_s cn52xx;
7347 struct cvmx_npei_win_wr_addr_s cn52xxp1;
7348 struct cvmx_npei_win_wr_addr_s cn56xx;
7349 struct cvmx_npei_win_wr_addr_s cn56xxp1;
7350 };
7351 typedef union cvmx_npei_win_wr_addr cvmx_npei_win_wr_addr_t;
7352
7353 /**
7354 * cvmx_npei_win_wr_data
7355 *
7356 * NPEI_WIN_WR_DATA = NPEI Window Write Data Register
7357 *
7358 * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR Register.
7359 * Writing the least-significant-byte of this register will cause a write operation to take place.
7360 */
7361 union cvmx_npei_win_wr_data {
7362 uint64_t u64;
7363 struct cvmx_npei_win_wr_data_s {
7364 #ifdef __BIG_ENDIAN_BITFIELD
7365 uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this
7366 register is written, the Window Write will take
7367 place. */
7368 #else
7369 uint64_t wr_data : 64;
7370 #endif
7371 } s;
7372 struct cvmx_npei_win_wr_data_s cn52xx;
7373 struct cvmx_npei_win_wr_data_s cn52xxp1;
7374 struct cvmx_npei_win_wr_data_s cn56xx;
7375 struct cvmx_npei_win_wr_data_s cn56xxp1;
7376 };
7377 typedef union cvmx_npei_win_wr_data cvmx_npei_win_wr_data_t;
7378
7379 /**
7380 * cvmx_npei_win_wr_mask
7381 *
7382 * NPEI_WIN_WR_MASK = NPEI Window Write Mask Register
7383 *
7384 * Contains the mask for the data in the NPEI_WIN_WR_DATA Register.
7385 */
7386 union cvmx_npei_win_wr_mask {
7387 uint64_t u64;
7388 struct cvmx_npei_win_wr_mask_s {
7389 #ifdef __BIG_ENDIAN_BITFIELD
7390 uint64_t reserved_8_63 : 56;
7391 uint64_t wr_mask : 8; /**< The data to be written. When a bit is '0'
7392 the corresponding byte will be written. */
7393 #else
7394 uint64_t wr_mask : 8;
7395 uint64_t reserved_8_63 : 56;
7396 #endif
7397 } s;
7398 struct cvmx_npei_win_wr_mask_s cn52xx;
7399 struct cvmx_npei_win_wr_mask_s cn52xxp1;
7400 struct cvmx_npei_win_wr_mask_s cn56xx;
7401 struct cvmx_npei_win_wr_mask_s cn56xxp1;
7402 };
7403 typedef union cvmx_npei_win_wr_mask cvmx_npei_win_wr_mask_t;
7404
7405 /**
7406 * cvmx_npei_window_ctl
7407 *
7408 * NPEI_WINDOW_CTL = NPEI's Window Control
7409 *
7410 * The name of this register is misleading. The timeout value is used for BAR0 access from PCIE0 and PCIE1.
7411 * Any access to the regigisters on the RML will timeout as 0xFFFF clock cycle. At time of timeout the next
7412 * RML access will start, and interrupt will be set, and in the case of reads no data will be returned.
7413 *
7414 * The value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
7415 * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#.
7416 */
7417 union cvmx_npei_window_ctl {
7418 uint64_t u64;
7419 struct cvmx_npei_window_ctl_s {
7420 #ifdef __BIG_ENDIAN_BITFIELD
7421 uint64_t reserved_32_63 : 32;
7422 uint64_t time : 32; /**< Time to wait in core clocks to wait for a
7423 BAR0 access to completeon the NCB
7424 before timing out. A value of 0 will cause no
7425 timeouts. A minimum value of 0x200000 should be
7426 used when this register is not set to 0x0. */
7427 #else
7428 uint64_t time : 32;
7429 uint64_t reserved_32_63 : 32;
7430 #endif
7431 } s;
7432 struct cvmx_npei_window_ctl_s cn52xx;
7433 struct cvmx_npei_window_ctl_s cn52xxp1;
7434 struct cvmx_npei_window_ctl_s cn56xx;
7435 struct cvmx_npei_window_ctl_s cn56xxp1;
7436 };
7437 typedef union cvmx_npei_window_ctl cvmx_npei_window_ctl_t;
7438
7439 #endif
7440