1 /*-
2 * Copyright (c) 2015 Adrian Chadd <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_ddb.h"
31
32 #include <sys/param.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/cons.h>
38 #include <sys/kdb.h>
39 #include <sys/reboot.h>
40
41 #include <vm/vm.h>
42 #include <vm/vm_page.h>
43
44 #include <net/ethernet.h>
45
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
53
54 #include <mips/atheros/ar71xxreg.h>
55 //#include <mips/atheros/ar934xreg.h>
56 #include <mips/atheros/qca955xreg.h>
57
58 #include <mips/atheros/ar71xx_cpudef.h>
59 #include <mips/atheros/ar71xx_setup.h>
60
61 #include <mips/atheros/ar71xx_chip.h>
62
63 #include <mips/atheros/qca955x_chip.h>
64
65 static void
qca955x_chip_detect_mem_size(void)66 qca955x_chip_detect_mem_size(void)
67 {
68 }
69
70 static void
qca955x_chip_detect_sys_frequency(void)71 qca955x_chip_detect_sys_frequency(void)
72 {
73 unsigned long ref_rate;
74 unsigned long cpu_rate;
75 unsigned long ddr_rate;
76 unsigned long ahb_rate;
77 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
78 uint32_t cpu_pll, ddr_pll;
79 uint32_t bootstrap;
80
81 bootstrap = ATH_READ_REG(QCA955X_RESET_REG_BOOTSTRAP);
82 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
83 ref_rate = 40 * 1000 * 1000;
84 else
85 ref_rate = 25 * 1000 * 1000;
86
87 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG);
88 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
89 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
90 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
91 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
92 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
93 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
94 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
95 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
96
97 cpu_pll = nint * ref_rate / ref_div;
98 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
99 cpu_pll /= (1 << out_div);
100
101 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG);
102 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
103 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
104 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
105 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
106 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
107 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
108 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
109 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
110
111 ddr_pll = nint * ref_rate / ref_div;
112 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
113 ddr_pll /= (1 << out_div);
114
115 clk_ctrl = ATH_READ_REG(QCA955X_PLL_CLK_CTRL_REG);
116
117 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
118 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
119
120 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
121 cpu_rate = ref_rate;
122 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
123 cpu_rate = ddr_pll / (postdiv + 1);
124 else
125 cpu_rate = cpu_pll / (postdiv + 1);
126
127 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
128 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
129
130 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
131 ddr_rate = ref_rate;
132 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
133 ddr_rate = cpu_pll / (postdiv + 1);
134 else
135 ddr_rate = ddr_pll / (postdiv + 1);
136
137 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
138 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
139
140 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
141 ahb_rate = ref_rate;
142 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
143 ahb_rate = ddr_pll / (postdiv + 1);
144 else
145 ahb_rate = cpu_pll / (postdiv + 1);
146
147 u_ar71xx_ddr_freq = ddr_rate;
148 u_ar71xx_cpu_freq = cpu_rate;
149 u_ar71xx_ahb_freq = ahb_rate;
150
151 u_ar71xx_wdt_freq = ref_rate;
152 u_ar71xx_uart_freq = ref_rate;
153 u_ar71xx_mdio_freq = ref_rate;
154 u_ar71xx_refclk = ref_rate;
155 }
156
157 static void
qca955x_chip_device_stop(uint32_t mask)158 qca955x_chip_device_stop(uint32_t mask)
159 {
160 uint32_t reg;
161
162 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
163 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg | mask);
164 }
165
166 static void
qca955x_chip_device_start(uint32_t mask)167 qca955x_chip_device_start(uint32_t mask)
168 {
169 uint32_t reg;
170
171 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
172 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg & ~mask);
173 }
174
175 static int
qca955x_chip_device_stopped(uint32_t mask)176 qca955x_chip_device_stopped(uint32_t mask)
177 {
178 uint32_t reg;
179
180 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
181 return ((reg & mask) == mask);
182 }
183
184 static void
qca955x_chip_set_mii_speed(uint32_t unit,uint32_t speed)185 qca955x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
186 {
187
188 /* XXX TODO */
189 return;
190 }
191
192 static void
qca955x_chip_set_pll_ge(int unit,int speed,uint32_t pll)193 qca955x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
194 {
195 switch (unit) {
196 case 0:
197 ATH_WRITE_REG(QCA955X_PLL_ETH_XMII_CONTROL_REG, pll);
198 break;
199 case 1:
200 ATH_WRITE_REG(QCA955X_PLL_ETH_SGMII_CONTROL_REG, pll);
201 break;
202 default:
203 printf("%s: invalid PLL set for arge unit: %d\n",
204 __func__, unit);
205 return;
206 }
207 }
208
209 static void
qca955x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)210 qca955x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
211 {
212
213 switch (id) {
214 case AR71XX_CPU_DDR_FLUSH_GE0:
215 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE0);
216 break;
217 case AR71XX_CPU_DDR_FLUSH_GE1:
218 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE1);
219 break;
220 case AR71XX_CPU_DDR_FLUSH_USB:
221 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_USB);
222 break;
223 case AR71XX_CPU_DDR_FLUSH_PCIE:
224 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_PCIE);
225 break;
226 case AR71XX_CPU_DDR_FLUSH_WMAC:
227 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_WMAC);
228 break;
229 case AR71XX_CPU_DDR_FLUSH_PCIE_EP:
230 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC1);
231 break;
232 case AR71XX_CPU_DDR_FLUSH_CHECKSUM:
233 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC2);
234 break;
235 default:
236 printf("%s: invalid flush (%d)\n", __func__, id);
237 }
238 }
239
240 static uint32_t
qca955x_chip_get_eth_pll(unsigned int mac,int speed)241 qca955x_chip_get_eth_pll(unsigned int mac, int speed)
242 {
243 uint32_t pll;
244
245 switch (speed) {
246 case 10:
247 pll = QCA955X_PLL_VAL_10;
248 break;
249 case 100:
250 pll = QCA955X_PLL_VAL_100;
251 break;
252 case 1000:
253 pll = QCA955X_PLL_VAL_1000;
254 break;
255 default:
256 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
257 pll = 0;
258 }
259 return (pll);
260 }
261
262 static void
qca955x_chip_reset_ethernet_switch(void)263 qca955x_chip_reset_ethernet_switch(void)
264 {
265 #if 0
266 ar71xx_device_stop(AR934X_RESET_ETH_SWITCH);
267 DELAY(100);
268 ar71xx_device_start(AR934X_RESET_ETH_SWITCH);
269 DELAY(100);
270 #endif
271 }
272
273 static void
qca955x_configure_gmac(uint32_t gmac_cfg)274 qca955x_configure_gmac(uint32_t gmac_cfg)
275 {
276 uint32_t reg;
277
278 reg = ATH_READ_REG(QCA955X_GMAC_REG_ETH_CFG);
279 printf("%s: ETH_CFG=0x%08x\n", __func__, reg);
280 reg &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
281 reg |= gmac_cfg;
282 ATH_WRITE_REG(QCA955X_GMAC_REG_ETH_CFG, reg);
283 }
284
285 static void
qca955x_chip_init_usb_peripheral(void)286 qca955x_chip_init_usb_peripheral(void)
287 {
288 }
289
290 static void
qca955x_chip_set_mii_if(uint32_t unit,uint32_t mii_mode)291 qca955x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
292 {
293
294 /*
295 * XXX !
296 *
297 * Nothing to see here; although gmac0 can have its
298 * MII configuration changed, the register values
299 * are slightly different.
300 */
301 }
302
303 /*
304 * XXX TODO: fetch default MII divider configuration
305 */
306
307 static void
qca955x_chip_reset_wmac(void)308 qca955x_chip_reset_wmac(void)
309 {
310
311 /* XXX TODO */
312 }
313
314 static void
qca955x_chip_init_gmac(void)315 qca955x_chip_init_gmac(void)
316 {
317 long gmac_cfg;
318
319 if (resource_long_value("qca955x_gmac", 0, "gmac_cfg",
320 &gmac_cfg) == 0) {
321 printf("%s: gmac_cfg=0x%08lx\n",
322 __func__,
323 (long) gmac_cfg);
324 qca955x_configure_gmac((uint32_t) gmac_cfg);
325 }
326 }
327
328 /*
329 * Reset the NAND Flash Controller.
330 *
331 * + active=1 means "make it active".
332 * + active=0 means "make it inactive".
333 */
334 static void
qca955x_chip_reset_nfc(int active)335 qca955x_chip_reset_nfc(int active)
336 {
337 #if 0
338 if (active) {
339 ar71xx_device_start(AR934X_RESET_NANDF);
340 DELAY(100);
341
342 ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG);
343 DELAY(250);
344 } else {
345 ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG);
346 DELAY(250);
347
348 ar71xx_device_stop(AR934X_RESET_NANDF);
349 DELAY(100);
350 }
351 #endif
352 }
353
354 /*
355 * Configure the GPIO output mux setup.
356 *
357 * The QCA955x has an output mux which allowed
358 * certain functions to be configured on any pin.
359 * Specifically, the switch PHY link LEDs and
360 * WMAC external RX LNA switches are not limited to
361 * a specific GPIO pin.
362 */
363 static void
qca955x_chip_gpio_output_configure(int gpio,uint8_t func)364 qca955x_chip_gpio_output_configure(int gpio, uint8_t func)
365 {
366 uint32_t reg, s;
367 uint32_t t;
368
369 if (gpio > QCA955X_GPIO_COUNT)
370 return;
371
372 reg = QCA955X_GPIO_REG_OUT_FUNC0 + rounddown(gpio, 4);
373 s = 8 * (gpio % 4);
374
375 /* read-modify-write */
376 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
377 t &= ~(0xff << s);
378 t |= func << s;
379 ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
380
381 /* flush write */
382 ATH_READ_REG(AR71XX_GPIO_BASE + reg);
383 }
384
385 struct ar71xx_cpu_def qca955x_chip_def = {
386 &qca955x_chip_detect_mem_size,
387 &qca955x_chip_detect_sys_frequency,
388 &qca955x_chip_device_stop,
389 &qca955x_chip_device_start,
390 &qca955x_chip_device_stopped,
391 &qca955x_chip_set_pll_ge,
392 &qca955x_chip_set_mii_speed,
393 &qca955x_chip_set_mii_if,
394 &qca955x_chip_get_eth_pll,
395 &qca955x_chip_ddr_flush,
396 &qca955x_chip_init_usb_peripheral,
397 &qca955x_chip_reset_ethernet_switch,
398 &qca955x_chip_reset_wmac,
399 &qca955x_chip_init_gmac,
400 &qca955x_chip_reset_nfc,
401 &qca955x_chip_gpio_output_configure,
402 };
403