1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-2010 Juli Mallett <[email protected]> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _MACHINE_PTE_H_ 32 #define _MACHINE_PTE_H_ 33 34 #ifndef _LOCORE 35 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 36 typedef uint64_t pt_entry_t; 37 #else 38 typedef uint32_t pt_entry_t; 39 #endif 40 typedef pt_entry_t *pd_entry_t; 41 #endif 42 43 /* 44 * TLB and PTE management. Most things operate within the context of 45 * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi 46 * start with TLBHI_. PTE bits begin with PTE_. 47 * 48 * Note that we use the same size VM and TLB pages. 49 */ 50 #define TLB_PAGE_SHIFT (PAGE_SHIFT) 51 #define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT) 52 #define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1) 53 54 /* 55 * TLB PageMask register. Has mask bits set above the default, 4K, page mask. 56 */ 57 #define TLBMASK_SHIFT (13) 58 #define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT) 59 60 /* 61 * FreeBSD/mips page-table entries take a near-identical format to MIPS TLB 62 * entries, each consisting of two 32-bit or 64-bit values ("EntryHi" and 63 * "EntryLo"). MIPS4k and MIPS64 both define certain bits in TLB entries as 64 * reserved, and these must be zero-filled by software. We overload these 65 * bits in PTE entries to hold PTE_ flags such as RO, W, and MANAGED. 66 * However, we must mask these out when writing to TLB entries to ensure that 67 * they do not become visible to hardware -- especially on MIPS64r2 which has 68 * an extended physical memory space. 69 * 70 * When using n64 and n32, shift software-defined bits into the MIPS64r2 71 * reserved range, which runs from bit 55 ... 63. In other configurations 72 * (32-bit MIPS4k and compatible), shift them out to bits 29 ... 31. 73 * 74 * NOTE: This means that for 32-bit use of CP0, we aren't able to set the top 75 * bit of PFN to a non-zero value, as software is using it! This physical 76 * memory size limit may not be sufficiently enforced elsewhere. 77 */ 78 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 79 #define TLBLO_SWBITS_SHIFT (55) 80 #define TLBLO_SWBITS_CLEAR_SHIFT (9) 81 #define TLBLO_PFN_MASK 0x3FFFFFFC0ULL 82 #else 83 #define TLBLO_SWBITS_SHIFT (29) 84 #define TLBLO_SWBITS_CLEAR_SHIFT (3) 85 #define TLBLO_PFN_MASK (0x1FFFFFC0) 86 #endif 87 #define TLBLO_PFN_SHIFT (6) 88 #define TLBLO_SWBITS_MASK ((pt_entry_t)0x7 << TLBLO_SWBITS_SHIFT) 89 #define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK) 90 #define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT) 91 #define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK) 92 #define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte)))) 93 94 /* 95 * XXX This comment is not correct for anything more modern than R4K. 96 * 97 * VPN for EntryHi register. Upper two bits select user, supervisor, 98 * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to 99 * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12 100 * to bit 8 there is a 5-bit 0 field. Low byte is ASID. 101 * 102 * XXX This comment is not correct for FreeBSD. 103 * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. 104 */ 105 #define TLBHI_ASID_MASK (0xff) 106 #if defined(__mips_n64) 107 #define TLBHI_R_SHIFT 62 108 #define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT) 109 #define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT) 110 #define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT) 111 #define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT) 112 #define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK) 113 #define TLBHI_FILL_SHIFT 40 114 #define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1) 115 #define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT)) 116 #define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK) 117 #define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \ 118 (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \ 119 ((asid) & TLBHI_ASID_MASK)) 120 #else /* !defined(__mips_n64) */ 121 #define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) 122 #define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) 123 #endif /* defined(__mips_n64) */ 124 125 /* 126 * TLB flags managed in hardware: 127 * C: Cache attribute. 128 * D: Dirty bit. This means a page is writable. It is not 129 * set at first, and a write is trapped, and the dirty 130 * bit is set. See also PTE_RO. 131 * V: Valid bit. Obvious, isn't it? 132 * G: Global bit. This means that this mapping is present 133 * in EVERY address space, and to ignore the ASID when 134 * it is matched. 135 */ 136 #define PTE_C(attr) ((attr & 0x07) << 3) 137 #define PTE_C_MASK (PTE_C(0x07)) 138 #define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED)) 139 #define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED)) 140 #define PTE_C_WC (PTE_C(MIPS_CCA_WC)) 141 #define PTE_D 0x04 142 #define PTE_V 0x02 143 #define PTE_G 0x01 144 145 /* 146 * VM flags managed in software: 147 * RO: Read only. Never set PTE_D on this page, and don't 148 * listen to requests to write to it. 149 * W: Wired. ??? 150 * MANAGED:Managed. This PTE maps a managed page. 151 * 152 * These bits should not be written into the TLB, so must first be masked out 153 * explicitly in C, or using CLEAR_PTE_SWBITS() in assembly. 154 */ 155 #define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT) 156 #define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT) 157 #define PTE_MANAGED ((pt_entry_t)0x04 << TLBLO_SWBITS_SHIFT) 158 159 /* 160 * PTE management functions for bits defined above. 161 */ 162 #define pte_clear(pte, bit) (*(pte) &= ~(bit)) 163 #define pte_set(pte, bit) (*(pte) |= (bit)) 164 #define pte_test(pte, bit) ((*(pte) & (bit)) == (bit)) 165 #define pte_cache_bits(pte) ((*(pte) >> 3) & 0x07) 166 167 /* Assembly support for PTE access*/ 168 #ifdef LOCORE 169 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 170 #define PTESHIFT 3 171 #define PTE2MASK 0xff0 /* for the 2-page lo0/lo1 */ 172 #define PTEMASK 0xff8 173 #define PTESIZE 8 174 #define PTE_L ld 175 #define PTE_MTC0 dmtc0 176 #define CLEAR_PTE_SWBITS(pr) 177 #else 178 #define PTESHIFT 2 179 #define PTE2MASK 0xff8 /* for the 2-page lo0/lo1 */ 180 #define PTEMASK 0xffc 181 #define PTESIZE 4 182 #define PTE_L lw 183 #define PTE_MTC0 mtc0 184 #define CLEAR_PTE_SWBITS(r) LONG_SLL r, TLBLO_SWBITS_CLEAR_SHIFT; LONG_SRL r, TLBLO_SWBITS_CLEAR_SHIFT /* remove swbits */ 185 #endif /* defined(__mips_n64) || defined(__mips_n32) */ 186 187 #if defined(__mips_n64) 188 #define PTRSHIFT 3 189 #define PDEPTRMASK 0xff8 190 #else 191 #define PTRSHIFT 2 192 #define PDEPTRMASK 0xffc 193 #endif 194 195 #endif /* LOCORE */ 196 197 /* PageMask Register (CP0 Register 5, Select 0) Values */ 198 #define MIPS3_PGMASK_MASKX 0x00001800 199 #define MIPS3_PGMASK_4K 0x00000000 200 #define MIPS3_PGMASK_16K 0x00006000 201 #define MIPS3_PGMASK_64K 0x0001e000 202 #define MIPS3_PGMASK_256K 0x0007e000 203 #define MIPS3_PGMASK_1M 0x001fe000 204 #define MIPS3_PGMASK_4M 0x007fe000 205 #define MIPS3_PGMASK_16M 0x01ffe000 206 #define MIPS3_PGMASK_64M 0x07ffe000 207 #define MIPS3_PGMASK_256M 0x1fffe000 208 209 #endif /* !_MACHINE_PTE_H_ */ 210