1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2000 Berkeley Software Design, Inc.
5 * Copyright (c) 1997, 1998, 1999, 2000
6 * Bill Paul <[email protected]>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 /*
40 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
41 * from http://www.amd.com.
42 *
43 * The AMD PCnet/PCI controllers are more advanced and functional
44 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
45 * backwards compatibility with the LANCE and thus can be made
46 * to work with older LANCE drivers. This is in fact how the
47 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
48 * is that the PCnet/PCI devices offer several performance enhancements
49 * which can't be exploited in LANCE compatibility mode. Chief among
50 * these enhancements is the ability to perform PCI DMA operations
51 * using 32-bit addressing (which eliminates the need for ISA
52 * bounce-buffering), and special receive buffer alignment (which
53 * allows the receive handler to pass packets to the upper protocol
54 * layers without copying on both the x86 and alpha platforms).
55 */
56
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/sockio.h>
60 #include <sys/mbuf.h>
61 #include <sys/malloc.h>
62 #include <sys/kernel.h>
63 #include <sys/module.h>
64 #include <sys/socket.h>
65
66 #include <net/if.h>
67 #include <net/if_var.h>
68 #include <net/if_arp.h>
69 #include <net/ethernet.h>
70 #include <net/if_dl.h>
71 #include <net/if_media.h>
72 #include <net/if_types.h>
73
74 #include <net/bpf.h>
75
76 #include <vm/vm.h> /* for vtophys */
77 #include <vm/pmap.h> /* for vtophys */
78 #include <machine/bus.h>
79 #include <machine/resource.h>
80 #include <sys/bus.h>
81 #include <sys/rman.h>
82
83 #include <dev/mii/mii.h>
84 #include <dev/mii/miivar.h>
85
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88
89 #define PCN_USEIOSPACE
90
91 #include <dev/pcn/if_pcnreg.h>
92
93 MODULE_DEPEND(pcn, pci, 1, 1, 1);
94 MODULE_DEPEND(pcn, ether, 1, 1, 1);
95 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
96
97 /* "device miibus" required. See GENERIC if you get errors here. */
98 #include "miibus_if.h"
99
100 /*
101 * Various supported device vendors/types and their names.
102 */
103 static const struct pcn_type pcn_devs[] = {
104 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
105 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
106 { 0, 0, NULL }
107 };
108
109 static const struct pcn_chipid {
110 u_int32_t id;
111 const char *name;
112 } pcn_chipid[] = {
113 { Am79C971, "Am79C971" },
114 { Am79C972, "Am79C972" },
115 { Am79C973, "Am79C973" },
116 { Am79C978, "Am79C978" },
117 { Am79C975, "Am79C975" },
118 { Am79C976, "Am79C976" },
119 { 0, NULL },
120 };
121
122 static const char *pcn_chipid_name(u_int32_t);
123 static u_int32_t pcn_chip_id(device_t);
124 static const struct pcn_type *pcn_match(u_int16_t, u_int16_t);
125
126 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
127 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
128 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
129 static void pcn_csr_write(struct pcn_softc *, int, int);
130 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
131 static void pcn_bcr_write(struct pcn_softc *, int, int);
132
133 static int pcn_probe(device_t);
134 static int pcn_attach(device_t);
135 static int pcn_detach(device_t);
136
137 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
138 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
139 static void pcn_rxeof(struct pcn_softc *);
140 static void pcn_txeof(struct pcn_softc *);
141 static void pcn_intr(void *);
142 static void pcn_tick(void *);
143 static void pcn_start(struct ifnet *);
144 static void pcn_start_locked(struct ifnet *);
145 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
146 static void pcn_init(void *);
147 static void pcn_init_locked(struct pcn_softc *);
148 static void pcn_stop(struct pcn_softc *);
149 static void pcn_watchdog(struct pcn_softc *);
150 static int pcn_shutdown(device_t);
151 static int pcn_ifmedia_upd(struct ifnet *);
152 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
153
154 static int pcn_miibus_readreg(device_t, int, int);
155 static int pcn_miibus_writereg(device_t, int, int, int);
156 static void pcn_miibus_statchg(device_t);
157
158 static void pcn_setfilt(struct ifnet *);
159 static void pcn_setmulti(struct pcn_softc *);
160 static void pcn_reset(struct pcn_softc *);
161 static int pcn_list_rx_init(struct pcn_softc *);
162 static int pcn_list_tx_init(struct pcn_softc *);
163
164 #ifdef PCN_USEIOSPACE
165 #define PCN_RES SYS_RES_IOPORT
166 #define PCN_RID PCN_PCI_LOIO
167 #else
168 #define PCN_RES SYS_RES_MEMORY
169 #define PCN_RID PCN_PCI_LOMEM
170 #endif
171
172 static device_method_t pcn_methods[] = {
173 /* Device interface */
174 DEVMETHOD(device_probe, pcn_probe),
175 DEVMETHOD(device_attach, pcn_attach),
176 DEVMETHOD(device_detach, pcn_detach),
177 DEVMETHOD(device_shutdown, pcn_shutdown),
178
179 /* MII interface */
180 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
181 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
182 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
183
184 DEVMETHOD_END
185 };
186
187 static driver_t pcn_driver = {
188 "pcn",
189 pcn_methods,
190 sizeof(struct pcn_softc)
191 };
192
193 static devclass_t pcn_devclass;
194
195 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
196 MODULE_PNP_INFO("U16:vendor;U16:device", pci, pcn, pcn_devs,
197 nitems(pcn_devs) - 1);
198 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
199
200 #define PCN_CSR_SETBIT(sc, reg, x) \
201 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
202
203 #define PCN_CSR_CLRBIT(sc, reg, x) \
204 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
205
206 #define PCN_BCR_SETBIT(sc, reg, x) \
207 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
208
209 #define PCN_BCR_CLRBIT(sc, reg, x) \
210 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
211
212 static u_int32_t
pcn_csr_read(sc,reg)213 pcn_csr_read(sc, reg)
214 struct pcn_softc *sc;
215 int reg;
216 {
217 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
218 return(CSR_READ_4(sc, PCN_IO32_RDP));
219 }
220
221 static u_int16_t
pcn_csr_read16(sc,reg)222 pcn_csr_read16(sc, reg)
223 struct pcn_softc *sc;
224 int reg;
225 {
226 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
227 return(CSR_READ_2(sc, PCN_IO16_RDP));
228 }
229
230 static void
pcn_csr_write(sc,reg,val)231 pcn_csr_write(sc, reg, val)
232 struct pcn_softc *sc;
233 int reg;
234 int val;
235 {
236 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
237 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
238 return;
239 }
240
241 static u_int32_t
pcn_bcr_read(sc,reg)242 pcn_bcr_read(sc, reg)
243 struct pcn_softc *sc;
244 int reg;
245 {
246 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
247 return(CSR_READ_4(sc, PCN_IO32_BDP));
248 }
249
250 static u_int16_t
pcn_bcr_read16(sc,reg)251 pcn_bcr_read16(sc, reg)
252 struct pcn_softc *sc;
253 int reg;
254 {
255 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
256 return(CSR_READ_2(sc, PCN_IO16_BDP));
257 }
258
259 static void
pcn_bcr_write(sc,reg,val)260 pcn_bcr_write(sc, reg, val)
261 struct pcn_softc *sc;
262 int reg;
263 int val;
264 {
265 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
266 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
267 return;
268 }
269
270 static int
pcn_miibus_readreg(dev,phy,reg)271 pcn_miibus_readreg(dev, phy, reg)
272 device_t dev;
273 int phy, reg;
274 {
275 struct pcn_softc *sc;
276 int val;
277
278 sc = device_get_softc(dev);
279
280 /*
281 * At least Am79C971 with DP83840A wedge when isolating the
282 * external PHY so we can't allow multiple external PHYs.
283 * There are cards that use Am79C971 with both the internal
284 * and an external PHY though.
285 * For internal PHYs it doesn't really matter whether we can
286 * isolate the remaining internal and the external ones in
287 * the PHY drivers as the internal PHYs have to be enabled
288 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc.
289 * With Am79C97{3,5,8} we don't support switching beetween
290 * the internal and external PHYs, yet, so we can't allow
291 * multiple PHYs with these either.
292 * Am79C97{2,6} actually only support external PHYs (not
293 * connectable internal ones respond at the usual addresses,
294 * which don't hurt if we let them show up on the bus) and
295 * isolating them works.
296 */
297 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
298 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
299 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 &&
300 phy != sc->pcn_extphyaddr)
301 return(0);
302
303 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
304 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
305 if (val == 0xFFFF)
306 return(0);
307
308 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
309 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
310 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1)
311 sc->pcn_extphyaddr = phy;
312
313 return(val);
314 }
315
316 static int
pcn_miibus_writereg(dev,phy,reg,data)317 pcn_miibus_writereg(dev, phy, reg, data)
318 device_t dev;
319 int phy, reg, data;
320 {
321 struct pcn_softc *sc;
322
323 sc = device_get_softc(dev);
324
325 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
326 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
327
328 return(0);
329 }
330
331 static void
pcn_miibus_statchg(dev)332 pcn_miibus_statchg(dev)
333 device_t dev;
334 {
335 struct pcn_softc *sc;
336 struct mii_data *mii;
337
338 sc = device_get_softc(dev);
339 mii = device_get_softc(sc->pcn_miibus);
340
341 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
342 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
343 } else {
344 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
345 }
346
347 return;
348 }
349
350 static void
pcn_setmulti(sc)351 pcn_setmulti(sc)
352 struct pcn_softc *sc;
353 {
354 struct ifnet *ifp;
355 struct ifmultiaddr *ifma;
356 u_int32_t h, i;
357 u_int16_t hashes[4] = { 0, 0, 0, 0 };
358
359 ifp = sc->pcn_ifp;
360
361 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
362
363 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
364 for (i = 0; i < 4; i++)
365 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
366 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
367 return;
368 }
369
370 /* first, zot all the existing hash bits */
371 for (i = 0; i < 4; i++)
372 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
373
374 /* now program new ones */
375 if_maddr_rlock(ifp);
376 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
377 if (ifma->ifma_addr->sa_family != AF_LINK)
378 continue;
379 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
380 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
381 hashes[h >> 4] |= 1 << (h & 0xF);
382 }
383 if_maddr_runlock(ifp);
384
385 for (i = 0; i < 4; i++)
386 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
387
388 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
389
390 return;
391 }
392
393 static void
pcn_reset(sc)394 pcn_reset(sc)
395 struct pcn_softc *sc;
396 {
397 /*
398 * Issue a reset by reading from the RESET register.
399 * Note that we don't know if the chip is operating in
400 * 16-bit or 32-bit mode at this point, so we attempt
401 * to reset the chip both ways. If one fails, the other
402 * will succeed.
403 */
404 CSR_READ_2(sc, PCN_IO16_RESET);
405 CSR_READ_4(sc, PCN_IO32_RESET);
406
407 /* Wait a little while for the chip to get its brains in order. */
408 DELAY(1000);
409
410 /* Select 32-bit (DWIO) mode */
411 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
412
413 /* Select software style 3. */
414 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
415
416 return;
417 }
418
419 static const char *
pcn_chipid_name(u_int32_t id)420 pcn_chipid_name(u_int32_t id)
421 {
422 const struct pcn_chipid *p;
423
424 p = pcn_chipid;
425 while (p->name) {
426 if (id == p->id)
427 return (p->name);
428 p++;
429 }
430 return ("Unknown");
431 }
432
433 static u_int32_t
pcn_chip_id(device_t dev)434 pcn_chip_id(device_t dev)
435 {
436 struct pcn_softc *sc;
437 u_int32_t chip_id;
438
439 sc = device_get_softc(dev);
440 /*
441 * Note: we can *NOT* put the chip into
442 * 32-bit mode yet. The le(4) driver will only
443 * work in 16-bit mode, and once the chip
444 * goes into 32-bit mode, the only way to
445 * get it out again is with a hardware reset.
446 * So if pcn_probe() is called before the
447 * le(4) driver's probe routine, the chip will
448 * be locked into 32-bit operation and the
449 * le(4) driver will be unable to attach to it.
450 * Note II: if the chip happens to already
451 * be in 32-bit mode, we still need to check
452 * the chip ID, but first we have to detect
453 * 32-bit mode using only 16-bit operations.
454 * The safest way to do this is to read the
455 * PCI subsystem ID from BCR23/24 and compare
456 * that with the value read from PCI config
457 * space.
458 */
459 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
460 chip_id <<= 16;
461 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
462 /*
463 * Note III: the test for 0x10001000 is a hack to
464 * pacify VMware, who's pseudo-PCnet interface is
465 * broken. Reading the subsystem register from PCI
466 * config space yields 0x00000000 while reading the
467 * same value from I/O space yields 0x10001000. It's
468 * not supposed to be that way.
469 */
470 if (chip_id == pci_read_config(dev,
471 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
472 /* We're in 16-bit mode. */
473 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
474 chip_id <<= 16;
475 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
476 } else {
477 /* We're in 32-bit mode. */
478 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
479 chip_id <<= 16;
480 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
481 }
482
483 return (chip_id);
484 }
485
486 static const struct pcn_type *
pcn_match(u_int16_t vid,u_int16_t did)487 pcn_match(u_int16_t vid, u_int16_t did)
488 {
489 const struct pcn_type *t;
490
491 t = pcn_devs;
492 while (t->pcn_name != NULL) {
493 if ((vid == t->pcn_vid) && (did == t->pcn_did))
494 return (t);
495 t++;
496 }
497 return (NULL);
498 }
499
500 /*
501 * Probe for an AMD chip. Check the PCI vendor and device
502 * IDs against our list and return a device name if we find a match.
503 */
504 static int
pcn_probe(dev)505 pcn_probe(dev)
506 device_t dev;
507 {
508 const struct pcn_type *t;
509 struct pcn_softc *sc;
510 int rid;
511 u_int32_t chip_id;
512
513 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
514 if (t == NULL)
515 return (ENXIO);
516 sc = device_get_softc(dev);
517
518 /*
519 * Temporarily map the I/O space so we can read the chip ID register.
520 */
521 rid = PCN_RID;
522 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
523 if (sc->pcn_res == NULL) {
524 device_printf(dev, "couldn't map ports/memory\n");
525 return(ENXIO);
526 }
527 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
528 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
529
530 chip_id = pcn_chip_id(dev);
531
532 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
533
534 switch((chip_id >> 12) & PART_MASK) {
535 case Am79C971:
536 case Am79C972:
537 case Am79C973:
538 case Am79C975:
539 case Am79C976:
540 case Am79C978:
541 break;
542 default:
543 return(ENXIO);
544 }
545 device_set_desc(dev, t->pcn_name);
546 return(BUS_PROBE_DEFAULT);
547 }
548
549 /*
550 * Attach the interface. Allocate softc structures, do ifmedia
551 * setup and ethernet/BPF attach.
552 */
553 static int
pcn_attach(dev)554 pcn_attach(dev)
555 device_t dev;
556 {
557 u_int32_t eaddr[2];
558 struct pcn_softc *sc;
559 struct mii_data *mii;
560 struct mii_softc *miisc;
561 struct ifnet *ifp;
562 int error = 0, rid;
563
564 sc = device_get_softc(dev);
565
566 /* Initialize our mutex. */
567 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
568 MTX_DEF);
569 /*
570 * Map control/status registers.
571 */
572 pci_enable_busmaster(dev);
573
574 /* Retrieve the chip ID */
575 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
576 device_printf(dev, "Chip ID %04x (%s)\n",
577 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
578
579 rid = PCN_RID;
580 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
581
582 if (sc->pcn_res == NULL) {
583 device_printf(dev, "couldn't map ports/memory\n");
584 error = ENXIO;
585 goto fail;
586 }
587
588 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
589 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
590
591 /* Allocate interrupt */
592 rid = 0;
593 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
594 RF_SHAREABLE | RF_ACTIVE);
595
596 if (sc->pcn_irq == NULL) {
597 device_printf(dev, "couldn't map interrupt\n");
598 error = ENXIO;
599 goto fail;
600 }
601
602 /* Reset the adapter. */
603 pcn_reset(sc);
604
605 /*
606 * Get station address from the EEPROM.
607 */
608 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
609 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
610
611 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0);
612
613 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
614 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
615
616 if (sc->pcn_ldata == NULL) {
617 device_printf(dev, "no memory for list buffers!\n");
618 error = ENXIO;
619 goto fail;
620 }
621 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
622
623 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
624 if (ifp == NULL) {
625 device_printf(dev, "can not if_alloc()\n");
626 error = ENOSPC;
627 goto fail;
628 }
629 ifp->if_softc = sc;
630 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
631 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
632 ifp->if_ioctl = pcn_ioctl;
633 ifp->if_start = pcn_start;
634 ifp->if_init = pcn_init;
635 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
636
637 /*
638 * Do MII setup.
639 * See the comment in pcn_miibus_readreg() for why we can't
640 * universally pass MIIF_NOISOLATE here.
641 */
642 sc->pcn_extphyaddr = -1;
643 error = mii_attach(dev, &sc->pcn_miibus, ifp, pcn_ifmedia_upd,
644 pcn_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
645 if (error != 0) {
646 device_printf(dev, "attaching PHYs failed\n");
647 goto fail;
648 }
649 /*
650 * Record the media instances of internal PHYs, which map the
651 * built-in interfaces to the MII, so we can set the active
652 * PHY/port based on the currently selected media.
653 */
654 sc->pcn_inst_10bt = -1;
655 mii = device_get_softc(sc->pcn_miibus);
656 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
657 switch (miisc->mii_phy) {
658 case PCN_PHYAD_10BT:
659 sc->pcn_inst_10bt = miisc->mii_inst;
660 break;
661 /*
662 * XXX deal with the Am79C97{3,5} internal 100baseT
663 * and the Am79C978 internal HomePNA PHYs.
664 */
665 }
666 }
667
668 /*
669 * Call MI attach routine.
670 */
671 ether_ifattach(ifp, (u_int8_t *) eaddr);
672
673 /* Hook interrupt last to avoid having to lock softc */
674 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE,
675 NULL, pcn_intr, sc, &sc->pcn_intrhand);
676
677 if (error) {
678 device_printf(dev, "couldn't set up irq\n");
679 ether_ifdetach(ifp);
680 goto fail;
681 }
682
683 fail:
684 if (error)
685 pcn_detach(dev);
686
687 gone_by_fcp101_dev(dev);
688
689 return(error);
690 }
691
692 /*
693 * Shutdown hardware and free up resources. This can be called any
694 * time after the mutex has been initialized. It is called in both
695 * the error case in attach and the normal detach case so it needs
696 * to be careful about only freeing resources that have actually been
697 * allocated.
698 */
699 static int
pcn_detach(dev)700 pcn_detach(dev)
701 device_t dev;
702 {
703 struct pcn_softc *sc;
704 struct ifnet *ifp;
705
706 sc = device_get_softc(dev);
707 ifp = sc->pcn_ifp;
708
709 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
710
711 /* These should only be active if attach succeeded */
712 if (device_is_attached(dev)) {
713 PCN_LOCK(sc);
714 pcn_reset(sc);
715 pcn_stop(sc);
716 PCN_UNLOCK(sc);
717 callout_drain(&sc->pcn_stat_callout);
718 ether_ifdetach(ifp);
719 }
720 if (sc->pcn_miibus)
721 device_delete_child(dev, sc->pcn_miibus);
722 bus_generic_detach(dev);
723
724 if (sc->pcn_intrhand)
725 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
726 if (sc->pcn_irq)
727 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
728 if (sc->pcn_res)
729 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
730
731 if (ifp)
732 if_free(ifp);
733
734 if (sc->pcn_ldata) {
735 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
736 M_DEVBUF);
737 }
738
739 mtx_destroy(&sc->pcn_mtx);
740
741 return(0);
742 }
743
744 /*
745 * Initialize the transmit descriptors.
746 */
747 static int
pcn_list_tx_init(sc)748 pcn_list_tx_init(sc)
749 struct pcn_softc *sc;
750 {
751 struct pcn_list_data *ld;
752 struct pcn_ring_data *cd;
753 int i;
754
755 cd = &sc->pcn_cdata;
756 ld = sc->pcn_ldata;
757
758 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
759 cd->pcn_tx_chain[i] = NULL;
760 ld->pcn_tx_list[i].pcn_tbaddr = 0;
761 ld->pcn_tx_list[i].pcn_txctl = 0;
762 ld->pcn_tx_list[i].pcn_txstat = 0;
763 }
764
765 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
766
767 return(0);
768 }
769
770
771 /*
772 * Initialize the RX descriptors and allocate mbufs for them.
773 */
774 static int
pcn_list_rx_init(sc)775 pcn_list_rx_init(sc)
776 struct pcn_softc *sc;
777 {
778 struct pcn_ring_data *cd;
779 int i;
780
781 cd = &sc->pcn_cdata;
782
783 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
784 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
785 return(ENOBUFS);
786 }
787
788 cd->pcn_rx_prod = 0;
789
790 return(0);
791 }
792
793 /*
794 * Initialize an RX descriptor and attach an MBUF cluster.
795 */
796 static int
pcn_newbuf(sc,idx,m)797 pcn_newbuf(sc, idx, m)
798 struct pcn_softc *sc;
799 int idx;
800 struct mbuf *m;
801 {
802 struct mbuf *m_new = NULL;
803 struct pcn_rx_desc *c;
804
805 c = &sc->pcn_ldata->pcn_rx_list[idx];
806
807 if (m == NULL) {
808 MGETHDR(m_new, M_NOWAIT, MT_DATA);
809 if (m_new == NULL)
810 return(ENOBUFS);
811
812 if (!(MCLGET(m_new, M_NOWAIT))) {
813 m_freem(m_new);
814 return(ENOBUFS);
815 }
816 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
817 } else {
818 m_new = m;
819 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
820 m_new->m_data = m_new->m_ext.ext_buf;
821 }
822
823 m_adj(m_new, ETHER_ALIGN);
824
825 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
826 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
827 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
828 c->pcn_bufsz |= PCN_RXLEN_MBO;
829 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
830
831 return(0);
832 }
833
834 /*
835 * A frame has been uploaded: pass the resulting mbuf chain up to
836 * the higher level protocols.
837 */
838 static void
pcn_rxeof(sc)839 pcn_rxeof(sc)
840 struct pcn_softc *sc;
841 {
842 struct mbuf *m;
843 struct ifnet *ifp;
844 struct pcn_rx_desc *cur_rx;
845 int i;
846
847 PCN_LOCK_ASSERT(sc);
848
849 ifp = sc->pcn_ifp;
850 i = sc->pcn_cdata.pcn_rx_prod;
851
852 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
853 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
854 m = sc->pcn_cdata.pcn_rx_chain[i];
855 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
856
857 /*
858 * If an error occurs, update stats, clear the
859 * status word and leave the mbuf cluster in place:
860 * it should simply get re-used next time this descriptor
861 * comes up in the ring.
862 */
863 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
864 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
865 pcn_newbuf(sc, i, m);
866 PCN_INC(i, PCN_RX_LIST_CNT);
867 continue;
868 }
869
870 if (pcn_newbuf(sc, i, NULL)) {
871 /* Ran out of mbufs; recycle this one. */
872 pcn_newbuf(sc, i, m);
873 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
874 PCN_INC(i, PCN_RX_LIST_CNT);
875 continue;
876 }
877
878 PCN_INC(i, PCN_RX_LIST_CNT);
879
880 /* No errors; receive the packet. */
881 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
882 m->m_len = m->m_pkthdr.len =
883 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
884 m->m_pkthdr.rcvif = ifp;
885
886 PCN_UNLOCK(sc);
887 (*ifp->if_input)(ifp, m);
888 PCN_LOCK(sc);
889 }
890
891 sc->pcn_cdata.pcn_rx_prod = i;
892
893 return;
894 }
895
896 /*
897 * A frame was downloaded to the chip. It's safe for us to clean up
898 * the list buffers.
899 */
900
901 static void
pcn_txeof(sc)902 pcn_txeof(sc)
903 struct pcn_softc *sc;
904 {
905 struct pcn_tx_desc *cur_tx = NULL;
906 struct ifnet *ifp;
907 u_int32_t idx;
908
909 ifp = sc->pcn_ifp;
910
911 /*
912 * Go through our tx list and free mbufs for those
913 * frames that have been transmitted.
914 */
915 idx = sc->pcn_cdata.pcn_tx_cons;
916 while (idx != sc->pcn_cdata.pcn_tx_prod) {
917 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
918
919 if (!PCN_OWN_TXDESC(cur_tx))
920 break;
921
922 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
923 sc->pcn_cdata.pcn_tx_cnt--;
924 PCN_INC(idx, PCN_TX_LIST_CNT);
925 continue;
926 }
927
928 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
929 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
930 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
931 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
932 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
933 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
934 }
935
936 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
937 cur_tx->pcn_txstat & PCN_TXSTAT_TRC);
938
939 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
940 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
941 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
942 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
943 }
944
945 sc->pcn_cdata.pcn_tx_cnt--;
946 PCN_INC(idx, PCN_TX_LIST_CNT);
947 }
948
949 if (idx != sc->pcn_cdata.pcn_tx_cons) {
950 /* Some buffers have been freed. */
951 sc->pcn_cdata.pcn_tx_cons = idx;
952 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
953 }
954 sc->pcn_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
955
956 return;
957 }
958
959 static void
pcn_tick(xsc)960 pcn_tick(xsc)
961 void *xsc;
962 {
963 struct pcn_softc *sc;
964 struct mii_data *mii;
965 struct ifnet *ifp;
966
967 sc = xsc;
968 ifp = sc->pcn_ifp;
969 PCN_LOCK_ASSERT(sc);
970
971 mii = device_get_softc(sc->pcn_miibus);
972 mii_tick(mii);
973
974 /* link just died */
975 if (sc->pcn_link && !(mii->mii_media_status & IFM_ACTIVE))
976 sc->pcn_link = 0;
977
978 /* link just came up, restart */
979 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
980 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
981 sc->pcn_link++;
982 if (ifp->if_snd.ifq_head != NULL)
983 pcn_start_locked(ifp);
984 }
985
986 if (sc->pcn_timer > 0 && --sc->pcn_timer == 0)
987 pcn_watchdog(sc);
988 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
989
990 return;
991 }
992
993 static void
pcn_intr(arg)994 pcn_intr(arg)
995 void *arg;
996 {
997 struct pcn_softc *sc;
998 struct ifnet *ifp;
999 u_int32_t status;
1000
1001 sc = arg;
1002 ifp = sc->pcn_ifp;
1003
1004 PCN_LOCK(sc);
1005
1006 /* Suppress unwanted interrupts */
1007 if (!(ifp->if_flags & IFF_UP)) {
1008 pcn_stop(sc);
1009 PCN_UNLOCK(sc);
1010 return;
1011 }
1012
1013 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
1014
1015 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
1016 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
1017
1018 if (status & PCN_CSR_RINT)
1019 pcn_rxeof(sc);
1020
1021 if (status & PCN_CSR_TINT)
1022 pcn_txeof(sc);
1023
1024 if (status & PCN_CSR_ERR) {
1025 pcn_init_locked(sc);
1026 break;
1027 }
1028 }
1029
1030 if (ifp->if_snd.ifq_head != NULL)
1031 pcn_start_locked(ifp);
1032
1033 PCN_UNLOCK(sc);
1034 return;
1035 }
1036
1037 /*
1038 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1039 * pointers to the fragment pointers.
1040 */
1041 static int
pcn_encap(sc,m_head,txidx)1042 pcn_encap(sc, m_head, txidx)
1043 struct pcn_softc *sc;
1044 struct mbuf *m_head;
1045 u_int32_t *txidx;
1046 {
1047 struct pcn_tx_desc *f = NULL;
1048 struct mbuf *m;
1049 int frag, cur, cnt = 0;
1050
1051 /*
1052 * Start packing the mbufs in this chain into
1053 * the fragment pointers. Stop when we run out
1054 * of fragments or hit the end of the mbuf chain.
1055 */
1056 m = m_head;
1057 cur = frag = *txidx;
1058
1059 for (m = m_head; m != NULL; m = m->m_next) {
1060 if (m->m_len == 0)
1061 continue;
1062
1063 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1064 return(ENOBUFS);
1065 f = &sc->pcn_ldata->pcn_tx_list[frag];
1066 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1067 f->pcn_txctl |= PCN_TXCTL_MBO;
1068 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1069 if (cnt == 0)
1070 f->pcn_txctl |= PCN_TXCTL_STP;
1071 else
1072 f->pcn_txctl |= PCN_TXCTL_OWN;
1073 cur = frag;
1074 PCN_INC(frag, PCN_TX_LIST_CNT);
1075 cnt++;
1076 }
1077
1078 if (m != NULL)
1079 return(ENOBUFS);
1080
1081 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1082 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1083 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1084 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1085 sc->pcn_cdata.pcn_tx_cnt += cnt;
1086 *txidx = frag;
1087
1088 return(0);
1089 }
1090
1091 /*
1092 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1093 * to the mbuf data regions directly in the transmit lists. We also save a
1094 * copy of the pointers since the transmit list fragment pointers are
1095 * physical addresses.
1096 */
1097 static void
pcn_start(ifp)1098 pcn_start(ifp)
1099 struct ifnet *ifp;
1100 {
1101 struct pcn_softc *sc;
1102
1103 sc = ifp->if_softc;
1104 PCN_LOCK(sc);
1105 pcn_start_locked(ifp);
1106 PCN_UNLOCK(sc);
1107 }
1108
1109 static void
pcn_start_locked(ifp)1110 pcn_start_locked(ifp)
1111 struct ifnet *ifp;
1112 {
1113 struct pcn_softc *sc;
1114 struct mbuf *m_head = NULL;
1115 u_int32_t idx;
1116
1117 sc = ifp->if_softc;
1118
1119 PCN_LOCK_ASSERT(sc);
1120
1121 if (!sc->pcn_link)
1122 return;
1123
1124 idx = sc->pcn_cdata.pcn_tx_prod;
1125
1126 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1127 return;
1128
1129 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1130 IF_DEQUEUE(&ifp->if_snd, m_head);
1131 if (m_head == NULL)
1132 break;
1133
1134 if (pcn_encap(sc, m_head, &idx)) {
1135 IF_PREPEND(&ifp->if_snd, m_head);
1136 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1137 break;
1138 }
1139
1140 /*
1141 * If there's a BPF listener, bounce a copy of this frame
1142 * to him.
1143 */
1144 BPF_MTAP(ifp, m_head);
1145
1146 }
1147
1148 /* Transmit */
1149 sc->pcn_cdata.pcn_tx_prod = idx;
1150 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1151
1152 /*
1153 * Set a timeout in case the chip goes out to lunch.
1154 */
1155 sc->pcn_timer = 5;
1156
1157 return;
1158 }
1159
1160 static void
pcn_setfilt(ifp)1161 pcn_setfilt(ifp)
1162 struct ifnet *ifp;
1163 {
1164 struct pcn_softc *sc;
1165
1166 sc = ifp->if_softc;
1167
1168 /* If we want promiscuous mode, set the allframes bit. */
1169 if (ifp->if_flags & IFF_PROMISC) {
1170 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1171 } else {
1172 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1173 }
1174
1175 /* Set the capture broadcast bit to capture broadcast frames. */
1176 if (ifp->if_flags & IFF_BROADCAST) {
1177 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1178 } else {
1179 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1180 }
1181
1182 return;
1183 }
1184
1185 static void
pcn_init(xsc)1186 pcn_init(xsc)
1187 void *xsc;
1188 {
1189 struct pcn_softc *sc = xsc;
1190
1191 PCN_LOCK(sc);
1192 pcn_init_locked(sc);
1193 PCN_UNLOCK(sc);
1194 }
1195
1196 static void
pcn_init_locked(sc)1197 pcn_init_locked(sc)
1198 struct pcn_softc *sc;
1199 {
1200 struct ifnet *ifp = sc->pcn_ifp;
1201 struct mii_data *mii = NULL;
1202 struct ifmedia_entry *ife;
1203
1204 PCN_LOCK_ASSERT(sc);
1205
1206 /*
1207 * Cancel pending I/O and free all RX/TX buffers.
1208 */
1209 pcn_stop(sc);
1210 pcn_reset(sc);
1211
1212 mii = device_get_softc(sc->pcn_miibus);
1213 ife = mii->mii_media.ifm_cur;
1214
1215 /* Set MAC address */
1216 pcn_csr_write(sc, PCN_CSR_PAR0,
1217 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]);
1218 pcn_csr_write(sc, PCN_CSR_PAR1,
1219 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]);
1220 pcn_csr_write(sc, PCN_CSR_PAR2,
1221 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]);
1222
1223 /* Init circular RX list. */
1224 if (pcn_list_rx_init(sc) == ENOBUFS) {
1225 if_printf(ifp, "initialization failed: no "
1226 "memory for rx buffers\n");
1227 pcn_stop(sc);
1228 return;
1229 }
1230
1231 /*
1232 * Init tx descriptors.
1233 */
1234 pcn_list_tx_init(sc);
1235
1236 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */
1237 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL);
1238
1239 /*
1240 * Set up the port based on the currently selected media.
1241 * For Am79C978 we've to unconditionally set PCN_PORT_MII and
1242 * set the PHY in PCN_BCR_PHYSEL instead.
1243 */
1244 if (sc->pcn_type != Am79C978 &&
1245 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt)
1246 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET);
1247 else
1248 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1249
1250 /* Set up RX filter. */
1251 pcn_setfilt(ifp);
1252
1253 /*
1254 * Load the multicast filter.
1255 */
1256 pcn_setmulti(sc);
1257
1258 /*
1259 * Load the addresses of the RX and TX lists.
1260 */
1261 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1262 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1263 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1264 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1265 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1266 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1267 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1268 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1269
1270 /* Set the RX and TX ring sizes. */
1271 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1272 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1273
1274 /* We're not using the initialization block. */
1275 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1276
1277 /* Enable fast suspend mode. */
1278 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1279
1280 /*
1281 * Enable burst read and write. Also set the no underflow
1282 * bit. This will avoid transmit underruns in certain
1283 * conditions while still providing decent performance.
1284 */
1285 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1286 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1287
1288 /* Enable graceful recovery from underflow. */
1289 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1290
1291 /* Enable auto-padding of short TX frames. */
1292 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1293
1294 /* Disable MII autoneg (we handle this ourselves). */
1295 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1296
1297 if (sc->pcn_type == Am79C978)
1298 /* XXX support other PHYs? */
1299 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1300 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1301
1302 /* Enable interrupts and start the controller running. */
1303 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1304
1305 mii_mediachg(mii);
1306
1307 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1308 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1309
1310 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
1311
1312 return;
1313 }
1314
1315 /*
1316 * Set media options.
1317 */
1318 static int
pcn_ifmedia_upd(ifp)1319 pcn_ifmedia_upd(ifp)
1320 struct ifnet *ifp;
1321 {
1322 struct pcn_softc *sc;
1323
1324 sc = ifp->if_softc;
1325
1326 PCN_LOCK(sc);
1327
1328 /*
1329 * At least Am79C971 with DP83840A can wedge when switching
1330 * from the internal 10baseT PHY to the external PHY without
1331 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE
1332 * the PCnet chip has to be powered down or stopped anyway
1333 * and although documented otherwise it doesn't take effect
1334 * until the next initialization.
1335 */
1336 sc->pcn_link = 0;
1337 pcn_stop(sc);
1338 pcn_reset(sc);
1339 pcn_init_locked(sc);
1340 if (ifp->if_snd.ifq_head != NULL)
1341 pcn_start_locked(ifp);
1342
1343 PCN_UNLOCK(sc);
1344
1345 return(0);
1346 }
1347
1348 /*
1349 * Report current media status.
1350 */
1351 static void
pcn_ifmedia_sts(ifp,ifmr)1352 pcn_ifmedia_sts(ifp, ifmr)
1353 struct ifnet *ifp;
1354 struct ifmediareq *ifmr;
1355 {
1356 struct pcn_softc *sc;
1357 struct mii_data *mii;
1358
1359 sc = ifp->if_softc;
1360
1361 mii = device_get_softc(sc->pcn_miibus);
1362 PCN_LOCK(sc);
1363 mii_pollstat(mii);
1364 ifmr->ifm_active = mii->mii_media_active;
1365 ifmr->ifm_status = mii->mii_media_status;
1366 PCN_UNLOCK(sc);
1367
1368 return;
1369 }
1370
1371 static int
pcn_ioctl(ifp,command,data)1372 pcn_ioctl(ifp, command, data)
1373 struct ifnet *ifp;
1374 u_long command;
1375 caddr_t data;
1376 {
1377 struct pcn_softc *sc = ifp->if_softc;
1378 struct ifreq *ifr = (struct ifreq *) data;
1379 struct mii_data *mii = NULL;
1380 int error = 0;
1381
1382 switch(command) {
1383 case SIOCSIFFLAGS:
1384 PCN_LOCK(sc);
1385 if (ifp->if_flags & IFF_UP) {
1386 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1387 ifp->if_flags & IFF_PROMISC &&
1388 !(sc->pcn_if_flags & IFF_PROMISC)) {
1389 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1390 PCN_EXTCTL1_SPND);
1391 pcn_setfilt(ifp);
1392 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1393 PCN_EXTCTL1_SPND);
1394 pcn_csr_write(sc, PCN_CSR_CSR,
1395 PCN_CSR_INTEN|PCN_CSR_START);
1396 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1397 !(ifp->if_flags & IFF_PROMISC) &&
1398 sc->pcn_if_flags & IFF_PROMISC) {
1399 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1400 PCN_EXTCTL1_SPND);
1401 pcn_setfilt(ifp);
1402 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1403 PCN_EXTCTL1_SPND);
1404 pcn_csr_write(sc, PCN_CSR_CSR,
1405 PCN_CSR_INTEN|PCN_CSR_START);
1406 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1407 pcn_init_locked(sc);
1408 } else {
1409 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1410 pcn_stop(sc);
1411 }
1412 sc->pcn_if_flags = ifp->if_flags;
1413 PCN_UNLOCK(sc);
1414 error = 0;
1415 break;
1416 case SIOCADDMULTI:
1417 case SIOCDELMULTI:
1418 PCN_LOCK(sc);
1419 pcn_setmulti(sc);
1420 PCN_UNLOCK(sc);
1421 error = 0;
1422 break;
1423 case SIOCGIFMEDIA:
1424 case SIOCSIFMEDIA:
1425 mii = device_get_softc(sc->pcn_miibus);
1426 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1427 break;
1428 default:
1429 error = ether_ioctl(ifp, command, data);
1430 break;
1431 }
1432
1433 return(error);
1434 }
1435
1436 static void
pcn_watchdog(struct pcn_softc * sc)1437 pcn_watchdog(struct pcn_softc *sc)
1438 {
1439 struct ifnet *ifp;
1440
1441 PCN_LOCK_ASSERT(sc);
1442 ifp = sc->pcn_ifp;
1443
1444 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1445 if_printf(ifp, "watchdog timeout\n");
1446
1447 pcn_stop(sc);
1448 pcn_reset(sc);
1449 pcn_init_locked(sc);
1450
1451 if (ifp->if_snd.ifq_head != NULL)
1452 pcn_start_locked(ifp);
1453 }
1454
1455 /*
1456 * Stop the adapter and free any mbufs allocated to the
1457 * RX and TX lists.
1458 */
1459 static void
pcn_stop(struct pcn_softc * sc)1460 pcn_stop(struct pcn_softc *sc)
1461 {
1462 int i;
1463 struct ifnet *ifp;
1464
1465 PCN_LOCK_ASSERT(sc);
1466 ifp = sc->pcn_ifp;
1467 sc->pcn_timer = 0;
1468
1469 callout_stop(&sc->pcn_stat_callout);
1470
1471 /* Turn off interrupts */
1472 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1473 /* Stop adapter */
1474 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1475 sc->pcn_link = 0;
1476
1477 /*
1478 * Free data in the RX lists.
1479 */
1480 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1481 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1482 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1483 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1484 }
1485 }
1486 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1487 sizeof(sc->pcn_ldata->pcn_rx_list));
1488
1489 /*
1490 * Free the TX list buffers.
1491 */
1492 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1493 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1494 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1495 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1496 }
1497 }
1498
1499 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1500 sizeof(sc->pcn_ldata->pcn_tx_list));
1501
1502 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1503
1504 return;
1505 }
1506
1507 /*
1508 * Stop all chip I/O so that the kernel's probe routines don't
1509 * get confused by errant DMAs when rebooting.
1510 */
1511 static int
pcn_shutdown(device_t dev)1512 pcn_shutdown(device_t dev)
1513 {
1514 struct pcn_softc *sc;
1515
1516 sc = device_get_softc(dev);
1517
1518 PCN_LOCK(sc);
1519 pcn_reset(sc);
1520 pcn_stop(sc);
1521 PCN_UNLOCK(sc);
1522
1523 return 0;
1524 }
1525