1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #include <rte_common.h>
6 #include <rte_cycles.h>
7 #include <rte_io.h>
8 #include <ethdev_driver.h>
9 #include <ethdev_pci.h>
10
11 #include "otx_ep_common.h"
12 #include "otx_ep_vf.h"
13
14
15 static void
otx_ep_setup_global_iq_reg(struct otx_ep_device * otx_ep,int q_no)16 otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
17 {
18 volatile uint64_t reg_val = 0ull;
19
20 /* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs
21 * IS_64B is by default enabled.
22 */
23 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));
24
25 reg_val |= OTX_EP_R_IN_CTL_RDSIZE;
26 reg_val |= OTX_EP_R_IN_CTL_IS_64B;
27 reg_val |= OTX_EP_R_IN_CTL_ESR;
28
29 otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_CONTROL(q_no));
30 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(q_no));
31
32 if (!(reg_val & OTX_EP_R_IN_CTL_IDLE)) {
33 do {
34 reg_val = rte_read64(otx_ep->hw_addr +
35 OTX_EP_R_IN_CONTROL(q_no));
36 } while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));
37 }
38 }
39
40 static void
otx_ep_setup_global_oq_reg(struct otx_ep_device * otx_ep,int q_no)41 otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
42 {
43 volatile uint64_t reg_val = 0ull;
44
45 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(q_no));
46
47 reg_val &= ~(OTX_EP_R_OUT_CTL_IMODE);
48 reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_P);
49 reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_P);
50 reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_I);
51 reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_I);
52 reg_val &= ~(OTX_EP_R_OUT_CTL_ES_I);
53 reg_val &= ~(OTX_EP_R_OUT_CTL_ROR_D);
54 reg_val &= ~(OTX_EP_R_OUT_CTL_NSR_D);
55 reg_val &= ~(OTX_EP_R_OUT_CTL_ES_D);
56
57 /* INFO/DATA ptr swap is required */
58 reg_val |= (OTX_EP_R_OUT_CTL_ES_P);
59
60 otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));
61 }
62
63 static void
otx_ep_setup_global_input_regs(struct otx_ep_device * otx_ep)64 otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)
65 {
66 uint64_t q_no = 0ull;
67
68 for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
69 otx_ep_setup_global_iq_reg(otx_ep, q_no);
70 }
71
72 static void
otx_ep_setup_global_output_regs(struct otx_ep_device * otx_ep)73 otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)
74 {
75 uint32_t q_no;
76
77 for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
78 otx_ep_setup_global_oq_reg(otx_ep, q_no);
79 }
80
81 static void
otx_ep_setup_device_regs(struct otx_ep_device * otx_ep)82 otx_ep_setup_device_regs(struct otx_ep_device *otx_ep)
83 {
84 otx_ep_setup_global_input_regs(otx_ep);
85 otx_ep_setup_global_output_regs(otx_ep);
86 }
87
88 static void
otx_ep_setup_iq_regs(struct otx_ep_device * otx_ep,uint32_t iq_no)89 otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
90 {
91 struct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];
92 volatile uint64_t reg_val = 0ull;
93
94 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no));
95
96 /* Wait till IDLE to set to 1, not supposed to configure BADDR
97 * as long as IDLE is 0
98 */
99 if (!(reg_val & OTX_EP_R_IN_CTL_IDLE)) {
100 do {
101 reg_val = rte_read64(otx_ep->hw_addr +
102 OTX_EP_R_IN_CONTROL(iq_no));
103 } while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));
104 }
105
106 /* Write the start of the input queue's ring and its size */
107 otx_ep_write64(iq->base_addr_dma, otx_ep->hw_addr,
108 OTX_EP_R_IN_INSTR_BADDR(iq_no));
109 otx_ep_write64(iq->nb_desc, otx_ep->hw_addr,
110 OTX_EP_R_IN_INSTR_RSIZE(iq_no));
111
112 /* Remember the doorbell & instruction count register addr
113 * for this queue
114 */
115 iq->doorbell_reg = (uint8_t *)otx_ep->hw_addr +
116 OTX_EP_R_IN_INSTR_DBELL(iq_no);
117 iq->inst_cnt_reg = (uint8_t *)otx_ep->hw_addr +
118 OTX_EP_R_IN_CNTS(iq_no);
119
120 otx_ep_dbg("InstQ[%d]:dbell reg @ 0x%p inst_cnt_reg @ 0x%p\n",
121 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
122
123 do {
124 reg_val = rte_read32(iq->inst_cnt_reg);
125 rte_write32(reg_val, iq->inst_cnt_reg);
126 } while (reg_val != 0);
127
128 /* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
129 * to raise
130 */
131 /* reg_val = rte_read64(otx_ep->hw_addr +
132 * OTX_EP_R_IN_INT_LEVELS(iq_no));
133 */
134 otx_ep_write64(OTX_EP_CLEAR_IN_INT_LVLS, otx_ep->hw_addr,
135 OTX_EP_R_IN_INT_LEVELS(iq_no));
136 }
137
138 static void
otx_ep_setup_oq_regs(struct otx_ep_device * otx_ep,uint32_t oq_no)139 otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
140 {
141 volatile uint64_t reg_val = 0ull;
142 uint64_t oq_ctl = 0ull;
143
144 struct otx_ep_droq *droq = otx_ep->droq[oq_no];
145
146 /* Wait on IDLE to set to 1, supposed to configure BADDR
147 * as log as IDLE is 0
148 */
149 otx_ep_write64(0ULL, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(oq_no));
150
151 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));
152
153 while (!(reg_val & OTX_EP_R_OUT_CTL_IDLE)) {
154 reg_val = rte_read64(otx_ep->hw_addr +
155 OTX_EP_R_OUT_CONTROL(oq_no));
156 }
157
158 otx_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr,
159 OTX_EP_R_OUT_SLIST_BADDR(oq_no));
160 otx_ep_write64(droq->nb_desc, otx_ep->hw_addr,
161 OTX_EP_R_OUT_SLIST_RSIZE(oq_no));
162
163 oq_ctl = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));
164
165 /* Clear the ISIZE and BSIZE (22-0) */
166 oq_ctl &= ~(OTX_EP_CLEAR_ISIZE_BSIZE);
167
168 /* Populate the BSIZE (15-0) */
169 oq_ctl |= (droq->buffer_size & OTX_EP_DROQ_BUFSZ_MASK);
170
171 otx_ep_write64(oq_ctl, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(oq_no));
172
173 /* Mapped address of the pkt_sent and pkts_credit regs */
174 droq->pkts_sent_reg = (uint8_t *)otx_ep->hw_addr +
175 OTX_EP_R_OUT_CNTS(oq_no);
176 droq->pkts_credit_reg = (uint8_t *)otx_ep->hw_addr +
177 OTX_EP_R_OUT_SLIST_DBELL(oq_no);
178
179 otx_ep_write64(OTX_EP_CLEAR_OUT_INT_LVLS, otx_ep->hw_addr,
180 OTX_EP_R_OUT_INT_LEVELS(oq_no));
181
182 /* Clear the OQ doorbell */
183 rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
184 while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
185 rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
186 rte_delay_ms(1);
187 }
188 otx_ep_dbg("OTX_EP_R[%d]_credit:%x\n", oq_no,
189 rte_read32(droq->pkts_credit_reg));
190
191 /* Clear the OQ_OUT_CNTS doorbell */
192 reg_val = rte_read32(droq->pkts_sent_reg);
193 rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
194
195 otx_ep_dbg("OTX_EP_R[%d]_sent: %x\n", oq_no,
196 rte_read32(droq->pkts_sent_reg));
197
198 while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
199 reg_val = rte_read32(droq->pkts_sent_reg);
200 rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
201 rte_delay_ms(1);
202 }
203 }
204
205 static int
otx_ep_enable_iq(struct otx_ep_device * otx_ep,uint32_t q_no)206 otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
207 {
208 uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
209 uint64_t reg_val = 0ull;
210
211 /* Resetting doorbells during IQ enabling also to handle abrupt
212 * guest reboot. IQ reset does not clear the doorbells.
213 */
214 otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,
215 OTX_EP_R_IN_INSTR_DBELL(q_no));
216
217 while (((rte_read64(otx_ep->hw_addr +
218 OTX_EP_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
219 rte_delay_ms(1);
220 }
221
222 if (loop == 0) {
223 otx_ep_err("dbell reset failed\n");
224 return -EIO;
225 }
226
227
228 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));
229 reg_val |= 0x1ull;
230
231 otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));
232
233 otx_ep_info("IQ[%d] enable done\n", q_no);
234
235 return 0;
236 }
237
238 static int
otx_ep_enable_oq(struct otx_ep_device * otx_ep,uint32_t q_no)239 otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
240 {
241 uint64_t reg_val = 0ull;
242 uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
243
244 /* Resetting doorbells during IQ enabling also to handle abrupt
245 * guest reboot. IQ reset does not clear the doorbells.
246 */
247 otx_ep_write64(0xFFFFFFFF, otx_ep->hw_addr,
248 OTX_EP_R_OUT_SLIST_DBELL(q_no));
249 while (((rte_read64(otx_ep->hw_addr +
250 OTX_EP_R_OUT_SLIST_DBELL(q_no))) != 0ull) && loop--) {
251 rte_delay_ms(1);
252 }
253 if (loop == 0) {
254 otx_ep_err("dbell reset failed\n");
255 return -EIO;
256 }
257
258
259 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));
260 reg_val |= 0x1ull;
261 otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));
262
263 otx_ep_info("OQ[%d] enable done\n", q_no);
264
265 return 0;
266 }
267
268 static int
otx_ep_enable_io_queues(struct otx_ep_device * otx_ep)269 otx_ep_enable_io_queues(struct otx_ep_device *otx_ep)
270 {
271 uint32_t q_no = 0;
272 int ret;
273
274 for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {
275 ret = otx_ep_enable_iq(otx_ep, q_no);
276 if (ret)
277 return ret;
278 }
279
280 for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++) {
281 ret = otx_ep_enable_oq(otx_ep, q_no);
282 if (ret)
283 return ret;
284 }
285
286 return 0;
287 }
288
289 static void
otx_ep_disable_iq(struct otx_ep_device * otx_ep,uint32_t q_no)290 otx_ep_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
291 {
292 uint64_t reg_val = 0ull;
293
294 /* Reset the doorbell register for this Input Queue. */
295 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_ENABLE(q_no));
296 reg_val &= ~0x1ull;
297
298 otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));
299 }
300
301 static void
otx_ep_disable_oq(struct otx_ep_device * otx_ep,uint32_t q_no)302 otx_ep_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
303 {
304 uint64_t reg_val = 0ull;
305
306 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_ENABLE(q_no));
307 reg_val &= ~0x1ull;
308
309 otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));
310 }
311
312 static void
otx_ep_disable_io_queues(struct otx_ep_device * otx_ep)313 otx_ep_disable_io_queues(struct otx_ep_device *otx_ep)
314 {
315 uint32_t q_no = 0;
316
317 for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
318 otx_ep_disable_iq(otx_ep, q_no);
319 otx_ep_disable_oq(otx_ep, q_no);
320 }
321 }
322
323 /* OTX_EP default configuration */
324 static const struct otx_ep_config default_otx_ep_conf = {
325 /* IQ attributes */
326 .iq = {
327 .max_iqs = OTX_EP_CFG_IO_QUEUES,
328 .instr_type = OTX_EP_64BYTE_INSTR,
329 .pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
330 OTX_EP_CFG_IO_QUEUES),
331 },
332
333 /* OQ attributes */
334 .oq = {
335 .max_oqs = OTX_EP_CFG_IO_QUEUES,
336 .info_ptr = OTX_EP_OQ_INFOPTR_MODE,
337 .refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,
338 },
339
340 .num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,
341 .num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,
342 .oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,
343
344 };
345
346
347 static const struct otx_ep_config*
otx_ep_get_defconf(struct otx_ep_device * otx_ep_dev __rte_unused)348 otx_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)
349 {
350 const struct otx_ep_config *default_conf = NULL;
351
352 default_conf = &default_otx_ep_conf;
353
354 return default_conf;
355 }
356
357 int
otx_ep_vf_setup_device(struct otx_ep_device * otx_ep)358 otx_ep_vf_setup_device(struct otx_ep_device *otx_ep)
359 {
360 uint64_t reg_val = 0ull;
361
362 /* If application doesn't provide its conf, use driver default conf */
363 if (otx_ep->conf == NULL) {
364 otx_ep->conf = otx_ep_get_defconf(otx_ep);
365 if (otx_ep->conf == NULL) {
366 otx_ep_err("OTX_EP VF default config not found\n");
367 return -ENOENT;
368 }
369 otx_ep_info("Default config is used\n");
370 }
371
372 /* Get IOQs (RPVF] count */
373 reg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(0));
374
375 otx_ep->sriov_info.rings_per_vf = ((reg_val >> OTX_EP_R_IN_CTL_RPVF_POS)
376 & OTX_EP_R_IN_CTL_RPVF_MASK);
377
378 otx_ep_info("OTX_EP RPVF: %d\n", otx_ep->sriov_info.rings_per_vf);
379
380 otx_ep->fn_list.setup_iq_regs = otx_ep_setup_iq_regs;
381 otx_ep->fn_list.setup_oq_regs = otx_ep_setup_oq_regs;
382
383 otx_ep->fn_list.setup_device_regs = otx_ep_setup_device_regs;
384
385 otx_ep->fn_list.enable_io_queues = otx_ep_enable_io_queues;
386 otx_ep->fn_list.disable_io_queues = otx_ep_disable_io_queues;
387
388 otx_ep->fn_list.enable_iq = otx_ep_enable_iq;
389 otx_ep->fn_list.disable_iq = otx_ep_disable_iq;
390
391 otx_ep->fn_list.enable_oq = otx_ep_enable_oq;
392 otx_ep->fn_list.disable_oq = otx_ep_disable_oq;
393
394
395 return 0;
396 }
397