1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2020 Marvell International Ltd.
3 */
4
5 #include "otx2_common.h"
6 #include "otx2_dev.h"
7 #include "otx2_regexdev_hw_access.h"
8 #include "otx2_regexdev_mbox.h"
9
10 static void
ree_lf_err_intr_handler(void * param)11 ree_lf_err_intr_handler(void *param)
12 {
13 uintptr_t base = (uintptr_t)param;
14 uint8_t lf_id;
15 uint64_t intr;
16
17 lf_id = (base >> 12) & 0xFF;
18
19 intr = otx2_read64(base + OTX2_REE_LF_MISC_INT);
20 if (intr == 0)
21 return;
22
23 otx2_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
24
25 /* Clear interrupt */
26 otx2_write64(intr, base + OTX2_REE_LF_MISC_INT);
27 }
28
29 static void
ree_lf_err_intr_unregister(const struct rte_regexdev * dev,uint16_t msix_off,uintptr_t base)30 ree_lf_err_intr_unregister(const struct rte_regexdev *dev, uint16_t msix_off,
31 uintptr_t base)
32 {
33 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
34 struct rte_intr_handle *handle = &pci_dev->intr_handle;
35
36 /* Disable error interrupts */
37 otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
38
39 otx2_unregister_irq(handle, ree_lf_err_intr_handler, (void *)base,
40 msix_off);
41 }
42
43 void
otx2_ree_err_intr_unregister(const struct rte_regexdev * dev)44 otx2_ree_err_intr_unregister(const struct rte_regexdev *dev)
45 {
46 struct otx2_ree_data *data = dev->data->dev_private;
47 struct otx2_ree_vf *vf = &data->vf;
48 uintptr_t base;
49 uint32_t i;
50
51 for (i = 0; i < vf->nb_queues; i++) {
52 base = OTX2_REE_LF_BAR2(vf, i);
53 ree_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
54 }
55
56 vf->err_intr_registered = 0;
57 }
58
59 static int
ree_lf_err_intr_register(const struct rte_regexdev * dev,uint16_t msix_off,uintptr_t base)60 ree_lf_err_intr_register(const struct rte_regexdev *dev, uint16_t msix_off,
61 uintptr_t base)
62 {
63 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
64 struct rte_intr_handle *handle = &pci_dev->intr_handle;
65 int ret;
66
67 /* Disable error interrupts */
68 otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C);
69
70 /* Register error interrupt handler */
71 ret = otx2_register_irq(handle, ree_lf_err_intr_handler, (void *)base,
72 msix_off);
73 if (ret)
74 return ret;
75
76 /* Enable error interrupts */
77 otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1S);
78
79 return 0;
80 }
81
82 int
otx2_ree_err_intr_register(const struct rte_regexdev * dev)83 otx2_ree_err_intr_register(const struct rte_regexdev *dev)
84 {
85 struct otx2_ree_data *data = dev->data->dev_private;
86 struct otx2_ree_vf *vf = &data->vf;
87 uint32_t i, j, ret;
88 uintptr_t base;
89
90 for (i = 0; i < vf->nb_queues; i++) {
91 if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
92 otx2_err("Invalid REE LF MSI-X offset: 0x%x",
93 vf->lf_msixoff[i]);
94 return -EINVAL;
95 }
96 }
97
98 for (i = 0; i < vf->nb_queues; i++) {
99 base = OTX2_REE_LF_BAR2(vf, i);
100 ret = ree_lf_err_intr_register(dev, vf->lf_msixoff[i], base);
101 if (ret)
102 goto intr_unregister;
103 }
104
105 vf->err_intr_registered = 1;
106 return 0;
107
108 intr_unregister:
109 /* Unregister the ones already registered */
110 for (j = 0; j < i; j++) {
111 base = OTX2_REE_LF_BAR2(vf, j);
112 ree_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
113 }
114 return ret;
115 }
116
117 int
otx2_ree_iq_enable(const struct rte_regexdev * dev,const struct otx2_ree_qp * qp,uint8_t pri,uint32_t size_div2)118 otx2_ree_iq_enable(const struct rte_regexdev *dev, const struct otx2_ree_qp *qp,
119 uint8_t pri, uint32_t size_div2)
120 {
121 union otx2_ree_lf_sbuf_addr base;
122 union otx2_ree_lf_ena lf_ena;
123
124 /* Set instruction queue size and priority */
125 otx2_ree_config_lf(dev, qp->id, pri, size_div2);
126
127 /* Set instruction queue base address */
128 /* Should be written after SBUF_CTL and before LF_ENA */
129
130 base.u = otx2_read64(qp->base + OTX2_REE_LF_SBUF_ADDR);
131 base.s.ptr = qp->iq_dma_addr >> 7;
132 otx2_write64(base.u, qp->base + OTX2_REE_LF_SBUF_ADDR);
133
134 /* Enable instruction queue */
135
136 lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
137 lf_ena.s.ena = 1;
138 otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
139
140 return 0;
141 }
142
143 void
otx2_ree_iq_disable(struct otx2_ree_qp * qp)144 otx2_ree_iq_disable(struct otx2_ree_qp *qp)
145 {
146 union otx2_ree_lf_ena lf_ena;
147
148 /* Stop instruction execution */
149 lf_ena.u = otx2_read64(qp->base + OTX2_REE_LF_ENA);
150 lf_ena.s.ena = 0x0;
151 otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA);
152 }
153
154 int
otx2_ree_max_matches_get(const struct rte_regexdev * dev,uint8_t * max_matches)155 otx2_ree_max_matches_get(const struct rte_regexdev *dev, uint8_t *max_matches)
156 {
157 union otx2_ree_af_reexm_max_match reexm_max_match;
158 int ret;
159
160 ret = otx2_ree_af_reg_read(dev, REE_AF_REEXM_MAX_MATCH,
161 &reexm_max_match.u);
162 if (ret)
163 return ret;
164
165 *max_matches = reexm_max_match.s.max;
166 return 0;
167 }
168