1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
3 */
4
5 #include <unistd.h>
6
7 #include <rte_cryptodev_pmd.h>
8 #include <rte_errno.h>
9 #include <rte_ethdev.h>
10
11 #include "otx2_cryptodev.h"
12 #include "otx2_cryptodev_capabilities.h"
13 #include "otx2_cryptodev_hw_access.h"
14 #include "otx2_cryptodev_mbox.h"
15 #include "otx2_cryptodev_ops.h"
16 #include "otx2_cryptodev_ops_helper.h"
17 #include "otx2_ipsec_po_ops.h"
18 #include "otx2_mbox.h"
19 #include "otx2_sec_idev.h"
20 #include "otx2_security.h"
21
22 #include "cpt_hw_types.h"
23 #include "cpt_pmd_logs.h"
24 #include "cpt_pmd_ops_helper.h"
25 #include "cpt_ucode.h"
26 #include "cpt_ucode_asym.h"
27
28 #define METABUF_POOL_CACHE_SIZE 512
29
30 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
31
32 /* Forward declarations */
33
34 static int
35 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
36
37 static void
qp_memzone_name_get(char * name,int size,int dev_id,int qp_id)38 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
39 {
40 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
41 }
42
43 static int
otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev * dev,struct otx2_cpt_qp * qp,uint8_t qp_id,int nb_elements)44 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
45 struct otx2_cpt_qp *qp, uint8_t qp_id,
46 int nb_elements)
47 {
48 char mempool_name[RTE_MEMPOOL_NAMESIZE];
49 struct cpt_qp_meta_info *meta_info;
50 struct rte_mempool *pool;
51 int ret, max_mlen;
52 int asym_mlen = 0;
53 int lb_mlen = 0;
54 int sg_mlen = 0;
55
56 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
57
58 /* Get meta len for scatter gather mode */
59 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
60
61 /* Extra 32B saved for future considerations */
62 sg_mlen += 4 * sizeof(uint64_t);
63
64 /* Get meta len for linear buffer (direct) mode */
65 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
66
67 /* Extra 32B saved for future considerations */
68 lb_mlen += 4 * sizeof(uint64_t);
69 }
70
71 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
72
73 /* Get meta len required for asymmetric operations */
74 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
75 }
76
77 /*
78 * Check max requirement for meta buffer to
79 * support crypto op of any type (sym/asym).
80 */
81 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
82
83 /* Allocate mempool */
84
85 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
86 dev->data->dev_id, qp_id);
87
88 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
89 METABUF_POOL_CACHE_SIZE, 0,
90 rte_socket_id(), 0);
91
92 if (pool == NULL) {
93 CPT_LOG_ERR("Could not create mempool for metabuf");
94 return rte_errno;
95 }
96
97 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
98 NULL);
99 if (ret) {
100 CPT_LOG_ERR("Could not set mempool ops");
101 goto mempool_free;
102 }
103
104 ret = rte_mempool_populate_default(pool);
105 if (ret <= 0) {
106 CPT_LOG_ERR("Could not populate metabuf pool");
107 goto mempool_free;
108 }
109
110 meta_info = &qp->meta_info;
111
112 meta_info->pool = pool;
113 meta_info->lb_mlen = lb_mlen;
114 meta_info->sg_mlen = sg_mlen;
115
116 return 0;
117
118 mempool_free:
119 rte_mempool_free(pool);
120 return ret;
121 }
122
123 static void
otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp * qp)124 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
125 {
126 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
127
128 rte_mempool_free(meta_info->pool);
129
130 meta_info->pool = NULL;
131 meta_info->lb_mlen = 0;
132 meta_info->sg_mlen = 0;
133 }
134
135 static int
otx2_cpt_qp_inline_cfg(const struct rte_cryptodev * dev,struct otx2_cpt_qp * qp)136 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
137 {
138 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
139 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
140 int i, ret;
141
142 for (i = 0; i < nb_ethport; i++) {
143 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
144 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
145 break;
146 }
147
148 if (i >= nb_ethport)
149 return 0;
150
151 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
152 if (ret)
153 return ret;
154
155 /* Publish inline Tx QP to eth dev security */
156 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
157 if (ret)
158 return ret;
159
160 return 0;
161 }
162
163 static struct otx2_cpt_qp *
otx2_cpt_qp_create(const struct rte_cryptodev * dev,uint16_t qp_id,uint8_t group)164 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
165 uint8_t group)
166 {
167 struct otx2_cpt_vf *vf = dev->data->dev_private;
168 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
169 const struct rte_memzone *lf_mem;
170 uint32_t len, iq_len, size_div40;
171 char name[RTE_MEMZONE_NAMESIZE];
172 uint64_t used_len, iova;
173 struct otx2_cpt_qp *qp;
174 uint64_t lmtline;
175 uint8_t *va;
176 int ret;
177
178 /* Allocate queue pair */
179 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
180 OTX2_ALIGN, 0);
181 if (qp == NULL) {
182 CPT_LOG_ERR("Could not allocate queue pair");
183 return NULL;
184 }
185
186 iq_len = OTX2_CPT_IQ_LEN;
187
188 /*
189 * Queue size must be a multiple of 40 and effective queue size to
190 * software is (size_div40 - 1) * 40
191 */
192 size_div40 = (iq_len + 40 - 1) / 40 + 1;
193
194 /* For pending queue */
195 len = iq_len * sizeof(uintptr_t);
196
197 /* Space for instruction group memory */
198 len += size_div40 * 16;
199
200 /* So that instruction queues start as pg size aligned */
201 len = RTE_ALIGN(len, pg_sz);
202
203 /* For instruction queues */
204 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
205
206 /* Wastage after instruction queues */
207 len = RTE_ALIGN(len, pg_sz);
208
209 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
210 qp_id);
211
212 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
213 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
214 RTE_CACHE_LINE_SIZE);
215 if (lf_mem == NULL) {
216 CPT_LOG_ERR("Could not allocate reserved memzone");
217 goto qp_free;
218 }
219
220 va = lf_mem->addr;
221 iova = lf_mem->iova;
222
223 memset(va, 0, len);
224
225 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
226 if (ret) {
227 CPT_LOG_ERR("Could not create mempool for metabuf");
228 goto lf_mem_free;
229 }
230
231 /* Initialize pending queue */
232 qp->pend_q.req_queue = (uintptr_t *)va;
233 qp->pend_q.enq_tail = 0;
234 qp->pend_q.deq_head = 0;
235 qp->pend_q.pending_count = 0;
236
237 used_len = iq_len * sizeof(uintptr_t);
238 used_len += size_div40 * 16;
239 used_len = RTE_ALIGN(used_len, pg_sz);
240 iova += used_len;
241
242 qp->iq_dma_addr = iova;
243 qp->id = qp_id;
244 qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
245
246 lmtline = vf->otx2_dev.bar2 +
247 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
248 OTX2_LMT_LF_LMTLINE(0);
249
250 qp->lmtline = (void *)lmtline;
251
252 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
253
254 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
255 if (ret && (ret != -ENOENT)) {
256 CPT_LOG_ERR("Could not delete inline configuration");
257 goto mempool_destroy;
258 }
259
260 otx2_cpt_iq_disable(qp);
261
262 ret = otx2_cpt_qp_inline_cfg(dev, qp);
263 if (ret) {
264 CPT_LOG_ERR("Could not configure queue for inline IPsec");
265 goto mempool_destroy;
266 }
267
268 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
269 size_div40);
270 if (ret) {
271 CPT_LOG_ERR("Could not enable instruction queue");
272 goto mempool_destroy;
273 }
274
275 return qp;
276
277 mempool_destroy:
278 otx2_cpt_metabuf_mempool_destroy(qp);
279 lf_mem_free:
280 rte_memzone_free(lf_mem);
281 qp_free:
282 rte_free(qp);
283 return NULL;
284 }
285
286 static int
otx2_cpt_qp_destroy(const struct rte_cryptodev * dev,struct otx2_cpt_qp * qp)287 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
288 {
289 const struct rte_memzone *lf_mem;
290 char name[RTE_MEMZONE_NAMESIZE];
291 int ret;
292
293 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
294 if (ret && (ret != -ENOENT)) {
295 CPT_LOG_ERR("Could not delete inline configuration");
296 return ret;
297 }
298
299 otx2_cpt_iq_disable(qp);
300
301 otx2_cpt_metabuf_mempool_destroy(qp);
302
303 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
304 qp->id);
305
306 lf_mem = rte_memzone_lookup(name);
307
308 ret = rte_memzone_free(lf_mem);
309 if (ret)
310 return ret;
311
312 rte_free(qp);
313
314 return 0;
315 }
316
317 static int
sym_xform_verify(struct rte_crypto_sym_xform * xform)318 sym_xform_verify(struct rte_crypto_sym_xform *xform)
319 {
320 if (xform->next) {
321 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
322 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
323 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
324 return -ENOTSUP;
325
326 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
327 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
328 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
329 return -ENOTSUP;
330
331 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
332 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
333 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
334 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
335 return -ENOTSUP;
336
337 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
338 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
339 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
340 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
341 return -ENOTSUP;
342
343 } else {
344 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
345 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
346 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
347 return -ENOTSUP;
348 }
349 return 0;
350 }
351
352 static int
sym_session_configure(int driver_id,struct rte_crypto_sym_xform * xform,struct rte_cryptodev_sym_session * sess,struct rte_mempool * pool)353 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
354 struct rte_cryptodev_sym_session *sess,
355 struct rte_mempool *pool)
356 {
357 struct rte_crypto_sym_xform *temp_xform = xform;
358 struct cpt_sess_misc *misc;
359 vq_cmd_word3_t vq_cmd_w3;
360 void *priv;
361 int ret;
362
363 ret = sym_xform_verify(xform);
364 if (unlikely(ret))
365 return ret;
366
367 if (unlikely(rte_mempool_get(pool, &priv))) {
368 CPT_LOG_ERR("Could not allocate session private data");
369 return -ENOMEM;
370 }
371
372 memset(priv, 0, sizeof(struct cpt_sess_misc) +
373 offsetof(struct cpt_ctx, mc_ctx));
374
375 misc = priv;
376
377 for ( ; xform != NULL; xform = xform->next) {
378 switch (xform->type) {
379 case RTE_CRYPTO_SYM_XFORM_AEAD:
380 ret = fill_sess_aead(xform, misc);
381 break;
382 case RTE_CRYPTO_SYM_XFORM_CIPHER:
383 ret = fill_sess_cipher(xform, misc);
384 break;
385 case RTE_CRYPTO_SYM_XFORM_AUTH:
386 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
387 ret = fill_sess_gmac(xform, misc);
388 else
389 ret = fill_sess_auth(xform, misc);
390 break;
391 default:
392 ret = -1;
393 }
394
395 if (ret)
396 goto priv_put;
397 }
398
399 if ((GET_SESS_FC_TYPE(misc) == HASH_HMAC) &&
400 cpt_mac_len_verify(&temp_xform->auth)) {
401 CPT_LOG_ERR("MAC length is not supported");
402 ret = -ENOTSUP;
403 goto priv_put;
404 }
405
406 set_sym_session_private_data(sess, driver_id, misc);
407
408 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
409 sizeof(struct cpt_sess_misc);
410
411 vq_cmd_w3.u64 = 0;
412 vq_cmd_w3.s.cptr = misc->ctx_dma_addr + offsetof(struct cpt_ctx,
413 mc_ctx);
414
415 /*
416 * IE engines support IPsec operations
417 * SE engines support IPsec operations, Chacha-Poly and
418 * Air-Crypto operations
419 */
420 if (misc->zsk_flag || misc->chacha_poly)
421 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE;
422 else
423 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE_IE;
424
425 misc->cpt_inst_w7 = vq_cmd_w3.u64;
426
427 return 0;
428
429 priv_put:
430 rte_mempool_put(pool, priv);
431
432 return -ENOTSUP;
433 }
434
435 static __rte_always_inline void __rte_hot
otx2_ca_enqueue_req(const struct otx2_cpt_qp * qp,struct cpt_request_info * req,void * lmtline,uint64_t cpt_inst_w7)436 otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,
437 struct cpt_request_info *req,
438 void *lmtline,
439 uint64_t cpt_inst_w7)
440 {
441 union cpt_inst_s inst;
442 uint64_t lmt_status;
443
444 inst.u[0] = 0;
445 inst.s9x.res_addr = req->comp_baddr;
446 inst.u[2] = 0;
447 inst.u[3] = 0;
448
449 inst.s9x.ei0 = req->ist.ei0;
450 inst.s9x.ei1 = req->ist.ei1;
451 inst.s9x.ei2 = req->ist.ei2;
452 inst.s9x.ei3 = cpt_inst_w7;
453
454 inst.s9x.qord = 1;
455 inst.s9x.grp = qp->ev.queue_id;
456 inst.s9x.tt = qp->ev.sched_type;
457 inst.s9x.tag = (RTE_EVENT_TYPE_CRYPTODEV << 28) |
458 qp->ev.flow_id;
459 inst.s9x.wq_ptr = (uint64_t)req >> 3;
460 req->qp = qp;
461
462 do {
463 /* Copy CPT command to LMTLINE */
464 memcpy(lmtline, &inst, sizeof(inst));
465
466 /*
467 * Make sure compiler does not reorder memcpy and ldeor.
468 * LMTST transactions are always flushed from the write
469 * buffer immediately, a DMB is not required to push out
470 * LMTSTs.
471 */
472 rte_io_wmb();
473 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
474 } while (lmt_status == 0);
475
476 }
477
478 static __rte_always_inline int32_t __rte_hot
otx2_cpt_enqueue_req(const struct otx2_cpt_qp * qp,struct pending_queue * pend_q,struct cpt_request_info * req,uint64_t cpt_inst_w7)479 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
480 struct pending_queue *pend_q,
481 struct cpt_request_info *req,
482 uint64_t cpt_inst_w7)
483 {
484 void *lmtline = qp->lmtline;
485 union cpt_inst_s inst;
486 uint64_t lmt_status;
487
488 if (qp->ca_enable) {
489 otx2_ca_enqueue_req(qp, req, lmtline, cpt_inst_w7);
490 return 0;
491 }
492
493 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
494 return -EAGAIN;
495
496 inst.u[0] = 0;
497 inst.s9x.res_addr = req->comp_baddr;
498 inst.u[2] = 0;
499 inst.u[3] = 0;
500
501 inst.s9x.ei0 = req->ist.ei0;
502 inst.s9x.ei1 = req->ist.ei1;
503 inst.s9x.ei2 = req->ist.ei2;
504 inst.s9x.ei3 = cpt_inst_w7;
505
506 req->time_out = rte_get_timer_cycles() +
507 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
508
509 do {
510 /* Copy CPT command to LMTLINE */
511 memcpy(lmtline, &inst, sizeof(inst));
512
513 /*
514 * Make sure compiler does not reorder memcpy and ldeor.
515 * LMTST transactions are always flushed from the write
516 * buffer immediately, a DMB is not required to push out
517 * LMTSTs.
518 */
519 rte_io_wmb();
520 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
521 } while (lmt_status == 0);
522
523 pend_q->req_queue[pend_q->enq_tail] = (uintptr_t)req;
524
525 /* We will use soft queue length here to limit requests */
526 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
527 pend_q->pending_count += 1;
528
529 return 0;
530 }
531
532 static __rte_always_inline int32_t __rte_hot
otx2_cpt_enqueue_asym(struct otx2_cpt_qp * qp,struct rte_crypto_op * op,struct pending_queue * pend_q)533 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
534 struct rte_crypto_op *op,
535 struct pending_queue *pend_q)
536 {
537 struct cpt_qp_meta_info *minfo = &qp->meta_info;
538 struct rte_crypto_asym_op *asym_op = op->asym;
539 struct asym_op_params params = {0};
540 struct cpt_asym_sess_misc *sess;
541 uintptr_t *cop;
542 void *mdata;
543 int ret;
544
545 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
546 CPT_LOG_ERR("Could not allocate meta buffer for request");
547 return -ENOMEM;
548 }
549
550 sess = get_asym_session_private_data(asym_op->session,
551 otx2_cryptodev_driver_id);
552
553 /* Store IO address of the mdata to meta_buf */
554 params.meta_buf = rte_mempool_virt2iova(mdata);
555
556 cop = mdata;
557 cop[0] = (uintptr_t)mdata;
558 cop[1] = (uintptr_t)op;
559 cop[2] = cop[3] = 0ULL;
560
561 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
562 params.req->op = cop;
563
564 /* Adjust meta_buf to point to end of cpt_request_info structure */
565 params.meta_buf += (4 * sizeof(uintptr_t)) +
566 sizeof(struct cpt_request_info);
567 switch (sess->xfrm_type) {
568 case RTE_CRYPTO_ASYM_XFORM_MODEX:
569 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
570 if (unlikely(ret))
571 goto req_fail;
572 break;
573 case RTE_CRYPTO_ASYM_XFORM_RSA:
574 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
575 if (unlikely(ret))
576 goto req_fail;
577 break;
578 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
579 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
580 if (unlikely(ret))
581 goto req_fail;
582 break;
583 case RTE_CRYPTO_ASYM_XFORM_ECPM:
584 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
585 sess->ec_ctx.curveid);
586 if (unlikely(ret))
587 goto req_fail;
588 break;
589 default:
590 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
591 ret = -EINVAL;
592 goto req_fail;
593 }
594
595 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req, sess->cpt_inst_w7);
596
597 if (unlikely(ret)) {
598 CPT_LOG_DP_ERR("Could not enqueue crypto req");
599 goto req_fail;
600 }
601
602 return 0;
603
604 req_fail:
605 free_op_meta(mdata, minfo->pool);
606
607 return ret;
608 }
609
610 static __rte_always_inline int __rte_hot
otx2_cpt_enqueue_sym(struct otx2_cpt_qp * qp,struct rte_crypto_op * op,struct pending_queue * pend_q)611 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
612 struct pending_queue *pend_q)
613 {
614 struct rte_crypto_sym_op *sym_op = op->sym;
615 struct cpt_request_info *req;
616 struct cpt_sess_misc *sess;
617 uint64_t cpt_op;
618 void *mdata;
619 int ret;
620
621 sess = get_sym_session_private_data(sym_op->session,
622 otx2_cryptodev_driver_id);
623
624 cpt_op = sess->cpt_op;
625
626 if (cpt_op & CPT_OP_CIPHER_MASK)
627 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
628 (void **)&req);
629 else
630 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
631 (void **)&req);
632
633 if (unlikely(ret)) {
634 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
635 op, (unsigned int)cpt_op, ret);
636 return ret;
637 }
638
639 ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
640
641 if (unlikely(ret)) {
642 /* Free buffer allocated by fill params routines */
643 free_op_meta(mdata, qp->meta_info.pool);
644 }
645
646 return ret;
647 }
648
649 static __rte_always_inline int __rte_hot
otx2_cpt_enqueue_sec(struct otx2_cpt_qp * qp,struct rte_crypto_op * op,struct pending_queue * pend_q)650 otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
651 struct pending_queue *pend_q)
652 {
653 struct otx2_sec_session_ipsec_lp *sess;
654 struct otx2_ipsec_po_sa_ctl *ctl_wrd;
655 struct otx2_sec_session *priv;
656 struct cpt_request_info *req;
657 int ret;
658
659 priv = get_sec_session_private_data(op->sym->sec_session);
660 sess = &priv->ipsec.lp;
661
662 ctl_wrd = &sess->in_sa.ctl;
663
664 if (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)
665 ret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);
666 else
667 ret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);
668
669 if (unlikely(ret)) {
670 otx2_err("Crypto req : op %p, ret 0x%x", op, ret);
671 return ret;
672 }
673
674 ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
675
676 return ret;
677 }
678
679 static __rte_always_inline int __rte_hot
otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp * qp,struct rte_crypto_op * op,struct pending_queue * pend_q)680 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
681 struct pending_queue *pend_q)
682 {
683 const int driver_id = otx2_cryptodev_driver_id;
684 struct rte_crypto_sym_op *sym_op = op->sym;
685 struct rte_cryptodev_sym_session *sess;
686 int ret;
687
688 /* Create temporary session */
689 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
690 if (sess == NULL)
691 return -ENOMEM;
692
693 ret = sym_session_configure(driver_id, sym_op->xform, sess,
694 qp->sess_mp_priv);
695 if (ret)
696 goto sess_put;
697
698 sym_op->session = sess;
699
700 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
701
702 if (unlikely(ret))
703 goto priv_put;
704
705 return 0;
706
707 priv_put:
708 sym_session_clear(driver_id, sess);
709 sess_put:
710 rte_mempool_put(qp->sess_mp, sess);
711 return ret;
712 }
713
714 static uint16_t
otx2_cpt_enqueue_burst(void * qptr,struct rte_crypto_op ** ops,uint16_t nb_ops)715 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
716 {
717 uint16_t nb_allowed, count = 0;
718 struct otx2_cpt_qp *qp = qptr;
719 struct pending_queue *pend_q;
720 struct rte_crypto_op *op;
721 int ret;
722
723 pend_q = &qp->pend_q;
724
725 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
726 if (nb_ops > nb_allowed)
727 nb_ops = nb_allowed;
728
729 for (count = 0; count < nb_ops; count++) {
730 op = ops[count];
731 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
732 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
733 ret = otx2_cpt_enqueue_sec(qp, op, pend_q);
734 else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
735 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
736 else
737 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
738 pend_q);
739 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
740 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
741 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
742 else
743 break;
744 } else
745 break;
746
747 if (unlikely(ret))
748 break;
749 }
750
751 return count;
752 }
753
754 static __rte_always_inline void
otx2_cpt_asym_rsa_op(struct rte_crypto_op * cop,struct cpt_request_info * req,struct rte_crypto_rsa_xform * rsa_ctx)755 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
756 struct rte_crypto_rsa_xform *rsa_ctx)
757 {
758 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
759
760 switch (rsa->op_type) {
761 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
762 rsa->cipher.length = rsa_ctx->n.length;
763 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
764 break;
765 case RTE_CRYPTO_ASYM_OP_DECRYPT:
766 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
767 rsa->message.length = rsa_ctx->n.length;
768 memcpy(rsa->message.data, req->rptr,
769 rsa->message.length);
770 } else {
771 /* Get length of decrypted output */
772 rsa->message.length = rte_cpu_to_be_16
773 (*((uint16_t *)req->rptr));
774 /*
775 * Offset output data pointer by length field
776 * (2 bytes) and copy decrypted data.
777 */
778 memcpy(rsa->message.data, req->rptr + 2,
779 rsa->message.length);
780 }
781 break;
782 case RTE_CRYPTO_ASYM_OP_SIGN:
783 rsa->sign.length = rsa_ctx->n.length;
784 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
785 break;
786 case RTE_CRYPTO_ASYM_OP_VERIFY:
787 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
788 rsa->sign.length = rsa_ctx->n.length;
789 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
790 } else {
791 /* Get length of signed output */
792 rsa->sign.length = rte_cpu_to_be_16
793 (*((uint16_t *)req->rptr));
794 /*
795 * Offset output data pointer by length field
796 * (2 bytes) and copy signed data.
797 */
798 memcpy(rsa->sign.data, req->rptr + 2,
799 rsa->sign.length);
800 }
801 if (memcmp(rsa->sign.data, rsa->message.data,
802 rsa->message.length)) {
803 CPT_LOG_DP_ERR("RSA verification failed");
804 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
805 }
806 break;
807 default:
808 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
809 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
810 break;
811 }
812 }
813
814 static __rte_always_inline void
otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param * ecdsa,struct cpt_request_info * req,struct cpt_asym_ec_ctx * ec)815 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
816 struct cpt_request_info *req,
817 struct cpt_asym_ec_ctx *ec)
818 {
819 int prime_len = ec_grp[ec->curveid].prime.length;
820
821 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
822 return;
823
824 /* Separate out sign r and s components */
825 memcpy(ecdsa->r.data, req->rptr, prime_len);
826 memcpy(ecdsa->s.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
827 prime_len);
828 ecdsa->r.length = prime_len;
829 ecdsa->s.length = prime_len;
830 }
831
832 static __rte_always_inline void
otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param * ecpm,struct cpt_request_info * req,struct cpt_asym_ec_ctx * ec)833 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
834 struct cpt_request_info *req,
835 struct cpt_asym_ec_ctx *ec)
836 {
837 int prime_len = ec_grp[ec->curveid].prime.length;
838
839 memcpy(ecpm->r.x.data, req->rptr, prime_len);
840 memcpy(ecpm->r.y.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
841 prime_len);
842 ecpm->r.x.length = prime_len;
843 ecpm->r.y.length = prime_len;
844 }
845
846 static void
otx2_cpt_asym_post_process(struct rte_crypto_op * cop,struct cpt_request_info * req)847 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
848 struct cpt_request_info *req)
849 {
850 struct rte_crypto_asym_op *op = cop->asym;
851 struct cpt_asym_sess_misc *sess;
852
853 sess = get_asym_session_private_data(op->session,
854 otx2_cryptodev_driver_id);
855
856 switch (sess->xfrm_type) {
857 case RTE_CRYPTO_ASYM_XFORM_RSA:
858 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
859 break;
860 case RTE_CRYPTO_ASYM_XFORM_MODEX:
861 op->modex.result.length = sess->mod_ctx.modulus.length;
862 memcpy(op->modex.result.data, req->rptr,
863 op->modex.result.length);
864 break;
865 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
866 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
867 break;
868 case RTE_CRYPTO_ASYM_XFORM_ECPM:
869 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
870 break;
871 default:
872 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
873 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
874 break;
875 }
876 }
877
878 static void
otx2_cpt_sec_post_process(struct rte_crypto_op * cop,uintptr_t * rsp)879 otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
880 {
881 struct cpt_request_info *req = (struct cpt_request_info *)rsp[2];
882 vq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;
883 struct rte_crypto_sym_op *sym_op = cop->sym;
884 struct rte_mbuf *m = sym_op->m_src;
885 struct rte_ipv6_hdr *ip6;
886 struct rte_ipv4_hdr *ip;
887 uint16_t m_len;
888 int mdata_len;
889 char *data;
890
891 mdata_len = (int)rsp[3];
892 rte_pktmbuf_trim(m, mdata_len);
893
894 if (word0->s.opcode.major == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {
895 data = rte_pktmbuf_mtod(m, char *);
896
897 if (rsp[4] == RTE_SECURITY_IPSEC_TUNNEL_IPV4) {
898 ip = (struct rte_ipv4_hdr *)(data +
899 OTX2_IPSEC_PO_INB_RPTR_HDR);
900 m_len = rte_be_to_cpu_16(ip->total_length);
901 } else {
902 ip6 = (struct rte_ipv6_hdr *)(data +
903 OTX2_IPSEC_PO_INB_RPTR_HDR);
904 m_len = rte_be_to_cpu_16(ip6->payload_len) +
905 sizeof(struct rte_ipv6_hdr);
906 }
907
908 m->data_len = m_len;
909 m->pkt_len = m_len;
910 m->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;
911 }
912 }
913
914 static inline void
otx2_cpt_dequeue_post_process(struct otx2_cpt_qp * qp,struct rte_crypto_op * cop,uintptr_t * rsp,uint8_t cc)915 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
916 uintptr_t *rsp, uint8_t cc)
917 {
918 unsigned int sz;
919
920 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
921 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
922 if (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {
923 otx2_cpt_sec_post_process(cop, rsp);
924 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
925 } else
926 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
927
928 return;
929 }
930
931 if (likely(cc == NO_ERR)) {
932 /* Verify authentication data if required */
933 if (unlikely(rsp[2]))
934 compl_auth_verify(cop, (uint8_t *)rsp[2],
935 rsp[3]);
936 else
937 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
938 } else {
939 if (cc == ERR_GC_ICV_MISCOMPARE)
940 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
941 else
942 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
943 }
944
945 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
946 sym_session_clear(otx2_cryptodev_driver_id,
947 cop->sym->session);
948 sz = rte_cryptodev_sym_get_existing_header_session_size(
949 cop->sym->session);
950 memset(cop->sym->session, 0, sz);
951 rte_mempool_put(qp->sess_mp, cop->sym->session);
952 cop->sym->session = NULL;
953 }
954 }
955
956 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
957 if (likely(cc == NO_ERR)) {
958 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
959 /*
960 * Pass cpt_req_info stored in metabuf during
961 * enqueue.
962 */
963 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
964 otx2_cpt_asym_post_process(cop,
965 (struct cpt_request_info *)rsp);
966 } else
967 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
968 }
969 }
970
971 static uint16_t
otx2_cpt_dequeue_burst(void * qptr,struct rte_crypto_op ** ops,uint16_t nb_ops)972 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
973 {
974 int i, nb_pending, nb_completed;
975 struct otx2_cpt_qp *qp = qptr;
976 struct pending_queue *pend_q;
977 struct cpt_request_info *req;
978 struct rte_crypto_op *cop;
979 uint8_t cc[nb_ops];
980 uintptr_t *rsp;
981 void *metabuf;
982
983 pend_q = &qp->pend_q;
984
985 nb_pending = pend_q->pending_count;
986
987 if (nb_ops > nb_pending)
988 nb_ops = nb_pending;
989
990 for (i = 0; i < nb_ops; i++) {
991 req = (struct cpt_request_info *)
992 pend_q->req_queue[pend_q->deq_head];
993
994 cc[i] = otx2_cpt_compcode_get(req);
995
996 if (unlikely(cc[i] == ERR_REQ_PENDING))
997 break;
998
999 ops[i] = req->op;
1000
1001 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
1002 pend_q->pending_count -= 1;
1003 }
1004
1005 nb_completed = i;
1006
1007 for (i = 0; i < nb_completed; i++) {
1008 rsp = (void *)ops[i];
1009
1010 metabuf = (void *)rsp[0];
1011 cop = (void *)rsp[1];
1012
1013 ops[i] = cop;
1014
1015 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
1016
1017 free_op_meta(metabuf, qp->meta_info.pool);
1018 }
1019
1020 return nb_completed;
1021 }
1022
1023 void
otx2_cpt_set_enqdeq_fns(struct rte_cryptodev * dev)1024 otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
1025 {
1026 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1027 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1028
1029 rte_mb();
1030 }
1031
1032 /* PMD ops */
1033
1034 static int
otx2_cpt_dev_config(struct rte_cryptodev * dev,struct rte_cryptodev_config * conf)1035 otx2_cpt_dev_config(struct rte_cryptodev *dev,
1036 struct rte_cryptodev_config *conf)
1037 {
1038 struct otx2_cpt_vf *vf = dev->data->dev_private;
1039 int ret;
1040
1041 if (conf->nb_queue_pairs > vf->max_queues) {
1042 CPT_LOG_ERR("Invalid number of queue pairs requested");
1043 return -EINVAL;
1044 }
1045
1046 dev->feature_flags &= ~conf->ff_disable;
1047
1048 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
1049 /* Initialize shared FPM table */
1050 ret = cpt_fpm_init(otx2_fpm_iova);
1051 if (ret)
1052 return ret;
1053 }
1054
1055 /* Unregister error interrupts */
1056 if (vf->err_intr_registered)
1057 otx2_cpt_err_intr_unregister(dev);
1058
1059 /* Detach queues */
1060 if (vf->nb_queues) {
1061 ret = otx2_cpt_queues_detach(dev);
1062 if (ret) {
1063 CPT_LOG_ERR("Could not detach CPT queues");
1064 return ret;
1065 }
1066 }
1067
1068 /* Attach queues */
1069 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
1070 if (ret) {
1071 CPT_LOG_ERR("Could not attach CPT queues");
1072 return -ENODEV;
1073 }
1074
1075 ret = otx2_cpt_msix_offsets_get(dev);
1076 if (ret) {
1077 CPT_LOG_ERR("Could not get MSI-X offsets");
1078 goto queues_detach;
1079 }
1080
1081 /* Register error interrupts */
1082 ret = otx2_cpt_err_intr_register(dev);
1083 if (ret) {
1084 CPT_LOG_ERR("Could not register error interrupts");
1085 goto queues_detach;
1086 }
1087
1088 ret = otx2_cpt_inline_init(dev);
1089 if (ret) {
1090 CPT_LOG_ERR("Could not enable inline IPsec");
1091 goto intr_unregister;
1092 }
1093
1094 otx2_cpt_set_enqdeq_fns(dev);
1095
1096 return 0;
1097
1098 intr_unregister:
1099 otx2_cpt_err_intr_unregister(dev);
1100 queues_detach:
1101 otx2_cpt_queues_detach(dev);
1102 return ret;
1103 }
1104
1105 static int
otx2_cpt_dev_start(struct rte_cryptodev * dev)1106 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1107 {
1108 RTE_SET_USED(dev);
1109
1110 CPT_PMD_INIT_FUNC_TRACE();
1111
1112 return 0;
1113 }
1114
1115 static void
otx2_cpt_dev_stop(struct rte_cryptodev * dev)1116 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1117 {
1118 CPT_PMD_INIT_FUNC_TRACE();
1119
1120 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1121 cpt_fpm_clear();
1122 }
1123
1124 static int
otx2_cpt_dev_close(struct rte_cryptodev * dev)1125 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1126 {
1127 struct otx2_cpt_vf *vf = dev->data->dev_private;
1128 int i, ret = 0;
1129
1130 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1131 ret = otx2_cpt_queue_pair_release(dev, i);
1132 if (ret)
1133 return ret;
1134 }
1135
1136 /* Unregister error interrupts */
1137 if (vf->err_intr_registered)
1138 otx2_cpt_err_intr_unregister(dev);
1139
1140 /* Detach queues */
1141 if (vf->nb_queues) {
1142 ret = otx2_cpt_queues_detach(dev);
1143 if (ret)
1144 CPT_LOG_ERR("Could not detach CPT queues");
1145 }
1146
1147 return ret;
1148 }
1149
1150 static void
otx2_cpt_dev_info_get(struct rte_cryptodev * dev,struct rte_cryptodev_info * info)1151 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1152 struct rte_cryptodev_info *info)
1153 {
1154 struct otx2_cpt_vf *vf = dev->data->dev_private;
1155
1156 if (info != NULL) {
1157 info->max_nb_queue_pairs = vf->max_queues;
1158 info->feature_flags = dev->feature_flags;
1159 info->capabilities = otx2_cpt_capabilities_get();
1160 info->sym.max_nb_sessions = 0;
1161 info->driver_id = otx2_cryptodev_driver_id;
1162 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1163 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1164 }
1165 }
1166
1167 static int
otx2_cpt_queue_pair_setup(struct rte_cryptodev * dev,uint16_t qp_id,const struct rte_cryptodev_qp_conf * conf,int socket_id __rte_unused)1168 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1169 const struct rte_cryptodev_qp_conf *conf,
1170 int socket_id __rte_unused)
1171 {
1172 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1173 struct rte_pci_device *pci_dev;
1174 struct otx2_cpt_qp *qp;
1175
1176 CPT_PMD_INIT_FUNC_TRACE();
1177
1178 if (dev->data->queue_pairs[qp_id] != NULL)
1179 otx2_cpt_queue_pair_release(dev, qp_id);
1180
1181 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1182 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1183 conf->nb_descriptors);
1184 return -EINVAL;
1185 }
1186
1187 pci_dev = RTE_DEV_TO_PCI(dev->device);
1188
1189 if (pci_dev->mem_resource[2].addr == NULL) {
1190 CPT_LOG_ERR("Invalid PCI mem address");
1191 return -EIO;
1192 }
1193
1194 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1195 if (qp == NULL) {
1196 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1197 return -ENOMEM;
1198 }
1199
1200 qp->sess_mp = conf->mp_session;
1201 qp->sess_mp_priv = conf->mp_session_private;
1202 dev->data->queue_pairs[qp_id] = qp;
1203
1204 return 0;
1205 }
1206
1207 static int
otx2_cpt_queue_pair_release(struct rte_cryptodev * dev,uint16_t qp_id)1208 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1209 {
1210 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1211 int ret;
1212
1213 CPT_PMD_INIT_FUNC_TRACE();
1214
1215 if (qp == NULL)
1216 return -EINVAL;
1217
1218 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1219
1220 ret = otx2_cpt_qp_destroy(dev, qp);
1221 if (ret) {
1222 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1223 return ret;
1224 }
1225
1226 dev->data->queue_pairs[qp_id] = NULL;
1227
1228 return 0;
1229 }
1230
1231 static unsigned int
otx2_cpt_sym_session_get_size(struct rte_cryptodev * dev __rte_unused)1232 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1233 {
1234 return cpt_get_session_size();
1235 }
1236
1237 static int
otx2_cpt_sym_session_configure(struct rte_cryptodev * dev,struct rte_crypto_sym_xform * xform,struct rte_cryptodev_sym_session * sess,struct rte_mempool * pool)1238 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1239 struct rte_crypto_sym_xform *xform,
1240 struct rte_cryptodev_sym_session *sess,
1241 struct rte_mempool *pool)
1242 {
1243 CPT_PMD_INIT_FUNC_TRACE();
1244
1245 return sym_session_configure(dev->driver_id, xform, sess, pool);
1246 }
1247
1248 static void
otx2_cpt_sym_session_clear(struct rte_cryptodev * dev,struct rte_cryptodev_sym_session * sess)1249 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1250 struct rte_cryptodev_sym_session *sess)
1251 {
1252 CPT_PMD_INIT_FUNC_TRACE();
1253
1254 return sym_session_clear(dev->driver_id, sess);
1255 }
1256
1257 static unsigned int
otx2_cpt_asym_session_size_get(struct rte_cryptodev * dev __rte_unused)1258 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1259 {
1260 return sizeof(struct cpt_asym_sess_misc);
1261 }
1262
1263 static int
otx2_cpt_asym_session_cfg(struct rte_cryptodev * dev,struct rte_crypto_asym_xform * xform,struct rte_cryptodev_asym_session * sess,struct rte_mempool * pool)1264 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1265 struct rte_crypto_asym_xform *xform,
1266 struct rte_cryptodev_asym_session *sess,
1267 struct rte_mempool *pool)
1268 {
1269 struct cpt_asym_sess_misc *priv;
1270 vq_cmd_word3_t vq_cmd_w3;
1271 int ret;
1272
1273 CPT_PMD_INIT_FUNC_TRACE();
1274
1275 if (rte_mempool_get(pool, (void **)&priv)) {
1276 CPT_LOG_ERR("Could not allocate session_private_data");
1277 return -ENOMEM;
1278 }
1279
1280 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1281
1282 ret = cpt_fill_asym_session_parameters(priv, xform);
1283 if (ret) {
1284 CPT_LOG_ERR("Could not configure session parameters");
1285
1286 /* Return session to mempool */
1287 rte_mempool_put(pool, priv);
1288 return ret;
1289 }
1290
1291 vq_cmd_w3.u64 = 0;
1292 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_AE;
1293 priv->cpt_inst_w7 = vq_cmd_w3.u64;
1294
1295 set_asym_session_private_data(sess, dev->driver_id, priv);
1296
1297 return 0;
1298 }
1299
1300 static void
otx2_cpt_asym_session_clear(struct rte_cryptodev * dev,struct rte_cryptodev_asym_session * sess)1301 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1302 struct rte_cryptodev_asym_session *sess)
1303 {
1304 struct cpt_asym_sess_misc *priv;
1305 struct rte_mempool *sess_mp;
1306
1307 CPT_PMD_INIT_FUNC_TRACE();
1308
1309 priv = get_asym_session_private_data(sess, dev->driver_id);
1310 if (priv == NULL)
1311 return;
1312
1313 /* Free resources allocated in session_cfg */
1314 cpt_free_asym_session_parameters(priv);
1315
1316 /* Reset and free object back to pool */
1317 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1318 sess_mp = rte_mempool_from_obj(priv);
1319 set_asym_session_private_data(sess, dev->driver_id, NULL);
1320 rte_mempool_put(sess_mp, priv);
1321 }
1322
1323 struct rte_cryptodev_ops otx2_cpt_ops = {
1324 /* Device control ops */
1325 .dev_configure = otx2_cpt_dev_config,
1326 .dev_start = otx2_cpt_dev_start,
1327 .dev_stop = otx2_cpt_dev_stop,
1328 .dev_close = otx2_cpt_dev_close,
1329 .dev_infos_get = otx2_cpt_dev_info_get,
1330
1331 .stats_get = NULL,
1332 .stats_reset = NULL,
1333 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1334 .queue_pair_release = otx2_cpt_queue_pair_release,
1335
1336 /* Symmetric crypto ops */
1337 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1338 .sym_session_configure = otx2_cpt_sym_session_configure,
1339 .sym_session_clear = otx2_cpt_sym_session_clear,
1340
1341 /* Asymmetric crypto ops */
1342 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1343 .asym_session_configure = otx2_cpt_asym_session_cfg,
1344 .asym_session_clear = otx2_cpt_asym_session_clear,
1345
1346 };
1347