1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
3 */
4
5 #ifndef __OTX2_TIM_EVDEV_H__
6 #define __OTX2_TIM_EVDEV_H__
7
8 #include <rte_event_timer_adapter.h>
9 #include <rte_event_timer_adapter_pmd.h>
10 #include <rte_reciprocal.h>
11
12 #include "otx2_dev.h"
13
14 #define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev
15
16 #define otx2_tim_func_trace otx2_tim_dbg
17
18 #define TIM_LF_RING_AURA (0x0)
19 #define TIM_LF_RING_BASE (0x130)
20 #define TIM_LF_NRSPERR_INT (0x200)
21 #define TIM_LF_NRSPERR_INT_W1S (0x208)
22 #define TIM_LF_NRSPERR_INT_ENA_W1S (0x210)
23 #define TIM_LF_NRSPERR_INT_ENA_W1C (0x218)
24 #define TIM_LF_RAS_INT (0x300)
25 #define TIM_LF_RAS_INT_W1S (0x308)
26 #define TIM_LF_RAS_INT_ENA_W1S (0x310)
27 #define TIM_LF_RAS_INT_ENA_W1C (0x318)
28 #define TIM_LF_RING_REL (0x400)
29
30 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)
31 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER ((1ULL << (64 - \
32 TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)
33 #define TIM_BUCKET_W1_S_LOCK (40)
34 #define TIM_BUCKET_W1_M_LOCK ((1ULL << \
35 (TIM_BUCKET_W1_S_CHUNK_REMAINDER - \
36 TIM_BUCKET_W1_S_LOCK)) - 1)
37 #define TIM_BUCKET_W1_S_RSVD (35)
38 #define TIM_BUCKET_W1_S_BSK (34)
39 #define TIM_BUCKET_W1_M_BSK ((1ULL << \
40 (TIM_BUCKET_W1_S_RSVD - \
41 TIM_BUCKET_W1_S_BSK)) - 1)
42 #define TIM_BUCKET_W1_S_HBT (33)
43 #define TIM_BUCKET_W1_M_HBT ((1ULL << \
44 (TIM_BUCKET_W1_S_BSK - \
45 TIM_BUCKET_W1_S_HBT)) - 1)
46 #define TIM_BUCKET_W1_S_SBT (32)
47 #define TIM_BUCKET_W1_M_SBT ((1ULL << \
48 (TIM_BUCKET_W1_S_HBT - \
49 TIM_BUCKET_W1_S_SBT)) - 1)
50 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0)
51 #define TIM_BUCKET_W1_M_NUM_ENTRIES ((1ULL << \
52 (TIM_BUCKET_W1_S_SBT - \
53 TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)
54
55 #define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN)
56
57 #define TIM_BUCKET_CHUNK_REMAIN \
58 (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)
59
60 #define TIM_BUCKET_LOCK \
61 (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)
62
63 #define TIM_BUCKET_SEMA_WLOCK \
64 (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))
65
66 #define OTX2_MAX_TIM_RINGS (256)
67 #define OTX2_TIM_MAX_BUCKETS (0xFFFFF)
68 #define OTX2_TIM_RING_DEF_CHUNK_SZ (4096)
69 #define OTX2_TIM_CHUNK_ALIGNMENT (16)
70 #define OTX2_TIM_MAX_BURST (RTE_CACHE_LINE_SIZE / \
71 OTX2_TIM_CHUNK_ALIGNMENT)
72 #define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)
73 #define OTX2_TIM_MIN_CHUNK_SLOTS (0x1)
74 #define OTX2_TIM_MAX_CHUNK_SLOTS (0x1FFE)
75 #define OTX2_TIM_MIN_TMO_TKS (256)
76
77 #define OTX2_TIM_SP 0x1
78 #define OTX2_TIM_MP 0x2
79 #define OTX2_TIM_BKT_AND 0x4
80 #define OTX2_TIM_BKT_MOD 0x8
81 #define OTX2_TIM_ENA_FB 0x10
82 #define OTX2_TIM_ENA_DFB 0x20
83 #define OTX2_TIM_ENA_STATS 0x40
84
85 enum otx2_tim_clk_src {
86 OTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
87 OTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
88 OTX2_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
89 OTX2_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
90 };
91
92 struct otx2_tim_bkt {
93 uint64_t first_chunk;
94 union {
95 uint64_t w1;
96 struct {
97 uint32_t nb_entry;
98 uint8_t sbt:1;
99 uint8_t hbt:1;
100 uint8_t bsk:1;
101 uint8_t rsvd:5;
102 uint8_t lock;
103 int16_t chunk_remainder;
104 };
105 };
106 uint64_t current_chunk;
107 uint64_t pad;
108 } __rte_packed __rte_aligned(32);
109
110 struct otx2_tim_ent {
111 uint64_t w0;
112 uint64_t wqe;
113 } __rte_packed;
114
115 struct otx2_tim_ctl {
116 uint16_t ring;
117 uint16_t chunk_slots;
118 uint16_t disable_npa;
119 uint16_t enable_stats;
120 };
121
122 struct otx2_tim_evdev {
123 struct rte_pci_device *pci_dev;
124 struct rte_eventdev *event_dev;
125 struct otx2_mbox *mbox;
126 uint16_t nb_rings;
127 uint32_t chunk_sz;
128 uintptr_t bar2;
129 /* Dev args */
130 uint8_t disable_npa;
131 uint16_t chunk_slots;
132 uint16_t min_ring_cnt;
133 uint8_t enable_stats;
134 uint16_t ring_ctl_cnt;
135 struct otx2_tim_ctl *ring_ctl_data;
136 /* HW const */
137 /* MSIX offsets */
138 uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];
139 };
140
141 struct otx2_tim_ring {
142 uintptr_t base;
143 uint16_t nb_chunk_slots;
144 uint32_t nb_bkts;
145 uint64_t last_updt_cyc;
146 uint64_t ring_start_cyc;
147 uint64_t tck_int;
148 uint64_t tot_int;
149 struct otx2_tim_bkt *bkt;
150 struct rte_mempool *chunk_pool;
151 struct rte_reciprocal_u64 fast_div;
152 uint64_t arm_cnt;
153 uint8_t prod_type_sp;
154 uint8_t enable_stats;
155 uint8_t disable_npa;
156 uint8_t optimized;
157 uint8_t ena_dfb;
158 uint16_t ring_id;
159 uint32_t aura;
160 uint64_t nb_timers;
161 uint64_t tck_nsec;
162 uint64_t max_tout;
163 uint64_t nb_chunks;
164 uint64_t chunk_sz;
165 uint64_t tenns_clk_freq;
166 enum otx2_tim_clk_src clk_src;
167 } __rte_cache_aligned;
168
169 static inline struct otx2_tim_evdev *
tim_priv_get(void)170 tim_priv_get(void)
171 {
172 const struct rte_memzone *mz;
173
174 mz = rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME));
175 if (mz == NULL)
176 return NULL;
177
178 return mz->addr;
179 }
180
181 #define TIM_ARM_FASTPATH_MODES \
182 FP(mod_sp, 0, 0, 0, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
183 FP(mod_mp, 0, 0, 0, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
184 FP(mod_fb_sp, 0, 0, 1, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
185 FP(mod_fb_mp, 0, 0, 1, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB | OTX2_TIM_MP) \
186 FP(and_sp, 0, 1, 0, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
187 FP(and_mp, 0, 1, 0, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
188 FP(and_fb_sp, 0, 1, 1, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
189 FP(and_fb_mp, 0, 1, 1, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB | OTX2_TIM_MP) \
190 FP(stats_mod_sp, 1, 0, 0, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_MOD | \
191 OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
192 FP(stats_mod_mp, 1, 0, 0, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_MOD | \
193 OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
194 FP(stats_mod_fb_sp, 1, 0, 1, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_MOD | \
195 OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
196 FP(stats_mod_fb_mp, 1, 0, 1, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_MOD | \
197 OTX2_TIM_ENA_FB | OTX2_TIM_MP) \
198 FP(stats_and_sp, 1, 1, 0, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_AND | \
199 OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \
200 FP(stats_and_mp, 1, 1, 0, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_AND | \
201 OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \
202 FP(stats_and_fb_sp, 1, 1, 1, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_AND | \
203 OTX2_TIM_ENA_FB | OTX2_TIM_SP) \
204 FP(stats_and_fb_mp, 1, 1, 1, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_AND | \
205 OTX2_TIM_ENA_FB | OTX2_TIM_MP)
206
207 #define TIM_ARM_TMO_FASTPATH_MODES \
208 FP(mod, 0, 0, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB) \
209 FP(mod_fb, 0, 0, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB) \
210 FP(and, 0, 1, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB) \
211 FP(and_fb, 0, 1, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB) \
212 FP(stats_mod, 1, 0, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_MOD | \
213 OTX2_TIM_ENA_DFB) \
214 FP(stats_mod_fb, 1, 0, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_MOD | \
215 OTX2_TIM_ENA_FB) \
216 FP(stats_and, 1, 1, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_AND | \
217 OTX2_TIM_ENA_DFB) \
218 FP(stats_and_fb, 1, 1, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_BKT_AND | \
219 OTX2_TIM_ENA_FB)
220
221 #define FP(_name, _f4, _f3, _f2, _f1, flags) \
222 uint16_t \
223 otx2_tim_arm_burst_ ## _name(const struct rte_event_timer_adapter *adptr, \
224 struct rte_event_timer **tim, \
225 const uint16_t nb_timers);
226 TIM_ARM_FASTPATH_MODES
227 #undef FP
228
229 #define FP(_name, _f3, _f2, _f1, flags) \
230 uint16_t \
231 otx2_tim_arm_tmo_tick_burst_ ## _name( \
232 const struct rte_event_timer_adapter *adptr, \
233 struct rte_event_timer **tim, \
234 const uint64_t timeout_tick, const uint16_t nb_timers);
235 TIM_ARM_TMO_FASTPATH_MODES
236 #undef FP
237
238 uint16_t otx2_tim_timer_cancel_burst(
239 const struct rte_event_timer_adapter *adptr,
240 struct rte_event_timer **tim, const uint16_t nb_timers);
241
242 int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
243 uint32_t *caps,
244 const struct rte_event_timer_adapter_ops **ops);
245
246 void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);
247 void otx2_tim_fini(void);
248
249 /* TIM IRQ */
250 int tim_register_irq(uint16_t ring_id);
251 void tim_unregister_irq(uint16_t ring_id);
252
253 #endif /* __OTX2_TIM_EVDEV_H__ */
254