1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
3 */
4
5 #include <inttypes.h>
6
7 #include <rte_ethdev_pci.h>
8 #include <rte_io.h>
9 #include <rte_malloc.h>
10 #include <rte_mbuf.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
13
14 #include "otx2_ethdev.h"
15 #include "otx2_ethdev_sec.h"
16
17 static inline uint64_t
nix_get_rx_offload_capa(struct otx2_eth_dev * dev)18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 {
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21
22 if (otx2_dev_is_vf(dev) ||
23 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
24 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
25
26 return capa;
27 }
28
29 static inline uint64_t
nix_get_tx_offload_capa(struct otx2_eth_dev * dev)30 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
31 {
32 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
33
34 /* TSO not supported for earlier chip revisions */
35 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
36 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
37 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
38 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
39 DEV_TX_OFFLOAD_GRE_TNL_TSO);
40 return capa;
41 }
42
43 static const struct otx2_dev_ops otx2_dev_ops = {
44 .link_status_update = otx2_eth_dev_link_status_update,
45 .ptp_info_update = otx2_eth_dev_ptp_info_update
46 };
47
48 static int
nix_lf_alloc(struct otx2_eth_dev * dev,uint32_t nb_rxq,uint32_t nb_txq)49 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
50 {
51 struct otx2_mbox *mbox = dev->mbox;
52 struct nix_lf_alloc_req *req;
53 struct nix_lf_alloc_rsp *rsp;
54 int rc;
55
56 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
57 req->rq_cnt = nb_rxq;
58 req->sq_cnt = nb_txq;
59 req->cq_cnt = nb_rxq;
60 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
61 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
62 req->xqe_sz = NIX_XQESZ_W16;
63 req->rss_sz = dev->rss_info.rss_size;
64 req->rss_grps = NIX_RSS_GRPS;
65 req->npa_func = otx2_npa_pf_func_get();
66 req->sso_func = otx2_sso_pf_func_get();
67 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
68 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
69 DEV_RX_OFFLOAD_UDP_CKSUM)) {
70 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
71 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
72 }
73 req->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) |
74 BIT_ULL(33 /* Outer L2 Length */) |
75 BIT_ULL(38 /* Inner L4 UDP Length */) |
76 BIT_ULL(39 /* Inner L3 Length */) |
77 BIT_ULL(40 /* Outer L4 UDP Length */) |
78 BIT_ULL(41 /* Outer L3 Length */));
79
80 if (dev->rss_tag_as_xor == 0)
81 req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
82
83 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
84 if (rc)
85 return rc;
86
87 dev->sqb_size = rsp->sqb_size;
88 dev->tx_chan_base = rsp->tx_chan_base;
89 dev->rx_chan_base = rsp->rx_chan_base;
90 dev->rx_chan_cnt = rsp->rx_chan_cnt;
91 dev->tx_chan_cnt = rsp->tx_chan_cnt;
92 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
93 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
94 dev->lf_tx_stats = rsp->lf_tx_stats;
95 dev->lf_rx_stats = rsp->lf_rx_stats;
96 dev->cints = rsp->cints;
97 dev->qints = rsp->qints;
98 dev->npc_flow.channel = dev->rx_chan_base;
99 dev->ptp_en = rsp->hw_rx_tstamp_en;
100
101 return 0;
102 }
103
104 static int
nix_lf_switch_header_type_enable(struct otx2_eth_dev * dev,bool enable)105 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
106 {
107 struct otx2_mbox *mbox = dev->mbox;
108 struct npc_set_pkind *req;
109 struct msg_resp *rsp;
110 int rc;
111
112 if (dev->npc_flow.switch_header_type == 0)
113 return 0;
114
115 if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B &&
116 !otx2_dev_is_sdp(dev)) {
117 otx2_err("chlen90b is not supported on non-SDP device");
118 return -EINVAL;
119 }
120
121 /* Notify AF about higig2 config */
122 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
123 req->mode = dev->npc_flow.switch_header_type;
124 if (enable == 0)
125 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
126 req->dir = PKIND_RX;
127 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
128 if (rc)
129 return rc;
130 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
131 req->mode = dev->npc_flow.switch_header_type;
132 if (enable == 0)
133 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
134 req->dir = PKIND_TX;
135 return otx2_mbox_process_msg(mbox, (void *)&rsp);
136 }
137
138 static int
nix_lf_free(struct otx2_eth_dev * dev)139 nix_lf_free(struct otx2_eth_dev *dev)
140 {
141 struct otx2_mbox *mbox = dev->mbox;
142 struct nix_lf_free_req *req;
143 struct ndc_sync_op *ndc_req;
144 int rc;
145
146 /* Sync NDC-NIX for LF */
147 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
148 ndc_req->nix_lf_tx_sync = 1;
149 ndc_req->nix_lf_rx_sync = 1;
150 rc = otx2_mbox_process(mbox);
151 if (rc)
152 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
153
154 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
155 /* Let AF driver free all this nix lf's
156 * NPC entries allocated using NPC MBOX.
157 */
158 req->flags = 0;
159
160 return otx2_mbox_process(mbox);
161 }
162
163 int
otx2_cgx_rxtx_start(struct otx2_eth_dev * dev)164 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
165 {
166 struct otx2_mbox *mbox = dev->mbox;
167
168 if (otx2_dev_is_vf_or_sdp(dev))
169 return 0;
170
171 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
172
173 return otx2_mbox_process(mbox);
174 }
175
176 int
otx2_cgx_rxtx_stop(struct otx2_eth_dev * dev)177 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
178 {
179 struct otx2_mbox *mbox = dev->mbox;
180
181 if (otx2_dev_is_vf_or_sdp(dev))
182 return 0;
183
184 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
185
186 return otx2_mbox_process(mbox);
187 }
188
189 static int
npc_rx_enable(struct otx2_eth_dev * dev)190 npc_rx_enable(struct otx2_eth_dev *dev)
191 {
192 struct otx2_mbox *mbox = dev->mbox;
193
194 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
195
196 return otx2_mbox_process(mbox);
197 }
198
199 static int
npc_rx_disable(struct otx2_eth_dev * dev)200 npc_rx_disable(struct otx2_eth_dev *dev)
201 {
202 struct otx2_mbox *mbox = dev->mbox;
203
204 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
205
206 return otx2_mbox_process(mbox);
207 }
208
209 static int
nix_cgx_start_link_event(struct otx2_eth_dev * dev)210 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
211 {
212 struct otx2_mbox *mbox = dev->mbox;
213
214 if (otx2_dev_is_vf_or_sdp(dev))
215 return 0;
216
217 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
218
219 return otx2_mbox_process(mbox);
220 }
221
222 static int
cgx_intlbk_enable(struct otx2_eth_dev * dev,bool en)223 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
224 {
225 struct otx2_mbox *mbox = dev->mbox;
226
227 if (en && otx2_dev_is_vf_or_sdp(dev))
228 return -ENOTSUP;
229
230 if (en)
231 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
232 else
233 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
234
235 return otx2_mbox_process(mbox);
236 }
237
238 static int
nix_cgx_stop_link_event(struct otx2_eth_dev * dev)239 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
240 {
241 struct otx2_mbox *mbox = dev->mbox;
242
243 if (otx2_dev_is_vf_or_sdp(dev))
244 return 0;
245
246 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
247
248 return otx2_mbox_process(mbox);
249 }
250
251 static inline void
nix_rx_queue_reset(struct otx2_eth_rxq * rxq)252 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
253 {
254 rxq->head = 0;
255 rxq->available = 0;
256 }
257
258 static inline uint32_t
nix_qsize_to_val(enum nix_q_size_e qsize)259 nix_qsize_to_val(enum nix_q_size_e qsize)
260 {
261 return (16UL << (qsize * 2));
262 }
263
264 static inline enum nix_q_size_e
nix_qsize_clampup_get(struct otx2_eth_dev * dev,uint32_t val)265 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
266 {
267 int i;
268
269 if (otx2_ethdev_fixup_is_min_4k_q(dev))
270 i = nix_q_size_4K;
271 else
272 i = nix_q_size_16;
273
274 for (; i < nix_q_size_max; i++)
275 if (val <= nix_qsize_to_val(i))
276 break;
277
278 if (i >= nix_q_size_max)
279 i = nix_q_size_max - 1;
280
281 return i;
282 }
283
284 static int
nix_cq_rq_init(struct rte_eth_dev * eth_dev,struct otx2_eth_dev * dev,uint16_t qid,struct otx2_eth_rxq * rxq,struct rte_mempool * mp)285 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
286 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
287 {
288 struct otx2_mbox *mbox = dev->mbox;
289 const struct rte_memzone *rz;
290 uint32_t ring_size, cq_size;
291 struct nix_aq_enq_req *aq;
292 uint16_t first_skip;
293 int rc;
294
295 cq_size = rxq->qlen;
296 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
297 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
298 NIX_CQ_ALIGN, dev->node);
299 if (rz == NULL) {
300 otx2_err("Failed to allocate mem for cq hw ring");
301 return -ENOMEM;
302 }
303 memset(rz->addr, 0, rz->len);
304 rxq->desc = (uintptr_t)rz->addr;
305 rxq->qmask = cq_size - 1;
306
307 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
308 aq->qidx = qid;
309 aq->ctype = NIX_AQ_CTYPE_CQ;
310 aq->op = NIX_AQ_INSTOP_INIT;
311
312 aq->cq.ena = 1;
313 aq->cq.caching = 1;
314 aq->cq.qsize = rxq->qsize;
315 aq->cq.base = rz->iova;
316 aq->cq.avg_level = 0xff;
317 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
318 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
319
320 /* Many to one reduction */
321 aq->cq.qint_idx = qid % dev->qints;
322 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
323 aq->cq.cint_idx = qid;
324
325 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
326 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
327 uint16_t min_rx_drop;
328
329 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
330 aq->cq.drop = min_rx_drop;
331 aq->cq.drop_ena = 1;
332 rxq->cq_drop = min_rx_drop;
333 } else {
334 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
335 aq->cq.drop = rxq->cq_drop;
336 aq->cq.drop_ena = 1;
337 }
338
339 /* TX pause frames enable flowctrl on RX side */
340 if (dev->fc_info.tx_pause) {
341 /* Single bpid is allocated for all rx channels for now */
342 aq->cq.bpid = dev->fc_info.bpid[0];
343 aq->cq.bp = rxq->cq_drop;
344 aq->cq.bp_ena = 1;
345 }
346
347 rc = otx2_mbox_process(mbox);
348 if (rc) {
349 otx2_err("Failed to init cq context");
350 return rc;
351 }
352
353 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
354 aq->qidx = qid;
355 aq->ctype = NIX_AQ_CTYPE_RQ;
356 aq->op = NIX_AQ_INSTOP_INIT;
357
358 aq->rq.sso_ena = 0;
359
360 if (rxq->offloads & DEV_RX_OFFLOAD_SECURITY)
361 aq->rq.ipsech_ena = 1;
362
363 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
364 aq->rq.spb_ena = 0;
365 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
366 first_skip = (sizeof(struct rte_mbuf));
367 first_skip += RTE_PKTMBUF_HEADROOM;
368 first_skip += rte_pktmbuf_priv_size(mp);
369 rxq->data_off = first_skip;
370
371 first_skip /= 8; /* Expressed in number of dwords */
372 aq->rq.first_skip = first_skip;
373 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
374 aq->rq.flow_tagw = 32; /* 32-bits */
375 aq->rq.lpb_sizem1 = mp->elt_size / 8;
376 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
377 aq->rq.ena = 1;
378 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
379 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
380 aq->rq.rq_int_ena = 0;
381 /* Many to one reduction */
382 aq->rq.qint_idx = qid % dev->qints;
383
384 aq->rq.xqe_drop_ena = 1;
385
386 rc = otx2_mbox_process(mbox);
387 if (rc) {
388 otx2_err("Failed to init rq context");
389 return rc;
390 }
391
392 if (dev->lock_rx_ctx) {
393 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
394 aq->qidx = qid;
395 aq->ctype = NIX_AQ_CTYPE_CQ;
396 aq->op = NIX_AQ_INSTOP_LOCK;
397
398 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
399 if (!aq) {
400 /* The shared memory buffer can be full.
401 * Flush it and retry
402 */
403 otx2_mbox_msg_send(mbox, 0);
404 rc = otx2_mbox_wait_for_rsp(mbox, 0);
405 if (rc < 0) {
406 otx2_err("Failed to LOCK cq context");
407 return rc;
408 }
409
410 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
411 if (!aq) {
412 otx2_err("Failed to LOCK rq context");
413 return -ENOMEM;
414 }
415 }
416 aq->qidx = qid;
417 aq->ctype = NIX_AQ_CTYPE_RQ;
418 aq->op = NIX_AQ_INSTOP_LOCK;
419 rc = otx2_mbox_process(mbox);
420 if (rc < 0) {
421 otx2_err("Failed to LOCK rq context");
422 return rc;
423 }
424 }
425
426 return 0;
427 }
428
429 static int
nix_rq_enb_dis(struct rte_eth_dev * eth_dev,struct otx2_eth_rxq * rxq,const bool enb)430 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
431 struct otx2_eth_rxq *rxq, const bool enb)
432 {
433 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
434 struct otx2_mbox *mbox = dev->mbox;
435 struct nix_aq_enq_req *aq;
436
437 /* Pkts will be dropped silently if RQ is disabled */
438 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
439 aq->qidx = rxq->rq;
440 aq->ctype = NIX_AQ_CTYPE_RQ;
441 aq->op = NIX_AQ_INSTOP_WRITE;
442
443 aq->rq.ena = enb;
444 aq->rq_mask.ena = ~(aq->rq_mask.ena);
445
446 return otx2_mbox_process(mbox);
447 }
448
449 static int
nix_cq_rq_uninit(struct rte_eth_dev * eth_dev,struct otx2_eth_rxq * rxq)450 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
451 {
452 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
453 struct otx2_mbox *mbox = dev->mbox;
454 struct nix_aq_enq_req *aq;
455 int rc;
456
457 /* RQ is already disabled */
458 /* Disable CQ */
459 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
460 aq->qidx = rxq->rq;
461 aq->ctype = NIX_AQ_CTYPE_CQ;
462 aq->op = NIX_AQ_INSTOP_WRITE;
463
464 aq->cq.ena = 0;
465 aq->cq_mask.ena = ~(aq->cq_mask.ena);
466
467 rc = otx2_mbox_process(mbox);
468 if (rc < 0) {
469 otx2_err("Failed to disable cq context");
470 return rc;
471 }
472
473 if (dev->lock_rx_ctx) {
474 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
475 aq->qidx = rxq->rq;
476 aq->ctype = NIX_AQ_CTYPE_CQ;
477 aq->op = NIX_AQ_INSTOP_UNLOCK;
478
479 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
480 if (!aq) {
481 /* The shared memory buffer can be full.
482 * Flush it and retry
483 */
484 otx2_mbox_msg_send(mbox, 0);
485 rc = otx2_mbox_wait_for_rsp(mbox, 0);
486 if (rc < 0) {
487 otx2_err("Failed to UNLOCK cq context");
488 return rc;
489 }
490
491 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
492 if (!aq) {
493 otx2_err("Failed to UNLOCK rq context");
494 return -ENOMEM;
495 }
496 }
497 aq->qidx = rxq->rq;
498 aq->ctype = NIX_AQ_CTYPE_RQ;
499 aq->op = NIX_AQ_INSTOP_UNLOCK;
500 rc = otx2_mbox_process(mbox);
501 if (rc < 0) {
502 otx2_err("Failed to UNLOCK rq context");
503 return rc;
504 }
505 }
506
507 return 0;
508 }
509
510 static inline int
nix_get_data_off(struct otx2_eth_dev * dev)511 nix_get_data_off(struct otx2_eth_dev *dev)
512 {
513 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
514 }
515
516 uint64_t
otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev * dev,uint16_t port_id)517 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
518 {
519 struct rte_mbuf mb_def;
520 uint64_t *tmp;
521
522 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
523 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
524 offsetof(struct rte_mbuf, data_off) != 2);
525 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
526 offsetof(struct rte_mbuf, data_off) != 4);
527 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
528 offsetof(struct rte_mbuf, data_off) != 6);
529 mb_def.nb_segs = 1;
530 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
531 mb_def.port = port_id;
532 rte_mbuf_refcnt_set(&mb_def, 1);
533
534 /* Prevent compiler reordering: rearm_data covers previous fields */
535 rte_compiler_barrier();
536 tmp = (uint64_t *)&mb_def.rearm_data;
537
538 return *tmp;
539 }
540
541 static void
otx2_nix_rx_queue_release(void * rx_queue)542 otx2_nix_rx_queue_release(void *rx_queue)
543 {
544 struct otx2_eth_rxq *rxq = rx_queue;
545
546 if (!rxq)
547 return;
548
549 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
550 nix_cq_rq_uninit(rxq->eth_dev, rxq);
551 rte_free(rx_queue);
552 }
553
554 static int
otx2_nix_rx_queue_setup(struct rte_eth_dev * eth_dev,uint16_t rq,uint16_t nb_desc,unsigned int socket,const struct rte_eth_rxconf * rx_conf,struct rte_mempool * mp)555 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
556 uint16_t nb_desc, unsigned int socket,
557 const struct rte_eth_rxconf *rx_conf,
558 struct rte_mempool *mp)
559 {
560 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
561 struct rte_mempool_ops *ops;
562 struct otx2_eth_rxq *rxq;
563 const char *platform_ops;
564 enum nix_q_size_e qsize;
565 uint64_t offloads;
566 int rc;
567
568 rc = -EINVAL;
569
570 /* Compile time check to make sure all fast path elements in a CL */
571 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
572
573 /* Sanity checks */
574 if (rx_conf->rx_deferred_start == 1) {
575 otx2_err("Deferred Rx start is not supported");
576 goto fail;
577 }
578
579 platform_ops = rte_mbuf_platform_mempool_ops();
580 /* This driver needs octeontx2_npa mempool ops to work */
581 ops = rte_mempool_get_ops(mp->ops_index);
582 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
583 otx2_err("mempool ops should be of octeontx2_npa type");
584 goto fail;
585 }
586
587 if (mp->pool_id == 0) {
588 otx2_err("Invalid pool_id");
589 goto fail;
590 }
591
592 /* Free memory prior to re-allocation if needed */
593 if (eth_dev->data->rx_queues[rq] != NULL) {
594 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
595 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
596 rte_eth_dma_zone_free(eth_dev, "cq", rq);
597 eth_dev->data->rx_queues[rq] = NULL;
598 }
599
600 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
601 dev->rx_offloads |= offloads;
602
603 /* Find the CQ queue size */
604 qsize = nix_qsize_clampup_get(dev, nb_desc);
605 /* Allocate rxq memory */
606 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
607 if (rxq == NULL) {
608 otx2_err("Failed to allocate rq=%d", rq);
609 rc = -ENOMEM;
610 goto fail;
611 }
612
613 rxq->eth_dev = eth_dev;
614 rxq->rq = rq;
615 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
616 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
617 rxq->wdata = (uint64_t)rq << 32;
618 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
619 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
620 eth_dev->data->port_id);
621 rxq->offloads = offloads;
622 rxq->pool = mp;
623 rxq->qlen = nix_qsize_to_val(qsize);
624 rxq->qsize = qsize;
625 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
626 rxq->tstamp = &dev->tstamp;
627
628 /* Alloc completion queue */
629 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
630 if (rc) {
631 otx2_err("Failed to allocate rxq=%u", rq);
632 goto free_rxq;
633 }
634
635 rxq->qconf.socket_id = socket;
636 rxq->qconf.nb_desc = nb_desc;
637 rxq->qconf.mempool = mp;
638 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
639
640 nix_rx_queue_reset(rxq);
641 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
642 rq, mp->name, qsize, nb_desc, rxq->qlen);
643
644 eth_dev->data->rx_queues[rq] = rxq;
645 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
646
647 /* Calculating delta and freq mult between PTP HI clock and tsc.
648 * These are needed in deriving raw clock value from tsc counter.
649 * read_clock eth op returns raw clock value.
650 */
651 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
652 otx2_ethdev_is_ptp_en(dev)) {
653 rc = otx2_nix_raw_clock_tsc_conv(dev);
654 if (rc) {
655 otx2_err("Failed to calculate delta and freq mult");
656 goto fail;
657 }
658 }
659
660 /* Setup scatter mode if needed by jumbo */
661 otx2_nix_enable_mseg_on_jumbo(rxq);
662
663 return 0;
664
665 free_rxq:
666 otx2_nix_rx_queue_release(rxq);
667 fail:
668 return rc;
669 }
670
671 static inline uint8_t
nix_sq_max_sqe_sz(struct otx2_eth_txq * txq)672 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
673 {
674 /*
675 * Maximum three segments can be supported with W8, Choose
676 * NIX_MAXSQESZ_W16 for multi segment offload.
677 */
678 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
679 return NIX_MAXSQESZ_W16;
680 else
681 return NIX_MAXSQESZ_W8;
682 }
683
684 static uint16_t
nix_rx_offload_flags(struct rte_eth_dev * eth_dev)685 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
686 {
687 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
688 struct rte_eth_dev_data *data = eth_dev->data;
689 struct rte_eth_conf *conf = &data->dev_conf;
690 struct rte_eth_rxmode *rxmode = &conf->rxmode;
691 uint16_t flags = 0;
692
693 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
694 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
695 flags |= NIX_RX_OFFLOAD_RSS_F;
696
697 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
698 DEV_RX_OFFLOAD_UDP_CKSUM))
699 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
700
701 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
702 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
703 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
704
705 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
706 flags |= NIX_RX_MULTI_SEG_F;
707
708 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
709 DEV_RX_OFFLOAD_QINQ_STRIP))
710 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
711
712 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
713 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
714
715 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
716 flags |= NIX_RX_OFFLOAD_SECURITY_F;
717
718 if (!dev->ptype_disable)
719 flags |= NIX_RX_OFFLOAD_PTYPE_F;
720
721 return flags;
722 }
723
724 static uint16_t
nix_tx_offload_flags(struct rte_eth_dev * eth_dev)725 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
726 {
727 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
728 uint64_t conf = dev->tx_offloads;
729 uint16_t flags = 0;
730
731 /* Fastpath is dependent on these enums */
732 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
733 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
734 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
735 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
736 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
737 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
738 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
739 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
740 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
741 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
742 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
743 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
744 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
745 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
746 offsetof(struct rte_mbuf, buf_iova) + 8);
747 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
748 offsetof(struct rte_mbuf, buf_iova) + 16);
749 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
750 offsetof(struct rte_mbuf, ol_flags) + 12);
751 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
752 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
753
754 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
755 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
756 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
757
758 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
759 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
760 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
761
762 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
763 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
764 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
765 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
766 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
767
768 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
769 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
770
771 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
772 flags |= NIX_TX_MULTI_SEG_F;
773
774 /* Enable Inner checksum for TSO */
775 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
776 flags |= (NIX_TX_OFFLOAD_TSO_F |
777 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
778
779 /* Enable Inner and Outer checksum for Tunnel TSO */
780 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
781 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
782 DEV_TX_OFFLOAD_GRE_TNL_TSO))
783 flags |= (NIX_TX_OFFLOAD_TSO_F |
784 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
785 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
786
787 if (conf & DEV_TX_OFFLOAD_SECURITY)
788 flags |= NIX_TX_OFFLOAD_SECURITY_F;
789
790 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
791 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
792
793 return flags;
794 }
795
796 static int
nix_sqb_lock(struct rte_mempool * mp)797 nix_sqb_lock(struct rte_mempool *mp)
798 {
799 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
800 struct npa_aq_enq_req *req;
801 int rc;
802
803 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
804 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
805 req->ctype = NPA_AQ_CTYPE_AURA;
806 req->op = NPA_AQ_INSTOP_LOCK;
807
808 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
809 if (!req) {
810 /* The shared memory buffer can be full.
811 * Flush it and retry
812 */
813 otx2_mbox_msg_send(npa_lf->mbox, 0);
814 rc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);
815 if (rc < 0) {
816 otx2_err("Failed to LOCK AURA context");
817 return rc;
818 }
819
820 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
821 if (!req) {
822 otx2_err("Failed to LOCK POOL context");
823 return -ENOMEM;
824 }
825 }
826
827 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
828 req->ctype = NPA_AQ_CTYPE_POOL;
829 req->op = NPA_AQ_INSTOP_LOCK;
830
831 rc = otx2_mbox_process(npa_lf->mbox);
832 if (rc < 0) {
833 otx2_err("Unable to lock POOL in NDC");
834 return rc;
835 }
836
837 return 0;
838 }
839
840 static int
nix_sqb_unlock(struct rte_mempool * mp)841 nix_sqb_unlock(struct rte_mempool *mp)
842 {
843 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
844 struct npa_aq_enq_req *req;
845 int rc;
846
847 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
848 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
849 req->ctype = NPA_AQ_CTYPE_AURA;
850 req->op = NPA_AQ_INSTOP_UNLOCK;
851
852 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
853 if (!req) {
854 /* The shared memory buffer can be full.
855 * Flush it and retry
856 */
857 otx2_mbox_msg_send(npa_lf->mbox, 0);
858 rc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);
859 if (rc < 0) {
860 otx2_err("Failed to UNLOCK AURA context");
861 return rc;
862 }
863
864 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
865 if (!req) {
866 otx2_err("Failed to UNLOCK POOL context");
867 return -ENOMEM;
868 }
869 }
870 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
871 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
872 req->ctype = NPA_AQ_CTYPE_POOL;
873 req->op = NPA_AQ_INSTOP_UNLOCK;
874
875 rc = otx2_mbox_process(npa_lf->mbox);
876 if (rc < 0) {
877 otx2_err("Unable to UNLOCK AURA in NDC");
878 return rc;
879 }
880
881 return 0;
882 }
883
884 void
otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq * rxq)885 otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq)
886 {
887 struct rte_pktmbuf_pool_private *mbp_priv;
888 struct rte_eth_dev *eth_dev;
889 struct otx2_eth_dev *dev;
890 uint32_t buffsz;
891
892 eth_dev = rxq->eth_dev;
893 dev = otx2_eth_pmd_priv(eth_dev);
894
895 /* Get rx buffer size */
896 mbp_priv = rte_mempool_get_priv(rxq->pool);
897 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
898
899 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buffsz) {
900 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
901 dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
902
903 /* Setting up the rx[tx]_offload_flags due to change
904 * in rx[tx]_offloads.
905 */
906 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
907 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
908 }
909 }
910
911 static int
nix_sq_init(struct otx2_eth_txq * txq)912 nix_sq_init(struct otx2_eth_txq *txq)
913 {
914 struct otx2_eth_dev *dev = txq->dev;
915 struct otx2_mbox *mbox = dev->mbox;
916 struct nix_aq_enq_req *sq;
917 uint32_t rr_quantum;
918 uint16_t smq;
919 int rc;
920
921 if (txq->sqb_pool->pool_id == 0)
922 return -EINVAL;
923
924 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
925 if (rc) {
926 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
927 return rc;
928 }
929
930 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
931 sq->qidx = txq->sq;
932 sq->ctype = NIX_AQ_CTYPE_SQ;
933 sq->op = NIX_AQ_INSTOP_INIT;
934 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
935
936 sq->sq.smq = smq;
937 sq->sq.smq_rr_quantum = rr_quantum;
938 sq->sq.default_chan = dev->tx_chan_base;
939 sq->sq.sqe_stype = NIX_STYPE_STF;
940 sq->sq.ena = 1;
941 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
942 sq->sq.sqe_stype = NIX_STYPE_STP;
943 sq->sq.sqb_aura =
944 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
945 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
946 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
947 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
948 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
949
950 /* Many to one reduction */
951 sq->sq.qint_idx = txq->sq % dev->qints;
952
953 rc = otx2_mbox_process(mbox);
954 if (rc < 0)
955 return rc;
956
957 if (dev->lock_tx_ctx) {
958 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
959 sq->qidx = txq->sq;
960 sq->ctype = NIX_AQ_CTYPE_SQ;
961 sq->op = NIX_AQ_INSTOP_LOCK;
962
963 rc = otx2_mbox_process(mbox);
964 }
965
966 return rc;
967 }
968
969 static int
nix_sq_uninit(struct otx2_eth_txq * txq)970 nix_sq_uninit(struct otx2_eth_txq *txq)
971 {
972 struct otx2_eth_dev *dev = txq->dev;
973 struct otx2_mbox *mbox = dev->mbox;
974 struct ndc_sync_op *ndc_req;
975 struct nix_aq_enq_rsp *rsp;
976 struct nix_aq_enq_req *aq;
977 uint16_t sqes_per_sqb;
978 void *sqb_buf;
979 int rc, count;
980
981 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
982
983 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
984 aq->qidx = txq->sq;
985 aq->ctype = NIX_AQ_CTYPE_SQ;
986 aq->op = NIX_AQ_INSTOP_READ;
987
988 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
989 if (rc)
990 return rc;
991
992 /* Check if sq is already cleaned up */
993 if (!rsp->sq.ena)
994 return 0;
995
996 /* Disable sq */
997 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
998 aq->qidx = txq->sq;
999 aq->ctype = NIX_AQ_CTYPE_SQ;
1000 aq->op = NIX_AQ_INSTOP_WRITE;
1001
1002 aq->sq_mask.ena = ~aq->sq_mask.ena;
1003 aq->sq.ena = 0;
1004
1005 rc = otx2_mbox_process(mbox);
1006 if (rc)
1007 return rc;
1008
1009 if (dev->lock_tx_ctx) {
1010 /* Unlock sq */
1011 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1012 aq->qidx = txq->sq;
1013 aq->ctype = NIX_AQ_CTYPE_SQ;
1014 aq->op = NIX_AQ_INSTOP_UNLOCK;
1015
1016 rc = otx2_mbox_process(mbox);
1017 if (rc < 0)
1018 return rc;
1019
1020 nix_sqb_unlock(txq->sqb_pool);
1021 }
1022
1023 /* Read SQ and free sqb's */
1024 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1025 aq->qidx = txq->sq;
1026 aq->ctype = NIX_AQ_CTYPE_SQ;
1027 aq->op = NIX_AQ_INSTOP_READ;
1028
1029 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1030 if (rc)
1031 return rc;
1032
1033 if (aq->sq.smq_pend)
1034 otx2_err("SQ has pending sqe's");
1035
1036 count = aq->sq.sqb_count;
1037 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
1038 /* Free SQB's that are used */
1039 sqb_buf = (void *)rsp->sq.head_sqb;
1040 while (count) {
1041 void *next_sqb;
1042
1043 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
1044 ((sqes_per_sqb - 1) *
1045 nix_sq_max_sqe_sz(txq)));
1046 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
1047 (uint64_t)sqb_buf);
1048 sqb_buf = next_sqb;
1049 count--;
1050 }
1051
1052 /* Free next to use sqb */
1053 if (rsp->sq.next_sqb)
1054 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
1055 rsp->sq.next_sqb);
1056
1057 /* Sync NDC-NIX-TX for LF */
1058 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
1059 ndc_req->nix_lf_tx_sync = 1;
1060 rc = otx2_mbox_process(mbox);
1061 if (rc)
1062 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
1063
1064 return rc;
1065 }
1066
1067 static int
nix_sqb_aura_limit_cfg(struct rte_mempool * mp,uint16_t nb_sqb_bufs)1068 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
1069 {
1070 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
1071 struct npa_aq_enq_req *aura_req;
1072
1073 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
1074 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
1075 aura_req->ctype = NPA_AQ_CTYPE_AURA;
1076 aura_req->op = NPA_AQ_INSTOP_WRITE;
1077
1078 aura_req->aura.limit = nb_sqb_bufs;
1079 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
1080
1081 return otx2_mbox_process(npa_lf->mbox);
1082 }
1083
1084 static int
nix_alloc_sqb_pool(int port,struct otx2_eth_txq * txq,uint16_t nb_desc)1085 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
1086 {
1087 struct otx2_eth_dev *dev = txq->dev;
1088 uint16_t sqes_per_sqb, nb_sqb_bufs;
1089 char name[RTE_MEMPOOL_NAMESIZE];
1090 struct rte_mempool_objsz sz;
1091 struct npa_aura_s *aura;
1092 uint32_t tmp, blk_sz;
1093
1094 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
1095 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
1096 blk_sz = dev->sqb_size;
1097
1098 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
1099 sqes_per_sqb = (dev->sqb_size / 8) / 16;
1100 else
1101 sqes_per_sqb = (dev->sqb_size / 8) / 8;
1102
1103 nb_sqb_bufs = nb_desc / sqes_per_sqb;
1104 /* Clamp up to devarg passed SQB count */
1105 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
1106 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
1107
1108 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
1109 0, 0, dev->node,
1110 MEMPOOL_F_NO_SPREAD);
1111 txq->nb_sqb_bufs = nb_sqb_bufs;
1112 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
1113 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
1114 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
1115 txq->nb_sqb_bufs_adj =
1116 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
1117
1118 if (txq->sqb_pool == NULL) {
1119 otx2_err("Failed to allocate sqe mempool");
1120 goto fail;
1121 }
1122
1123 memset(aura, 0, sizeof(*aura));
1124 aura->fc_ena = 1;
1125 aura->fc_addr = txq->fc_iova;
1126 aura->fc_hyst_bits = 0; /* Store count on all updates */
1127 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
1128 otx2_err("Failed to set ops for sqe mempool");
1129 goto fail;
1130 }
1131 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
1132 otx2_err("Failed to populate sqe mempool");
1133 goto fail;
1134 }
1135
1136 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
1137 if (dev->sqb_size != sz.elt_size) {
1138 otx2_err("sqe pool block size is not expected %d != %d",
1139 dev->sqb_size, tmp);
1140 goto fail;
1141 }
1142
1143 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
1144 if (dev->lock_tx_ctx)
1145 nix_sqb_lock(txq->sqb_pool);
1146
1147 return 0;
1148 fail:
1149 return -ENOMEM;
1150 }
1151
1152 void
otx2_nix_form_default_desc(struct otx2_eth_txq * txq)1153 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
1154 {
1155 struct nix_send_ext_s *send_hdr_ext;
1156 struct nix_send_hdr_s *send_hdr;
1157 struct nix_send_mem_s *send_mem;
1158 union nix_send_sg_s *sg;
1159
1160 /* Initialize the fields based on basic single segment packet */
1161 memset(&txq->cmd, 0, sizeof(txq->cmd));
1162
1163 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
1164 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
1165 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
1166 send_hdr->w0.sizem1 = 2;
1167
1168 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
1169 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
1170 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
1171 /* Default: one seg packet would have:
1172 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
1173 * => 8/2 - 1 = 3
1174 */
1175 send_hdr->w0.sizem1 = 3;
1176 send_hdr_ext->w0.tstmp = 1;
1177
1178 /* To calculate the offset for send_mem,
1179 * send_hdr->w0.sizem1 * 2
1180 */
1181 send_mem = (struct nix_send_mem_s *)(txq->cmd +
1182 (send_hdr->w0.sizem1 << 1));
1183 send_mem->subdc = NIX_SUBDC_MEM;
1184 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
1185 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
1186 }
1187 sg = (union nix_send_sg_s *)&txq->cmd[4];
1188 } else {
1189 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
1190 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
1191 send_hdr->w0.sizem1 = 1;
1192 sg = (union nix_send_sg_s *)&txq->cmd[2];
1193 }
1194
1195 send_hdr->w0.sq = txq->sq;
1196 sg->subdc = NIX_SUBDC_SG;
1197 sg->segs = 1;
1198 sg->ld_type = NIX_SENDLDTYPE_LDD;
1199
1200 rte_smp_wmb();
1201 }
1202
1203 static void
otx2_nix_tx_queue_release(void * _txq)1204 otx2_nix_tx_queue_release(void *_txq)
1205 {
1206 struct otx2_eth_txq *txq = _txq;
1207 struct rte_eth_dev *eth_dev;
1208
1209 if (!txq)
1210 return;
1211
1212 eth_dev = txq->dev->eth_dev;
1213
1214 otx2_nix_dbg("Releasing txq %u", txq->sq);
1215
1216 /* Flush and disable tm */
1217 otx2_nix_sq_flush_pre(txq, eth_dev->data->dev_started);
1218
1219 /* Free sqb's and disable sq */
1220 nix_sq_uninit(txq);
1221
1222 if (txq->sqb_pool) {
1223 rte_mempool_free(txq->sqb_pool);
1224 txq->sqb_pool = NULL;
1225 }
1226 otx2_nix_sq_flush_post(txq);
1227 rte_free(txq);
1228 }
1229
1230
1231 static int
otx2_nix_tx_queue_setup(struct rte_eth_dev * eth_dev,uint16_t sq,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_txconf * tx_conf)1232 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
1233 uint16_t nb_desc, unsigned int socket_id,
1234 const struct rte_eth_txconf *tx_conf)
1235 {
1236 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1237 const struct rte_memzone *fc;
1238 struct otx2_eth_txq *txq;
1239 uint64_t offloads;
1240 int rc;
1241
1242 rc = -EINVAL;
1243
1244 /* Compile time check to make sure all fast path elements in a CL */
1245 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1246
1247 if (tx_conf->tx_deferred_start) {
1248 otx2_err("Tx deferred start is not supported");
1249 goto fail;
1250 }
1251
1252 /* Free memory prior to re-allocation if needed. */
1253 if (eth_dev->data->tx_queues[sq] != NULL) {
1254 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1255 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1256 eth_dev->data->tx_queues[sq] = NULL;
1257 }
1258
1259 /* Find the expected offloads for this queue */
1260 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1261
1262 /* Allocating tx queue data structure */
1263 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1264 OTX2_ALIGN, socket_id);
1265 if (txq == NULL) {
1266 otx2_err("Failed to alloc txq=%d", sq);
1267 rc = -ENOMEM;
1268 goto fail;
1269 }
1270 txq->sq = sq;
1271 txq->dev = dev;
1272 txq->sqb_pool = NULL;
1273 txq->offloads = offloads;
1274 dev->tx_offloads |= offloads;
1275
1276 /*
1277 * Allocate memory for flow control updates from HW.
1278 * Alloc one cache line, so that fits all FC_STYPE modes.
1279 */
1280 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1281 OTX2_ALIGN + sizeof(struct npa_aura_s),
1282 OTX2_ALIGN, dev->node);
1283 if (fc == NULL) {
1284 otx2_err("Failed to allocate mem for fcmem");
1285 rc = -ENOMEM;
1286 goto free_txq;
1287 }
1288 txq->fc_iova = fc->iova;
1289 txq->fc_mem = fc->addr;
1290
1291 /* Initialize the aura sqb pool */
1292 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1293 if (rc) {
1294 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1295 goto free_txq;
1296 }
1297
1298 /* Initialize the SQ */
1299 rc = nix_sq_init(txq);
1300 if (rc) {
1301 otx2_err("Failed to init sq=%d context", sq);
1302 goto free_txq;
1303 }
1304
1305 txq->fc_cache_pkts = 0;
1306 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1307 /* Evenly distribute LMT slot for each sq */
1308 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1309
1310 txq->qconf.socket_id = socket_id;
1311 txq->qconf.nb_desc = nb_desc;
1312 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1313
1314 otx2_nix_form_default_desc(txq);
1315
1316 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1317 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1318 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1319 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1320 eth_dev->data->tx_queues[sq] = txq;
1321 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1322 return 0;
1323
1324 free_txq:
1325 otx2_nix_tx_queue_release(txq);
1326 fail:
1327 return rc;
1328 }
1329
1330 static int
nix_store_queue_cfg_and_then_release(struct rte_eth_dev * eth_dev)1331 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1332 {
1333 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1334 struct otx2_eth_qconf *tx_qconf = NULL;
1335 struct otx2_eth_qconf *rx_qconf = NULL;
1336 struct otx2_eth_txq **txq;
1337 struct otx2_eth_rxq **rxq;
1338 int i, nb_rxq, nb_txq;
1339
1340 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1341 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1342
1343 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1344 if (tx_qconf == NULL) {
1345 otx2_err("Failed to allocate memory for tx_qconf");
1346 goto fail;
1347 }
1348
1349 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1350 if (rx_qconf == NULL) {
1351 otx2_err("Failed to allocate memory for rx_qconf");
1352 goto fail;
1353 }
1354
1355 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1356 for (i = 0; i < nb_txq; i++) {
1357 if (txq[i] == NULL) {
1358 tx_qconf[i].valid = false;
1359 otx2_info("txq[%d] is already released", i);
1360 continue;
1361 }
1362 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1363 tx_qconf[i].valid = true;
1364 otx2_nix_tx_queue_release(txq[i]);
1365 eth_dev->data->tx_queues[i] = NULL;
1366 }
1367
1368 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1369 for (i = 0; i < nb_rxq; i++) {
1370 if (rxq[i] == NULL) {
1371 rx_qconf[i].valid = false;
1372 otx2_info("rxq[%d] is already released", i);
1373 continue;
1374 }
1375 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1376 rx_qconf[i].valid = true;
1377 otx2_nix_rx_queue_release(rxq[i]);
1378 eth_dev->data->rx_queues[i] = NULL;
1379 }
1380
1381 dev->tx_qconf = tx_qconf;
1382 dev->rx_qconf = rx_qconf;
1383 return 0;
1384
1385 fail:
1386 free(tx_qconf);
1387 free(rx_qconf);
1388
1389 return -ENOMEM;
1390 }
1391
1392 static int
nix_restore_queue_cfg(struct rte_eth_dev * eth_dev)1393 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1394 {
1395 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1396 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1397 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1398 struct otx2_eth_txq **txq;
1399 struct otx2_eth_rxq **rxq;
1400 int rc, i, nb_rxq, nb_txq;
1401
1402 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1403 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1404
1405 rc = -ENOMEM;
1406 /* Setup tx & rx queues with previous configuration so
1407 * that the queues can be functional in cases like ports
1408 * are started without re configuring queues.
1409 *
1410 * Usual re config sequence is like below:
1411 * port_configure() {
1412 * if(reconfigure) {
1413 * queue_release()
1414 * queue_setup()
1415 * }
1416 * queue_configure() {
1417 * queue_release()
1418 * queue_setup()
1419 * }
1420 * }
1421 * port_start()
1422 *
1423 * In some application's control path, queue_configure() would
1424 * NOT be invoked for TXQs/RXQs in port_configure().
1425 * In such cases, queues can be functional after start as the
1426 * queues are already setup in port_configure().
1427 */
1428 for (i = 0; i < nb_txq; i++) {
1429 if (!tx_qconf[i].valid)
1430 continue;
1431 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1432 tx_qconf[i].socket_id,
1433 &tx_qconf[i].conf.tx);
1434 if (rc) {
1435 otx2_err("Failed to setup tx queue rc=%d", rc);
1436 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1437 for (i -= 1; i >= 0; i--)
1438 otx2_nix_tx_queue_release(txq[i]);
1439 goto fail;
1440 }
1441 }
1442
1443 free(tx_qconf); tx_qconf = NULL;
1444
1445 for (i = 0; i < nb_rxq; i++) {
1446 if (!rx_qconf[i].valid)
1447 continue;
1448 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1449 rx_qconf[i].socket_id,
1450 &rx_qconf[i].conf.rx,
1451 rx_qconf[i].mempool);
1452 if (rc) {
1453 otx2_err("Failed to setup rx queue rc=%d", rc);
1454 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1455 for (i -= 1; i >= 0; i--)
1456 otx2_nix_rx_queue_release(rxq[i]);
1457 goto release_tx_queues;
1458 }
1459 }
1460
1461 free(rx_qconf); rx_qconf = NULL;
1462
1463 return 0;
1464
1465 release_tx_queues:
1466 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1467 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1468 otx2_nix_tx_queue_release(txq[i]);
1469 fail:
1470 if (tx_qconf)
1471 free(tx_qconf);
1472 if (rx_qconf)
1473 free(rx_qconf);
1474
1475 return rc;
1476 }
1477
1478 static uint16_t
nix_eth_nop_burst(void * queue,struct rte_mbuf ** mbufs,uint16_t pkts)1479 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1480 {
1481 RTE_SET_USED(queue);
1482 RTE_SET_USED(mbufs);
1483 RTE_SET_USED(pkts);
1484
1485 return 0;
1486 }
1487
1488 static void
nix_set_nop_rxtx_function(struct rte_eth_dev * eth_dev)1489 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1490 {
1491 /* These dummy functions are required for supporting
1492 * some applications which reconfigure queues without
1493 * stopping tx burst and rx burst threads(eg kni app)
1494 * When the queues context is saved, txq/rxqs are released
1495 * which caused app crash since rx/tx burst is still
1496 * on different lcores
1497 */
1498 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1499 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1500 rte_mb();
1501 }
1502
1503 static void
nix_lso_tcp(struct nix_lso_format_cfg * req,bool v4)1504 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1505 {
1506 volatile struct nix_lso_format *field;
1507
1508 /* Format works only with TCP packet marked by OL3/OL4 */
1509 field = (volatile struct nix_lso_format *)&req->fields[0];
1510 req->field_mask = NIX_LSO_FIELD_MASK;
1511 /* Outer IPv4/IPv6 */
1512 field->layer = NIX_TXLAYER_OL3;
1513 field->offset = v4 ? 2 : 4;
1514 field->sizem1 = 1; /* 2B */
1515 field->alg = NIX_LSOALG_ADD_PAYLEN;
1516 field++;
1517 if (v4) {
1518 /* IPID field */
1519 field->layer = NIX_TXLAYER_OL3;
1520 field->offset = 4;
1521 field->sizem1 = 1;
1522 /* Incremented linearly per segment */
1523 field->alg = NIX_LSOALG_ADD_SEGNUM;
1524 field++;
1525 }
1526
1527 /* TCP sequence number update */
1528 field->layer = NIX_TXLAYER_OL4;
1529 field->offset = 4;
1530 field->sizem1 = 3; /* 4 bytes */
1531 field->alg = NIX_LSOALG_ADD_OFFSET;
1532 field++;
1533 /* TCP flags field */
1534 field->layer = NIX_TXLAYER_OL4;
1535 field->offset = 12;
1536 field->sizem1 = 1;
1537 field->alg = NIX_LSOALG_TCP_FLAGS;
1538 field++;
1539 }
1540
1541 static void
nix_lso_udp_tun_tcp(struct nix_lso_format_cfg * req,bool outer_v4,bool inner_v4)1542 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1543 bool outer_v4, bool inner_v4)
1544 {
1545 volatile struct nix_lso_format *field;
1546
1547 field = (volatile struct nix_lso_format *)&req->fields[0];
1548 req->field_mask = NIX_LSO_FIELD_MASK;
1549 /* Outer IPv4/IPv6 len */
1550 field->layer = NIX_TXLAYER_OL3;
1551 field->offset = outer_v4 ? 2 : 4;
1552 field->sizem1 = 1; /* 2B */
1553 field->alg = NIX_LSOALG_ADD_PAYLEN;
1554 field++;
1555 if (outer_v4) {
1556 /* IPID */
1557 field->layer = NIX_TXLAYER_OL3;
1558 field->offset = 4;
1559 field->sizem1 = 1;
1560 /* Incremented linearly per segment */
1561 field->alg = NIX_LSOALG_ADD_SEGNUM;
1562 field++;
1563 }
1564
1565 /* Outer UDP length */
1566 field->layer = NIX_TXLAYER_OL4;
1567 field->offset = 4;
1568 field->sizem1 = 1;
1569 field->alg = NIX_LSOALG_ADD_PAYLEN;
1570 field++;
1571
1572 /* Inner IPv4/IPv6 */
1573 field->layer = NIX_TXLAYER_IL3;
1574 field->offset = inner_v4 ? 2 : 4;
1575 field->sizem1 = 1; /* 2B */
1576 field->alg = NIX_LSOALG_ADD_PAYLEN;
1577 field++;
1578 if (inner_v4) {
1579 /* IPID field */
1580 field->layer = NIX_TXLAYER_IL3;
1581 field->offset = 4;
1582 field->sizem1 = 1;
1583 /* Incremented linearly per segment */
1584 field->alg = NIX_LSOALG_ADD_SEGNUM;
1585 field++;
1586 }
1587
1588 /* TCP sequence number update */
1589 field->layer = NIX_TXLAYER_IL4;
1590 field->offset = 4;
1591 field->sizem1 = 3; /* 4 bytes */
1592 field->alg = NIX_LSOALG_ADD_OFFSET;
1593 field++;
1594
1595 /* TCP flags field */
1596 field->layer = NIX_TXLAYER_IL4;
1597 field->offset = 12;
1598 field->sizem1 = 1;
1599 field->alg = NIX_LSOALG_TCP_FLAGS;
1600 field++;
1601 }
1602
1603 static void
nix_lso_tun_tcp(struct nix_lso_format_cfg * req,bool outer_v4,bool inner_v4)1604 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1605 bool outer_v4, bool inner_v4)
1606 {
1607 volatile struct nix_lso_format *field;
1608
1609 field = (volatile struct nix_lso_format *)&req->fields[0];
1610 req->field_mask = NIX_LSO_FIELD_MASK;
1611 /* Outer IPv4/IPv6 len */
1612 field->layer = NIX_TXLAYER_OL3;
1613 field->offset = outer_v4 ? 2 : 4;
1614 field->sizem1 = 1; /* 2B */
1615 field->alg = NIX_LSOALG_ADD_PAYLEN;
1616 field++;
1617 if (outer_v4) {
1618 /* IPID */
1619 field->layer = NIX_TXLAYER_OL3;
1620 field->offset = 4;
1621 field->sizem1 = 1;
1622 /* Incremented linearly per segment */
1623 field->alg = NIX_LSOALG_ADD_SEGNUM;
1624 field++;
1625 }
1626
1627 /* Inner IPv4/IPv6 */
1628 field->layer = NIX_TXLAYER_IL3;
1629 field->offset = inner_v4 ? 2 : 4;
1630 field->sizem1 = 1; /* 2B */
1631 field->alg = NIX_LSOALG_ADD_PAYLEN;
1632 field++;
1633 if (inner_v4) {
1634 /* IPID field */
1635 field->layer = NIX_TXLAYER_IL3;
1636 field->offset = 4;
1637 field->sizem1 = 1;
1638 /* Incremented linearly per segment */
1639 field->alg = NIX_LSOALG_ADD_SEGNUM;
1640 field++;
1641 }
1642
1643 /* TCP sequence number update */
1644 field->layer = NIX_TXLAYER_IL4;
1645 field->offset = 4;
1646 field->sizem1 = 3; /* 4 bytes */
1647 field->alg = NIX_LSOALG_ADD_OFFSET;
1648 field++;
1649
1650 /* TCP flags field */
1651 field->layer = NIX_TXLAYER_IL4;
1652 field->offset = 12;
1653 field->sizem1 = 1;
1654 field->alg = NIX_LSOALG_TCP_FLAGS;
1655 field++;
1656 }
1657
1658 static int
nix_setup_lso_formats(struct otx2_eth_dev * dev)1659 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1660 {
1661 struct otx2_mbox *mbox = dev->mbox;
1662 struct nix_lso_format_cfg_rsp *rsp;
1663 struct nix_lso_format_cfg *req;
1664 uint8_t base;
1665 int rc;
1666
1667 /* Skip if TSO was not requested */
1668 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1669 return 0;
1670 /*
1671 * IPv4/TCP LSO
1672 */
1673 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1674 nix_lso_tcp(req, true);
1675 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1676 if (rc)
1677 return rc;
1678
1679 base = rsp->lso_format_idx;
1680 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1681 return -EFAULT;
1682 dev->lso_base_idx = base;
1683 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1684
1685
1686 /*
1687 * IPv6/TCP LSO
1688 */
1689 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1690 nix_lso_tcp(req, false);
1691 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1692 if (rc)
1693 return rc;
1694
1695 if (rsp->lso_format_idx != base + 1)
1696 return -EFAULT;
1697 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1698
1699 /*
1700 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1701 */
1702 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1703 nix_lso_udp_tun_tcp(req, true, true);
1704 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1705 if (rc)
1706 return rc;
1707
1708 if (rsp->lso_format_idx != base + 2)
1709 return -EFAULT;
1710 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1711
1712 /*
1713 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1714 */
1715 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1716 nix_lso_udp_tun_tcp(req, true, false);
1717 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1718 if (rc)
1719 return rc;
1720
1721 if (rsp->lso_format_idx != base + 3)
1722 return -EFAULT;
1723 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1724
1725 /*
1726 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1727 */
1728 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1729 nix_lso_udp_tun_tcp(req, false, true);
1730 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1731 if (rc)
1732 return rc;
1733
1734 if (rsp->lso_format_idx != base + 4)
1735 return -EFAULT;
1736 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1737
1738 /*
1739 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1740 */
1741 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1742 nix_lso_udp_tun_tcp(req, false, false);
1743 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1744 if (rc)
1745 return rc;
1746 if (rsp->lso_format_idx != base + 5)
1747 return -EFAULT;
1748 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1749
1750 /*
1751 * IPv4/TUN HDR/IPv4/TCP LSO
1752 */
1753 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1754 nix_lso_tun_tcp(req, true, true);
1755 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1756 if (rc)
1757 return rc;
1758
1759 if (rsp->lso_format_idx != base + 6)
1760 return -EFAULT;
1761 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1762
1763 /*
1764 * IPv4/TUN HDR/IPv6/TCP LSO
1765 */
1766 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1767 nix_lso_tun_tcp(req, true, false);
1768 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1769 if (rc)
1770 return rc;
1771
1772 if (rsp->lso_format_idx != base + 7)
1773 return -EFAULT;
1774 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1775
1776 /*
1777 * IPv6/TUN HDR/IPv4/TCP LSO
1778 */
1779 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1780 nix_lso_tun_tcp(req, false, true);
1781 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1782 if (rc)
1783 return rc;
1784
1785 if (rsp->lso_format_idx != base + 8)
1786 return -EFAULT;
1787 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1788
1789 /*
1790 * IPv6/TUN HDR/IPv6/TCP LSO
1791 */
1792 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1793 nix_lso_tun_tcp(req, false, false);
1794 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1795 if (rc)
1796 return rc;
1797 if (rsp->lso_format_idx != base + 9)
1798 return -EFAULT;
1799 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1800 return 0;
1801 }
1802
1803 static int
otx2_nix_configure(struct rte_eth_dev * eth_dev)1804 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1805 {
1806 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1807 struct rte_eth_dev_data *data = eth_dev->data;
1808 struct rte_eth_conf *conf = &data->dev_conf;
1809 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1810 struct rte_eth_txmode *txmode = &conf->txmode;
1811 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1812 struct rte_ether_addr *ea;
1813 uint8_t nb_rxq, nb_txq;
1814 int rc;
1815
1816 rc = -EINVAL;
1817
1818 /* Sanity checks */
1819 if (rte_eal_has_hugepages() == 0) {
1820 otx2_err("Huge page is not configured");
1821 goto fail_configure;
1822 }
1823
1824 if (conf->dcb_capability_en == 1) {
1825 otx2_err("dcb enable is not supported");
1826 goto fail_configure;
1827 }
1828
1829 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1830 otx2_err("Flow director is not supported");
1831 goto fail_configure;
1832 }
1833
1834 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1835 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1836 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1837 goto fail_configure;
1838 }
1839
1840 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1841 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1842 goto fail_configure;
1843 }
1844
1845 if (otx2_dev_is_Ax(dev) &&
1846 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1847 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1848 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1849 otx2_err("Outer IP and SCTP checksum unsupported");
1850 goto fail_configure;
1851 }
1852
1853 /* Free the resources allocated from the previous configure */
1854 if (dev->configured == 1) {
1855 otx2_eth_sec_fini(eth_dev);
1856 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1857 otx2_nix_vlan_fini(eth_dev);
1858 otx2_nix_mc_addr_list_uninstall(eth_dev);
1859 otx2_flow_free_all_resources(dev);
1860 oxt2_nix_unregister_queue_irqs(eth_dev);
1861 if (eth_dev->data->dev_conf.intr_conf.rxq)
1862 oxt2_nix_unregister_cq_irqs(eth_dev);
1863 nix_set_nop_rxtx_function(eth_dev);
1864 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1865 if (rc)
1866 goto fail_configure;
1867 otx2_nix_tm_fini(eth_dev);
1868 nix_lf_free(dev);
1869 }
1870
1871 dev->rx_offloads = rxmode->offloads;
1872 dev->tx_offloads = txmode->offloads;
1873 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1874 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1875 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1876
1877 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1878 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1879
1880 /* Alloc a nix lf */
1881 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1882 if (rc) {
1883 otx2_err("Failed to init nix_lf rc=%d", rc);
1884 goto fail_offloads;
1885 }
1886
1887 otx2_nix_err_intr_enb_dis(eth_dev, true);
1888 otx2_nix_ras_intr_enb_dis(eth_dev, true);
1889
1890 if (dev->ptp_en &&
1891 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
1892 otx2_err("Both PTP and switch header enabled");
1893 goto free_nix_lf;
1894 }
1895
1896 rc = nix_lf_switch_header_type_enable(dev, true);
1897 if (rc) {
1898 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1899 goto free_nix_lf;
1900 }
1901
1902 rc = nix_setup_lso_formats(dev);
1903 if (rc) {
1904 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1905 goto free_nix_lf;
1906 }
1907
1908 /* Configure RSS */
1909 rc = otx2_nix_rss_config(eth_dev);
1910 if (rc) {
1911 otx2_err("Failed to configure rss rc=%d", rc);
1912 goto free_nix_lf;
1913 }
1914
1915 /* Init the default TM scheduler hierarchy */
1916 rc = otx2_nix_tm_init_default(eth_dev);
1917 if (rc) {
1918 otx2_err("Failed to init traffic manager rc=%d", rc);
1919 goto free_nix_lf;
1920 }
1921
1922 rc = otx2_nix_vlan_offload_init(eth_dev);
1923 if (rc) {
1924 otx2_err("Failed to init vlan offload rc=%d", rc);
1925 goto tm_fini;
1926 }
1927
1928 /* Register queue IRQs */
1929 rc = oxt2_nix_register_queue_irqs(eth_dev);
1930 if (rc) {
1931 otx2_err("Failed to register queue interrupts rc=%d", rc);
1932 goto vlan_fini;
1933 }
1934
1935 /* Register cq IRQs */
1936 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1937 if (eth_dev->data->nb_rx_queues > dev->cints) {
1938 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1939 dev->cints);
1940 goto q_irq_fini;
1941 }
1942 /* Rx interrupt feature cannot work with vector mode because,
1943 * vector mode doesn't process packets unless min 4 pkts are
1944 * received, while cq interrupts are generated even for 1 pkt
1945 * in the CQ.
1946 */
1947 dev->scalar_ena = true;
1948
1949 rc = oxt2_nix_register_cq_irqs(eth_dev);
1950 if (rc) {
1951 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1952 goto q_irq_fini;
1953 }
1954 }
1955
1956 /* Configure loop back mode */
1957 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1958 if (rc) {
1959 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1960 goto cq_fini;
1961 }
1962
1963 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1964 if (rc) {
1965 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1966 goto cq_fini;
1967 }
1968
1969 /* Enable security */
1970 rc = otx2_eth_sec_init(eth_dev);
1971 if (rc)
1972 goto cq_fini;
1973
1974 rc = otx2_nix_flow_ctrl_init(eth_dev);
1975 if (rc) {
1976 otx2_err("Failed to init flow ctrl mode %d", rc);
1977 goto cq_fini;
1978 }
1979
1980 rc = otx2_nix_mc_addr_list_install(eth_dev);
1981 if (rc < 0) {
1982 otx2_err("Failed to install mc address list rc=%d", rc);
1983 goto sec_fini;
1984 }
1985
1986 /*
1987 * Restore queue config when reconfigure followed by
1988 * reconfigure and no queue configure invoked from application case.
1989 */
1990 if (dev->configured == 1) {
1991 rc = nix_restore_queue_cfg(eth_dev);
1992 if (rc)
1993 goto uninstall_mc_list;
1994 }
1995
1996 /* Update the mac address */
1997 ea = eth_dev->data->mac_addrs;
1998 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1999 if (rte_is_zero_ether_addr(ea))
2000 rte_eth_random_addr((uint8_t *)ea);
2001
2002 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
2003
2004 /* Apply new link configurations if changed */
2005 rc = otx2_apply_link_speed(eth_dev);
2006 if (rc) {
2007 otx2_err("Failed to set link configuration");
2008 goto uninstall_mc_list;
2009 }
2010
2011 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
2012 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
2013 " rx_flags=0x%x tx_flags=0x%x",
2014 eth_dev->data->port_id, ea_fmt, nb_rxq,
2015 nb_txq, dev->rx_offloads, dev->tx_offloads,
2016 dev->rx_offload_flags, dev->tx_offload_flags);
2017
2018 /* All good */
2019 dev->configured = 1;
2020 dev->configured_nb_rx_qs = data->nb_rx_queues;
2021 dev->configured_nb_tx_qs = data->nb_tx_queues;
2022 return 0;
2023
2024 uninstall_mc_list:
2025 otx2_nix_mc_addr_list_uninstall(eth_dev);
2026 sec_fini:
2027 otx2_eth_sec_fini(eth_dev);
2028 cq_fini:
2029 oxt2_nix_unregister_cq_irqs(eth_dev);
2030 q_irq_fini:
2031 oxt2_nix_unregister_queue_irqs(eth_dev);
2032 vlan_fini:
2033 otx2_nix_vlan_fini(eth_dev);
2034 tm_fini:
2035 otx2_nix_tm_fini(eth_dev);
2036 free_nix_lf:
2037 nix_lf_free(dev);
2038 fail_offloads:
2039 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
2040 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
2041 fail_configure:
2042 dev->configured = 0;
2043 return rc;
2044 }
2045
2046 int
otx2_nix_tx_queue_start(struct rte_eth_dev * eth_dev,uint16_t qidx)2047 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
2048 {
2049 struct rte_eth_dev_data *data = eth_dev->data;
2050 struct otx2_eth_txq *txq;
2051 int rc = -EINVAL;
2052
2053 txq = eth_dev->data->tx_queues[qidx];
2054
2055 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
2056 return 0;
2057
2058 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
2059 if (rc) {
2060 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
2061 qidx, rc);
2062 goto done;
2063 }
2064
2065 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
2066
2067 done:
2068 return rc;
2069 }
2070
2071 int
otx2_nix_tx_queue_stop(struct rte_eth_dev * eth_dev,uint16_t qidx)2072 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
2073 {
2074 struct rte_eth_dev_data *data = eth_dev->data;
2075 struct otx2_eth_txq *txq;
2076 int rc;
2077
2078 txq = eth_dev->data->tx_queues[qidx];
2079
2080 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
2081 return 0;
2082
2083 txq->fc_cache_pkts = 0;
2084
2085 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
2086 if (rc) {
2087 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
2088 qidx, rc);
2089 goto done;
2090 }
2091
2092 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
2093
2094 done:
2095 return rc;
2096 }
2097
2098 static int
otx2_nix_rx_queue_start(struct rte_eth_dev * eth_dev,uint16_t qidx)2099 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
2100 {
2101 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
2102 struct rte_eth_dev_data *data = eth_dev->data;
2103 int rc;
2104
2105 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
2106 return 0;
2107
2108 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
2109 if (rc) {
2110 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
2111 goto done;
2112 }
2113
2114 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
2115
2116 done:
2117 return rc;
2118 }
2119
2120 static int
otx2_nix_rx_queue_stop(struct rte_eth_dev * eth_dev,uint16_t qidx)2121 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
2122 {
2123 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
2124 struct rte_eth_dev_data *data = eth_dev->data;
2125 int rc;
2126
2127 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
2128 return 0;
2129
2130 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
2131 if (rc) {
2132 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
2133 goto done;
2134 }
2135
2136 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
2137
2138 done:
2139 return rc;
2140 }
2141
2142 static int
otx2_nix_dev_stop(struct rte_eth_dev * eth_dev)2143 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
2144 {
2145 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2146 struct rte_mbuf *rx_pkts[32];
2147 struct otx2_eth_rxq *rxq;
2148 int count, i, j, rc;
2149
2150 nix_lf_switch_header_type_enable(dev, false);
2151 nix_cgx_stop_link_event(dev);
2152 npc_rx_disable(dev);
2153
2154 /* Stop rx queues and free up pkts pending */
2155 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2156 rc = otx2_nix_rx_queue_stop(eth_dev, i);
2157 if (rc)
2158 continue;
2159
2160 rxq = eth_dev->data->rx_queues[i];
2161 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
2162 while (count) {
2163 for (j = 0; j < count; j++)
2164 rte_pktmbuf_free(rx_pkts[j]);
2165 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
2166 }
2167 }
2168
2169 /* Stop tx queues */
2170 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
2171 otx2_nix_tx_queue_stop(eth_dev, i);
2172
2173 return 0;
2174 }
2175
2176 static int
otx2_nix_dev_start(struct rte_eth_dev * eth_dev)2177 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
2178 {
2179 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2180 int rc, i;
2181
2182 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
2183 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
2184 * call below.
2185 */
2186 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
2187 rc = otx2_nix_recalc_mtu(eth_dev);
2188 if (rc)
2189 return rc;
2190 }
2191
2192 /* Start rx queues */
2193 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2194 rc = otx2_nix_rx_queue_start(eth_dev, i);
2195 if (rc)
2196 return rc;
2197 }
2198
2199 /* Start tx queues */
2200 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2201 rc = otx2_nix_tx_queue_start(eth_dev, i);
2202 if (rc)
2203 return rc;
2204 }
2205
2206 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
2207 if (rc) {
2208 otx2_err("Failed to update flow ctrl mode %d", rc);
2209 return rc;
2210 }
2211
2212 /* Enable PTP if it was requested by the app or if it is already
2213 * enabled in PF owning this VF
2214 */
2215 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
2216 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
2217 otx2_ethdev_is_ptp_en(dev))
2218 otx2_nix_timesync_enable(eth_dev);
2219 else
2220 otx2_nix_timesync_disable(eth_dev);
2221
2222 /* Update VF about data off shifted by 8 bytes if PTP already
2223 * enabled in PF owning this VF
2224 */
2225 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
2226 otx2_nix_ptp_enable_vf(eth_dev);
2227
2228 if (dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F) {
2229 rc = rte_mbuf_dyn_rx_timestamp_register(
2230 &dev->tstamp.tstamp_dynfield_offset,
2231 &dev->tstamp.rx_tstamp_dynflag);
2232 if (rc != 0) {
2233 otx2_err("Failed to register Rx timestamp field/flag");
2234 return -rte_errno;
2235 }
2236 }
2237
2238 rc = npc_rx_enable(dev);
2239 if (rc) {
2240 otx2_err("Failed to enable NPC rx %d", rc);
2241 return rc;
2242 }
2243
2244 otx2_nix_toggle_flag_link_cfg(dev, true);
2245
2246 rc = nix_cgx_start_link_event(dev);
2247 if (rc) {
2248 otx2_err("Failed to start cgx link event %d", rc);
2249 goto rx_disable;
2250 }
2251
2252 otx2_nix_toggle_flag_link_cfg(dev, false);
2253 otx2_eth_set_tx_function(eth_dev);
2254 otx2_eth_set_rx_function(eth_dev);
2255
2256 return 0;
2257
2258 rx_disable:
2259 npc_rx_disable(dev);
2260 otx2_nix_toggle_flag_link_cfg(dev, false);
2261 return rc;
2262 }
2263
2264 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
2265 static int otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
2266
2267 /* Initialize and register driver with DPDK Application */
2268 static const struct eth_dev_ops otx2_eth_dev_ops = {
2269 .dev_infos_get = otx2_nix_info_get,
2270 .dev_configure = otx2_nix_configure,
2271 .link_update = otx2_nix_link_update,
2272 .tx_queue_setup = otx2_nix_tx_queue_setup,
2273 .tx_queue_release = otx2_nix_tx_queue_release,
2274 .tm_ops_get = otx2_nix_tm_ops_get,
2275 .rx_queue_setup = otx2_nix_rx_queue_setup,
2276 .rx_queue_release = otx2_nix_rx_queue_release,
2277 .dev_start = otx2_nix_dev_start,
2278 .dev_stop = otx2_nix_dev_stop,
2279 .dev_close = otx2_nix_dev_close,
2280 .tx_queue_start = otx2_nix_tx_queue_start,
2281 .tx_queue_stop = otx2_nix_tx_queue_stop,
2282 .rx_queue_start = otx2_nix_rx_queue_start,
2283 .rx_queue_stop = otx2_nix_rx_queue_stop,
2284 .dev_set_link_up = otx2_nix_dev_set_link_up,
2285 .dev_set_link_down = otx2_nix_dev_set_link_down,
2286 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2287 .dev_ptypes_set = otx2_nix_ptypes_set,
2288 .dev_reset = otx2_nix_dev_reset,
2289 .stats_get = otx2_nix_dev_stats_get,
2290 .stats_reset = otx2_nix_dev_stats_reset,
2291 .get_reg = otx2_nix_dev_get_reg,
2292 .mtu_set = otx2_nix_mtu_set,
2293 .mac_addr_add = otx2_nix_mac_addr_add,
2294 .mac_addr_remove = otx2_nix_mac_addr_del,
2295 .mac_addr_set = otx2_nix_mac_addr_set,
2296 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2297 .promiscuous_enable = otx2_nix_promisc_enable,
2298 .promiscuous_disable = otx2_nix_promisc_disable,
2299 .allmulticast_enable = otx2_nix_allmulticast_enable,
2300 .allmulticast_disable = otx2_nix_allmulticast_disable,
2301 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2302 .reta_update = otx2_nix_dev_reta_update,
2303 .reta_query = otx2_nix_dev_reta_query,
2304 .rss_hash_update = otx2_nix_rss_hash_update,
2305 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2306 .xstats_get = otx2_nix_xstats_get,
2307 .xstats_get_names = otx2_nix_xstats_get_names,
2308 .xstats_reset = otx2_nix_xstats_reset,
2309 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2310 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2311 .rxq_info_get = otx2_nix_rxq_info_get,
2312 .txq_info_get = otx2_nix_txq_info_get,
2313 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2314 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2315 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2316 .set_queue_rate_limit = otx2_nix_tm_set_queue_rate_limit,
2317 .pool_ops_supported = otx2_nix_pool_ops_supported,
2318 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2319 .get_module_info = otx2_nix_get_module_info,
2320 .get_module_eeprom = otx2_nix_get_module_eeprom,
2321 .fw_version_get = otx2_nix_fw_version_get,
2322 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2323 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2324 .timesync_enable = otx2_nix_timesync_enable,
2325 .timesync_disable = otx2_nix_timesync_disable,
2326 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2327 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2328 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2329 .timesync_read_time = otx2_nix_timesync_read_time,
2330 .timesync_write_time = otx2_nix_timesync_write_time,
2331 .vlan_offload_set = otx2_nix_vlan_offload_set,
2332 .vlan_filter_set = otx2_nix_vlan_filter_set,
2333 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2334 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2335 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2336 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2337 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2338 .read_clock = otx2_nix_read_clock,
2339 };
2340
2341 static inline int
nix_lf_attach(struct otx2_eth_dev * dev)2342 nix_lf_attach(struct otx2_eth_dev *dev)
2343 {
2344 struct otx2_mbox *mbox = dev->mbox;
2345 struct rsrc_attach_req *req;
2346
2347 /* Attach NIX(lf) */
2348 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2349 req->modify = true;
2350 req->nixlf = true;
2351
2352 return otx2_mbox_process(mbox);
2353 }
2354
2355 static inline int
nix_lf_get_msix_offset(struct otx2_eth_dev * dev)2356 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2357 {
2358 struct otx2_mbox *mbox = dev->mbox;
2359 struct msix_offset_rsp *msix_rsp;
2360 int rc;
2361
2362 /* Get NPA and NIX MSIX vector offsets */
2363 otx2_mbox_alloc_msg_msix_offset(mbox);
2364
2365 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2366
2367 dev->nix_msixoff = msix_rsp->nix_msixoff;
2368
2369 return rc;
2370 }
2371
2372 static inline int
otx2_eth_dev_lf_detach(struct otx2_mbox * mbox)2373 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2374 {
2375 struct rsrc_detach_req *req;
2376
2377 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2378
2379 /* Detach all except npa lf */
2380 req->partial = true;
2381 req->nixlf = true;
2382 req->sso = true;
2383 req->ssow = true;
2384 req->timlfs = true;
2385 req->cptlfs = true;
2386
2387 return otx2_mbox_process(mbox);
2388 }
2389
2390 static bool
otx2_eth_dev_is_sdp(struct rte_pci_device * pci_dev)2391 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2392 {
2393 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2394 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2395 return true;
2396 return false;
2397 }
2398
2399 static inline uint64_t
nix_get_blkaddr(struct otx2_eth_dev * dev)2400 nix_get_blkaddr(struct otx2_eth_dev *dev)
2401 {
2402 uint64_t reg;
2403
2404 /* Reading the discovery register to know which NIX is the LF
2405 * attached to.
2406 */
2407 reg = otx2_read64(dev->bar2 +
2408 RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
2409
2410 return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
2411 }
2412
2413 static int
otx2_eth_dev_init(struct rte_eth_dev * eth_dev)2414 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2415 {
2416 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2417 struct rte_pci_device *pci_dev;
2418 int rc, max_entries;
2419
2420 eth_dev->dev_ops = &otx2_eth_dev_ops;
2421 eth_dev->rx_descriptor_done = otx2_nix_rx_descriptor_done;
2422 eth_dev->rx_queue_count = otx2_nix_rx_queue_count;
2423 eth_dev->rx_descriptor_status = otx2_nix_rx_descriptor_status;
2424 eth_dev->tx_descriptor_status = otx2_nix_tx_descriptor_status;
2425
2426 /* For secondary processes, the primary has done all the work */
2427 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2428 /* Setup callbacks for secondary process */
2429 otx2_eth_set_tx_function(eth_dev);
2430 otx2_eth_set_rx_function(eth_dev);
2431 return 0;
2432 }
2433
2434 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2435
2436 rte_eth_copy_pci_info(eth_dev, pci_dev);
2437 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2438
2439 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2440 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2441 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2442
2443 /* Parse devargs string */
2444 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2445 if (rc) {
2446 otx2_err("Failed to parse devargs rc=%d", rc);
2447 goto error;
2448 }
2449
2450 if (!dev->mbox_active) {
2451 /* Initialize the base otx2_dev object
2452 * only if already present
2453 */
2454 rc = otx2_dev_init(pci_dev, dev);
2455 if (rc) {
2456 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2457 goto error;
2458 }
2459 }
2460 if (otx2_eth_dev_is_sdp(pci_dev))
2461 dev->sdp_link = true;
2462 else
2463 dev->sdp_link = false;
2464 /* Device generic callbacks */
2465 dev->ops = &otx2_dev_ops;
2466 dev->eth_dev = eth_dev;
2467
2468 /* Grab the NPA LF if required */
2469 rc = otx2_npa_lf_init(pci_dev, dev);
2470 if (rc)
2471 goto otx2_dev_uninit;
2472
2473 dev->configured = 0;
2474 dev->drv_inited = true;
2475 dev->ptype_disable = 0;
2476 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2477
2478 /* Attach NIX LF */
2479 rc = nix_lf_attach(dev);
2480 if (rc)
2481 goto otx2_npa_uninit;
2482
2483 dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);
2484
2485 /* Get NIX MSIX offset */
2486 rc = nix_lf_get_msix_offset(dev);
2487 if (rc)
2488 goto otx2_npa_uninit;
2489
2490 /* Register LF irq handlers */
2491 rc = otx2_nix_register_irqs(eth_dev);
2492 if (rc)
2493 goto mbox_detach;
2494
2495 /* Get maximum number of supported MAC entries */
2496 max_entries = otx2_cgx_mac_max_entries_get(dev);
2497 if (max_entries < 0) {
2498 otx2_err("Failed to get max entries for mac addr");
2499 rc = -ENOTSUP;
2500 goto unregister_irq;
2501 }
2502
2503 /* For VFs, returned max_entries will be 0. But to keep default MAC
2504 * address, one entry must be allocated. So setting up to 1.
2505 */
2506 if (max_entries == 0)
2507 max_entries = 1;
2508
2509 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2510 RTE_ETHER_ADDR_LEN, 0);
2511 if (eth_dev->data->mac_addrs == NULL) {
2512 otx2_err("Failed to allocate memory for mac addr");
2513 rc = -ENOMEM;
2514 goto unregister_irq;
2515 }
2516
2517 dev->max_mac_entries = max_entries;
2518
2519 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2520 if (rc)
2521 goto free_mac_addrs;
2522
2523 /* Update the mac address */
2524 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2525
2526 /* Also sync same MAC address to CGX table */
2527 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2528
2529 /* Initialize the tm data structures */
2530 otx2_nix_tm_conf_init(eth_dev);
2531
2532 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2533 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2534
2535 if (otx2_dev_is_96xx_A0(dev) ||
2536 otx2_dev_is_95xx_Ax(dev)) {
2537 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2538 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2539 }
2540
2541 /* Create security ctx */
2542 rc = otx2_eth_sec_ctx_create(eth_dev);
2543 if (rc)
2544 goto free_mac_addrs;
2545 dev->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2546 dev->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
2547
2548 /* Initialize rte-flow */
2549 rc = otx2_flow_init(dev);
2550 if (rc)
2551 goto sec_ctx_destroy;
2552
2553 otx2_nix_mc_filter_init(dev);
2554
2555 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2556 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2557 eth_dev->data->port_id, dev->pf, dev->vf,
2558 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2559 dev->rx_offload_capa, dev->tx_offload_capa);
2560 return 0;
2561
2562 sec_ctx_destroy:
2563 otx2_eth_sec_ctx_destroy(eth_dev);
2564 free_mac_addrs:
2565 rte_free(eth_dev->data->mac_addrs);
2566 unregister_irq:
2567 otx2_nix_unregister_irqs(eth_dev);
2568 mbox_detach:
2569 otx2_eth_dev_lf_detach(dev->mbox);
2570 otx2_npa_uninit:
2571 otx2_npa_lf_fini();
2572 otx2_dev_uninit:
2573 otx2_dev_fini(pci_dev, dev);
2574 error:
2575 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2576 return rc;
2577 }
2578
2579 static int
otx2_eth_dev_uninit(struct rte_eth_dev * eth_dev,bool mbox_close)2580 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2581 {
2582 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2583 struct rte_pci_device *pci_dev;
2584 int rc, i;
2585
2586 /* Nothing to be done for secondary processes */
2587 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2588 return 0;
2589
2590 /* Clear the flag since we are closing down */
2591 dev->configured = 0;
2592
2593 /* Disable nix bpid config */
2594 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2595
2596 npc_rx_disable(dev);
2597
2598 /* Disable vlan offloads */
2599 otx2_nix_vlan_fini(eth_dev);
2600
2601 /* Disable other rte_flow entries */
2602 otx2_flow_fini(dev);
2603
2604 /* Free multicast filter list */
2605 otx2_nix_mc_filter_fini(dev);
2606
2607 /* Disable PTP if already enabled */
2608 if (otx2_ethdev_is_ptp_en(dev))
2609 otx2_nix_timesync_disable(eth_dev);
2610
2611 nix_cgx_stop_link_event(dev);
2612
2613 /* Free up SQs */
2614 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2615 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2616 eth_dev->data->tx_queues[i] = NULL;
2617 }
2618 eth_dev->data->nb_tx_queues = 0;
2619
2620 /* Free up RQ's and CQ's */
2621 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2622 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2623 eth_dev->data->rx_queues[i] = NULL;
2624 }
2625 eth_dev->data->nb_rx_queues = 0;
2626
2627 /* Free tm resources */
2628 rc = otx2_nix_tm_fini(eth_dev);
2629 if (rc)
2630 otx2_err("Failed to cleanup tm, rc=%d", rc);
2631
2632 /* Unregister queue irqs */
2633 oxt2_nix_unregister_queue_irqs(eth_dev);
2634
2635 /* Unregister cq irqs */
2636 if (eth_dev->data->dev_conf.intr_conf.rxq)
2637 oxt2_nix_unregister_cq_irqs(eth_dev);
2638
2639 rc = nix_lf_free(dev);
2640 if (rc)
2641 otx2_err("Failed to free nix lf, rc=%d", rc);
2642
2643 rc = otx2_npa_lf_fini();
2644 if (rc)
2645 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2646
2647 /* Disable security */
2648 otx2_eth_sec_fini(eth_dev);
2649
2650 /* Destroy security ctx */
2651 otx2_eth_sec_ctx_destroy(eth_dev);
2652
2653 rte_free(eth_dev->data->mac_addrs);
2654 eth_dev->data->mac_addrs = NULL;
2655 dev->drv_inited = false;
2656
2657 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2658 otx2_nix_unregister_irqs(eth_dev);
2659
2660 rc = otx2_eth_dev_lf_detach(dev->mbox);
2661 if (rc)
2662 otx2_err("Failed to detach resources, rc=%d", rc);
2663
2664 /* Check if mbox close is needed */
2665 if (!mbox_close)
2666 return 0;
2667
2668 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2669 /* Will be freed later by PMD */
2670 eth_dev->data->dev_private = NULL;
2671 return 0;
2672 }
2673
2674 otx2_dev_fini(pci_dev, dev);
2675 return 0;
2676 }
2677
2678 static int
otx2_nix_dev_close(struct rte_eth_dev * eth_dev)2679 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2680 {
2681 otx2_eth_dev_uninit(eth_dev, true);
2682 return 0;
2683 }
2684
2685 static int
otx2_nix_dev_reset(struct rte_eth_dev * eth_dev)2686 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2687 {
2688 int rc;
2689
2690 rc = otx2_eth_dev_uninit(eth_dev, false);
2691 if (rc)
2692 return rc;
2693
2694 return otx2_eth_dev_init(eth_dev);
2695 }
2696
2697 static int
nix_remove(struct rte_pci_device * pci_dev)2698 nix_remove(struct rte_pci_device *pci_dev)
2699 {
2700 struct rte_eth_dev *eth_dev;
2701 struct otx2_idev_cfg *idev;
2702 struct otx2_dev *otx2_dev;
2703 int rc;
2704
2705 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2706 if (eth_dev) {
2707 /* Cleanup eth dev */
2708 rc = otx2_eth_dev_uninit(eth_dev, true);
2709 if (rc)
2710 return rc;
2711
2712 rte_eth_dev_release_port(eth_dev);
2713 }
2714
2715 /* Nothing to be done for secondary processes */
2716 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2717 return 0;
2718
2719 /* Check for common resources */
2720 idev = otx2_intra_dev_get_cfg();
2721 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2722 return 0;
2723
2724 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2725
2726 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2727 goto exit;
2728
2729 /* Safe to cleanup mbox as no more users */
2730 otx2_dev_fini(pci_dev, otx2_dev);
2731 rte_free(otx2_dev);
2732 return 0;
2733
2734 exit:
2735 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2736 return -EAGAIN;
2737 }
2738
2739 static int
nix_probe(struct rte_pci_driver * pci_drv,struct rte_pci_device * pci_dev)2740 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2741 {
2742 int rc;
2743
2744 RTE_SET_USED(pci_drv);
2745
2746 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2747 otx2_eth_dev_init);
2748
2749 /* On error on secondary, recheck if port exists in primary or
2750 * in mid of detach state.
2751 */
2752 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2753 if (!rte_eth_dev_allocated(pci_dev->device.name))
2754 return 0;
2755 return rc;
2756 }
2757
2758 static const struct rte_pci_id pci_nix_map[] = {
2759 {
2760 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2761 },
2762 {
2763 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2764 },
2765 {
2766 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2767 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2768 },
2769 {
2770 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2771 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2772 },
2773 {
2774 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2775 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2776 },
2777 {
2778 .vendor_id = 0,
2779 },
2780 };
2781
2782 static struct rte_pci_driver pci_nix = {
2783 .id_table = pci_nix_map,
2784 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2785 RTE_PCI_DRV_INTR_LSC,
2786 .probe = nix_probe,
2787 .remove = nix_remove,
2788 };
2789
2790 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2791 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2792 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");
2793