1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
4 */
5
6 #include "ngbe_type.h"
7 #include "ngbe_mbx.h"
8 #include "ngbe_phy.h"
9 #include "ngbe_eeprom.h"
10 #include "ngbe_mng.h"
11 #include "ngbe_hw.h"
12
13 /**
14 * ngbe_start_hw - Prepare hardware for Tx/Rx
15 * @hw: pointer to hardware structure
16 *
17 * Starts the hardware.
18 **/
ngbe_start_hw(struct ngbe_hw * hw)19 s32 ngbe_start_hw(struct ngbe_hw *hw)
20 {
21 s32 err;
22
23 /* Clear the VLAN filter table */
24 hw->mac.clear_vfta(hw);
25
26 /* Clear statistics registers */
27 hw->mac.clear_hw_cntrs(hw);
28
29 /* Setup flow control */
30 err = hw->mac.setup_fc(hw);
31 if (err != 0 && err != NGBE_NOT_IMPLEMENTED) {
32 DEBUGOUT("Flow control setup failed, returning %d", err);
33 return err;
34 }
35
36 /* Clear adapter stopped flag */
37 hw->adapter_stopped = false;
38
39 return 0;
40 }
41
42 /**
43 * ngbe_init_hw - Generic hardware initialization
44 * @hw: pointer to hardware structure
45 *
46 * Initialize the hardware by resetting the hardware, filling the bus info
47 * structure and media type, clears all on chip counters, initializes receive
48 * address registers, multicast table, VLAN filter table, calls routine to set
49 * up link and flow control settings, and leaves transmit and receive units
50 * disabled and uninitialized
51 **/
ngbe_init_hw(struct ngbe_hw * hw)52 s32 ngbe_init_hw(struct ngbe_hw *hw)
53 {
54 s32 status;
55
56 ngbe_save_eeprom_version(hw);
57
58 /* Reset the hardware */
59 status = hw->mac.reset_hw(hw);
60 if (status == 0) {
61 /* Start the HW */
62 status = hw->mac.start_hw(hw);
63 }
64
65 if (status != 0)
66 DEBUGOUT("Failed to initialize HW, STATUS = %d", status);
67
68 return status;
69 }
70
71 static void
ngbe_reset_misc_em(struct ngbe_hw * hw)72 ngbe_reset_misc_em(struct ngbe_hw *hw)
73 {
74 int i;
75
76 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF);
77 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32);
78
79 /* receive packets that size > 2048 */
80 wr32m(hw, NGBE_MACRXCFG,
81 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO);
82
83 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK,
84 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT));
85
86 /* clear counters on read */
87 wr32m(hw, NGBE_MACCNTCTL,
88 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC);
89
90 wr32m(hw, NGBE_RXFCCFG,
91 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC);
92 wr32m(hw, NGBE_TXFCCFG,
93 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC);
94
95 wr32m(hw, NGBE_MACRXFLT,
96 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC);
97
98 wr32m(hw, NGBE_RSTSTAT,
99 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30));
100
101 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
102 wr32(hw, NGBE_MNGFLEXSEL, 0);
103 for (i = 0; i < 16; i++) {
104 wr32(hw, NGBE_MNGFLEXDWL(i), 0);
105 wr32(hw, NGBE_MNGFLEXDWH(i), 0);
106 wr32(hw, NGBE_MNGFLEXMSK(i), 0);
107 }
108 wr32(hw, NGBE_LANFLEXSEL, 0);
109 for (i = 0; i < 16; i++) {
110 wr32(hw, NGBE_LANFLEXDWL(i), 0);
111 wr32(hw, NGBE_LANFLEXDWH(i), 0);
112 wr32(hw, NGBE_LANFLEXMSK(i), 0);
113 }
114
115 /* set pause frame dst mac addr */
116 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001);
117 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180);
118
119 wr32(hw, NGBE_MDIOMODE, 0xF);
120
121 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX);
122
123 if (hw->gpio_ctl) {
124 /* gpio0 is used to power on/off control*/
125 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1));
126 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0);
127 }
128
129 hw->mac.init_thermal_sensor_thresh(hw);
130
131 /* enable mac transmitter */
132 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE);
133
134 /* sellect GMII */
135 wr32m(hw, NGBE_MACTXCFG,
136 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G);
137
138 for (i = 0; i < 4; i++)
139 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0);
140 }
141
142 /**
143 * ngbe_reset_hw_em - Perform hardware reset
144 * @hw: pointer to hardware structure
145 *
146 * Resets the hardware by resetting the transmit and receive units, masks
147 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
148 * reset.
149 **/
ngbe_reset_hw_em(struct ngbe_hw * hw)150 s32 ngbe_reset_hw_em(struct ngbe_hw *hw)
151 {
152 s32 status;
153
154 /* Call adapter stop to disable tx/rx and clear interrupts */
155 status = hw->mac.stop_hw(hw);
156 if (status != 0)
157 return status;
158
159 /* Identify PHY and related function pointers */
160 status = ngbe_init_phy(hw);
161 if (status)
162 return status;
163
164 /* Reset PHY */
165 if (!hw->phy.reset_disable)
166 hw->phy.reset_hw(hw);
167
168 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));
169 ngbe_flush(hw);
170 msec_delay(50);
171
172 ngbe_reset_misc_em(hw);
173 hw->mac.clear_hw_cntrs(hw);
174
175 msec_delay(50);
176
177 /* Store the permanent mac address */
178 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
179
180 /*
181 * Store MAC address from RAR0, clear receive address registers, and
182 * clear the multicast table.
183 */
184 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES;
185 hw->mac.init_rx_addrs(hw);
186
187 return status;
188 }
189
190 /**
191 * ngbe_clear_hw_cntrs - Generic clear hardware counters
192 * @hw: pointer to hardware structure
193 *
194 * Clears all hardware statistics counters by reading them from the hardware
195 * Statistics counters are clear on read.
196 **/
ngbe_clear_hw_cntrs(struct ngbe_hw * hw)197 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw)
198 {
199 u16 i = 0;
200
201 /* QP Stats */
202 /* don't write clear queue stats */
203 for (i = 0; i < NGBE_MAX_QP; i++) {
204 hw->qp_last[i].rx_qp_packets = 0;
205 hw->qp_last[i].tx_qp_packets = 0;
206 hw->qp_last[i].rx_qp_bytes = 0;
207 hw->qp_last[i].tx_qp_bytes = 0;
208 hw->qp_last[i].rx_qp_mc_packets = 0;
209 hw->qp_last[i].tx_qp_mc_packets = 0;
210 hw->qp_last[i].rx_qp_bc_packets = 0;
211 hw->qp_last[i].tx_qp_bc_packets = 0;
212 }
213
214 /* PB Stats */
215 rd32(hw, NGBE_PBRXLNKXON);
216 rd32(hw, NGBE_PBRXLNKXOFF);
217 rd32(hw, NGBE_PBTXLNKXON);
218 rd32(hw, NGBE_PBTXLNKXOFF);
219
220 /* DMA Stats */
221 rd32(hw, NGBE_DMARXPKT);
222 rd32(hw, NGBE_DMATXPKT);
223
224 rd64(hw, NGBE_DMARXOCTL);
225 rd64(hw, NGBE_DMATXOCTL);
226
227 /* MAC Stats */
228 rd64(hw, NGBE_MACRXERRCRCL);
229 rd64(hw, NGBE_MACRXMPKTL);
230 rd64(hw, NGBE_MACTXMPKTL);
231
232 rd64(hw, NGBE_MACRXPKTL);
233 rd64(hw, NGBE_MACTXPKTL);
234 rd64(hw, NGBE_MACRXGBOCTL);
235
236 rd64(hw, NGBE_MACRXOCTL);
237 rd32(hw, NGBE_MACTXOCTL);
238
239 rd64(hw, NGBE_MACRX1TO64L);
240 rd64(hw, NGBE_MACRX65TO127L);
241 rd64(hw, NGBE_MACRX128TO255L);
242 rd64(hw, NGBE_MACRX256TO511L);
243 rd64(hw, NGBE_MACRX512TO1023L);
244 rd64(hw, NGBE_MACRX1024TOMAXL);
245 rd64(hw, NGBE_MACTX1TO64L);
246 rd64(hw, NGBE_MACTX65TO127L);
247 rd64(hw, NGBE_MACTX128TO255L);
248 rd64(hw, NGBE_MACTX256TO511L);
249 rd64(hw, NGBE_MACTX512TO1023L);
250 rd64(hw, NGBE_MACTX1024TOMAXL);
251
252 rd64(hw, NGBE_MACRXERRLENL);
253 rd32(hw, NGBE_MACRXOVERSIZE);
254 rd32(hw, NGBE_MACRXJABBER);
255
256 /* MACsec Stats */
257 rd32(hw, NGBE_LSECTX_UTPKT);
258 rd32(hw, NGBE_LSECTX_ENCPKT);
259 rd32(hw, NGBE_LSECTX_PROTPKT);
260 rd32(hw, NGBE_LSECTX_ENCOCT);
261 rd32(hw, NGBE_LSECTX_PROTOCT);
262 rd32(hw, NGBE_LSECRX_UTPKT);
263 rd32(hw, NGBE_LSECRX_BTPKT);
264 rd32(hw, NGBE_LSECRX_NOSCIPKT);
265 rd32(hw, NGBE_LSECRX_UNSCIPKT);
266 rd32(hw, NGBE_LSECRX_DECOCT);
267 rd32(hw, NGBE_LSECRX_VLDOCT);
268 rd32(hw, NGBE_LSECRX_UNCHKPKT);
269 rd32(hw, NGBE_LSECRX_DLYPKT);
270 rd32(hw, NGBE_LSECRX_LATEPKT);
271 for (i = 0; i < 2; i++) {
272 rd32(hw, NGBE_LSECRX_OKPKT(i));
273 rd32(hw, NGBE_LSECRX_INVPKT(i));
274 rd32(hw, NGBE_LSECRX_BADPKT(i));
275 }
276 for (i = 0; i < 4; i++) {
277 rd32(hw, NGBE_LSECRX_INVSAPKT(i));
278 rd32(hw, NGBE_LSECRX_BADSAPKT(i));
279 }
280
281 return 0;
282 }
283
284 /**
285 * ngbe_get_mac_addr - Generic get MAC address
286 * @hw: pointer to hardware structure
287 * @mac_addr: Adapter MAC address
288 *
289 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
290 * A reset of the adapter must be performed prior to calling this function
291 * in order for the MAC address to have been loaded from the EEPROM into RAR0
292 **/
ngbe_get_mac_addr(struct ngbe_hw * hw,u8 * mac_addr)293 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr)
294 {
295 u32 rar_high;
296 u32 rar_low;
297 u16 i;
298
299 wr32(hw, NGBE_ETHADDRIDX, 0);
300 rar_high = rd32(hw, NGBE_ETHADDRH);
301 rar_low = rd32(hw, NGBE_ETHADDRL);
302
303 for (i = 0; i < 2; i++)
304 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
305
306 for (i = 0; i < 4; i++)
307 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
308
309 return 0;
310 }
311
312 /**
313 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
314 * @hw: pointer to the HW structure
315 *
316 * Determines the LAN function id by reading memory-mapped registers and swaps
317 * the port value if requested, and set MAC instance for devices.
318 **/
ngbe_set_lan_id_multi_port(struct ngbe_hw * hw)319 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw)
320 {
321 struct ngbe_bus_info *bus = &hw->bus;
322 u32 reg = 0;
323
324 reg = rd32(hw, NGBE_PORTSTAT);
325 bus->lan_id = NGBE_PORTSTAT_ID(reg);
326 bus->func = bus->lan_id;
327 }
328
329 /**
330 * ngbe_stop_hw - Generic stop Tx/Rx units
331 * @hw: pointer to hardware structure
332 *
333 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts,
334 * disables transmit and receive units. The adapter_stopped flag is used by
335 * the shared code and drivers to determine if the adapter is in a stopped
336 * state and should not touch the hardware.
337 **/
ngbe_stop_hw(struct ngbe_hw * hw)338 s32 ngbe_stop_hw(struct ngbe_hw *hw)
339 {
340 u16 i;
341 s32 status = 0;
342
343 /*
344 * Set the adapter_stopped flag so other driver functions stop touching
345 * the hardware
346 */
347 hw->adapter_stopped = true;
348
349 /* Disable the receive unit */
350 ngbe_disable_rx(hw);
351
352 /* Clear interrupt mask to stop interrupts from being generated */
353 wr32(hw, NGBE_IENMISC, 0);
354 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK);
355
356 /* Clear any pending interrupts, flush previous writes */
357 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK);
358 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK);
359
360 wr32(hw, NGBE_BMECTL, 0x3);
361
362 /* Disable the receive unit by stopping each queue */
363 for (i = 0; i < hw->mac.max_rx_queues; i++)
364 wr32(hw, NGBE_RXCFG(i), 0);
365
366 /* flush all queues disables */
367 ngbe_flush(hw);
368 msec_delay(2);
369
370 /*
371 * Prevent the PCI-E bus from hanging by disabling PCI-E master
372 * access and verify no pending requests
373 */
374 status = ngbe_set_pcie_master(hw, false);
375 if (status)
376 return status;
377
378 /* Disable the transmit unit. Each queue must be disabled. */
379 for (i = 0; i < hw->mac.max_tx_queues; i++)
380 wr32(hw, NGBE_TXCFG(i), 0);
381
382 /* flush all queues disables */
383 ngbe_flush(hw);
384 msec_delay(2);
385
386 return 0;
387 }
388
389 /**
390 * ngbe_led_on - Turns on the software controllable LEDs.
391 * @hw: pointer to hardware structure
392 * @index: led number to turn on
393 **/
ngbe_led_on(struct ngbe_hw * hw,u32 index)394 s32 ngbe_led_on(struct ngbe_hw *hw, u32 index)
395 {
396 u32 led_reg = rd32(hw, NGBE_LEDCTL);
397
398 if (index > 3)
399 return NGBE_ERR_PARAM;
400
401 /* To turn on the LED, set mode to ON. */
402 led_reg |= NGBE_LEDCTL_100M;
403 wr32(hw, NGBE_LEDCTL, led_reg);
404 ngbe_flush(hw);
405
406 return 0;
407 }
408
409 /**
410 * ngbe_led_off - Turns off the software controllable LEDs.
411 * @hw: pointer to hardware structure
412 * @index: led number to turn off
413 **/
ngbe_led_off(struct ngbe_hw * hw,u32 index)414 s32 ngbe_led_off(struct ngbe_hw *hw, u32 index)
415 {
416 u32 led_reg = rd32(hw, NGBE_LEDCTL);
417
418 if (index > 3)
419 return NGBE_ERR_PARAM;
420
421 /* To turn off the LED, set mode to OFF. */
422 led_reg &= ~NGBE_LEDCTL_100M;
423 wr32(hw, NGBE_LEDCTL, led_reg);
424 ngbe_flush(hw);
425
426 return 0;
427 }
428
429 /**
430 * ngbe_validate_mac_addr - Validate MAC address
431 * @mac_addr: pointer to MAC address.
432 *
433 * Tests a MAC address to ensure it is a valid Individual Address.
434 **/
ngbe_validate_mac_addr(u8 * mac_addr)435 s32 ngbe_validate_mac_addr(u8 *mac_addr)
436 {
437 s32 status = 0;
438
439 /* Make sure it is not a multicast address */
440 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) {
441 status = NGBE_ERR_INVALID_MAC_ADDR;
442 /* Not a broadcast address */
443 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) {
444 status = NGBE_ERR_INVALID_MAC_ADDR;
445 /* Reject the zero address */
446 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
447 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
448 status = NGBE_ERR_INVALID_MAC_ADDR;
449 }
450 return status;
451 }
452
453 /**
454 * ngbe_set_rar - Set Rx address register
455 * @hw: pointer to hardware structure
456 * @index: Receive address register to write
457 * @addr: Address to put into receive address register
458 * @vmdq: VMDq "set" or "pool" index
459 * @enable_addr: set flag that address is active
460 *
461 * Puts an ethernet address into a receive address register.
462 **/
ngbe_set_rar(struct ngbe_hw * hw,u32 index,u8 * addr,u32 vmdq,u32 enable_addr)463 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
464 u32 enable_addr)
465 {
466 u32 rar_low, rar_high;
467 u32 rar_entries = hw->mac.num_rar_entries;
468
469 /* Make sure we are using a valid rar index range */
470 if (index >= rar_entries) {
471 DEBUGOUT("RAR index %d is out of range.", index);
472 return NGBE_ERR_INVALID_ARGUMENT;
473 }
474
475 /* setup VMDq pool selection before this RAR gets enabled */
476 hw->mac.set_vmdq(hw, index, vmdq);
477
478 /*
479 * HW expects these in little endian so we reverse the byte
480 * order from network order (big endian) to little endian
481 */
482 rar_low = NGBE_ETHADDRL_AD0(addr[5]) |
483 NGBE_ETHADDRL_AD1(addr[4]) |
484 NGBE_ETHADDRL_AD2(addr[3]) |
485 NGBE_ETHADDRL_AD3(addr[2]);
486 /*
487 * Some parts put the VMDq setting in the extra RAH bits,
488 * so save everything except the lower 16 bits that hold part
489 * of the address and the address valid bit.
490 */
491 rar_high = rd32(hw, NGBE_ETHADDRH);
492 rar_high &= ~NGBE_ETHADDRH_AD_MASK;
493 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) |
494 NGBE_ETHADDRH_AD5(addr[0]));
495
496 rar_high &= ~NGBE_ETHADDRH_VLD;
497 if (enable_addr != 0)
498 rar_high |= NGBE_ETHADDRH_VLD;
499
500 wr32(hw, NGBE_ETHADDRIDX, index);
501 wr32(hw, NGBE_ETHADDRL, rar_low);
502 wr32(hw, NGBE_ETHADDRH, rar_high);
503
504 return 0;
505 }
506
507 /**
508 * ngbe_clear_rar - Remove Rx address register
509 * @hw: pointer to hardware structure
510 * @index: Receive address register to write
511 *
512 * Clears an ethernet address from a receive address register.
513 **/
ngbe_clear_rar(struct ngbe_hw * hw,u32 index)514 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index)
515 {
516 u32 rar_high;
517 u32 rar_entries = hw->mac.num_rar_entries;
518
519 /* Make sure we are using a valid rar index range */
520 if (index >= rar_entries) {
521 DEBUGOUT("RAR index %d is out of range.", index);
522 return NGBE_ERR_INVALID_ARGUMENT;
523 }
524
525 /*
526 * Some parts put the VMDq setting in the extra RAH bits,
527 * so save everything except the lower 16 bits that hold part
528 * of the address and the address valid bit.
529 */
530 wr32(hw, NGBE_ETHADDRIDX, index);
531 rar_high = rd32(hw, NGBE_ETHADDRH);
532 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD);
533
534 wr32(hw, NGBE_ETHADDRL, 0);
535 wr32(hw, NGBE_ETHADDRH, rar_high);
536
537 /* clear VMDq pool/queue selection for this RAR */
538 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
539
540 return 0;
541 }
542
543 /**
544 * ngbe_init_rx_addrs - Initializes receive address filters.
545 * @hw: pointer to hardware structure
546 *
547 * Places the MAC address in receive address register 0 and clears the rest
548 * of the receive address registers. Clears the multicast table. Assumes
549 * the receiver is in reset when the routine is called.
550 **/
ngbe_init_rx_addrs(struct ngbe_hw * hw)551 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw)
552 {
553 u32 i;
554 u32 psrctl;
555 u32 rar_entries = hw->mac.num_rar_entries;
556
557 /*
558 * If the current mac address is valid, assume it is a software override
559 * to the permanent address.
560 * Otherwise, use the permanent address from the eeprom.
561 */
562 if (ngbe_validate_mac_addr(hw->mac.addr) ==
563 NGBE_ERR_INVALID_MAC_ADDR) {
564 /* Get the MAC address from the RAR0 for later reference */
565 hw->mac.get_mac_addr(hw, hw->mac.addr);
566
567 DEBUGOUT(" Keeping Current RAR0 Addr = "
568 RTE_ETHER_ADDR_PRT_FMT,
569 hw->mac.addr[0], hw->mac.addr[1],
570 hw->mac.addr[2], hw->mac.addr[3],
571 hw->mac.addr[4], hw->mac.addr[5]);
572 } else {
573 /* Setup the receive address. */
574 DEBUGOUT("Overriding MAC Address in RAR[0]");
575 DEBUGOUT(" New MAC Addr = "
576 RTE_ETHER_ADDR_PRT_FMT,
577 hw->mac.addr[0], hw->mac.addr[1],
578 hw->mac.addr[2], hw->mac.addr[3],
579 hw->mac.addr[4], hw->mac.addr[5]);
580
581 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
582 }
583
584 /* clear VMDq pool/queue selection for RAR 0 */
585 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
586
587 /* Zero out the other receive addresses. */
588 DEBUGOUT("Clearing RAR[1-%d]", rar_entries - 1);
589 for (i = 1; i < rar_entries; i++) {
590 wr32(hw, NGBE_ETHADDRIDX, i);
591 wr32(hw, NGBE_ETHADDRL, 0);
592 wr32(hw, NGBE_ETHADDRH, 0);
593 }
594
595 /* Clear the MTA */
596 hw->addr_ctrl.mta_in_use = 0;
597 psrctl = rd32(hw, NGBE_PSRCTL);
598 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
599 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
600 wr32(hw, NGBE_PSRCTL, psrctl);
601
602 DEBUGOUT(" Clearing MTA");
603 for (i = 0; i < hw->mac.mcft_size; i++)
604 wr32(hw, NGBE_MCADDRTBL(i), 0);
605
606 ngbe_init_uta_tables(hw);
607
608 return 0;
609 }
610
611 /**
612 * ngbe_mta_vector - Determines bit-vector in multicast table to set
613 * @hw: pointer to hardware structure
614 * @mc_addr: the multicast address
615 *
616 * Extracts the 12 bits, from a multicast address, to determine which
617 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
618 * incoming rx multicast addresses, to determine the bit-vector to check in
619 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
620 * by the MO field of the PSRCTRL. The MO field is set during initialization
621 * to mc_filter_type.
622 **/
ngbe_mta_vector(struct ngbe_hw * hw,u8 * mc_addr)623 static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr)
624 {
625 u32 vector = 0;
626
627 switch (hw->mac.mc_filter_type) {
628 case 0: /* use bits [47:36] of the address */
629 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
630 break;
631 case 1: /* use bits [46:35] of the address */
632 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
633 break;
634 case 2: /* use bits [45:34] of the address */
635 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
636 break;
637 case 3: /* use bits [43:32] of the address */
638 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
639 break;
640 default: /* Invalid mc_filter_type */
641 DEBUGOUT("MC filter type param set incorrectly");
642 ASSERT(0);
643 break;
644 }
645
646 /* vector can only be 12-bits or boundary will be exceeded */
647 vector &= 0xFFF;
648 return vector;
649 }
650
651 /**
652 * ngbe_set_mta - Set bit-vector in multicast table
653 * @hw: pointer to hardware structure
654 * @mc_addr: Multicast address
655 *
656 * Sets the bit-vector in the multicast table.
657 **/
ngbe_set_mta(struct ngbe_hw * hw,u8 * mc_addr)658 void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr)
659 {
660 u32 vector;
661 u32 vector_bit;
662 u32 vector_reg;
663
664 hw->addr_ctrl.mta_in_use++;
665
666 vector = ngbe_mta_vector(hw, mc_addr);
667 DEBUGOUT(" bit-vector = 0x%03X", vector);
668
669 /*
670 * The MTA is a register array of 128 32-bit registers. It is treated
671 * like an array of 4096 bits. We want to set bit
672 * BitArray[vector_value]. So we figure out what register the bit is
673 * in, read it, OR in the new bit, then write back the new value. The
674 * register is determined by the upper 7 bits of the vector value and
675 * the bit within that register are determined by the lower 5 bits of
676 * the value.
677 */
678 vector_reg = (vector >> 5) & 0x7F;
679 vector_bit = vector & 0x1F;
680 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
681 }
682
683 /**
684 * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses
685 * @hw: pointer to hardware structure
686 * @mc_addr_list: the list of new multicast addresses
687 * @mc_addr_count: number of addresses
688 * @next: iterator function to walk the multicast address list
689 * @clear: flag, when set clears the table beforehand
690 *
691 * When the clear flag is set, the given list replaces any existing list.
692 * Hashes the given addresses into the multicast table.
693 **/
ngbe_update_mc_addr_list(struct ngbe_hw * hw,u8 * mc_addr_list,u32 mc_addr_count,ngbe_mc_addr_itr next,bool clear)694 s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list,
695 u32 mc_addr_count, ngbe_mc_addr_itr next,
696 bool clear)
697 {
698 u32 i;
699 u32 vmdq;
700
701 /*
702 * Set the new number of MC addresses that we are being requested to
703 * use.
704 */
705 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
706 hw->addr_ctrl.mta_in_use = 0;
707
708 /* Clear mta_shadow */
709 if (clear) {
710 DEBUGOUT(" Clearing MTA");
711 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
712 }
713
714 /* Update mta_shadow */
715 for (i = 0; i < mc_addr_count; i++) {
716 DEBUGOUT(" Adding the multicast addresses:");
717 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
718 }
719
720 /* Enable mta */
721 for (i = 0; i < hw->mac.mcft_size; i++)
722 wr32a(hw, NGBE_MCADDRTBL(0), i,
723 hw->mac.mta_shadow[i]);
724
725 if (hw->addr_ctrl.mta_in_use > 0) {
726 u32 psrctl = rd32(hw, NGBE_PSRCTL);
727 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA);
728 psrctl |= NGBE_PSRCTL_MCHFENA |
729 NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
730 wr32(hw, NGBE_PSRCTL, psrctl);
731 }
732
733 DEBUGOUT("ngbe update mc addr list complete");
734 return 0;
735 }
736
737 /**
738 * ngbe_setup_fc_em - Set up flow control
739 * @hw: pointer to hardware structure
740 *
741 * Called at init time to set up flow control.
742 **/
ngbe_setup_fc_em(struct ngbe_hw * hw)743 s32 ngbe_setup_fc_em(struct ngbe_hw *hw)
744 {
745 s32 err = 0;
746 u16 reg_cu = 0;
747
748 /* Validate the requested mode */
749 if (hw->fc.strict_ieee && hw->fc.requested_mode == ngbe_fc_rx_pause) {
750 DEBUGOUT("ngbe_fc_rx_pause not valid in strict IEEE mode");
751 err = NGBE_ERR_INVALID_LINK_SETTINGS;
752 goto out;
753 }
754
755 /*
756 * 1gig parts do not have a word in the EEPROM to determine the
757 * default flow control setting, so we explicitly set it to full.
758 */
759 if (hw->fc.requested_mode == ngbe_fc_default)
760 hw->fc.requested_mode = ngbe_fc_full;
761
762 /*
763 * The possible values of fc.requested_mode are:
764 * 0: Flow control is completely disabled
765 * 1: Rx flow control is enabled (we can receive pause frames,
766 * but not send pause frames).
767 * 2: Tx flow control is enabled (we can send pause frames but
768 * we do not support receiving pause frames).
769 * 3: Both Rx and Tx flow control (symmetric) are enabled.
770 * other: Invalid.
771 */
772 switch (hw->fc.requested_mode) {
773 case ngbe_fc_none:
774 /* Flow control completely disabled by software override. */
775 break;
776 case ngbe_fc_tx_pause:
777 /*
778 * Tx Flow control is enabled, and Rx Flow control is
779 * disabled by software override.
780 */
781 if (hw->phy.type == ngbe_phy_mvl_sfi ||
782 hw->phy.type == ngbe_phy_yt8521s_sfi)
783 reg_cu |= MVL_FANA_ASM_PAUSE;
784 else
785 reg_cu |= 0x800; /*need to merge rtl and mvl on page 0*/
786 break;
787 case ngbe_fc_rx_pause:
788 /*
789 * Rx Flow control is enabled and Tx Flow control is
790 * disabled by software override. Since there really
791 * isn't a way to advertise that we are capable of RX
792 * Pause ONLY, we will advertise that we support both
793 * symmetric and asymmetric Rx PAUSE, as such we fall
794 * through to the fc_full statement. Later, we will
795 * disable the adapter's ability to send PAUSE frames.
796 */
797 case ngbe_fc_full:
798 /* Flow control (both Rx and Tx) is enabled by SW override. */
799 if (hw->phy.type == ngbe_phy_mvl_sfi ||
800 hw->phy.type == ngbe_phy_yt8521s_sfi)
801 reg_cu |= MVL_FANA_SYM_PAUSE;
802 else
803 reg_cu |= 0xC00; /*need to merge rtl and mvl on page 0*/
804 break;
805 default:
806 DEBUGOUT("Flow control param set incorrectly");
807 err = NGBE_ERR_CONFIG;
808 goto out;
809 }
810
811 err = hw->phy.set_pause_adv(hw, reg_cu);
812
813 out:
814 return err;
815 }
816
817 /**
818 * ngbe_fc_enable - Enable flow control
819 * @hw: pointer to hardware structure
820 *
821 * Enable flow control according to the current settings.
822 **/
ngbe_fc_enable(struct ngbe_hw * hw)823 s32 ngbe_fc_enable(struct ngbe_hw *hw)
824 {
825 s32 err = 0;
826 u32 mflcn_reg, fccfg_reg;
827 u32 pause_time;
828 u32 fcrtl, fcrth;
829
830 /* Validate the water mark configuration */
831 if (!hw->fc.pause_time) {
832 err = NGBE_ERR_INVALID_LINK_SETTINGS;
833 goto out;
834 }
835
836 /* Low water mark of zero causes XOFF floods */
837 if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) {
838 if (!hw->fc.low_water ||
839 hw->fc.low_water >= hw->fc.high_water) {
840 DEBUGOUT("Invalid water mark configuration");
841 err = NGBE_ERR_INVALID_LINK_SETTINGS;
842 goto out;
843 }
844 }
845
846 /* Negotiate the fc mode to use */
847 hw->mac.fc_autoneg(hw);
848
849 /* Disable any previous flow control settings */
850 mflcn_reg = rd32(hw, NGBE_RXFCCFG);
851 mflcn_reg &= ~NGBE_RXFCCFG_FC;
852
853 fccfg_reg = rd32(hw, NGBE_TXFCCFG);
854 fccfg_reg &= ~NGBE_TXFCCFG_FC;
855 /*
856 * The possible values of fc.current_mode are:
857 * 0: Flow control is completely disabled
858 * 1: Rx flow control is enabled (we can receive pause frames,
859 * but not send pause frames).
860 * 2: Tx flow control is enabled (we can send pause frames but
861 * we do not support receiving pause frames).
862 * 3: Both Rx and Tx flow control (symmetric) are enabled.
863 * other: Invalid.
864 */
865 switch (hw->fc.current_mode) {
866 case ngbe_fc_none:
867 /*
868 * Flow control is disabled by software override or autoneg.
869 * The code below will actually disable it in the HW.
870 */
871 break;
872 case ngbe_fc_rx_pause:
873 /*
874 * Rx Flow control is enabled and Tx Flow control is
875 * disabled by software override. Since there really
876 * isn't a way to advertise that we are capable of RX
877 * Pause ONLY, we will advertise that we support both
878 * symmetric and asymmetric Rx PAUSE. Later, we will
879 * disable the adapter's ability to send PAUSE frames.
880 */
881 mflcn_reg |= NGBE_RXFCCFG_FC;
882 break;
883 case ngbe_fc_tx_pause:
884 /*
885 * Tx Flow control is enabled, and Rx Flow control is
886 * disabled by software override.
887 */
888 fccfg_reg |= NGBE_TXFCCFG_FC;
889 break;
890 case ngbe_fc_full:
891 /* Flow control (both Rx and Tx) is enabled by SW override. */
892 mflcn_reg |= NGBE_RXFCCFG_FC;
893 fccfg_reg |= NGBE_TXFCCFG_FC;
894 break;
895 default:
896 DEBUGOUT("Flow control param set incorrectly");
897 err = NGBE_ERR_CONFIG;
898 goto out;
899 }
900
901 /* Set 802.3x based flow control settings. */
902 wr32(hw, NGBE_RXFCCFG, mflcn_reg);
903 wr32(hw, NGBE_TXFCCFG, fccfg_reg);
904
905 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
906 if ((hw->fc.current_mode & ngbe_fc_tx_pause) &&
907 hw->fc.high_water) {
908 fcrtl = NGBE_FCWTRLO_TH(hw->fc.low_water) |
909 NGBE_FCWTRLO_XON;
910 fcrth = NGBE_FCWTRHI_TH(hw->fc.high_water) |
911 NGBE_FCWTRHI_XOFF;
912 } else {
913 /*
914 * In order to prevent Tx hangs when the internal Tx
915 * switch is enabled we must set the high water mark
916 * to the Rx packet buffer size - 24KB. This allows
917 * the Tx switch to function even under heavy Rx
918 * workloads.
919 */
920 fcrtl = 0;
921 fcrth = rd32(hw, NGBE_PBRXSIZE) - 24576;
922 }
923 wr32(hw, NGBE_FCWTRLO, fcrtl);
924 wr32(hw, NGBE_FCWTRHI, fcrth);
925
926 /* Configure pause time */
927 pause_time = NGBE_RXFCFSH_TIME(hw->fc.pause_time);
928 wr32(hw, NGBE_FCXOFFTM, pause_time * 0x00010000);
929
930 /* Configure flow control refresh threshold value */
931 wr32(hw, NGBE_RXFCRFSH, hw->fc.pause_time / 2);
932
933 out:
934 return err;
935 }
936
937 /**
938 * ngbe_negotiate_fc - Negotiate flow control
939 * @hw: pointer to hardware structure
940 * @adv_reg: flow control advertised settings
941 * @lp_reg: link partner's flow control settings
942 * @adv_sym: symmetric pause bit in advertisement
943 * @adv_asm: asymmetric pause bit in advertisement
944 * @lp_sym: symmetric pause bit in link partner advertisement
945 * @lp_asm: asymmetric pause bit in link partner advertisement
946 *
947 * Find the intersection between advertised settings and link partner's
948 * advertised settings
949 **/
ngbe_negotiate_fc(struct ngbe_hw * hw,u32 adv_reg,u32 lp_reg,u32 adv_sym,u32 adv_asm,u32 lp_sym,u32 lp_asm)950 s32 ngbe_negotiate_fc(struct ngbe_hw *hw, u32 adv_reg, u32 lp_reg,
951 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
952 {
953 if ((!(adv_reg)) || (!(lp_reg))) {
954 DEBUGOUT("Local or link partner's advertised flow control settings are NULL. Local: %x, link partner: %x",
955 adv_reg, lp_reg);
956 return NGBE_ERR_FC_NOT_NEGOTIATED;
957 }
958
959 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
960 /*
961 * Now we need to check if the user selected Rx ONLY
962 * of pause frames. In this case, we had to advertise
963 * FULL flow control because we could not advertise RX
964 * ONLY. Hence, we must now check to see if we need to
965 * turn OFF the TRANSMISSION of PAUSE frames.
966 */
967 if (hw->fc.requested_mode == ngbe_fc_full) {
968 hw->fc.current_mode = ngbe_fc_full;
969 DEBUGOUT("Flow Control = FULL.");
970 } else {
971 hw->fc.current_mode = ngbe_fc_rx_pause;
972 DEBUGOUT("Flow Control=RX PAUSE frames only");
973 }
974 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
975 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
976 hw->fc.current_mode = ngbe_fc_tx_pause;
977 DEBUGOUT("Flow Control = TX PAUSE frames only.");
978 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
979 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
980 hw->fc.current_mode = ngbe_fc_rx_pause;
981 DEBUGOUT("Flow Control = RX PAUSE frames only.");
982 } else {
983 hw->fc.current_mode = ngbe_fc_none;
984 DEBUGOUT("Flow Control = NONE.");
985 }
986 return 0;
987 }
988
989 /**
990 * ngbe_fc_autoneg_em - Enable flow control IEEE clause 37
991 * @hw: pointer to hardware structure
992 *
993 * Enable flow control according to IEEE clause 37.
994 **/
ngbe_fc_autoneg_em(struct ngbe_hw * hw)995 STATIC s32 ngbe_fc_autoneg_em(struct ngbe_hw *hw)
996 {
997 u8 technology_ability_reg = 0;
998 u8 lp_technology_ability_reg = 0;
999
1000 hw->phy.get_adv_pause(hw, &technology_ability_reg);
1001 hw->phy.get_lp_adv_pause(hw, &lp_technology_ability_reg);
1002
1003 return ngbe_negotiate_fc(hw, (u32)technology_ability_reg,
1004 (u32)lp_technology_ability_reg,
1005 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE,
1006 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE);
1007 }
1008
1009 /**
1010 * ngbe_fc_autoneg - Configure flow control
1011 * @hw: pointer to hardware structure
1012 *
1013 * Compares our advertised flow control capabilities to those advertised by
1014 * our link partner, and determines the proper flow control mode to use.
1015 **/
ngbe_fc_autoneg(struct ngbe_hw * hw)1016 void ngbe_fc_autoneg(struct ngbe_hw *hw)
1017 {
1018 s32 err = NGBE_ERR_FC_NOT_NEGOTIATED;
1019 u32 speed;
1020 bool link_up;
1021
1022 /*
1023 * AN should have completed when the cable was plugged in.
1024 * Look for reasons to bail out. Bail out if:
1025 * - FC autoneg is disabled, or if
1026 * - link is not up.
1027 */
1028 if (hw->fc.disable_fc_autoneg) {
1029 DEBUGOUT("Flow control autoneg is disabled");
1030 goto out;
1031 }
1032
1033 hw->mac.check_link(hw, &speed, &link_up, false);
1034 if (!link_up) {
1035 DEBUGOUT("The link is down");
1036 goto out;
1037 }
1038
1039 err = ngbe_fc_autoneg_em(hw);
1040
1041 out:
1042 if (err == 0) {
1043 hw->fc.fc_was_autonegged = true;
1044 } else {
1045 hw->fc.fc_was_autonegged = false;
1046 hw->fc.current_mode = hw->fc.requested_mode;
1047 }
1048 }
1049
1050 /**
1051 * ngbe_set_pcie_master - Disable or Enable PCI-express master access
1052 * @hw: pointer to hardware structure
1053 *
1054 * Disables PCI-Express master access and verifies there are no pending
1055 * requests. NGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1056 * bit hasn't caused the master requests to be disabled, else 0
1057 * is returned signifying master requests disabled.
1058 **/
ngbe_set_pcie_master(struct ngbe_hw * hw,bool enable)1059 s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
1060 {
1061 s32 status = 0;
1062 u16 addr = 0x04;
1063 u32 data, i;
1064
1065 ngbe_hic_pcie_read(hw, addr, &data, 4);
1066 if (enable)
1067 data |= 0x04;
1068 else
1069 data &= ~0x04;
1070
1071 ngbe_hic_pcie_write(hw, addr, &data, 4);
1072
1073 if (enable)
1074 goto out;
1075
1076 /* Exit if master requests are blocked */
1077 if (!(rd32(hw, NGBE_BMEPEND)) ||
1078 NGBE_REMOVED(hw->hw_addr))
1079 goto out;
1080
1081 /* Poll for master request bit to clear */
1082 for (i = 0; i < NGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1083 usec_delay(100);
1084 if (!(rd32(hw, NGBE_BMEPEND)))
1085 goto out;
1086 }
1087
1088 DEBUGOUT("PCIe transaction pending bit also did not clear.");
1089 status = NGBE_ERR_MASTER_REQUESTS_PENDING;
1090
1091 out:
1092 return status;
1093 }
1094
1095 /**
1096 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore
1097 * @hw: pointer to hardware structure
1098 * @mask: Mask to specify which semaphore to acquire
1099 *
1100 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1101 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1102 **/
ngbe_acquire_swfw_sync(struct ngbe_hw * hw,u32 mask)1103 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask)
1104 {
1105 u32 mngsem = 0;
1106 u32 fwsm = 0;
1107 u32 swmask = NGBE_MNGSEM_SW(mask);
1108 u32 fwmask = NGBE_MNGSEM_FW(mask);
1109 u32 timeout = 200;
1110 u32 i;
1111
1112 for (i = 0; i < timeout; i++) {
1113 /*
1114 * SW NVM semaphore bit is used for access to all
1115 * SW_FW_SYNC bits (not just NVM)
1116 */
1117 if (ngbe_get_eeprom_semaphore(hw))
1118 return NGBE_ERR_SWFW_SYNC;
1119
1120 mngsem = rd32(hw, NGBE_MNGSEM);
1121 if (mngsem & (fwmask | swmask)) {
1122 /* Resource is currently in use by FW or SW */
1123 ngbe_release_eeprom_semaphore(hw);
1124 msec_delay(5);
1125 } else {
1126 mngsem |= swmask;
1127 wr32(hw, NGBE_MNGSEM, mngsem);
1128 ngbe_release_eeprom_semaphore(hw);
1129 return 0;
1130 }
1131 }
1132
1133 fwsm = rd32(hw, NGBE_MNGFWSYNC);
1134 DEBUGOUT("SWFW semaphore not granted: MNG_SWFW_SYNC = 0x%x, MNG_FW_SM = 0x%x",
1135 mngsem, fwsm);
1136
1137 msec_delay(5);
1138 return NGBE_ERR_SWFW_SYNC;
1139 }
1140
1141 /**
1142 * ngbe_release_swfw_sync - Release SWFW semaphore
1143 * @hw: pointer to hardware structure
1144 * @mask: Mask to specify which semaphore to release
1145 *
1146 * Releases the SWFW semaphore through the MNGSEM register for the specified
1147 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1148 **/
ngbe_release_swfw_sync(struct ngbe_hw * hw,u32 mask)1149 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask)
1150 {
1151 u32 mngsem;
1152 u32 swmask = mask;
1153
1154 ngbe_get_eeprom_semaphore(hw);
1155
1156 mngsem = rd32(hw, NGBE_MNGSEM);
1157 mngsem &= ~swmask;
1158 wr32(hw, NGBE_MNGSEM, mngsem);
1159
1160 ngbe_release_eeprom_semaphore(hw);
1161 }
1162
1163 /**
1164 * ngbe_disable_sec_rx_path - Stops the receive data path
1165 * @hw: pointer to hardware structure
1166 *
1167 * Stops the receive data path and waits for the HW to internally empty
1168 * the Rx security block
1169 **/
ngbe_disable_sec_rx_path(struct ngbe_hw * hw)1170 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw)
1171 {
1172 #define NGBE_MAX_SECRX_POLL 4000
1173
1174 int i;
1175 u32 secrxreg;
1176
1177 secrxreg = rd32(hw, NGBE_SECRXCTL);
1178 secrxreg |= NGBE_SECRXCTL_XDSA;
1179 wr32(hw, NGBE_SECRXCTL, secrxreg);
1180 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) {
1181 secrxreg = rd32(hw, NGBE_SECRXSTAT);
1182 if (!(secrxreg & NGBE_SECRXSTAT_RDY))
1183 /* Use interrupt-safe sleep just in case */
1184 usec_delay(10);
1185 else
1186 break;
1187 }
1188
1189 /* For informational purposes only */
1190 if (i >= NGBE_MAX_SECRX_POLL)
1191 DEBUGOUT("Rx unit being enabled before security path fully disabled. Continuing with init.");
1192
1193 return 0;
1194 }
1195
1196 /**
1197 * ngbe_enable_sec_rx_path - Enables the receive data path
1198 * @hw: pointer to hardware structure
1199 *
1200 * Enables the receive data path.
1201 **/
ngbe_enable_sec_rx_path(struct ngbe_hw * hw)1202 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw)
1203 {
1204 u32 secrxreg;
1205
1206 secrxreg = rd32(hw, NGBE_SECRXCTL);
1207 secrxreg &= ~NGBE_SECRXCTL_XDSA;
1208 wr32(hw, NGBE_SECRXCTL, secrxreg);
1209 ngbe_flush(hw);
1210
1211 return 0;
1212 }
1213
1214 /**
1215 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1216 * @hw: pointer to hardware struct
1217 * @rar: receive address register index to disassociate
1218 * @vmdq: VMDq pool index to remove from the rar
1219 **/
ngbe_clear_vmdq(struct ngbe_hw * hw,u32 rar,u32 vmdq)1220 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1221 {
1222 u32 mpsar;
1223 u32 rar_entries = hw->mac.num_rar_entries;
1224
1225 /* Make sure we are using a valid rar index range */
1226 if (rar >= rar_entries) {
1227 DEBUGOUT("RAR index %d is out of range.", rar);
1228 return NGBE_ERR_INVALID_ARGUMENT;
1229 }
1230
1231 wr32(hw, NGBE_ETHADDRIDX, rar);
1232 mpsar = rd32(hw, NGBE_ETHADDRASS);
1233
1234 if (NGBE_REMOVED(hw->hw_addr))
1235 goto done;
1236
1237 if (!mpsar)
1238 goto done;
1239
1240 mpsar &= ~(1 << vmdq);
1241 wr32(hw, NGBE_ETHADDRASS, mpsar);
1242
1243 /* was that the last pool using this rar? */
1244 if (mpsar == 0 && rar != 0)
1245 hw->mac.clear_rar(hw, rar);
1246 done:
1247 return 0;
1248 }
1249
1250 /**
1251 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address
1252 * @hw: pointer to hardware struct
1253 * @rar: receive address register index to associate with a VMDq index
1254 * @vmdq: VMDq pool index
1255 **/
ngbe_set_vmdq(struct ngbe_hw * hw,u32 rar,u32 vmdq)1256 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq)
1257 {
1258 u32 mpsar;
1259 u32 rar_entries = hw->mac.num_rar_entries;
1260
1261 /* Make sure we are using a valid rar index range */
1262 if (rar >= rar_entries) {
1263 DEBUGOUT("RAR index %d is out of range.", rar);
1264 return NGBE_ERR_INVALID_ARGUMENT;
1265 }
1266
1267 wr32(hw, NGBE_ETHADDRIDX, rar);
1268
1269 mpsar = rd32(hw, NGBE_ETHADDRASS);
1270 mpsar |= 1 << vmdq;
1271 wr32(hw, NGBE_ETHADDRASS, mpsar);
1272
1273 return 0;
1274 }
1275
1276 /**
1277 * ngbe_init_uta_tables - Initialize the Unicast Table Array
1278 * @hw: pointer to hardware structure
1279 **/
ngbe_init_uta_tables(struct ngbe_hw * hw)1280 s32 ngbe_init_uta_tables(struct ngbe_hw *hw)
1281 {
1282 int i;
1283
1284 DEBUGOUT(" Clearing UTA");
1285
1286 for (i = 0; i < 128; i++)
1287 wr32(hw, NGBE_UCADDRTBL(i), 0);
1288
1289 return 0;
1290 }
1291
1292 /**
1293 * ngbe_find_vlvf_slot - find the vlanid or the first empty slot
1294 * @hw: pointer to hardware structure
1295 * @vlan: VLAN id to write to VLAN filter
1296 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1297 * vlanid not found
1298 *
1299 *
1300 * return the VLVF index where this VLAN id should be placed
1301 *
1302 **/
ngbe_find_vlvf_slot(struct ngbe_hw * hw,u32 vlan,bool vlvf_bypass)1303 s32 ngbe_find_vlvf_slot(struct ngbe_hw *hw, u32 vlan, bool vlvf_bypass)
1304 {
1305 s32 regindex, first_empty_slot;
1306 u32 bits;
1307
1308 /* short cut the special case */
1309 if (vlan == 0)
1310 return 0;
1311
1312 /* if vlvf_bypass is set we don't want to use an empty slot, we
1313 * will simply bypass the VLVF if there are no entries present in the
1314 * VLVF that contain our VLAN
1315 */
1316 first_empty_slot = vlvf_bypass ? NGBE_ERR_NO_SPACE : 0;
1317
1318 /* add VLAN enable bit for comparison */
1319 vlan |= NGBE_PSRVLAN_EA;
1320
1321 /* Search for the vlan id in the VLVF entries. Save off the first empty
1322 * slot found along the way.
1323 *
1324 * pre-decrement loop covering (NGBE_NUM_POOL - 1) .. 1
1325 */
1326 for (regindex = NGBE_NUM_POOL; --regindex;) {
1327 wr32(hw, NGBE_PSRVLANIDX, regindex);
1328 bits = rd32(hw, NGBE_PSRVLAN);
1329 if (bits == vlan)
1330 return regindex;
1331 if (!first_empty_slot && !bits)
1332 first_empty_slot = regindex;
1333 }
1334
1335 /* If we are here then we didn't find the VLAN. Return first empty
1336 * slot we found during our search, else error.
1337 */
1338 if (!first_empty_slot)
1339 DEBUGOUT("No space in VLVF.");
1340
1341 return first_empty_slot ? first_empty_slot : NGBE_ERR_NO_SPACE;
1342 }
1343
1344 /**
1345 * ngbe_set_vfta - Set VLAN filter table
1346 * @hw: pointer to hardware structure
1347 * @vlan: VLAN id to write to VLAN filter
1348 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1349 * @vlan_on: boolean flag to turn on/off VLAN
1350 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1351 *
1352 * Turn on/off specified VLAN in the VLAN filter table.
1353 **/
ngbe_set_vfta(struct ngbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool vlvf_bypass)1354 s32 ngbe_set_vfta(struct ngbe_hw *hw, u32 vlan, u32 vind,
1355 bool vlan_on, bool vlvf_bypass)
1356 {
1357 u32 regidx, vfta_delta, vfta;
1358 s32 err;
1359
1360 if (vlan > 4095 || vind > 63)
1361 return NGBE_ERR_PARAM;
1362
1363 /*
1364 * this is a 2 part operation - first the VFTA, then the
1365 * VLVF and VLVFB if VT Mode is set
1366 * We don't write the VFTA until we know the VLVF part succeeded.
1367 */
1368
1369 /* Part 1
1370 * The VFTA is a bitstring made up of 128 32-bit registers
1371 * that enable the particular VLAN id, much like the MTA:
1372 * bits[11-5]: which register
1373 * bits[4-0]: which bit in the register
1374 */
1375 regidx = vlan / 32;
1376 vfta_delta = 1 << (vlan % 32);
1377 vfta = rd32(hw, NGBE_VLANTBL(regidx));
1378
1379 /*
1380 * vfta_delta represents the difference between the current value
1381 * of vfta and the value we want in the register. Since the diff
1382 * is an XOR mask we can just update the vfta using an XOR
1383 */
1384 vfta_delta &= vlan_on ? ~vfta : vfta;
1385 vfta ^= vfta_delta;
1386
1387 /* Part 2
1388 * Call ngbe_set_vlvf to set VLVFB and VLVF
1389 */
1390 err = ngbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1391 vfta, vlvf_bypass);
1392 if (err != 0) {
1393 if (vlvf_bypass)
1394 goto vfta_update;
1395 return err;
1396 }
1397
1398 vfta_update:
1399 /* Update VFTA now that we are ready for traffic */
1400 if (vfta_delta)
1401 wr32(hw, NGBE_VLANTBL(regidx), vfta);
1402
1403 return 0;
1404 }
1405
1406 /**
1407 * ngbe_set_vlvf - Set VLAN Pool Filter
1408 * @hw: pointer to hardware structure
1409 * @vlan: VLAN id to write to VLAN filter
1410 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1411 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1412 * @vfta_delta: pointer to the difference between the current value
1413 * of PSRVLANPLM and the desired value
1414 * @vfta: the desired value of the VFTA
1415 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1416 *
1417 * Turn on/off specified bit in VLVF table.
1418 **/
ngbe_set_vlvf(struct ngbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,u32 * vfta_delta,u32 vfta,bool vlvf_bypass)1419 s32 ngbe_set_vlvf(struct ngbe_hw *hw, u32 vlan, u32 vind,
1420 bool vlan_on, u32 *vfta_delta, u32 vfta,
1421 bool vlvf_bypass)
1422 {
1423 u32 bits;
1424 u32 portctl;
1425 s32 vlvf_index;
1426
1427 if (vlan > 4095 || vind > 63)
1428 return NGBE_ERR_PARAM;
1429
1430 /* If VT Mode is set
1431 * Either vlan_on
1432 * make sure the vlan is in PSRVLAN
1433 * set the vind bit in the matching PSRVLANPLM
1434 * Or !vlan_on
1435 * clear the pool bit and possibly the vind
1436 */
1437 portctl = rd32(hw, NGBE_PORTCTL);
1438 if (!(portctl & NGBE_PORTCTL_NUMVT_MASK))
1439 return 0;
1440
1441 vlvf_index = ngbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1442 if (vlvf_index < 0)
1443 return vlvf_index;
1444
1445 wr32(hw, NGBE_PSRVLANIDX, vlvf_index);
1446 bits = rd32(hw, NGBE_PSRVLANPLM(vind / 32));
1447
1448 /* set the pool bit */
1449 bits |= 1 << (vind % 32);
1450 if (vlan_on)
1451 goto vlvf_update;
1452
1453 /* clear the pool bit */
1454 bits ^= 1 << (vind % 32);
1455
1456 if (!bits &&
1457 !rd32(hw, NGBE_PSRVLANPLM(vind / 32))) {
1458 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1459 * we run the risk of stray packets leaking into
1460 * the PF via the default pool
1461 */
1462 if (*vfta_delta)
1463 wr32(hw, NGBE_PSRVLANPLM(vlan / 32), vfta);
1464
1465 /* disable VLVF and clear remaining bit from pool */
1466 wr32(hw, NGBE_PSRVLAN, 0);
1467 wr32(hw, NGBE_PSRVLANPLM(vind / 32), 0);
1468
1469 return 0;
1470 }
1471
1472 /* If there are still bits set in the PSRVLANPLM registers
1473 * for the VLAN ID indicated we need to see if the
1474 * caller is requesting that we clear the PSRVLANPLM entry bit.
1475 * If the caller has requested that we clear the PSRVLANPLM
1476 * entry bit but there are still pools/VFs using this VLAN
1477 * ID entry then ignore the request. We're not worried
1478 * about the case where we're turning the PSRVLANPLM VLAN ID
1479 * entry bit on, only when requested to turn it off as
1480 * there may be multiple pools and/or VFs using the
1481 * VLAN ID entry. In that case we cannot clear the
1482 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1483 * been cleared. This will be indicated by "bits" being
1484 * zero.
1485 */
1486 *vfta_delta = 0;
1487
1488 vlvf_update:
1489 /* record pool change and enable VLAN ID if not already enabled */
1490 wr32(hw, NGBE_PSRVLANPLM(vind / 32), bits);
1491 wr32(hw, NGBE_PSRVLAN, NGBE_PSRVLAN_EA | vlan);
1492
1493 return 0;
1494 }
1495
1496 /**
1497 * ngbe_clear_vfta - Clear VLAN filter table
1498 * @hw: pointer to hardware structure
1499 *
1500 * Clears the VLAN filer table, and the VMDq index associated with the filter
1501 **/
ngbe_clear_vfta(struct ngbe_hw * hw)1502 s32 ngbe_clear_vfta(struct ngbe_hw *hw)
1503 {
1504 u32 offset;
1505
1506 for (offset = 0; offset < hw->mac.vft_size; offset++)
1507 wr32(hw, NGBE_VLANTBL(offset), 0);
1508
1509 for (offset = 0; offset < NGBE_NUM_POOL; offset++) {
1510 wr32(hw, NGBE_PSRVLANIDX, offset);
1511 wr32(hw, NGBE_PSRVLAN, 0);
1512 wr32(hw, NGBE_PSRVLANPLM(0), 0);
1513 }
1514
1515 return 0;
1516 }
1517
1518 /**
1519 * ngbe_check_mac_link_em - Determine link and speed status
1520 * @hw: pointer to hardware structure
1521 * @speed: pointer to link speed
1522 * @link_up: true when link is up
1523 * @link_up_wait_to_complete: bool used to wait for link up or not
1524 *
1525 * Reads the links register to determine if link is up and the current speed
1526 **/
ngbe_check_mac_link_em(struct ngbe_hw * hw,u32 * speed,bool * link_up,bool link_up_wait_to_complete)1527 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed,
1528 bool *link_up, bool link_up_wait_to_complete)
1529 {
1530 u32 i, reg;
1531 s32 status = 0;
1532
1533 reg = rd32(hw, NGBE_GPIOINTSTAT);
1534 wr32(hw, NGBE_GPIOEOI, reg);
1535
1536 if (link_up_wait_to_complete) {
1537 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1538 status = hw->phy.check_link(hw, speed, link_up);
1539 if (*link_up)
1540 break;
1541 msec_delay(100);
1542 }
1543 } else {
1544 status = hw->phy.check_link(hw, speed, link_up);
1545 }
1546
1547 return status;
1548 }
1549
ngbe_get_link_capabilities_em(struct ngbe_hw * hw,u32 * speed,bool * autoneg)1550 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw,
1551 u32 *speed,
1552 bool *autoneg)
1553 {
1554 s32 status = 0;
1555 u16 value = 0;
1556
1557 hw->mac.autoneg = *autoneg;
1558
1559 if (hw->phy.type == ngbe_phy_rtl) {
1560 *speed = NGBE_LINK_SPEED_1GB_FULL |
1561 NGBE_LINK_SPEED_100M_FULL |
1562 NGBE_LINK_SPEED_10M_FULL;
1563 }
1564
1565 if (hw->phy.type == ngbe_phy_yt8521s_sfi) {
1566 ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);
1567 if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1))
1568 *speed = NGBE_LINK_SPEED_1GB_FULL;
1569 }
1570
1571 return status;
1572 }
1573
ngbe_setup_mac_link_em(struct ngbe_hw * hw,u32 speed,bool autoneg_wait_to_complete)1574 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw,
1575 u32 speed,
1576 bool autoneg_wait_to_complete)
1577 {
1578 s32 status;
1579
1580 /* Setup the PHY according to input speed */
1581 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete);
1582
1583 return status;
1584 }
1585
1586 /**
1587 * ngbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1588 * @hw: pointer to hardware structure
1589 * @enable: enable or disable switch for MAC anti-spoofing
1590 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1591 *
1592 **/
ngbe_set_mac_anti_spoofing(struct ngbe_hw * hw,bool enable,int vf)1593 void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1594 {
1595 u32 pfvfspoof;
1596
1597 pfvfspoof = rd32(hw, NGBE_POOLTXASMAC);
1598 if (enable)
1599 pfvfspoof |= (1 << vf);
1600 else
1601 pfvfspoof &= ~(1 << vf);
1602 wr32(hw, NGBE_POOLTXASMAC, pfvfspoof);
1603 }
1604
1605 /**
1606 * ngbe_set_pba - Initialize Rx packet buffer
1607 * @hw: pointer to hardware structure
1608 * @headroom: reserve n KB of headroom
1609 **/
ngbe_set_pba(struct ngbe_hw * hw)1610 void ngbe_set_pba(struct ngbe_hw *hw)
1611 {
1612 u32 rxpktsize = hw->mac.rx_pb_size;
1613 u32 txpktsize, txpbthresh;
1614
1615 /* Reserve 256 KB of headroom */
1616 rxpktsize -= 256;
1617
1618 rxpktsize <<= 10;
1619 wr32(hw, NGBE_PBRXSIZE, rxpktsize);
1620
1621 /* Only support an equally distributed Tx packet buffer strategy. */
1622 txpktsize = NGBE_PBTXSIZE_MAX;
1623 txpbthresh = (txpktsize / 1024) - NGBE_TXPKT_SIZE_MAX;
1624
1625 wr32(hw, NGBE_PBTXSIZE, txpktsize);
1626 wr32(hw, NGBE_PBTXDMATH, txpbthresh);
1627 }
1628
1629 /**
1630 * ngbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
1631 * @hw: pointer to hardware structure
1632 * @enable: enable or disable switch for VLAN anti-spoofing
1633 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
1634 *
1635 **/
ngbe_set_vlan_anti_spoofing(struct ngbe_hw * hw,bool enable,int vf)1636 void ngbe_set_vlan_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf)
1637 {
1638 u32 pfvfspoof;
1639
1640 pfvfspoof = rd32(hw, NGBE_POOLTXASVLAN);
1641 if (enable)
1642 pfvfspoof |= (1 << vf);
1643 else
1644 pfvfspoof &= ~(1 << vf);
1645 wr32(hw, NGBE_POOLTXASVLAN, pfvfspoof);
1646 }
1647
1648 /**
1649 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1650 * @hw: pointer to hardware structure
1651 *
1652 * Inits the thermal sensor thresholds according to the NVM map
1653 * and save off the threshold and location values into mac.thermal_sensor_data
1654 **/
ngbe_init_thermal_sensor_thresh(struct ngbe_hw * hw)1655 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)
1656 {
1657 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1658
1659 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data));
1660
1661 if (hw->bus.lan_id != 0)
1662 return NGBE_NOT_IMPLEMENTED;
1663
1664 wr32(hw, NGBE_TSINTR,
1665 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN);
1666 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA);
1667
1668
1669 data->sensor[0].alarm_thresh = 115;
1670 wr32(hw, NGBE_TSATHRE, 0x344);
1671 data->sensor[0].dalarm_thresh = 110;
1672 wr32(hw, NGBE_TSDTHRE, 0x330);
1673
1674 return 0;
1675 }
1676
ngbe_mac_check_overtemp(struct ngbe_hw * hw)1677 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)
1678 {
1679 s32 status = 0;
1680 u32 ts_state;
1681
1682 /* Check that the LASI temp alarm status was triggered */
1683 ts_state = rd32(hw, NGBE_TSALM);
1684
1685 if (ts_state & NGBE_TSALM_HI)
1686 status = NGBE_ERR_UNDERTEMP;
1687 else if (ts_state & NGBE_TSALM_LO)
1688 status = NGBE_ERR_OVERTEMP;
1689
1690 return status;
1691 }
1692
ngbe_disable_rx(struct ngbe_hw * hw)1693 void ngbe_disable_rx(struct ngbe_hw *hw)
1694 {
1695 u32 pfdtxgswc;
1696
1697 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1698 if (pfdtxgswc & NGBE_PSRCTL_LBENA) {
1699 pfdtxgswc &= ~NGBE_PSRCTL_LBENA;
1700 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1701 hw->mac.set_lben = true;
1702 } else {
1703 hw->mac.set_lben = false;
1704 }
1705
1706 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0);
1707 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0);
1708 }
1709
ngbe_enable_rx(struct ngbe_hw * hw)1710 void ngbe_enable_rx(struct ngbe_hw *hw)
1711 {
1712 u32 pfdtxgswc;
1713
1714 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA);
1715 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA);
1716
1717 if (hw->mac.set_lben) {
1718 pfdtxgswc = rd32(hw, NGBE_PSRCTL);
1719 pfdtxgswc |= NGBE_PSRCTL_LBENA;
1720 wr32(hw, NGBE_PSRCTL, pfdtxgswc);
1721 hw->mac.set_lben = false;
1722 }
1723 }
1724
1725 /**
1726 * ngbe_set_mac_type - Sets MAC type
1727 * @hw: pointer to the HW structure
1728 *
1729 * This function sets the mac type of the adapter based on the
1730 * vendor ID and device ID stored in the hw structure.
1731 **/
ngbe_set_mac_type(struct ngbe_hw * hw)1732 s32 ngbe_set_mac_type(struct ngbe_hw *hw)
1733 {
1734 s32 err = 0;
1735
1736 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1737 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1738 return NGBE_ERR_DEVICE_NOT_SUPPORTED;
1739 }
1740
1741 switch (hw->sub_device_id) {
1742 case NGBE_SUB_DEV_ID_EM_RTL_SGMII:
1743 case NGBE_SUB_DEV_ID_EM_MVL_RGMII:
1744 hw->phy.media_type = ngbe_media_type_copper;
1745 hw->mac.type = ngbe_mac_em;
1746 hw->mac.link_type = ngbe_link_copper;
1747 break;
1748 case NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP:
1749 hw->phy.media_type = ngbe_media_type_copper;
1750 hw->mac.type = ngbe_mac_em;
1751 hw->mac.link_type = ngbe_link_fiber;
1752 break;
1753 case NGBE_SUB_DEV_ID_EM_MVL_SFP:
1754 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP:
1755 hw->phy.media_type = ngbe_media_type_fiber;
1756 hw->mac.type = ngbe_mac_em;
1757 hw->mac.link_type = ngbe_link_fiber;
1758 break;
1759 case NGBE_SUB_DEV_ID_EM_MVL_MIX:
1760 hw->phy.media_type = ngbe_media_type_unknown;
1761 hw->mac.type = ngbe_mac_em;
1762 hw->mac.link_type = ngbe_link_type_unknown;
1763 break;
1764 case NGBE_SUB_DEV_ID_EM_VF:
1765 hw->phy.media_type = ngbe_media_type_virtual;
1766 hw->mac.type = ngbe_mac_em_vf;
1767 break;
1768 default:
1769 err = NGBE_ERR_DEVICE_NOT_SUPPORTED;
1770 hw->phy.media_type = ngbe_media_type_unknown;
1771 hw->mac.type = ngbe_mac_unknown;
1772 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1773 break;
1774 }
1775
1776 DEBUGOUT("found mac: %d media: %d, returns: %d",
1777 hw->mac.type, hw->phy.media_type, err);
1778 return err;
1779 }
1780
1781 /**
1782 * ngbe_enable_rx_dma - Enable the Rx DMA unit
1783 * @hw: pointer to hardware structure
1784 * @regval: register value to write to RXCTRL
1785 *
1786 * Enables the Rx DMA unit
1787 **/
ngbe_enable_rx_dma(struct ngbe_hw * hw,u32 regval)1788 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
1789 {
1790 /*
1791 * Workaround silicon errata when enabling the Rx datapath.
1792 * If traffic is incoming before we enable the Rx unit, it could hang
1793 * the Rx DMA unit. Therefore, make sure the security engine is
1794 * completely disabled prior to enabling the Rx unit.
1795 */
1796 hw->mac.disable_sec_rx_path(hw);
1797
1798 if (regval & NGBE_PBRXCTL_ENA)
1799 ngbe_enable_rx(hw);
1800 else
1801 ngbe_disable_rx(hw);
1802
1803 hw->mac.enable_sec_rx_path(hw);
1804
1805 return 0;
1806 }
1807
ngbe_map_device_id(struct ngbe_hw * hw)1808 void ngbe_map_device_id(struct ngbe_hw *hw)
1809 {
1810 u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
1811
1812 hw->is_pf = true;
1813
1814 /* move subsystem_device_id to device_id */
1815 switch (hw->device_id) {
1816 case NGBE_DEV_ID_EM_WX1860AL_W_VF:
1817 case NGBE_DEV_ID_EM_WX1860A2_VF:
1818 case NGBE_DEV_ID_EM_WX1860A2S_VF:
1819 case NGBE_DEV_ID_EM_WX1860A4_VF:
1820 case NGBE_DEV_ID_EM_WX1860A4S_VF:
1821 case NGBE_DEV_ID_EM_WX1860AL2_VF:
1822 case NGBE_DEV_ID_EM_WX1860AL2S_VF:
1823 case NGBE_DEV_ID_EM_WX1860AL4_VF:
1824 case NGBE_DEV_ID_EM_WX1860AL4S_VF:
1825 case NGBE_DEV_ID_EM_WX1860NCSI_VF:
1826 case NGBE_DEV_ID_EM_WX1860A1_VF:
1827 case NGBE_DEV_ID_EM_WX1860A1L_VF:
1828 hw->device_id = NGBE_DEV_ID_EM_VF;
1829 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF;
1830 hw->is_pf = false;
1831 break;
1832 case NGBE_DEV_ID_EM_WX1860AL_W:
1833 case NGBE_DEV_ID_EM_WX1860A2:
1834 case NGBE_DEV_ID_EM_WX1860A2S:
1835 case NGBE_DEV_ID_EM_WX1860A4:
1836 case NGBE_DEV_ID_EM_WX1860A4S:
1837 case NGBE_DEV_ID_EM_WX1860AL2:
1838 case NGBE_DEV_ID_EM_WX1860AL2S:
1839 case NGBE_DEV_ID_EM_WX1860AL4:
1840 case NGBE_DEV_ID_EM_WX1860AL4S:
1841 case NGBE_DEV_ID_EM_WX1860NCSI:
1842 case NGBE_DEV_ID_EM_WX1860A1:
1843 case NGBE_DEV_ID_EM_WX1860A1L:
1844 hw->device_id = NGBE_DEV_ID_EM;
1845 if (oem == NGBE_M88E1512_SFP || oem == NGBE_LY_M88E1512_SFP)
1846 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP;
1847 else if (oem == NGBE_M88E1512_RJ45 ||
1848 (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45))
1849 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII;
1850 else if (oem == NGBE_M88E1512_MIX)
1851 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_MIX;
1852 else if (oem == NGBE_YT8521S_SFP ||
1853 oem == NGBE_YT8521S_SFP_GPIO ||
1854 oem == NGBE_LY_YT8521S_SFP)
1855 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP;
1856 else if (oem == NGBE_INTERNAL_YT8521S_SFP ||
1857 oem == NGBE_INTERNAL_YT8521S_SFP_GPIO)
1858 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP;
1859 else
1860 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII;
1861 break;
1862 default:
1863 break;
1864 }
1865
1866 if (oem == NGBE_LY_M88E1512_SFP || oem == NGBE_YT8521S_SFP_GPIO ||
1867 oem == NGBE_INTERNAL_YT8521S_SFP_GPIO ||
1868 oem == NGBE_LY_YT8521S_SFP)
1869 hw->gpio_ctl = true;
1870 }
1871
1872 /**
1873 * ngbe_init_ops_pf - Inits func ptrs and MAC type
1874 * @hw: pointer to hardware structure
1875 *
1876 * Initialize the function pointers and assign the MAC type.
1877 * Does not touch the hardware.
1878 **/
ngbe_init_ops_pf(struct ngbe_hw * hw)1879 s32 ngbe_init_ops_pf(struct ngbe_hw *hw)
1880 {
1881 struct ngbe_bus_info *bus = &hw->bus;
1882 struct ngbe_mac_info *mac = &hw->mac;
1883 struct ngbe_phy_info *phy = &hw->phy;
1884 struct ngbe_rom_info *rom = &hw->rom;
1885 struct ngbe_mbx_info *mbx = &hw->mbx;
1886
1887 /* BUS */
1888 bus->set_lan_id = ngbe_set_lan_id_multi_port;
1889
1890 /* PHY */
1891 phy->identify = ngbe_identify_phy;
1892 phy->read_reg = ngbe_read_phy_reg;
1893 phy->write_reg = ngbe_write_phy_reg;
1894 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi;
1895 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi;
1896 phy->reset_hw = ngbe_reset_phy;
1897 phy->led_oem_chk = ngbe_phy_led_oem_chk;
1898
1899 /* MAC */
1900 mac->init_hw = ngbe_init_hw;
1901 mac->reset_hw = ngbe_reset_hw_em;
1902 mac->start_hw = ngbe_start_hw;
1903 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs;
1904 mac->enable_rx_dma = ngbe_enable_rx_dma;
1905 mac->get_mac_addr = ngbe_get_mac_addr;
1906 mac->stop_hw = ngbe_stop_hw;
1907 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync;
1908 mac->release_swfw_sync = ngbe_release_swfw_sync;
1909
1910 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path;
1911 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path;
1912
1913 /* LEDs */
1914 mac->led_on = ngbe_led_on;
1915 mac->led_off = ngbe_led_off;
1916
1917 /* RAR, VLAN, Multicast */
1918 mac->set_rar = ngbe_set_rar;
1919 mac->clear_rar = ngbe_clear_rar;
1920 mac->init_rx_addrs = ngbe_init_rx_addrs;
1921 mac->update_mc_addr_list = ngbe_update_mc_addr_list;
1922 mac->set_vmdq = ngbe_set_vmdq;
1923 mac->clear_vmdq = ngbe_clear_vmdq;
1924 mac->set_vfta = ngbe_set_vfta;
1925 mac->set_vlvf = ngbe_set_vlvf;
1926 mac->clear_vfta = ngbe_clear_vfta;
1927 mac->set_mac_anti_spoofing = ngbe_set_mac_anti_spoofing;
1928 mac->set_vlan_anti_spoofing = ngbe_set_vlan_anti_spoofing;
1929
1930 /* Flow Control */
1931 mac->fc_enable = ngbe_fc_enable;
1932 mac->fc_autoneg = ngbe_fc_autoneg;
1933 mac->setup_fc = ngbe_setup_fc_em;
1934
1935 /* Link */
1936 mac->get_link_capabilities = ngbe_get_link_capabilities_em;
1937 mac->check_link = ngbe_check_mac_link_em;
1938 mac->setup_link = ngbe_setup_mac_link_em;
1939
1940 mac->setup_pba = ngbe_set_pba;
1941
1942 /* Manageability interface */
1943 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;
1944 mac->check_overtemp = ngbe_mac_check_overtemp;
1945
1946 mbx->init_params = ngbe_init_mbx_params_pf;
1947 mbx->read = ngbe_read_mbx_pf;
1948 mbx->write = ngbe_write_mbx_pf;
1949 mbx->check_for_msg = ngbe_check_for_msg_pf;
1950 mbx->check_for_ack = ngbe_check_for_ack_pf;
1951 mbx->check_for_rst = ngbe_check_for_rst_pf;
1952
1953 /* EEPROM */
1954 rom->init_params = ngbe_init_eeprom_params;
1955 rom->readw_buffer = ngbe_ee_readw_buffer;
1956 rom->read32 = ngbe_ee_read32;
1957 rom->writew_buffer = ngbe_ee_writew_buffer;
1958 rom->validate_checksum = ngbe_validate_eeprom_checksum_em;
1959
1960 mac->mcft_size = NGBE_EM_MC_TBL_SIZE;
1961 mac->vft_size = NGBE_EM_VFT_TBL_SIZE;
1962 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES;
1963 mac->rx_pb_size = NGBE_EM_RX_PB_SIZE;
1964 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES;
1965 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES;
1966
1967 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL |
1968 NGBE_LINK_SPEED_100M_FULL |
1969 NGBE_LINK_SPEED_1GB_FULL;
1970
1971 return 0;
1972 }
1973
1974 /**
1975 * ngbe_init_shared_code - Initialize the shared code
1976 * @hw: pointer to hardware structure
1977 *
1978 * This will assign function pointers and assign the MAC type and PHY code.
1979 * Does not touch the hardware. This function must be called prior to any
1980 * other function in the shared code. The ngbe_hw structure should be
1981 * memset to 0 prior to calling this function. The following fields in
1982 * hw structure should be filled in prior to calling this function:
1983 * hw_addr, back, device_id, vendor_id, subsystem_device_id
1984 **/
ngbe_init_shared_code(struct ngbe_hw * hw)1985 s32 ngbe_init_shared_code(struct ngbe_hw *hw)
1986 {
1987 s32 status = 0;
1988
1989 /*
1990 * Set the mac type
1991 */
1992 ngbe_set_mac_type(hw);
1993
1994 ngbe_init_ops_dummy(hw);
1995 switch (hw->mac.type) {
1996 case ngbe_mac_em:
1997 ngbe_init_ops_pf(hw);
1998 break;
1999 default:
2000 status = NGBE_ERR_DEVICE_NOT_SUPPORTED;
2001 break;
2002 }
2003 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME;
2004
2005 hw->bus.set_lan_id(hw);
2006
2007 return status;
2008 }
2009
2010