1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
4 * All rights reserved.
5 */
6
7 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_kvargs.h>
10 #include <rte_log.h>
11 #include <rte_malloc.h>
12 #include <rte_bus_vdev.h>
13
14 #include <fcntl.h>
15 #include <linux/ethtool.h>
16 #include <linux/sockios.h>
17 #include <net/if.h>
18 #include <net/if_arp.h>
19 #include <sys/ioctl.h>
20 #include <sys/socket.h>
21 #include <sys/stat.h>
22 #include <sys/types.h>
23
24 #include <rte_mvep_common.h>
25 #include "mrvl_ethdev.h"
26 #include "mrvl_qos.h"
27 #include "mrvl_flow.h"
28 #include "mrvl_mtr.h"
29 #include "mrvl_tm.h"
30
31 /* bitmask with reserved hifs */
32 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
33 /* bitmask with reserved bpools */
34 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
35 /* bitmask with reserved kernel RSS tables */
36 #define MRVL_MUSDK_RSS_RESERVED 0x01
37 /* maximum number of available hifs */
38 #define MRVL_MUSDK_HIFS_MAX 9
39
40 /* prefetch shift */
41 #define MRVL_MUSDK_PREFETCH_SHIFT 2
42
43 /* TCAM has 25 entries reserved for uc/mc filter entries */
44 #define MRVL_MAC_ADDRS_MAX 25
45 #define MRVL_MATCH_LEN 16
46 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
47 /* Maximum allowable packet size */
48 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
49
50 #define MRVL_IFACE_NAME_ARG "iface"
51 #define MRVL_CFG_ARG "cfg"
52
53 #define MRVL_BURST_SIZE 64
54
55 #define MRVL_ARP_LENGTH 28
56
57 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
58 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
59
60 /** Port Rx offload capabilities */
61 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
62 DEV_RX_OFFLOAD_JUMBO_FRAME | \
63 DEV_RX_OFFLOAD_CHECKSUM)
64
65 /** Port Tx offloads capabilities */
66 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
67 DEV_TX_OFFLOAD_UDP_CKSUM | \
68 DEV_TX_OFFLOAD_TCP_CKSUM | \
69 DEV_TX_OFFLOAD_MULTI_SEGS)
70
71 static const char * const valid_args[] = {
72 MRVL_IFACE_NAME_ARG,
73 MRVL_CFG_ARG,
74 NULL
75 };
76
77 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
78 static struct pp2_hif *hifs[RTE_MAX_LCORE];
79 static int used_bpools[PP2_NUM_PKT_PROC] = {
80 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
81 };
82
83 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
84 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
85 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
86
87 struct mrvl_ifnames {
88 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
89 int idx;
90 };
91
92 /*
93 * To use buffer harvesting based on loopback port shadow queue structure
94 * was introduced for buffers information bookkeeping.
95 *
96 * Before sending the packet, related buffer information (pp2_buff_inf) is
97 * stored in shadow queue. After packet is transmitted no longer used
98 * packet buffer is released back to it's original hardware pool,
99 * on condition it originated from interface.
100 * In case it was generated by application itself i.e: mbuf->port field is
101 * 0xff then its released to software mempool.
102 */
103 struct mrvl_shadow_txq {
104 int head; /* write index - used when sending buffers */
105 int tail; /* read index - used when releasing buffers */
106 u16 size; /* queue occupied size */
107 u16 num_to_release; /* number of descriptors sent, that can be
108 * released
109 */
110 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
111 };
112
113 struct mrvl_rxq {
114 struct mrvl_priv *priv;
115 struct rte_mempool *mp;
116 int queue_id;
117 int port_id;
118 int cksum_enabled;
119 uint64_t bytes_recv;
120 uint64_t drop_mac;
121 };
122
123 struct mrvl_txq {
124 struct mrvl_priv *priv;
125 int queue_id;
126 int port_id;
127 uint64_t bytes_sent;
128 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
129 int tx_deferred_start;
130 };
131
132 static int mrvl_lcore_first;
133 static int mrvl_lcore_last;
134 static int mrvl_dev_num;
135
136 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
137 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
138 struct pp2_hif *hif, unsigned int core_id,
139 struct mrvl_shadow_txq *sq, int qid, int force);
140
141 static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
142 uint16_t nb_pkts);
143 static uint16_t mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
144 uint16_t nb_pkts);
145 static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev);
146 static void mrvl_deinit_pp2(void);
147 static void mrvl_deinit_hifs(void);
148
149
150 #define MRVL_XSTATS_TBL_ENTRY(name) { \
151 #name, offsetof(struct pp2_ppio_statistics, name), \
152 sizeof(((struct pp2_ppio_statistics *)0)->name) \
153 }
154
155 /* Table with xstats data */
156 static struct {
157 const char *name;
158 unsigned int offset;
159 unsigned int size;
160 } mrvl_xstats_tbl[] = {
161 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
162 MRVL_XSTATS_TBL_ENTRY(rx_packets),
163 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
164 MRVL_XSTATS_TBL_ENTRY(rx_errors),
165 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
168 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
169 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
170 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
171 MRVL_XSTATS_TBL_ENTRY(tx_packets),
172 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
173 MRVL_XSTATS_TBL_ENTRY(tx_errors)
174 };
175
176 static inline void
mrvl_fill_shadowq(struct mrvl_shadow_txq * sq,struct rte_mbuf * buf)177 mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
178 {
179 sq->ent[sq->head].buff.cookie = (uint64_t)buf;
180 sq->ent[sq->head].buff.addr = buf ?
181 rte_mbuf_data_iova_default(buf) : 0;
182
183 sq->ent[sq->head].bpool =
184 (unlikely(!buf || buf->port >= RTE_MAX_ETHPORTS ||
185 buf->refcnt > 1)) ? NULL :
186 mrvl_port_to_bpool_lookup[buf->port];
187
188 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
189 sq->size++;
190 }
191
192 static inline void
mrvl_fill_desc(struct pp2_ppio_desc * desc,struct rte_mbuf * buf)193 mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
194 {
195 pp2_ppio_outq_desc_reset(desc);
196 pp2_ppio_outq_desc_set_phys_addr(desc, rte_pktmbuf_iova(buf));
197 pp2_ppio_outq_desc_set_pkt_offset(desc, 0);
198 pp2_ppio_outq_desc_set_pkt_len(desc, rte_pktmbuf_data_len(buf));
199 }
200
201 static inline int
mrvl_get_bpool_size(int pp2_id,int pool_id)202 mrvl_get_bpool_size(int pp2_id, int pool_id)
203 {
204 int i;
205 int size = 0;
206
207 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
208 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
209
210 return size;
211 }
212
213 static inline int
mrvl_reserve_bit(int * bitmap,int max)214 mrvl_reserve_bit(int *bitmap, int max)
215 {
216 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
217
218 if (n >= max)
219 return -1;
220
221 *bitmap |= 1 << n;
222
223 return n;
224 }
225
226 static int
mrvl_init_hif(int core_id)227 mrvl_init_hif(int core_id)
228 {
229 struct pp2_hif_params params;
230 char match[MRVL_MATCH_LEN];
231 int ret;
232
233 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
234 if (ret < 0) {
235 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
236 return ret;
237 }
238
239 snprintf(match, sizeof(match), "hif-%d", ret);
240 memset(¶ms, 0, sizeof(params));
241 params.match = match;
242 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
243 ret = pp2_hif_init(¶ms, &hifs[core_id]);
244 if (ret) {
245 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
246 return ret;
247 }
248
249 return 0;
250 }
251
252 static inline struct pp2_hif*
mrvl_get_hif(struct mrvl_priv * priv,int core_id)253 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
254 {
255 int ret;
256
257 if (likely(hifs[core_id] != NULL))
258 return hifs[core_id];
259
260 rte_spinlock_lock(&priv->lock);
261
262 ret = mrvl_init_hif(core_id);
263 if (ret < 0) {
264 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
265 goto out;
266 }
267
268 if (core_id < mrvl_lcore_first)
269 mrvl_lcore_first = core_id;
270
271 if (core_id > mrvl_lcore_last)
272 mrvl_lcore_last = core_id;
273 out:
274 rte_spinlock_unlock(&priv->lock);
275
276 return hifs[core_id];
277 }
278
279 /**
280 * Set tx burst function according to offload flag
281 *
282 * @param dev
283 * Pointer to Ethernet device structure.
284 */
285 static void
mrvl_set_tx_function(struct rte_eth_dev * dev)286 mrvl_set_tx_function(struct rte_eth_dev *dev)
287 {
288 struct mrvl_priv *priv = dev->data->dev_private;
289
290 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
291 if (priv->multiseg) {
292 RTE_LOG(INFO, PMD, "Using multi-segment tx callback\n");
293 dev->tx_pkt_burst = mrvl_tx_sg_pkt_burst;
294 } else {
295 RTE_LOG(INFO, PMD, "Using single-segment tx callback\n");
296 dev->tx_pkt_burst = mrvl_tx_pkt_burst;
297 }
298 }
299
300 /**
301 * Configure rss based on dpdk rss configuration.
302 *
303 * @param priv
304 * Pointer to private structure.
305 * @param rss_conf
306 * Pointer to RSS configuration.
307 *
308 * @return
309 * 0 on success, negative error value otherwise.
310 */
311 static int
mrvl_configure_rss(struct mrvl_priv * priv,struct rte_eth_rss_conf * rss_conf)312 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
313 {
314 if (rss_conf->rss_key)
315 MRVL_LOG(WARNING, "Changing hash key is not supported");
316
317 if (rss_conf->rss_hf == 0) {
318 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
319 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
320 priv->ppio_params.inqs_params.hash_type =
321 PP2_PPIO_HASH_T_2_TUPLE;
322 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
323 priv->ppio_params.inqs_params.hash_type =
324 PP2_PPIO_HASH_T_5_TUPLE;
325 priv->rss_hf_tcp = 1;
326 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
327 priv->ppio_params.inqs_params.hash_type =
328 PP2_PPIO_HASH_T_5_TUPLE;
329 priv->rss_hf_tcp = 0;
330 } else {
331 return -EINVAL;
332 }
333
334 return 0;
335 }
336
337 /**
338 * Ethernet device configuration.
339 *
340 * Prepare the driver for a given number of TX and RX queues and
341 * configure RSS.
342 *
343 * @param dev
344 * Pointer to Ethernet device structure.
345 *
346 * @return
347 * 0 on success, negative error value otherwise.
348 */
349 static int
mrvl_dev_configure(struct rte_eth_dev * dev)350 mrvl_dev_configure(struct rte_eth_dev *dev)
351 {
352 struct mrvl_priv *priv = dev->data->dev_private;
353 int ret;
354
355 if (priv->ppio) {
356 MRVL_LOG(INFO, "Device reconfiguration is not supported");
357 return -EINVAL;
358 }
359
360 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
361 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
362 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
363 dev->data->dev_conf.rxmode.mq_mode);
364 return -EINVAL;
365 }
366
367 if (dev->data->dev_conf.rxmode.split_hdr_size) {
368 MRVL_LOG(INFO, "Split headers not supported");
369 return -EINVAL;
370 }
371
372 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
373 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
374 MRVL_PP2_ETH_HDRS_LEN;
375
376 if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
377 priv->multiseg = 1;
378
379 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
380 dev->data->nb_rx_queues);
381 if (ret < 0)
382 return ret;
383
384 ret = mrvl_configure_txqs(priv, dev->data->port_id,
385 dev->data->nb_tx_queues);
386 if (ret < 0)
387 return ret;
388
389 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
390 priv->ppio_params.maintain_stats = 1;
391 priv->nb_rx_queues = dev->data->nb_rx_queues;
392
393 ret = mrvl_tm_init(dev);
394 if (ret < 0)
395 return ret;
396
397 if (dev->data->nb_rx_queues == 1 &&
398 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
399 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
400 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
401
402 return 0;
403 }
404
405 return mrvl_configure_rss(priv,
406 &dev->data->dev_conf.rx_adv_conf.rss_conf);
407 }
408
409 /**
410 * DPDK callback to change the MTU.
411 *
412 * Setting the MTU affects hardware MRU (packets larger than the MRU
413 * will be dropped).
414 *
415 * @param dev
416 * Pointer to Ethernet device structure.
417 * @param mtu
418 * New MTU.
419 *
420 * @return
421 * 0 on success, negative error value otherwise.
422 */
423 static int
mrvl_mtu_set(struct rte_eth_dev * dev,uint16_t mtu)424 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
425 {
426 struct mrvl_priv *priv = dev->data->dev_private;
427 uint16_t mru;
428 uint16_t mbuf_data_size = 0; /* SW buffer size */
429 int ret;
430
431 mru = MRVL_PP2_MTU_TO_MRU(mtu);
432 /*
433 * min_rx_buf_size is equal to mbuf data size
434 * if pmd didn't set it differently
435 */
436 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
437 /* Prevent PMD from:
438 * - setting mru greater than the mbuf size resulting in
439 * hw and sw buffer size mismatch
440 * - setting mtu that requires the support of scattered packets
441 * when this feature has not been enabled/supported so far
442 * (TODO check scattered_rx flag here once scattered RX is supported).
443 */
444 if (mru + MRVL_PKT_OFFS > mbuf_data_size) {
445 mru = mbuf_data_size - MRVL_PKT_OFFS;
446 mtu = MRVL_PP2_MRU_TO_MTU(mru);
447 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
448 "by current mbuf size: %u. Set MTU to %u, MRU to %u",
449 mbuf_data_size, mtu, mru);
450 }
451
452 if (mtu < RTE_ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
453 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
454 return -EINVAL;
455 }
456
457 dev->data->mtu = mtu;
458 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
459
460 if (!priv->ppio)
461 return 0;
462
463 ret = pp2_ppio_set_mru(priv->ppio, mru);
464 if (ret) {
465 MRVL_LOG(ERR, "Failed to change MRU");
466 return ret;
467 }
468
469 ret = pp2_ppio_set_mtu(priv->ppio, mtu);
470 if (ret) {
471 MRVL_LOG(ERR, "Failed to change MTU");
472 return ret;
473 }
474
475 return 0;
476 }
477
478 /**
479 * DPDK callback to bring the link up.
480 *
481 * @param dev
482 * Pointer to Ethernet device structure.
483 *
484 * @return
485 * 0 on success, negative error value otherwise.
486 */
487 static int
mrvl_dev_set_link_up(struct rte_eth_dev * dev)488 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
489 {
490 struct mrvl_priv *priv = dev->data->dev_private;
491 int ret;
492
493 if (!priv->ppio)
494 return -EPERM;
495
496 ret = pp2_ppio_enable(priv->ppio);
497 if (ret)
498 return ret;
499
500 /*
501 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
502 * as pp2_ppio_enable() changes port->t_mode from default 0 to
503 * PP2_TRAFFIC_INGRESS_EGRESS.
504 *
505 * Set mtu to default DPDK value here.
506 */
507 ret = mrvl_mtu_set(dev, dev->data->mtu);
508 if (ret)
509 pp2_ppio_disable(priv->ppio);
510
511 return ret;
512 }
513
514 /**
515 * DPDK callback to bring the link down.
516 *
517 * @param dev
518 * Pointer to Ethernet device structure.
519 *
520 * @return
521 * 0 on success, negative error value otherwise.
522 */
523 static int
mrvl_dev_set_link_down(struct rte_eth_dev * dev)524 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
525 {
526 struct mrvl_priv *priv = dev->data->dev_private;
527
528 if (!priv->ppio)
529 return -EPERM;
530
531 return pp2_ppio_disable(priv->ppio);
532 }
533
534 /**
535 * DPDK callback to start tx queue.
536 *
537 * @param dev
538 * Pointer to Ethernet device structure.
539 * @param queue_id
540 * Transmit queue index.
541 *
542 * @return
543 * 0 on success, negative error value otherwise.
544 */
545 static int
mrvl_tx_queue_start(struct rte_eth_dev * dev,uint16_t queue_id)546 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
547 {
548 struct mrvl_priv *priv = dev->data->dev_private;
549 int ret;
550
551 if (!priv)
552 return -EPERM;
553
554 /* passing 1 enables given tx queue */
555 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
556 if (ret) {
557 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
558 return ret;
559 }
560
561 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
562
563 return 0;
564 }
565
566 /**
567 * DPDK callback to stop tx queue.
568 *
569 * @param dev
570 * Pointer to Ethernet device structure.
571 * @param queue_id
572 * Transmit queue index.
573 *
574 * @return
575 * 0 on success, negative error value otherwise.
576 */
577 static int
mrvl_tx_queue_stop(struct rte_eth_dev * dev,uint16_t queue_id)578 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
579 {
580 struct mrvl_priv *priv = dev->data->dev_private;
581 int ret;
582
583 if (!priv->ppio)
584 return -EPERM;
585
586 /* passing 0 disables given tx queue */
587 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
588 if (ret) {
589 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
590 return ret;
591 }
592
593 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
594
595 return 0;
596 }
597
598 /**
599 * DPDK callback to start the device.
600 *
601 * @param dev
602 * Pointer to Ethernet device structure.
603 *
604 * @return
605 * 0 on success, negative errno value on failure.
606 */
607 static int
mrvl_dev_start(struct rte_eth_dev * dev)608 mrvl_dev_start(struct rte_eth_dev *dev)
609 {
610 struct mrvl_priv *priv = dev->data->dev_private;
611 char match[MRVL_MATCH_LEN];
612 int ret = 0, i, def_init_size;
613
614 if (priv->ppio)
615 return mrvl_dev_set_link_up(dev);
616
617 snprintf(match, sizeof(match), "ppio-%d:%d",
618 priv->pp_id, priv->ppio_id);
619 priv->ppio_params.match = match;
620
621 /*
622 * Calculate the minimum bpool size for refill feature as follows:
623 * 2 default burst sizes multiply by number of rx queues.
624 * If the bpool size will be below this value, new buffers will
625 * be added to the pool.
626 */
627 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
628
629 /* In case initial bpool size configured in queues setup is
630 * smaller than minimum size add more buffers
631 */
632 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
633 if (priv->bpool_init_size < def_init_size) {
634 int buffs_to_add = def_init_size - priv->bpool_init_size;
635
636 priv->bpool_init_size += buffs_to_add;
637 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
638 if (ret)
639 MRVL_LOG(ERR, "Failed to add buffers to bpool");
640 }
641
642 /*
643 * Calculate the maximum bpool size for refill feature as follows:
644 * maximum number of descriptors in rx queue multiply by number
645 * of rx queues plus minimum bpool size.
646 * In case the bpool size will exceed this value, superfluous buffers
647 * will be removed
648 */
649 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
650 priv->bpool_min_size;
651
652 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
653 if (ret) {
654 MRVL_LOG(ERR, "Failed to init ppio");
655 return ret;
656 }
657
658 /*
659 * In case there are some some stale uc/mc mac addresses flush them
660 * here. It cannot be done during mrvl_dev_close() as port information
661 * is already gone at that point (due to pp2_ppio_deinit() in
662 * mrvl_dev_stop()).
663 */
664 if (!priv->uc_mc_flushed) {
665 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
666 if (ret) {
667 MRVL_LOG(ERR,
668 "Failed to flush uc/mc filter list");
669 goto out;
670 }
671 priv->uc_mc_flushed = 1;
672 }
673
674 if (!priv->vlan_flushed) {
675 ret = pp2_ppio_flush_vlan(priv->ppio);
676 if (ret) {
677 MRVL_LOG(ERR, "Failed to flush vlan list");
678 /*
679 * TODO
680 * once pp2_ppio_flush_vlan() is supported jump to out
681 * goto out;
682 */
683 }
684 priv->vlan_flushed = 1;
685 }
686 ret = mrvl_mtu_set(dev, dev->data->mtu);
687 if (ret)
688 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
689
690 /* For default QoS config, don't start classifier. */
691 if (mrvl_qos_cfg &&
692 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
693 ret = mrvl_start_qos_mapping(priv);
694 if (ret) {
695 MRVL_LOG(ERR, "Failed to setup QoS mapping");
696 goto out;
697 }
698 }
699
700 ret = mrvl_dev_set_link_up(dev);
701 if (ret) {
702 MRVL_LOG(ERR, "Failed to set link up");
703 goto out;
704 }
705
706 /* start tx queues */
707 for (i = 0; i < dev->data->nb_tx_queues; i++) {
708 struct mrvl_txq *txq = dev->data->tx_queues[i];
709
710 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
711
712 if (!txq->tx_deferred_start)
713 continue;
714
715 /*
716 * All txqs are started by default. Stop them
717 * so that tx_deferred_start works as expected.
718 */
719 ret = mrvl_tx_queue_stop(dev, i);
720 if (ret)
721 goto out;
722 }
723
724 mrvl_flow_init(dev);
725 mrvl_mtr_init(dev);
726 mrvl_set_tx_function(dev);
727
728 return 0;
729 out:
730 MRVL_LOG(ERR, "Failed to start device");
731 pp2_ppio_deinit(priv->ppio);
732 return ret;
733 }
734
735 /**
736 * Flush receive queues.
737 *
738 * @param dev
739 * Pointer to Ethernet device structure.
740 */
741 static void
mrvl_flush_rx_queues(struct rte_eth_dev * dev)742 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
743 {
744 int i;
745
746 MRVL_LOG(INFO, "Flushing rx queues");
747 for (i = 0; i < dev->data->nb_rx_queues; i++) {
748 int ret, num;
749
750 do {
751 struct mrvl_rxq *q = dev->data->rx_queues[i];
752 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
753
754 num = MRVL_PP2_RXD_MAX;
755 ret = pp2_ppio_recv(q->priv->ppio,
756 q->priv->rxq_map[q->queue_id].tc,
757 q->priv->rxq_map[q->queue_id].inq,
758 descs, (uint16_t *)&num);
759 } while (ret == 0 && num);
760 }
761 }
762
763 /**
764 * Flush transmit shadow queues.
765 *
766 * @param dev
767 * Pointer to Ethernet device structure.
768 */
769 static void
mrvl_flush_tx_shadow_queues(struct rte_eth_dev * dev)770 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
771 {
772 int i, j;
773 struct mrvl_txq *txq;
774
775 MRVL_LOG(INFO, "Flushing tx shadow queues");
776 for (i = 0; i < dev->data->nb_tx_queues; i++) {
777 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
778
779 for (j = 0; j < RTE_MAX_LCORE; j++) {
780 struct mrvl_shadow_txq *sq;
781
782 if (!hifs[j])
783 continue;
784
785 sq = &txq->shadow_txqs[j];
786 mrvl_free_sent_buffers(txq->priv->ppio,
787 hifs[j], j, sq, txq->queue_id, 1);
788 while (sq->tail != sq->head) {
789 uint64_t addr = cookie_addr_high |
790 sq->ent[sq->tail].buff.cookie;
791 rte_pktmbuf_free(
792 (struct rte_mbuf *)addr);
793 sq->tail = (sq->tail + 1) &
794 MRVL_PP2_TX_SHADOWQ_MASK;
795 }
796 memset(sq, 0, sizeof(*sq));
797 }
798 }
799 }
800
801 /**
802 * Flush hardware bpool (buffer-pool).
803 *
804 * @param dev
805 * Pointer to Ethernet device structure.
806 */
807 static void
mrvl_flush_bpool(struct rte_eth_dev * dev)808 mrvl_flush_bpool(struct rte_eth_dev *dev)
809 {
810 struct mrvl_priv *priv = dev->data->dev_private;
811 struct pp2_hif *hif;
812 uint32_t num;
813 int ret;
814 unsigned int core_id = rte_lcore_id();
815
816 if (core_id == LCORE_ID_ANY)
817 core_id = rte_get_main_lcore();
818
819 hif = mrvl_get_hif(priv, core_id);
820
821 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
822 if (ret) {
823 MRVL_LOG(ERR, "Failed to get bpool buffers number");
824 return;
825 }
826
827 while (num--) {
828 struct pp2_buff_inf inf;
829 uint64_t addr;
830
831 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
832 if (ret)
833 break;
834
835 addr = cookie_addr_high | inf.cookie;
836 rte_pktmbuf_free((struct rte_mbuf *)addr);
837 }
838 }
839
840 /**
841 * DPDK callback to stop the device.
842 *
843 * @param dev
844 * Pointer to Ethernet device structure.
845 */
846 static int
mrvl_dev_stop(struct rte_eth_dev * dev)847 mrvl_dev_stop(struct rte_eth_dev *dev)
848 {
849 return mrvl_dev_set_link_down(dev);
850 }
851
852 /**
853 * DPDK callback to close the device.
854 *
855 * @param dev
856 * Pointer to Ethernet device structure.
857 */
858 static int
mrvl_dev_close(struct rte_eth_dev * dev)859 mrvl_dev_close(struct rte_eth_dev *dev)
860 {
861 struct mrvl_priv *priv = dev->data->dev_private;
862 size_t i;
863
864 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
865 return 0;
866
867 mrvl_flush_rx_queues(dev);
868 mrvl_flush_tx_shadow_queues(dev);
869 mrvl_flow_deinit(dev);
870 mrvl_mtr_deinit(dev);
871
872 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
873 struct pp2_ppio_tc_params *tc_params =
874 &priv->ppio_params.inqs_params.tcs_params[i];
875
876 if (tc_params->inqs_params) {
877 rte_free(tc_params->inqs_params);
878 tc_params->inqs_params = NULL;
879 }
880 }
881
882 if (priv->cls_tbl) {
883 pp2_cls_tbl_deinit(priv->cls_tbl);
884 priv->cls_tbl = NULL;
885 }
886
887 if (priv->qos_tbl) {
888 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
889 priv->qos_tbl = NULL;
890 }
891
892 mrvl_flush_bpool(dev);
893 mrvl_tm_deinit(dev);
894
895 if (priv->ppio) {
896 pp2_ppio_deinit(priv->ppio);
897 priv->ppio = NULL;
898 }
899
900 /* policer must be released after ppio deinitialization */
901 if (priv->default_policer) {
902 pp2_cls_plcr_deinit(priv->default_policer);
903 priv->default_policer = NULL;
904 }
905
906
907 if (priv->bpool) {
908 pp2_bpool_deinit(priv->bpool);
909 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
910 priv->bpool = NULL;
911 }
912
913 mrvl_dev_num--;
914
915 if (mrvl_dev_num == 0) {
916 MRVL_LOG(INFO, "Perform MUSDK deinit");
917 mrvl_deinit_hifs();
918 mrvl_deinit_pp2();
919 rte_mvep_deinit(MVEP_MOD_T_PP2);
920 }
921
922 return 0;
923 }
924
925 /**
926 * DPDK callback to retrieve physical link information.
927 *
928 * @param dev
929 * Pointer to Ethernet device structure.
930 * @param wait_to_complete
931 * Wait for request completion (ignored).
932 *
933 * @return
934 * 0 on success, negative error value otherwise.
935 */
936 static int
mrvl_link_update(struct rte_eth_dev * dev,int wait_to_complete __rte_unused)937 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
938 {
939 /*
940 * TODO
941 * once MUSDK provides necessary API use it here
942 */
943 struct mrvl_priv *priv = dev->data->dev_private;
944 struct ethtool_cmd edata;
945 struct ifreq req;
946 int ret, fd, link_up;
947
948 if (!priv->ppio)
949 return -EPERM;
950
951 edata.cmd = ETHTOOL_GSET;
952
953 strcpy(req.ifr_name, dev->data->name);
954 req.ifr_data = (void *)&edata;
955
956 fd = socket(AF_INET, SOCK_DGRAM, 0);
957 if (fd == -1)
958 return -EFAULT;
959
960 ret = ioctl(fd, SIOCETHTOOL, &req);
961 if (ret == -1) {
962 close(fd);
963 return -EFAULT;
964 }
965
966 close(fd);
967
968 switch (ethtool_cmd_speed(&edata)) {
969 case SPEED_10:
970 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
971 break;
972 case SPEED_100:
973 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
974 break;
975 case SPEED_1000:
976 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
977 break;
978 case SPEED_10000:
979 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
980 break;
981 default:
982 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
983 }
984
985 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
986 ETH_LINK_HALF_DUPLEX;
987 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
988 ETH_LINK_FIXED;
989 pp2_ppio_get_link_state(priv->ppio, &link_up);
990 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
991
992 return 0;
993 }
994
995 /**
996 * DPDK callback to enable promiscuous mode.
997 *
998 * @param dev
999 * Pointer to Ethernet device structure.
1000 *
1001 * @return
1002 * 0 on success, negative error value otherwise.
1003 */
1004 static int
mrvl_promiscuous_enable(struct rte_eth_dev * dev)1005 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
1006 {
1007 struct mrvl_priv *priv = dev->data->dev_private;
1008 int ret;
1009
1010 if (!priv->ppio)
1011 return 0;
1012
1013 if (priv->isolated)
1014 return 0;
1015
1016 ret = pp2_ppio_set_promisc(priv->ppio, 1);
1017 if (ret) {
1018 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
1019 return -EAGAIN;
1020 }
1021
1022 return 0;
1023 }
1024
1025 /**
1026 * DPDK callback to enable allmulti mode.
1027 *
1028 * @param dev
1029 * Pointer to Ethernet device structure.
1030 *
1031 * @return
1032 * 0 on success, negative error value otherwise.
1033 */
1034 static int
mrvl_allmulticast_enable(struct rte_eth_dev * dev)1035 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
1036 {
1037 struct mrvl_priv *priv = dev->data->dev_private;
1038 int ret;
1039
1040 if (!priv->ppio)
1041 return 0;
1042
1043 if (priv->isolated)
1044 return 0;
1045
1046 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
1047 if (ret) {
1048 MRVL_LOG(ERR, "Failed enable all-multicast mode");
1049 return -EAGAIN;
1050 }
1051
1052 return 0;
1053 }
1054
1055 /**
1056 * DPDK callback to disable promiscuous mode.
1057 *
1058 * @param dev
1059 * Pointer to Ethernet device structure.
1060 *
1061 * @return
1062 * 0 on success, negative error value otherwise.
1063 */
1064 static int
mrvl_promiscuous_disable(struct rte_eth_dev * dev)1065 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
1066 {
1067 struct mrvl_priv *priv = dev->data->dev_private;
1068 int ret;
1069
1070 if (!priv->ppio)
1071 return 0;
1072
1073 ret = pp2_ppio_set_promisc(priv->ppio, 0);
1074 if (ret) {
1075 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
1076 return -EAGAIN;
1077 }
1078
1079 return 0;
1080 }
1081
1082 /**
1083 * DPDK callback to disable allmulticast mode.
1084 *
1085 * @param dev
1086 * Pointer to Ethernet device structure.
1087 *
1088 * @return
1089 * 0 on success, negative error value otherwise.
1090 */
1091 static int
mrvl_allmulticast_disable(struct rte_eth_dev * dev)1092 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
1093 {
1094 struct mrvl_priv *priv = dev->data->dev_private;
1095 int ret;
1096
1097 if (!priv->ppio)
1098 return 0;
1099
1100 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
1101 if (ret) {
1102 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1103 return -EAGAIN;
1104 }
1105
1106 return 0;
1107 }
1108
1109 /**
1110 * DPDK callback to remove a MAC address.
1111 *
1112 * @param dev
1113 * Pointer to Ethernet device structure.
1114 * @param index
1115 * MAC address index.
1116 */
1117 static void
mrvl_mac_addr_remove(struct rte_eth_dev * dev,uint32_t index)1118 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1119 {
1120 struct mrvl_priv *priv = dev->data->dev_private;
1121 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1122 int ret;
1123
1124 if (!priv->ppio)
1125 return;
1126
1127 if (priv->isolated)
1128 return;
1129
1130 ret = pp2_ppio_remove_mac_addr(priv->ppio,
1131 dev->data->mac_addrs[index].addr_bytes);
1132 if (ret) {
1133 rte_ether_format_addr(buf, sizeof(buf),
1134 &dev->data->mac_addrs[index]);
1135 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1136 }
1137 }
1138
1139 /**
1140 * DPDK callback to add a MAC address.
1141 *
1142 * @param dev
1143 * Pointer to Ethernet device structure.
1144 * @param mac_addr
1145 * MAC address to register.
1146 * @param index
1147 * MAC address index.
1148 * @param vmdq
1149 * VMDq pool index to associate address with (unused).
1150 *
1151 * @return
1152 * 0 on success, negative error value otherwise.
1153 */
1154 static int
mrvl_mac_addr_add(struct rte_eth_dev * dev,struct rte_ether_addr * mac_addr,uint32_t index,uint32_t vmdq __rte_unused)1155 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1156 uint32_t index, uint32_t vmdq __rte_unused)
1157 {
1158 struct mrvl_priv *priv = dev->data->dev_private;
1159 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1160 int ret;
1161
1162 if (priv->isolated)
1163 return -ENOTSUP;
1164
1165 if (index == 0)
1166 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1167 return -1;
1168
1169 if (!priv->ppio)
1170 return 0;
1171
1172 /*
1173 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1174 * parameter uc_filter_max. Maximum number of mc addresses is then
1175 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1176 * 21 respectively.
1177 *
1178 * If more than uc_filter_max uc addresses were added to filter list
1179 * then NIC will switch to promiscuous mode automatically.
1180 *
1181 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1182 * were added to filter list then NIC will switch to all-multicast mode
1183 * automatically.
1184 */
1185 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1186 if (ret) {
1187 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1188 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1189 return -1;
1190 }
1191
1192 return 0;
1193 }
1194
1195 /**
1196 * DPDK callback to set the primary MAC address.
1197 *
1198 * @param dev
1199 * Pointer to Ethernet device structure.
1200 * @param mac_addr
1201 * MAC address to register.
1202 *
1203 * @return
1204 * 0 on success, negative error value otherwise.
1205 */
1206 static int
mrvl_mac_addr_set(struct rte_eth_dev * dev,struct rte_ether_addr * mac_addr)1207 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1208 {
1209 struct mrvl_priv *priv = dev->data->dev_private;
1210 int ret;
1211
1212 if (!priv->ppio)
1213 return 0;
1214
1215 if (priv->isolated)
1216 return -ENOTSUP;
1217
1218 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1219 if (ret) {
1220 char buf[RTE_ETHER_ADDR_FMT_SIZE];
1221 rte_ether_format_addr(buf, sizeof(buf), mac_addr);
1222 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1223 }
1224
1225 return ret;
1226 }
1227
1228 /**
1229 * DPDK callback to get device statistics.
1230 *
1231 * @param dev
1232 * Pointer to Ethernet device structure.
1233 * @param stats
1234 * Stats structure output buffer.
1235 *
1236 * @return
1237 * 0 on success, negative error value otherwise.
1238 */
1239 static int
mrvl_stats_get(struct rte_eth_dev * dev,struct rte_eth_stats * stats)1240 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1241 {
1242 struct mrvl_priv *priv = dev->data->dev_private;
1243 struct pp2_ppio_statistics ppio_stats;
1244 uint64_t drop_mac = 0;
1245 unsigned int i, idx, ret;
1246
1247 if (!priv->ppio)
1248 return -EPERM;
1249
1250 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1251 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1252 struct pp2_ppio_inq_statistics rx_stats;
1253
1254 if (!rxq)
1255 continue;
1256
1257 idx = rxq->queue_id;
1258 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1259 MRVL_LOG(ERR,
1260 "rx queue %d stats out of range (0 - %d)",
1261 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1262 continue;
1263 }
1264
1265 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1266 priv->rxq_map[idx].tc,
1267 priv->rxq_map[idx].inq,
1268 &rx_stats, 0);
1269 if (unlikely(ret)) {
1270 MRVL_LOG(ERR,
1271 "Failed to update rx queue %d stats", idx);
1272 break;
1273 }
1274
1275 stats->q_ibytes[idx] = rxq->bytes_recv;
1276 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1277 stats->q_errors[idx] = rx_stats.drop_early +
1278 rx_stats.drop_fullq +
1279 rx_stats.drop_bm +
1280 rxq->drop_mac;
1281 stats->ibytes += rxq->bytes_recv;
1282 drop_mac += rxq->drop_mac;
1283 }
1284
1285 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1286 struct mrvl_txq *txq = dev->data->tx_queues[i];
1287 struct pp2_ppio_outq_statistics tx_stats;
1288
1289 if (!txq)
1290 continue;
1291
1292 idx = txq->queue_id;
1293 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1294 MRVL_LOG(ERR,
1295 "tx queue %d stats out of range (0 - %d)",
1296 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1297 }
1298
1299 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1300 &tx_stats, 0);
1301 if (unlikely(ret)) {
1302 MRVL_LOG(ERR,
1303 "Failed to update tx queue %d stats", idx);
1304 break;
1305 }
1306
1307 stats->q_opackets[idx] = tx_stats.deq_desc;
1308 stats->q_obytes[idx] = txq->bytes_sent;
1309 stats->obytes += txq->bytes_sent;
1310 }
1311
1312 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1313 if (unlikely(ret)) {
1314 MRVL_LOG(ERR, "Failed to update port statistics");
1315 return ret;
1316 }
1317
1318 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1319 stats->opackets += ppio_stats.tx_packets;
1320 stats->imissed += ppio_stats.rx_fullq_dropped +
1321 ppio_stats.rx_bm_dropped +
1322 ppio_stats.rx_early_dropped +
1323 ppio_stats.rx_fifo_dropped +
1324 ppio_stats.rx_cls_dropped;
1325 stats->ierrors = drop_mac;
1326
1327 return 0;
1328 }
1329
1330 /**
1331 * DPDK callback to clear device statistics.
1332 *
1333 * @param dev
1334 * Pointer to Ethernet device structure.
1335 *
1336 * @return
1337 * 0 on success, negative error value otherwise.
1338 */
1339 static int
mrvl_stats_reset(struct rte_eth_dev * dev)1340 mrvl_stats_reset(struct rte_eth_dev *dev)
1341 {
1342 struct mrvl_priv *priv = dev->data->dev_private;
1343 int i;
1344
1345 if (!priv->ppio)
1346 return 0;
1347
1348 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1349 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1350
1351 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1352 priv->rxq_map[i].inq, NULL, 1);
1353 rxq->bytes_recv = 0;
1354 rxq->drop_mac = 0;
1355 }
1356
1357 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1358 struct mrvl_txq *txq = dev->data->tx_queues[i];
1359
1360 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1361 txq->bytes_sent = 0;
1362 }
1363
1364 return pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1365 }
1366
1367 /**
1368 * DPDK callback to get extended statistics.
1369 *
1370 * @param dev
1371 * Pointer to Ethernet device structure.
1372 * @param stats
1373 * Pointer to xstats table.
1374 * @param n
1375 * Number of entries in xstats table.
1376 * @return
1377 * Negative value on error, number of read xstats otherwise.
1378 */
1379 static int
mrvl_xstats_get(struct rte_eth_dev * dev,struct rte_eth_xstat * stats,unsigned int n)1380 mrvl_xstats_get(struct rte_eth_dev *dev,
1381 struct rte_eth_xstat *stats, unsigned int n)
1382 {
1383 struct mrvl_priv *priv = dev->data->dev_private;
1384 struct pp2_ppio_statistics ppio_stats;
1385 unsigned int i;
1386
1387 if (!stats)
1388 return 0;
1389
1390 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1391 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1392 uint64_t val;
1393
1394 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1395 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1396 mrvl_xstats_tbl[i].offset);
1397 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1398 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1399 mrvl_xstats_tbl[i].offset);
1400 else
1401 return -EINVAL;
1402
1403 stats[i].id = i;
1404 stats[i].value = val;
1405 }
1406
1407 return n;
1408 }
1409
1410 /**
1411 * DPDK callback to reset extended statistics.
1412 *
1413 * @param dev
1414 * Pointer to Ethernet device structure.
1415 *
1416 * @return
1417 * 0 on success, negative error value otherwise.
1418 */
1419 static int
mrvl_xstats_reset(struct rte_eth_dev * dev)1420 mrvl_xstats_reset(struct rte_eth_dev *dev)
1421 {
1422 return mrvl_stats_reset(dev);
1423 }
1424
1425 /**
1426 * DPDK callback to get extended statistics names.
1427 *
1428 * @param dev (unused)
1429 * Pointer to Ethernet device structure.
1430 * @param xstats_names
1431 * Pointer to xstats names table.
1432 * @param size
1433 * Size of the xstats names table.
1434 * @return
1435 * Number of read names.
1436 */
1437 static int
mrvl_xstats_get_names(struct rte_eth_dev * dev __rte_unused,struct rte_eth_xstat_name * xstats_names,unsigned int size)1438 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1439 struct rte_eth_xstat_name *xstats_names,
1440 unsigned int size)
1441 {
1442 unsigned int i;
1443
1444 if (!xstats_names)
1445 return RTE_DIM(mrvl_xstats_tbl);
1446
1447 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1448 strlcpy(xstats_names[i].name, mrvl_xstats_tbl[i].name,
1449 RTE_ETH_XSTATS_NAME_SIZE);
1450
1451 return size;
1452 }
1453
1454 /**
1455 * DPDK callback to get information about the device.
1456 *
1457 * @param dev
1458 * Pointer to Ethernet device structure (unused).
1459 * @param info
1460 * Info structure output buffer.
1461 */
1462 static int
mrvl_dev_infos_get(struct rte_eth_dev * dev __rte_unused,struct rte_eth_dev_info * info)1463 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1464 struct rte_eth_dev_info *info)
1465 {
1466 info->speed_capa = ETH_LINK_SPEED_10M |
1467 ETH_LINK_SPEED_100M |
1468 ETH_LINK_SPEED_1G |
1469 ETH_LINK_SPEED_10G;
1470
1471 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1472 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1473 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1474
1475 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1476 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1477 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1478
1479 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1480 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1481 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1482
1483 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1484 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1485
1486 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1487 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1488
1489 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1490 ETH_RSS_NONFRAG_IPV4_TCP |
1491 ETH_RSS_NONFRAG_IPV4_UDP;
1492
1493 /* By default packets are dropped if no descriptors are available */
1494 info->default_rxconf.rx_drop_en = 1;
1495
1496 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1497
1498 return 0;
1499 }
1500
1501 /**
1502 * Return supported packet types.
1503 *
1504 * @param dev
1505 * Pointer to Ethernet device structure (unused).
1506 *
1507 * @return
1508 * Const pointer to the table with supported packet types.
1509 */
1510 static const uint32_t *
mrvl_dev_supported_ptypes_get(struct rte_eth_dev * dev __rte_unused)1511 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1512 {
1513 static const uint32_t ptypes[] = {
1514 RTE_PTYPE_L2_ETHER,
1515 RTE_PTYPE_L2_ETHER_VLAN,
1516 RTE_PTYPE_L2_ETHER_QINQ,
1517 RTE_PTYPE_L3_IPV4,
1518 RTE_PTYPE_L3_IPV4_EXT,
1519 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1520 RTE_PTYPE_L3_IPV6,
1521 RTE_PTYPE_L3_IPV6_EXT,
1522 RTE_PTYPE_L2_ETHER_ARP,
1523 RTE_PTYPE_L4_TCP,
1524 RTE_PTYPE_L4_UDP
1525 };
1526
1527 return ptypes;
1528 }
1529
1530 /**
1531 * DPDK callback to get information about specific receive queue.
1532 *
1533 * @param dev
1534 * Pointer to Ethernet device structure.
1535 * @param rx_queue_id
1536 * Receive queue index.
1537 * @param qinfo
1538 * Receive queue information structure.
1539 */
mrvl_rxq_info_get(struct rte_eth_dev * dev,uint16_t rx_queue_id,struct rte_eth_rxq_info * qinfo)1540 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1541 struct rte_eth_rxq_info *qinfo)
1542 {
1543 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1544 struct mrvl_priv *priv = dev->data->dev_private;
1545 int inq = priv->rxq_map[rx_queue_id].inq;
1546 int tc = priv->rxq_map[rx_queue_id].tc;
1547 struct pp2_ppio_tc_params *tc_params =
1548 &priv->ppio_params.inqs_params.tcs_params[tc];
1549
1550 qinfo->mp = q->mp;
1551 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1552 }
1553
1554 /**
1555 * DPDK callback to get information about specific transmit queue.
1556 *
1557 * @param dev
1558 * Pointer to Ethernet device structure.
1559 * @param tx_queue_id
1560 * Transmit queue index.
1561 * @param qinfo
1562 * Transmit queue information structure.
1563 */
mrvl_txq_info_get(struct rte_eth_dev * dev,uint16_t tx_queue_id,struct rte_eth_txq_info * qinfo)1564 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1565 struct rte_eth_txq_info *qinfo)
1566 {
1567 struct mrvl_priv *priv = dev->data->dev_private;
1568 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1569
1570 qinfo->nb_desc =
1571 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1572 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1573 }
1574
1575 /**
1576 * DPDK callback to Configure a VLAN filter.
1577 *
1578 * @param dev
1579 * Pointer to Ethernet device structure.
1580 * @param vlan_id
1581 * VLAN ID to filter.
1582 * @param on
1583 * Toggle filter.
1584 *
1585 * @return
1586 * 0 on success, negative error value otherwise.
1587 */
1588 static int
mrvl_vlan_filter_set(struct rte_eth_dev * dev,uint16_t vlan_id,int on)1589 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1590 {
1591 struct mrvl_priv *priv = dev->data->dev_private;
1592
1593 if (!priv->ppio)
1594 return -EPERM;
1595
1596 if (priv->isolated)
1597 return -ENOTSUP;
1598
1599 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1600 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1601 }
1602
1603 /**
1604 * Release buffers to hardware bpool (buffer-pool)
1605 *
1606 * @param rxq
1607 * Receive queue pointer.
1608 * @param num
1609 * Number of buffers to release to bpool.
1610 *
1611 * @return
1612 * 0 on success, negative error value otherwise.
1613 */
1614 static int
mrvl_fill_bpool(struct mrvl_rxq * rxq,int num)1615 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1616 {
1617 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1618 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1619 int i, ret;
1620 unsigned int core_id;
1621 struct pp2_hif *hif;
1622 struct pp2_bpool *bpool;
1623
1624 core_id = rte_lcore_id();
1625 if (core_id == LCORE_ID_ANY)
1626 core_id = rte_get_main_lcore();
1627
1628 hif = mrvl_get_hif(rxq->priv, core_id);
1629 if (!hif)
1630 return -1;
1631
1632 bpool = rxq->priv->bpool;
1633
1634 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1635 if (ret)
1636 return ret;
1637
1638 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1639 cookie_addr_high =
1640 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1641
1642 for (i = 0; i < num; i++) {
1643 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1644 != cookie_addr_high) {
1645 MRVL_LOG(ERR,
1646 "mbuf virtual addr high 0x%lx out of range",
1647 (uint64_t)mbufs[i] >> 32);
1648 goto out;
1649 }
1650
1651 entries[i].buff.addr =
1652 rte_mbuf_data_iova_default(mbufs[i]);
1653 entries[i].buff.cookie = (uint64_t)mbufs[i];
1654 entries[i].bpool = bpool;
1655 }
1656
1657 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1658 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1659
1660 if (i != num)
1661 goto out;
1662
1663 return 0;
1664 out:
1665 for (; i < num; i++)
1666 rte_pktmbuf_free(mbufs[i]);
1667
1668 return -1;
1669 }
1670
1671 /**
1672 * DPDK callback to configure the receive queue.
1673 *
1674 * @param dev
1675 * Pointer to Ethernet device structure.
1676 * @param idx
1677 * RX queue index.
1678 * @param desc
1679 * Number of descriptors to configure in queue.
1680 * @param socket
1681 * NUMA socket on which memory must be allocated.
1682 * @param conf
1683 * Thresholds parameters.
1684 * @param mp
1685 * Memory pool for buffer allocations.
1686 *
1687 * @return
1688 * 0 on success, negative error value otherwise.
1689 */
1690 static int
mrvl_rx_queue_setup(struct rte_eth_dev * dev,uint16_t idx,uint16_t desc,unsigned int socket,const struct rte_eth_rxconf * conf,struct rte_mempool * mp)1691 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1692 unsigned int socket,
1693 const struct rte_eth_rxconf *conf,
1694 struct rte_mempool *mp)
1695 {
1696 struct mrvl_priv *priv = dev->data->dev_private;
1697 struct mrvl_rxq *rxq;
1698 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1699 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1700 int ret, tc, inq;
1701 uint64_t offloads;
1702
1703 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1704
1705 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1706 /*
1707 * Unknown TC mapping, mapping will not have a correct queue.
1708 */
1709 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1710 idx, priv->ppio_id);
1711 return -EFAULT;
1712 }
1713
1714 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
1715 if (frame_size < max_rx_pkt_len) {
1716 MRVL_LOG(WARNING,
1717 "Mbuf size must be increased to %u bytes to hold up "
1718 "to %u bytes of data.",
1719 buf_size + max_rx_pkt_len - frame_size,
1720 max_rx_pkt_len);
1721 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1722 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1723 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1724 }
1725
1726 if (dev->data->rx_queues[idx]) {
1727 rte_free(dev->data->rx_queues[idx]);
1728 dev->data->rx_queues[idx] = NULL;
1729 }
1730
1731 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1732 if (!rxq)
1733 return -ENOMEM;
1734
1735 rxq->priv = priv;
1736 rxq->mp = mp;
1737 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1738 rxq->queue_id = idx;
1739 rxq->port_id = dev->data->port_id;
1740 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1741
1742 tc = priv->rxq_map[rxq->queue_id].tc,
1743 inq = priv->rxq_map[rxq->queue_id].inq;
1744 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1745 desc;
1746
1747 ret = mrvl_fill_bpool(rxq, desc);
1748 if (ret) {
1749 rte_free(rxq);
1750 return ret;
1751 }
1752
1753 priv->bpool_init_size += desc;
1754
1755 dev->data->rx_queues[idx] = rxq;
1756
1757 return 0;
1758 }
1759
1760 /**
1761 * DPDK callback to release the receive queue.
1762 *
1763 * @param rxq
1764 * Generic receive queue pointer.
1765 */
1766 static void
mrvl_rx_queue_release(void * rxq)1767 mrvl_rx_queue_release(void *rxq)
1768 {
1769 struct mrvl_rxq *q = rxq;
1770 struct pp2_ppio_tc_params *tc_params;
1771 int i, num, tc, inq;
1772 struct pp2_hif *hif;
1773 unsigned int core_id = rte_lcore_id();
1774
1775 if (core_id == LCORE_ID_ANY)
1776 core_id = rte_get_main_lcore();
1777
1778 if (!q)
1779 return;
1780
1781 hif = mrvl_get_hif(q->priv, core_id);
1782
1783 if (!hif)
1784 return;
1785
1786 tc = q->priv->rxq_map[q->queue_id].tc;
1787 inq = q->priv->rxq_map[q->queue_id].inq;
1788 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1789 num = tc_params->inqs_params[inq].size;
1790 for (i = 0; i < num; i++) {
1791 struct pp2_buff_inf inf;
1792 uint64_t addr;
1793
1794 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1795 addr = cookie_addr_high | inf.cookie;
1796 rte_pktmbuf_free((struct rte_mbuf *)addr);
1797 }
1798
1799 rte_free(q);
1800 }
1801
1802 /**
1803 * DPDK callback to configure the transmit queue.
1804 *
1805 * @param dev
1806 * Pointer to Ethernet device structure.
1807 * @param idx
1808 * Transmit queue index.
1809 * @param desc
1810 * Number of descriptors to configure in the queue.
1811 * @param socket
1812 * NUMA socket on which memory must be allocated.
1813 * @param conf
1814 * Tx queue configuration parameters.
1815 *
1816 * @return
1817 * 0 on success, negative error value otherwise.
1818 */
1819 static int
mrvl_tx_queue_setup(struct rte_eth_dev * dev,uint16_t idx,uint16_t desc,unsigned int socket,const struct rte_eth_txconf * conf)1820 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1821 unsigned int socket,
1822 const struct rte_eth_txconf *conf)
1823 {
1824 struct mrvl_priv *priv = dev->data->dev_private;
1825 struct mrvl_txq *txq;
1826
1827 if (dev->data->tx_queues[idx]) {
1828 rte_free(dev->data->tx_queues[idx]);
1829 dev->data->tx_queues[idx] = NULL;
1830 }
1831
1832 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1833 if (!txq)
1834 return -ENOMEM;
1835
1836 txq->priv = priv;
1837 txq->queue_id = idx;
1838 txq->port_id = dev->data->port_id;
1839 txq->tx_deferred_start = conf->tx_deferred_start;
1840 dev->data->tx_queues[idx] = txq;
1841
1842 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1843
1844 return 0;
1845 }
1846
1847 /**
1848 * DPDK callback to release the transmit queue.
1849 *
1850 * @param txq
1851 * Generic transmit queue pointer.
1852 */
1853 static void
mrvl_tx_queue_release(void * txq)1854 mrvl_tx_queue_release(void *txq)
1855 {
1856 struct mrvl_txq *q = txq;
1857
1858 if (!q)
1859 return;
1860
1861 rte_free(q);
1862 }
1863
1864 /**
1865 * DPDK callback to get flow control configuration.
1866 *
1867 * @param dev
1868 * Pointer to Ethernet device structure.
1869 * @param fc_conf
1870 * Pointer to the flow control configuration.
1871 *
1872 * @return
1873 * 0 on success, negative error value otherwise.
1874 */
1875 static int
mrvl_flow_ctrl_get(struct rte_eth_dev * dev,struct rte_eth_fc_conf * fc_conf)1876 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1877 {
1878 struct mrvl_priv *priv = dev->data->dev_private;
1879 int ret, en;
1880
1881 if (!priv)
1882 return -EPERM;
1883
1884 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1885 if (ret) {
1886 MRVL_LOG(ERR, "Failed to read rx pause state");
1887 return ret;
1888 }
1889
1890 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1891
1892 return 0;
1893 }
1894
1895 /**
1896 * DPDK callback to set flow control configuration.
1897 *
1898 * @param dev
1899 * Pointer to Ethernet device structure.
1900 * @param fc_conf
1901 * Pointer to the flow control configuration.
1902 *
1903 * @return
1904 * 0 on success, negative error value otherwise.
1905 */
1906 static int
mrvl_flow_ctrl_set(struct rte_eth_dev * dev,struct rte_eth_fc_conf * fc_conf)1907 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1908 {
1909 struct mrvl_priv *priv = dev->data->dev_private;
1910
1911 if (!priv)
1912 return -EPERM;
1913
1914 if (fc_conf->high_water ||
1915 fc_conf->low_water ||
1916 fc_conf->pause_time ||
1917 fc_conf->mac_ctrl_frame_fwd ||
1918 fc_conf->autoneg) {
1919 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1920
1921 return -EINVAL;
1922 }
1923
1924 if (fc_conf->mode == RTE_FC_NONE ||
1925 fc_conf->mode == RTE_FC_RX_PAUSE) {
1926 int ret, en;
1927
1928 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1929 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1930 if (ret)
1931 MRVL_LOG(ERR,
1932 "Failed to change flowctrl on RX side");
1933
1934 return ret;
1935 }
1936
1937 return 0;
1938 }
1939
1940 /**
1941 * Update RSS hash configuration
1942 *
1943 * @param dev
1944 * Pointer to Ethernet device structure.
1945 * @param rss_conf
1946 * Pointer to RSS configuration.
1947 *
1948 * @return
1949 * 0 on success, negative error value otherwise.
1950 */
1951 static int
mrvl_rss_hash_update(struct rte_eth_dev * dev,struct rte_eth_rss_conf * rss_conf)1952 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1953 struct rte_eth_rss_conf *rss_conf)
1954 {
1955 struct mrvl_priv *priv = dev->data->dev_private;
1956
1957 if (priv->isolated)
1958 return -ENOTSUP;
1959
1960 return mrvl_configure_rss(priv, rss_conf);
1961 }
1962
1963 /**
1964 * DPDK callback to get RSS hash configuration.
1965 *
1966 * @param dev
1967 * Pointer to Ethernet device structure.
1968 * @rss_conf
1969 * Pointer to RSS configuration.
1970 *
1971 * @return
1972 * Always 0.
1973 */
1974 static int
mrvl_rss_hash_conf_get(struct rte_eth_dev * dev,struct rte_eth_rss_conf * rss_conf)1975 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1976 struct rte_eth_rss_conf *rss_conf)
1977 {
1978 struct mrvl_priv *priv = dev->data->dev_private;
1979 enum pp2_ppio_hash_type hash_type =
1980 priv->ppio_params.inqs_params.hash_type;
1981
1982 rss_conf->rss_key = NULL;
1983
1984 if (hash_type == PP2_PPIO_HASH_T_NONE)
1985 rss_conf->rss_hf = 0;
1986 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1987 rss_conf->rss_hf = ETH_RSS_IPV4;
1988 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1989 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1990 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1991 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1992
1993 return 0;
1994 }
1995
1996 /**
1997 * DPDK callback to get rte_flow callbacks.
1998 *
1999 * @param dev
2000 * Pointer to the device structure.
2001 * @param filer_type
2002 * Flow filter type.
2003 * @param filter_op
2004 * Flow filter operation.
2005 * @param arg
2006 * Pointer to pass the flow ops.
2007 *
2008 * @return
2009 * 0 on success, negative error value otherwise.
2010 */
2011 static int
mrvl_eth_filter_ctrl(struct rte_eth_dev * dev __rte_unused,enum rte_filter_type filter_type,enum rte_filter_op filter_op,void * arg)2012 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
2013 enum rte_filter_type filter_type,
2014 enum rte_filter_op filter_op, void *arg)
2015 {
2016 switch (filter_type) {
2017 case RTE_ETH_FILTER_GENERIC:
2018 if (filter_op != RTE_ETH_FILTER_GET)
2019 return -EINVAL;
2020 *(const void **)arg = &mrvl_flow_ops;
2021 return 0;
2022 default:
2023 MRVL_LOG(WARNING, "Filter type (%d) not supported",
2024 filter_type);
2025 return -EINVAL;
2026 }
2027 }
2028
2029 /**
2030 * DPDK callback to get rte_mtr callbacks.
2031 *
2032 * @param dev
2033 * Pointer to the device structure.
2034 * @param ops
2035 * Pointer to pass the mtr ops.
2036 *
2037 * @return
2038 * Always 0.
2039 */
2040 static int
mrvl_mtr_ops_get(struct rte_eth_dev * dev __rte_unused,void * ops)2041 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2042 {
2043 *(const void **)ops = &mrvl_mtr_ops;
2044
2045 return 0;
2046 }
2047
2048 /**
2049 * DPDK callback to get rte_tm callbacks.
2050 *
2051 * @param dev
2052 * Pointer to the device structure.
2053 * @param ops
2054 * Pointer to pass the tm ops.
2055 *
2056 * @return
2057 * Always 0.
2058 */
2059 static int
mrvl_tm_ops_get(struct rte_eth_dev * dev __rte_unused,void * ops)2060 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2061 {
2062 *(const void **)ops = &mrvl_tm_ops;
2063
2064 return 0;
2065 }
2066
2067 static const struct eth_dev_ops mrvl_ops = {
2068 .dev_configure = mrvl_dev_configure,
2069 .dev_start = mrvl_dev_start,
2070 .dev_stop = mrvl_dev_stop,
2071 .dev_set_link_up = mrvl_dev_set_link_up,
2072 .dev_set_link_down = mrvl_dev_set_link_down,
2073 .dev_close = mrvl_dev_close,
2074 .link_update = mrvl_link_update,
2075 .promiscuous_enable = mrvl_promiscuous_enable,
2076 .allmulticast_enable = mrvl_allmulticast_enable,
2077 .promiscuous_disable = mrvl_promiscuous_disable,
2078 .allmulticast_disable = mrvl_allmulticast_disable,
2079 .mac_addr_remove = mrvl_mac_addr_remove,
2080 .mac_addr_add = mrvl_mac_addr_add,
2081 .mac_addr_set = mrvl_mac_addr_set,
2082 .mtu_set = mrvl_mtu_set,
2083 .stats_get = mrvl_stats_get,
2084 .stats_reset = mrvl_stats_reset,
2085 .xstats_get = mrvl_xstats_get,
2086 .xstats_reset = mrvl_xstats_reset,
2087 .xstats_get_names = mrvl_xstats_get_names,
2088 .dev_infos_get = mrvl_dev_infos_get,
2089 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
2090 .rxq_info_get = mrvl_rxq_info_get,
2091 .txq_info_get = mrvl_txq_info_get,
2092 .vlan_filter_set = mrvl_vlan_filter_set,
2093 .tx_queue_start = mrvl_tx_queue_start,
2094 .tx_queue_stop = mrvl_tx_queue_stop,
2095 .rx_queue_setup = mrvl_rx_queue_setup,
2096 .rx_queue_release = mrvl_rx_queue_release,
2097 .tx_queue_setup = mrvl_tx_queue_setup,
2098 .tx_queue_release = mrvl_tx_queue_release,
2099 .flow_ctrl_get = mrvl_flow_ctrl_get,
2100 .flow_ctrl_set = mrvl_flow_ctrl_set,
2101 .rss_hash_update = mrvl_rss_hash_update,
2102 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
2103 .filter_ctrl = mrvl_eth_filter_ctrl,
2104 .mtr_ops_get = mrvl_mtr_ops_get,
2105 .tm_ops_get = mrvl_tm_ops_get,
2106 };
2107
2108 /**
2109 * Return packet type information and l3/l4 offsets.
2110 *
2111 * @param desc
2112 * Pointer to the received packet descriptor.
2113 * @param l3_offset
2114 * l3 packet offset.
2115 * @param l4_offset
2116 * l4 packet offset.
2117 *
2118 * @return
2119 * Packet type information.
2120 */
2121 static inline uint64_t
mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc * desc,uint8_t * l3_offset,uint8_t * l4_offset)2122 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2123 uint8_t *l3_offset, uint8_t *l4_offset)
2124 {
2125 enum pp2_inq_l3_type l3_type;
2126 enum pp2_inq_l4_type l4_type;
2127 enum pp2_inq_vlan_tag vlan_tag;
2128 uint64_t packet_type;
2129
2130 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2131 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2132 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2133
2134 packet_type = RTE_PTYPE_L2_ETHER;
2135
2136 switch (vlan_tag) {
2137 case PP2_INQ_VLAN_TAG_SINGLE:
2138 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2139 break;
2140 case PP2_INQ_VLAN_TAG_DOUBLE:
2141 case PP2_INQ_VLAN_TAG_TRIPLE:
2142 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2143 break;
2144 default:
2145 break;
2146 }
2147
2148 switch (l3_type) {
2149 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2150 packet_type |= RTE_PTYPE_L3_IPV4;
2151 break;
2152 case PP2_INQ_L3_TYPE_IPV4_OK:
2153 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2154 break;
2155 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2156 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2157 break;
2158 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2159 packet_type |= RTE_PTYPE_L3_IPV6;
2160 break;
2161 case PP2_INQ_L3_TYPE_IPV6_EXT:
2162 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2163 break;
2164 case PP2_INQ_L3_TYPE_ARP:
2165 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2166 /*
2167 * In case of ARP l4_offset is set to wrong value.
2168 * Set it to proper one so that later on mbuf->l3_len can be
2169 * calculated subtracting l4_offset and l3_offset.
2170 */
2171 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2172 break;
2173 default:
2174 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
2175 break;
2176 }
2177
2178 switch (l4_type) {
2179 case PP2_INQ_L4_TYPE_TCP:
2180 packet_type |= RTE_PTYPE_L4_TCP;
2181 break;
2182 case PP2_INQ_L4_TYPE_UDP:
2183 packet_type |= RTE_PTYPE_L4_UDP;
2184 break;
2185 default:
2186 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
2187 break;
2188 }
2189
2190 return packet_type;
2191 }
2192
2193 /**
2194 * Get offload information from the received packet descriptor.
2195 *
2196 * @param desc
2197 * Pointer to the received packet descriptor.
2198 *
2199 * @return
2200 * Mbuf offload flags.
2201 */
2202 static inline uint64_t
mrvl_desc_to_ol_flags(struct pp2_ppio_desc * desc)2203 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2204 {
2205 uint64_t flags;
2206 enum pp2_inq_desc_status status;
2207
2208 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2209 if (unlikely(status != PP2_DESC_ERR_OK))
2210 flags = PKT_RX_IP_CKSUM_BAD;
2211 else
2212 flags = PKT_RX_IP_CKSUM_GOOD;
2213
2214 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2215 if (unlikely(status != PP2_DESC_ERR_OK))
2216 flags |= PKT_RX_L4_CKSUM_BAD;
2217 else
2218 flags |= PKT_RX_L4_CKSUM_GOOD;
2219
2220 return flags;
2221 }
2222
2223 /**
2224 * DPDK callback for receive.
2225 *
2226 * @param rxq
2227 * Generic pointer to the receive queue.
2228 * @param rx_pkts
2229 * Array to store received packets.
2230 * @param nb_pkts
2231 * Maximum number of packets in array.
2232 *
2233 * @return
2234 * Number of packets successfully received.
2235 */
2236 static uint16_t
mrvl_rx_pkt_burst(void * rxq,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)2237 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2238 {
2239 struct mrvl_rxq *q = rxq;
2240 struct pp2_ppio_desc descs[nb_pkts];
2241 struct pp2_bpool *bpool;
2242 int i, ret, rx_done = 0;
2243 int num;
2244 struct pp2_hif *hif;
2245 unsigned int core_id = rte_lcore_id();
2246
2247 hif = mrvl_get_hif(q->priv, core_id);
2248
2249 if (unlikely(!q->priv->ppio || !hif))
2250 return 0;
2251
2252 bpool = q->priv->bpool;
2253
2254 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2255 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2256 if (unlikely(ret < 0)) {
2257 MRVL_LOG(ERR, "Failed to receive packets");
2258 return 0;
2259 }
2260 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2261
2262 for (i = 0; i < nb_pkts; i++) {
2263 struct rte_mbuf *mbuf;
2264 uint8_t l3_offset, l4_offset;
2265 enum pp2_inq_desc_status status;
2266 uint64_t addr;
2267
2268 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2269 struct pp2_ppio_desc *pref_desc;
2270 u64 pref_addr;
2271
2272 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2273 pref_addr = cookie_addr_high |
2274 pp2_ppio_inq_desc_get_cookie(pref_desc);
2275 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2276 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2277 }
2278
2279 addr = cookie_addr_high |
2280 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2281 mbuf = (struct rte_mbuf *)addr;
2282 rte_pktmbuf_reset(mbuf);
2283
2284 /* drop packet in case of mac, overrun or resource error */
2285 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2286 if (unlikely(status != PP2_DESC_ERR_OK)) {
2287 struct pp2_buff_inf binf = {
2288 .addr = rte_mbuf_data_iova_default(mbuf),
2289 .cookie = (uint64_t)mbuf,
2290 };
2291
2292 pp2_bpool_put_buff(hif, bpool, &binf);
2293 mrvl_port_bpool_size
2294 [bpool->pp2_id][bpool->id][core_id]++;
2295 q->drop_mac++;
2296 continue;
2297 }
2298
2299 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2300 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2301 mbuf->data_len = mbuf->pkt_len;
2302 mbuf->port = q->port_id;
2303 mbuf->packet_type =
2304 mrvl_desc_to_packet_type_and_offset(&descs[i],
2305 &l3_offset,
2306 &l4_offset);
2307 mbuf->l2_len = l3_offset;
2308 mbuf->l3_len = l4_offset - l3_offset;
2309
2310 if (likely(q->cksum_enabled))
2311 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2312
2313 rx_pkts[rx_done++] = mbuf;
2314 q->bytes_recv += mbuf->pkt_len;
2315 }
2316
2317 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2318 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2319
2320 if (unlikely(num <= q->priv->bpool_min_size ||
2321 (!rx_done && num < q->priv->bpool_init_size))) {
2322 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2323 if (ret)
2324 MRVL_LOG(ERR, "Failed to fill bpool");
2325 } else if (unlikely(num > q->priv->bpool_max_size)) {
2326 int i;
2327 int pkt_to_remove = num - q->priv->bpool_init_size;
2328 struct rte_mbuf *mbuf;
2329 struct pp2_buff_inf buff;
2330
2331 MRVL_LOG(DEBUG,
2332 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2333 bpool->pp2_id, q->priv->ppio->port_id,
2334 bpool->id, pkt_to_remove, num,
2335 q->priv->bpool_init_size);
2336
2337 for (i = 0; i < pkt_to_remove; i++) {
2338 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2339 if (ret)
2340 break;
2341 mbuf = (struct rte_mbuf *)
2342 (cookie_addr_high | buff.cookie);
2343 rte_pktmbuf_free(mbuf);
2344 }
2345 mrvl_port_bpool_size
2346 [bpool->pp2_id][bpool->id][core_id] -= i;
2347 }
2348 rte_spinlock_unlock(&q->priv->lock);
2349 }
2350
2351 return rx_done;
2352 }
2353
2354 /**
2355 * Prepare offload information.
2356 *
2357 * @param ol_flags
2358 * Offload flags.
2359 * @param packet_type
2360 * Packet type bitfield.
2361 * @param l3_type
2362 * Pointer to the pp2_ouq_l3_type structure.
2363 * @param l4_type
2364 * Pointer to the pp2_outq_l4_type structure.
2365 * @param gen_l3_cksum
2366 * Will be set to 1 in case l3 checksum is computed.
2367 * @param l4_cksum
2368 * Will be set to 1 in case l4 checksum is computed.
2369 *
2370 * @return
2371 * 0 on success, negative error value otherwise.
2372 */
2373 static inline int
mrvl_prepare_proto_info(uint64_t ol_flags,uint32_t packet_type,enum pp2_outq_l3_type * l3_type,enum pp2_outq_l4_type * l4_type,int * gen_l3_cksum,int * gen_l4_cksum)2374 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2375 enum pp2_outq_l3_type *l3_type,
2376 enum pp2_outq_l4_type *l4_type,
2377 int *gen_l3_cksum,
2378 int *gen_l4_cksum)
2379 {
2380 /*
2381 * Based on ol_flags prepare information
2382 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2383 * for offloading.
2384 */
2385 if (ol_flags & PKT_TX_IPV4) {
2386 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2387 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2388 } else if (ol_flags & PKT_TX_IPV6) {
2389 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2390 /* no checksum for ipv6 header */
2391 *gen_l3_cksum = 0;
2392 } else {
2393 /* if something different then stop processing */
2394 return -1;
2395 }
2396
2397 ol_flags &= PKT_TX_L4_MASK;
2398 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2399 ol_flags == PKT_TX_TCP_CKSUM) {
2400 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2401 *gen_l4_cksum = 1;
2402 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2403 ol_flags == PKT_TX_UDP_CKSUM) {
2404 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2405 *gen_l4_cksum = 1;
2406 } else {
2407 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2408 /* no checksum for other type */
2409 *gen_l4_cksum = 0;
2410 }
2411
2412 return 0;
2413 }
2414
2415 /**
2416 * Release already sent buffers to bpool (buffer-pool).
2417 *
2418 * @param ppio
2419 * Pointer to the port structure.
2420 * @param hif
2421 * Pointer to the MUSDK hardware interface.
2422 * @param sq
2423 * Pointer to the shadow queue.
2424 * @param qid
2425 * Queue id number.
2426 * @param force
2427 * Force releasing packets.
2428 */
2429 static inline void
mrvl_free_sent_buffers(struct pp2_ppio * ppio,struct pp2_hif * hif,unsigned int core_id,struct mrvl_shadow_txq * sq,int qid,int force)2430 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2431 unsigned int core_id, struct mrvl_shadow_txq *sq,
2432 int qid, int force)
2433 {
2434 struct buff_release_entry *entry;
2435 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2436 int i;
2437
2438 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2439
2440 sq->num_to_release += nb_done;
2441
2442 if (likely(!force &&
2443 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2444 return;
2445
2446 nb_done = sq->num_to_release;
2447 sq->num_to_release = 0;
2448
2449 for (i = 0; i < nb_done; i++) {
2450 entry = &sq->ent[sq->tail + num];
2451 if (unlikely(!entry->buff.addr)) {
2452 MRVL_LOG(ERR,
2453 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2454 sq->tail, (u64)entry->buff.cookie,
2455 (u64)entry->buff.addr);
2456 skip_bufs = 1;
2457 goto skip;
2458 }
2459
2460 if (unlikely(!entry->bpool)) {
2461 struct rte_mbuf *mbuf;
2462
2463 mbuf = (struct rte_mbuf *)
2464 (cookie_addr_high | entry->buff.cookie);
2465 rte_pktmbuf_free(mbuf);
2466 skip_bufs = 1;
2467 goto skip;
2468 }
2469
2470 mrvl_port_bpool_size
2471 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2472 num++;
2473 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2474 goto skip;
2475 continue;
2476 skip:
2477 if (likely(num))
2478 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2479 num += skip_bufs;
2480 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2481 sq->size -= num;
2482 num = 0;
2483 skip_bufs = 0;
2484 }
2485
2486 if (likely(num)) {
2487 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2488 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2489 sq->size -= num;
2490 }
2491 }
2492
2493 /**
2494 * DPDK callback for transmit.
2495 *
2496 * @param txq
2497 * Generic pointer transmit queue.
2498 * @param tx_pkts
2499 * Packets to transmit.
2500 * @param nb_pkts
2501 * Number of packets in array.
2502 *
2503 * @return
2504 * Number of packets successfully transmitted.
2505 */
2506 static uint16_t
mrvl_tx_pkt_burst(void * txq,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)2507 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2508 {
2509 struct mrvl_txq *q = txq;
2510 struct mrvl_shadow_txq *sq;
2511 struct pp2_hif *hif;
2512 struct pp2_ppio_desc descs[nb_pkts];
2513 unsigned int core_id = rte_lcore_id();
2514 int i, ret, bytes_sent = 0;
2515 uint16_t num, sq_free_size;
2516 uint64_t addr;
2517
2518 hif = mrvl_get_hif(q->priv, core_id);
2519 sq = &q->shadow_txqs[core_id];
2520
2521 if (unlikely(!q->priv->ppio || !hif))
2522 return 0;
2523
2524 if (sq->size)
2525 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2526 sq, q->queue_id, 0);
2527
2528 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2529 if (unlikely(nb_pkts > sq_free_size)) {
2530 MRVL_LOG(DEBUG,
2531 "No room in shadow queue for %d packets! %d packets will be sent.",
2532 nb_pkts, sq_free_size);
2533 nb_pkts = sq_free_size;
2534 }
2535
2536 for (i = 0; i < nb_pkts; i++) {
2537 struct rte_mbuf *mbuf = tx_pkts[i];
2538 int gen_l3_cksum, gen_l4_cksum;
2539 enum pp2_outq_l3_type l3_type;
2540 enum pp2_outq_l4_type l4_type;
2541
2542 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2543 struct rte_mbuf *pref_pkt_hdr;
2544
2545 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2546 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2547 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2548 }
2549
2550 mrvl_fill_shadowq(sq, mbuf);
2551 mrvl_fill_desc(&descs[i], mbuf);
2552
2553 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2554 /*
2555 * in case unsupported ol_flags were passed
2556 * do not update descriptor offload information
2557 */
2558 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2559 &l3_type, &l4_type, &gen_l3_cksum,
2560 &gen_l4_cksum);
2561 if (unlikely(ret))
2562 continue;
2563
2564 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2565 mbuf->l2_len,
2566 mbuf->l2_len + mbuf->l3_len,
2567 gen_l3_cksum, gen_l4_cksum);
2568 }
2569
2570 num = nb_pkts;
2571 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2572 /* number of packets that were not sent */
2573 if (unlikely(num > nb_pkts)) {
2574 for (i = nb_pkts; i < num; i++) {
2575 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2576 MRVL_PP2_TX_SHADOWQ_MASK;
2577 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2578 bytes_sent -=
2579 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2580 }
2581 sq->size -= num - nb_pkts;
2582 }
2583
2584 q->bytes_sent += bytes_sent;
2585
2586 return nb_pkts;
2587 }
2588
2589 /** DPDK callback for S/G transmit.
2590 *
2591 * @param txq
2592 * Generic pointer transmit queue.
2593 * @param tx_pkts
2594 * Packets to transmit.
2595 * @param nb_pkts
2596 * Number of packets in array.
2597 *
2598 * @return
2599 * Number of packets successfully transmitted.
2600 */
2601 static uint16_t
mrvl_tx_sg_pkt_burst(void * txq,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)2602 mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts,
2603 uint16_t nb_pkts)
2604 {
2605 struct mrvl_txq *q = txq;
2606 struct mrvl_shadow_txq *sq;
2607 struct pp2_hif *hif;
2608 struct pp2_ppio_desc descs[nb_pkts * PP2_PPIO_DESC_NUM_FRAGS];
2609 struct pp2_ppio_sg_pkts pkts;
2610 uint8_t frags[nb_pkts];
2611 unsigned int core_id = rte_lcore_id();
2612 int i, j, ret, bytes_sent = 0;
2613 int tail, tail_first;
2614 uint16_t num, sq_free_size;
2615 uint16_t nb_segs, total_descs = 0;
2616 uint64_t addr;
2617
2618 hif = mrvl_get_hif(q->priv, core_id);
2619 sq = &q->shadow_txqs[core_id];
2620 pkts.frags = frags;
2621 pkts.num = 0;
2622
2623 if (unlikely(!q->priv->ppio || !hif))
2624 return 0;
2625
2626 if (sq->size)
2627 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2628 sq, q->queue_id, 0);
2629
2630 /* Save shadow queue free size */
2631 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2632
2633 tail = 0;
2634 for (i = 0; i < nb_pkts; i++) {
2635 struct rte_mbuf *mbuf = tx_pkts[i];
2636 struct rte_mbuf *seg = NULL;
2637 int gen_l3_cksum, gen_l4_cksum;
2638 enum pp2_outq_l3_type l3_type;
2639 enum pp2_outq_l4_type l4_type;
2640
2641 nb_segs = mbuf->nb_segs;
2642 tail_first = tail;
2643 total_descs += nb_segs;
2644
2645 /*
2646 * Check if total_descs does not exceed
2647 * shadow queue free size
2648 */
2649 if (unlikely(total_descs > sq_free_size)) {
2650 total_descs -= nb_segs;
2651 RTE_LOG(DEBUG, PMD,
2652 "No room in shadow queue for %d packets! "
2653 "%d packets will be sent.\n",
2654 nb_pkts, i);
2655 break;
2656 }
2657
2658 /* Check if nb_segs does not exceed the max nb of desc per
2659 * fragmented packet
2660 */
2661 if (nb_segs > PP2_PPIO_DESC_NUM_FRAGS) {
2662 total_descs -= nb_segs;
2663 RTE_LOG(ERR, PMD,
2664 "Too many segments. Packet won't be sent.\n");
2665 break;
2666 }
2667
2668 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2669 struct rte_mbuf *pref_pkt_hdr;
2670
2671 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2672 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2673 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2674 }
2675
2676 pkts.frags[pkts.num] = nb_segs;
2677 pkts.num++;
2678
2679 seg = mbuf;
2680 for (j = 0; j < nb_segs - 1; j++) {
2681 /* For the subsequent segments, set shadow queue
2682 * buffer to NULL
2683 */
2684 mrvl_fill_shadowq(sq, NULL);
2685 mrvl_fill_desc(&descs[tail], seg);
2686
2687 tail++;
2688 seg = seg->next;
2689 }
2690 /* Put first mbuf info in last shadow queue entry */
2691 mrvl_fill_shadowq(sq, mbuf);
2692 /* Update descriptor with last segment */
2693 mrvl_fill_desc(&descs[tail++], seg);
2694
2695 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2696 /* In case unsupported ol_flags were passed
2697 * do not update descriptor offload information
2698 */
2699 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2700 &l3_type, &l4_type, &gen_l3_cksum,
2701 &gen_l4_cksum);
2702 if (unlikely(ret))
2703 continue;
2704
2705 pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
2706 l4_type, mbuf->l2_len,
2707 mbuf->l2_len + mbuf->l3_len,
2708 gen_l3_cksum, gen_l4_cksum);
2709 }
2710
2711 num = total_descs;
2712 pp2_ppio_send_sg(q->priv->ppio, hif, q->queue_id, descs,
2713 &total_descs, &pkts);
2714 /* number of packets that were not sent */
2715 if (unlikely(num > total_descs)) {
2716 for (i = total_descs; i < num; i++) {
2717 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2718 MRVL_PP2_TX_SHADOWQ_MASK;
2719
2720 addr = sq->ent[sq->head].buff.cookie;
2721 if (addr)
2722 bytes_sent -=
2723 rte_pktmbuf_pkt_len((struct rte_mbuf *)
2724 (cookie_addr_high | addr));
2725 }
2726 sq->size -= num - total_descs;
2727 nb_pkts = pkts.num;
2728 }
2729
2730 q->bytes_sent += bytes_sent;
2731
2732 return nb_pkts;
2733 }
2734
2735 /**
2736 * Initialize packet processor.
2737 *
2738 * @return
2739 * 0 on success, negative error value otherwise.
2740 */
2741 static int
mrvl_init_pp2(void)2742 mrvl_init_pp2(void)
2743 {
2744 struct pp2_init_params init_params;
2745
2746 memset(&init_params, 0, sizeof(init_params));
2747 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2748 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2749 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2750
2751 return pp2_init(&init_params);
2752 }
2753
2754 /**
2755 * Deinitialize packet processor.
2756 *
2757 * @return
2758 * 0 on success, negative error value otherwise.
2759 */
2760 static void
mrvl_deinit_pp2(void)2761 mrvl_deinit_pp2(void)
2762 {
2763 pp2_deinit();
2764 }
2765
2766 /**
2767 * Create private device structure.
2768 *
2769 * @param dev_name
2770 * Pointer to the port name passed in the initialization parameters.
2771 *
2772 * @return
2773 * Pointer to the newly allocated private device structure.
2774 */
2775 static struct mrvl_priv *
mrvl_priv_create(const char * dev_name)2776 mrvl_priv_create(const char *dev_name)
2777 {
2778 struct pp2_bpool_params bpool_params;
2779 char match[MRVL_MATCH_LEN];
2780 struct mrvl_priv *priv;
2781 int ret, bpool_bit;
2782
2783 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2784 if (!priv)
2785 return NULL;
2786
2787 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2788 &priv->pp_id, &priv->ppio_id);
2789 if (ret)
2790 goto out_free_priv;
2791
2792 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2793 PP2_BPOOL_NUM_POOLS);
2794 if (bpool_bit < 0)
2795 goto out_free_priv;
2796 priv->bpool_bit = bpool_bit;
2797
2798 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2799 priv->bpool_bit);
2800 memset(&bpool_params, 0, sizeof(bpool_params));
2801 bpool_params.match = match;
2802 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2803 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2804 if (ret)
2805 goto out_clear_bpool_bit;
2806
2807 priv->ppio_params.type = PP2_PPIO_T_NIC;
2808 rte_spinlock_init(&priv->lock);
2809
2810 return priv;
2811 out_clear_bpool_bit:
2812 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2813 out_free_priv:
2814 rte_free(priv);
2815 return NULL;
2816 }
2817
2818 /**
2819 * Create device representing Ethernet port.
2820 *
2821 * @param name
2822 * Pointer to the port's name.
2823 *
2824 * @return
2825 * 0 on success, negative error value otherwise.
2826 */
2827 static int
mrvl_eth_dev_create(struct rte_vdev_device * vdev,const char * name)2828 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2829 {
2830 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2831 struct rte_eth_dev *eth_dev;
2832 struct mrvl_priv *priv;
2833 struct ifreq req;
2834
2835 eth_dev = rte_eth_dev_allocate(name);
2836 if (!eth_dev)
2837 return -ENOMEM;
2838
2839 priv = mrvl_priv_create(name);
2840 if (!priv) {
2841 ret = -ENOMEM;
2842 goto out_free;
2843 }
2844 eth_dev->data->dev_private = priv;
2845
2846 eth_dev->data->mac_addrs =
2847 rte_zmalloc("mac_addrs",
2848 RTE_ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2849 if (!eth_dev->data->mac_addrs) {
2850 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2851 ret = -ENOMEM;
2852 goto out_free;
2853 }
2854
2855 memset(&req, 0, sizeof(req));
2856 strcpy(req.ifr_name, name);
2857 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2858 if (ret)
2859 goto out_free;
2860
2861 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2862 req.ifr_addr.sa_data, RTE_ETHER_ADDR_LEN);
2863
2864 eth_dev->device = &vdev->device;
2865 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2866 mrvl_set_tx_function(eth_dev);
2867 eth_dev->dev_ops = &mrvl_ops;
2868 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2869
2870 rte_eth_dev_probing_finish(eth_dev);
2871 return 0;
2872 out_free:
2873 rte_eth_dev_release_port(eth_dev);
2874
2875 return ret;
2876 }
2877
2878 /**
2879 * Callback used by rte_kvargs_process() during argument parsing.
2880 *
2881 * @param key
2882 * Pointer to the parsed key (unused).
2883 * @param value
2884 * Pointer to the parsed value.
2885 * @param extra_args
2886 * Pointer to the extra arguments which contains address of the
2887 * table of pointers to parsed interface names.
2888 *
2889 * @return
2890 * Always 0.
2891 */
2892 static int
mrvl_get_ifnames(const char * key __rte_unused,const char * value,void * extra_args)2893 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2894 void *extra_args)
2895 {
2896 struct mrvl_ifnames *ifnames = extra_args;
2897
2898 ifnames->names[ifnames->idx++] = value;
2899
2900 return 0;
2901 }
2902
2903 /**
2904 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2905 */
2906 static void
mrvl_deinit_hifs(void)2907 mrvl_deinit_hifs(void)
2908 {
2909 int i;
2910
2911 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2912 if (hifs[i])
2913 pp2_hif_deinit(hifs[i]);
2914 }
2915 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2916 memset(hifs, 0, sizeof(hifs));
2917 }
2918
2919 /**
2920 * DPDK callback to register the virtual device.
2921 *
2922 * @param vdev
2923 * Pointer to the virtual device.
2924 *
2925 * @return
2926 * 0 on success, negative error value otherwise.
2927 */
2928 static int
rte_pmd_mrvl_probe(struct rte_vdev_device * vdev)2929 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2930 {
2931 struct rte_kvargs *kvlist;
2932 struct mrvl_ifnames ifnames;
2933 int ret = -EINVAL;
2934 uint32_t i, ifnum, cfgnum;
2935 const char *params;
2936
2937 params = rte_vdev_device_args(vdev);
2938 if (!params)
2939 return -EINVAL;
2940
2941 kvlist = rte_kvargs_parse(params, valid_args);
2942 if (!kvlist)
2943 return -EINVAL;
2944
2945 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2946 if (ifnum > RTE_DIM(ifnames.names))
2947 goto out_free_kvlist;
2948
2949 ifnames.idx = 0;
2950 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2951 mrvl_get_ifnames, &ifnames);
2952
2953
2954 /*
2955 * The below system initialization should be done only once,
2956 * on the first provided configuration file
2957 */
2958 if (!mrvl_qos_cfg) {
2959 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2960 MRVL_LOG(INFO, "Parsing config file!");
2961 if (cfgnum > 1) {
2962 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2963 goto out_free_kvlist;
2964 } else if (cfgnum == 1) {
2965 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2966 mrvl_get_qoscfg, &mrvl_qos_cfg);
2967 }
2968 }
2969
2970 if (mrvl_dev_num)
2971 goto init_devices;
2972
2973 MRVL_LOG(INFO, "Perform MUSDK initializations");
2974
2975 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2976 if (ret)
2977 goto out_free_kvlist;
2978
2979 ret = mrvl_init_pp2();
2980 if (ret) {
2981 MRVL_LOG(ERR, "Failed to init PP!");
2982 rte_mvep_deinit(MVEP_MOD_T_PP2);
2983 goto out_free_kvlist;
2984 }
2985
2986 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2987 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2988
2989 mrvl_lcore_first = RTE_MAX_LCORE;
2990 mrvl_lcore_last = 0;
2991
2992 init_devices:
2993 for (i = 0; i < ifnum; i++) {
2994 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2995 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2996 if (ret)
2997 goto out_cleanup;
2998 mrvl_dev_num++;
2999 }
3000
3001 rte_kvargs_free(kvlist);
3002
3003 return 0;
3004 out_cleanup:
3005 rte_pmd_mrvl_remove(vdev);
3006
3007 out_free_kvlist:
3008 rte_kvargs_free(kvlist);
3009
3010 return ret;
3011 }
3012
3013 /**
3014 * DPDK callback to remove virtual device.
3015 *
3016 * @param vdev
3017 * Pointer to the removed virtual device.
3018 *
3019 * @return
3020 * 0 on success, negative error value otherwise.
3021 */
3022 static int
rte_pmd_mrvl_remove(struct rte_vdev_device * vdev)3023 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
3024 {
3025 uint16_t port_id;
3026 int ret = 0;
3027
3028 RTE_ETH_FOREACH_DEV(port_id) {
3029 if (rte_eth_devices[port_id].device != &vdev->device)
3030 continue;
3031 ret |= rte_eth_dev_close(port_id);
3032 }
3033
3034 return ret == 0 ? 0 : -EIO;
3035 }
3036
3037 static struct rte_vdev_driver pmd_mrvl_drv = {
3038 .probe = rte_pmd_mrvl_probe,
3039 .remove = rte_pmd_mrvl_remove,
3040 };
3041
3042 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
3043 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
3044 RTE_LOG_REGISTER(mrvl_logtype, pmd.net.mvpp2, NOTICE);
3045