1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006 Bernd Walter. All rights reserved.
5 * Copyright (c) 2006 M. Warner Losh <[email protected]>
6 * Copyright (c) 2017 Marius Strobl <[email protected]>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Portions of this software may have been developed with reference to
29 * the SD Simplified Specification. The following disclaimer may apply:
30 *
31 * The following conditions apply to the release of the simplified
32 * specification ("Simplified Specification") by the SD Card Association and
33 * the SD Group. The Simplified Specification is a subset of the complete SD
34 * Specification which is owned by the SD Card Association and the SD
35 * Group. This Simplified Specification is provided on a non-confidential
36 * basis subject to the disclaimers below. Any implementation of the
37 * Simplified Specification may require a license from the SD Card
38 * Association, SD Group, SD-3C LLC or other third parties.
39 *
40 * Disclaimers:
41 *
42 * The information contained in the Simplified Specification is presented only
43 * as a standard specification for SD Cards and SD Host/Ancillary products and
44 * is provided "AS-IS" without any representations or warranties of any
45 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
46 * Card Association for any damages, any infringements of patents or other
47 * right of the SD Group, SD-3C LLC, the SD Card Association or any third
48 * parties, which may result from its use. No license is granted by
49 * implication, estoppel or otherwise under any patent or other rights of the
50 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
51 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
52 * or the SD Card Association to disclose or distribute any technical
53 * information, know-how or other confidential information to any third party.
54 */
55
56 #include <sys/cdefs.h>
57 __FBSDID("$FreeBSD$");
58
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/kernel.h>
62 #include <sys/malloc.h>
63 #include <sys/lock.h>
64 #include <sys/module.h>
65 #include <sys/mutex.h>
66 #include <sys/bus.h>
67 #include <sys/endian.h>
68 #include <sys/sysctl.h>
69 #include <sys/time.h>
70
71 #include <dev/mmc/bridge.h>
72 #include <dev/mmc/mmc_private.h>
73 #include <dev/mmc/mmc_subr.h>
74 #include <dev/mmc/mmcreg.h>
75 #include <dev/mmc/mmcbrvar.h>
76 #include <dev/mmc/mmcvar.h>
77
78 #include "mmcbr_if.h"
79 #include "mmcbus_if.h"
80
81 CTASSERT(bus_timing_max <= sizeof(uint32_t) * NBBY);
82
83 /*
84 * Per-card data
85 */
86 struct mmc_ivars {
87 uint32_t raw_cid[4]; /* Raw bits of the CID */
88 uint32_t raw_csd[4]; /* Raw bits of the CSD */
89 uint32_t raw_scr[2]; /* Raw bits of the SCR */
90 uint8_t raw_ext_csd[MMC_EXTCSD_SIZE]; /* Raw bits of the EXT_CSD */
91 uint32_t raw_sd_status[16]; /* Raw bits of the SD_STATUS */
92 uint16_t rca;
93 u_char read_only; /* True when the device is read-only */
94 u_char high_cap; /* High Capacity device (block addressed) */
95 enum mmc_card_mode mode;
96 enum mmc_bus_width bus_width; /* Bus width to use */
97 struct mmc_cid cid; /* cid decoded */
98 struct mmc_csd csd; /* csd decoded */
99 struct mmc_scr scr; /* scr decoded */
100 struct mmc_sd_status sd_status; /* SD_STATUS decoded */
101 uint32_t sec_count; /* Card capacity in 512byte blocks */
102 uint32_t timings; /* Mask of bus timings supported */
103 uint32_t vccq_120; /* Mask of bus timings at VCCQ of 1.2 V */
104 uint32_t vccq_180; /* Mask of bus timings at VCCQ of 1.8 V */
105 uint32_t tran_speed; /* Max speed in normal mode */
106 uint32_t hs_tran_speed; /* Max speed in high speed mode */
107 uint32_t erase_sector; /* Card native erase sector size */
108 uint32_t cmd6_time; /* Generic switch timeout [us] */
109 uint32_t quirks; /* Quirks as per mmc_quirk->quirks */
110 char card_id_string[64];/* Formatted CID info (serial, MFG, etc) */
111 char card_sn_string[16];/* Formatted serial # for disk->d_ident */
112 };
113
114 #define CMD_RETRIES 3
115
116 static const struct mmc_quirk mmc_quirks[] = {
117 /*
118 * For some SanDisk iNAND devices, the CMD38 argument needs to be
119 * provided in EXT_CSD[113].
120 */
121 { 0x2, 0x100, "SEM02G", MMC_QUIRK_INAND_CMD38 },
122 { 0x2, 0x100, "SEM04G", MMC_QUIRK_INAND_CMD38 },
123 { 0x2, 0x100, "SEM08G", MMC_QUIRK_INAND_CMD38 },
124 { 0x2, 0x100, "SEM16G", MMC_QUIRK_INAND_CMD38 },
125 { 0x2, 0x100, "SEM32G", MMC_QUIRK_INAND_CMD38 },
126
127 /*
128 * Disable TRIM for Kingston eMMCs where a firmware bug can lead to
129 * unrecoverable data corruption.
130 */
131 { 0x70, MMC_QUIRK_OID_ANY, "V10008", MMC_QUIRK_BROKEN_TRIM },
132 { 0x70, MMC_QUIRK_OID_ANY, "V10016", MMC_QUIRK_BROKEN_TRIM },
133 { 0x0, 0x0, NULL, 0x0 }
134 };
135
136 static SYSCTL_NODE(_hw, OID_AUTO, mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
137 "mmc driver");
138
139 static int mmc_debug;
140 SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &mmc_debug, 0,
141 "Debug level");
142
143 /* bus entry points */
144 static int mmc_acquire_bus(device_t busdev, device_t dev);
145 static int mmc_attach(device_t dev);
146 static int mmc_child_location_str(device_t dev, device_t child, char *buf,
147 size_t buflen);
148 static int mmc_detach(device_t dev);
149 static int mmc_probe(device_t dev);
150 static int mmc_read_ivar(device_t bus, device_t child, int which,
151 uintptr_t *result);
152 static int mmc_release_bus(device_t busdev, device_t dev);
153 static int mmc_resume(device_t dev);
154 static void mmc_retune_pause(device_t busdev, device_t dev, bool retune);
155 static void mmc_retune_unpause(device_t busdev, device_t dev);
156 static int mmc_suspend(device_t dev);
157 static int mmc_wait_for_request(device_t busdev, device_t dev,
158 struct mmc_request *req);
159 static int mmc_write_ivar(device_t bus, device_t child, int which,
160 uintptr_t value);
161
162 #define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
163 #define MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
164 #define MMC_LOCK_INIT(_sc) \
165 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->dev), \
166 "mmc", MTX_DEF)
167 #define MMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx);
168 #define MMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED);
169 #define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED);
170
171 static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid);
172 static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr);
173 static void mmc_app_decode_sd_status(uint32_t *raw_sd_status,
174 struct mmc_sd_status *sd_status);
175 static int mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca,
176 uint32_t *rawsdstatus);
177 static int mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca,
178 uint32_t *rawscr);
179 static int mmc_calculate_clock(struct mmc_softc *sc);
180 static void mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid,
181 bool is_4_41p);
182 static void mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid);
183 static void mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd);
184 static int mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd);
185 static void mmc_delayed_attach(void *xsc);
186 static int mmc_delete_cards(struct mmc_softc *sc, bool final);
187 static void mmc_discover_cards(struct mmc_softc *sc);
188 static void mmc_format_card_id_string(struct mmc_ivars *ivar);
189 static void mmc_go_discovery(struct mmc_softc *sc);
190 static uint32_t mmc_get_bits(uint32_t *bits, int bit_len, int start,
191 int size);
192 static int mmc_highest_voltage(uint32_t ocr);
193 static bool mmc_host_timing(device_t dev, enum mmc_bus_timing timing);
194 static void mmc_idle_cards(struct mmc_softc *sc);
195 static void mmc_ms_delay(int ms);
196 static void mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard);
197 static void mmc_power_down(struct mmc_softc *sc);
198 static void mmc_power_up(struct mmc_softc *sc);
199 static void mmc_rescan_cards(struct mmc_softc *sc);
200 static int mmc_retune(device_t busdev, device_t dev, bool reset);
201 static void mmc_scan(struct mmc_softc *sc);
202 static int mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp,
203 uint8_t value, uint8_t *res);
204 static int mmc_select_card(struct mmc_softc *sc, uint16_t rca);
205 static uint32_t mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr);
206 static int mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr,
207 uint32_t *rocr);
208 static int mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd);
209 static int mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs);
210 static int mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr,
211 uint32_t *rocr);
212 static int mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp);
213 static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len);
214 static int mmc_set_card_bus_width(struct mmc_softc *sc, struct mmc_ivars *ivar,
215 enum mmc_bus_timing timing);
216 static int mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar);
217 static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp);
218 static int mmc_set_timing(struct mmc_softc *sc, struct mmc_ivars *ivar,
219 enum mmc_bus_timing timing);
220 static int mmc_set_vccq(struct mmc_softc *sc, struct mmc_ivars *ivar,
221 enum mmc_bus_timing timing);
222 static int mmc_switch_to_hs200(struct mmc_softc *sc, struct mmc_ivars *ivar,
223 uint32_t clock);
224 static int mmc_switch_to_hs400(struct mmc_softc *sc, struct mmc_ivars *ivar,
225 uint32_t max_dtr, enum mmc_bus_timing max_timing);
226 static int mmc_test_bus_width(struct mmc_softc *sc);
227 static uint32_t mmc_timing_to_dtr(struct mmc_ivars *ivar,
228 enum mmc_bus_timing timing);
229 static const char *mmc_timing_to_string(enum mmc_bus_timing timing);
230 static void mmc_update_child_list(struct mmc_softc *sc);
231 static int mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode,
232 uint32_t arg, uint32_t flags, uint32_t *resp, int retries);
233 static int mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req);
234 static void mmc_wakeup(struct mmc_request *req);
235
236 static void
mmc_ms_delay(int ms)237 mmc_ms_delay(int ms)
238 {
239
240 DELAY(1000 * ms); /* XXX BAD */
241 }
242
243 static int
mmc_probe(device_t dev)244 mmc_probe(device_t dev)
245 {
246
247 device_set_desc(dev, "MMC/SD bus");
248 return (0);
249 }
250
251 static int
mmc_attach(device_t dev)252 mmc_attach(device_t dev)
253 {
254 struct mmc_softc *sc;
255
256 sc = device_get_softc(dev);
257 sc->dev = dev;
258 MMC_LOCK_INIT(sc);
259
260 /* We'll probe and attach our children later, but before / mount */
261 sc->config_intrhook.ich_func = mmc_delayed_attach;
262 sc->config_intrhook.ich_arg = sc;
263 if (config_intrhook_establish(&sc->config_intrhook) != 0)
264 device_printf(dev, "config_intrhook_establish failed\n");
265 return (0);
266 }
267
268 static int
mmc_detach(device_t dev)269 mmc_detach(device_t dev)
270 {
271 struct mmc_softc *sc = device_get_softc(dev);
272 int err;
273
274 config_intrhook_drain(&sc->config_intrhook);
275 err = mmc_delete_cards(sc, true);
276 if (err != 0)
277 return (err);
278 mmc_power_down(sc);
279 MMC_LOCK_DESTROY(sc);
280
281 return (0);
282 }
283
284 static int
mmc_suspend(device_t dev)285 mmc_suspend(device_t dev)
286 {
287 struct mmc_softc *sc = device_get_softc(dev);
288 int err;
289
290 err = bus_generic_suspend(dev);
291 if (err != 0)
292 return (err);
293 /*
294 * We power down with the bus acquired here, mainly so that no device
295 * is selected any longer and sc->last_rca gets set to 0. Otherwise,
296 * the deselect as part of the bus acquisition in mmc_scan() may fail
297 * during resume, as the bus isn't powered up again before later in
298 * mmc_go_discovery().
299 */
300 err = mmc_acquire_bus(dev, dev);
301 if (err != 0)
302 return (err);
303 mmc_power_down(sc);
304 err = mmc_release_bus(dev, dev);
305 return (err);
306 }
307
308 static int
mmc_resume(device_t dev)309 mmc_resume(device_t dev)
310 {
311 struct mmc_softc *sc = device_get_softc(dev);
312
313 mmc_scan(sc);
314 return (bus_generic_resume(dev));
315 }
316
317 static int
mmc_acquire_bus(device_t busdev,device_t dev)318 mmc_acquire_bus(device_t busdev, device_t dev)
319 {
320 struct mmc_softc *sc;
321 struct mmc_ivars *ivar;
322 int err;
323 uint16_t rca;
324 enum mmc_bus_timing timing;
325
326 err = MMCBR_ACQUIRE_HOST(device_get_parent(busdev), busdev);
327 if (err)
328 return (err);
329 sc = device_get_softc(busdev);
330 MMC_LOCK(sc);
331 if (sc->owner)
332 panic("mmc: host bridge didn't serialize us.");
333 sc->owner = dev;
334 MMC_UNLOCK(sc);
335
336 if (busdev != dev) {
337 /*
338 * Keep track of the last rca that we've selected. If
339 * we're asked to do it again, don't. We never
340 * unselect unless the bus code itself wants the mmc
341 * bus, and constantly reselecting causes problems.
342 */
343 ivar = device_get_ivars(dev);
344 rca = ivar->rca;
345 if (sc->last_rca != rca) {
346 if (mmc_select_card(sc, rca) != MMC_ERR_NONE) {
347 device_printf(busdev, "Card at relative "
348 "address %d failed to select\n", rca);
349 return (ENXIO);
350 }
351 sc->last_rca = rca;
352 timing = mmcbr_get_timing(busdev);
353 /*
354 * For eMMC modes, setting/updating bus width and VCCQ
355 * only really is necessary if there actually is more
356 * than one device on the bus as generally that already
357 * had to be done by mmc_calculate_clock() or one of
358 * its calees. Moreover, setting the bus width anew
359 * can trigger re-tuning (via a CRC error on the next
360 * CMD), even if not switching between devices an the
361 * previously selected one is still tuned. Obviously,
362 * we need to re-tune the host controller if devices
363 * are actually switched, though.
364 */
365 if (timing >= bus_timing_mmc_ddr52 &&
366 sc->child_count == 1)
367 return (0);
368 /* Prepare bus width for the new card. */
369 if (bootverbose || mmc_debug) {
370 device_printf(busdev,
371 "setting bus width to %d bits %s timing\n",
372 (ivar->bus_width == bus_width_4) ? 4 :
373 (ivar->bus_width == bus_width_8) ? 8 : 1,
374 mmc_timing_to_string(timing));
375 }
376 if (mmc_set_card_bus_width(sc, ivar, timing) !=
377 MMC_ERR_NONE) {
378 device_printf(busdev, "Card at relative "
379 "address %d failed to set bus width\n",
380 rca);
381 return (ENXIO);
382 }
383 mmcbr_set_bus_width(busdev, ivar->bus_width);
384 mmcbr_update_ios(busdev);
385 if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) {
386 device_printf(busdev, "Failed to set VCCQ "
387 "for card at relative address %d\n", rca);
388 return (ENXIO);
389 }
390 if (timing >= bus_timing_mmc_hs200 &&
391 mmc_retune(busdev, dev, true) != 0) {
392 device_printf(busdev, "Card at relative "
393 "address %d failed to re-tune\n", rca);
394 return (ENXIO);
395 }
396 }
397 } else {
398 /*
399 * If there's a card selected, stand down.
400 */
401 if (sc->last_rca != 0) {
402 if (mmc_select_card(sc, 0) != MMC_ERR_NONE)
403 return (ENXIO);
404 sc->last_rca = 0;
405 }
406 }
407
408 return (0);
409 }
410
411 static int
mmc_release_bus(device_t busdev,device_t dev)412 mmc_release_bus(device_t busdev, device_t dev)
413 {
414 struct mmc_softc *sc;
415 int err;
416
417 sc = device_get_softc(busdev);
418
419 MMC_LOCK(sc);
420 if (!sc->owner)
421 panic("mmc: releasing unowned bus.");
422 if (sc->owner != dev)
423 panic("mmc: you don't own the bus. game over.");
424 MMC_UNLOCK(sc);
425 err = MMCBR_RELEASE_HOST(device_get_parent(busdev), busdev);
426 if (err)
427 return (err);
428 MMC_LOCK(sc);
429 sc->owner = NULL;
430 MMC_UNLOCK(sc);
431 return (0);
432 }
433
434 static uint32_t
mmc_select_vdd(struct mmc_softc * sc,uint32_t ocr)435 mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr)
436 {
437
438 return (ocr & MMC_OCR_VOLTAGE);
439 }
440
441 static int
mmc_highest_voltage(uint32_t ocr)442 mmc_highest_voltage(uint32_t ocr)
443 {
444 int i;
445
446 for (i = MMC_OCR_MAX_VOLTAGE_SHIFT;
447 i >= MMC_OCR_MIN_VOLTAGE_SHIFT; i--)
448 if (ocr & (1 << i))
449 return (i);
450 return (-1);
451 }
452
453 static void
mmc_wakeup(struct mmc_request * req)454 mmc_wakeup(struct mmc_request *req)
455 {
456 struct mmc_softc *sc;
457
458 sc = (struct mmc_softc *)req->done_data;
459 MMC_LOCK(sc);
460 req->flags |= MMC_REQ_DONE;
461 MMC_UNLOCK(sc);
462 wakeup(req);
463 }
464
465 static int
mmc_wait_for_req(struct mmc_softc * sc,struct mmc_request * req)466 mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req)
467 {
468
469 req->done = mmc_wakeup;
470 req->done_data = sc;
471 if (__predict_false(mmc_debug > 1)) {
472 device_printf(sc->dev, "REQUEST: CMD%d arg %#x flags %#x",
473 req->cmd->opcode, req->cmd->arg, req->cmd->flags);
474 if (req->cmd->data) {
475 printf(" data %d\n", (int)req->cmd->data->len);
476 } else
477 printf("\n");
478 }
479 MMCBR_REQUEST(device_get_parent(sc->dev), sc->dev, req);
480 MMC_LOCK(sc);
481 while ((req->flags & MMC_REQ_DONE) == 0)
482 msleep(req, &sc->sc_mtx, 0, "mmcreq", 0);
483 MMC_UNLOCK(sc);
484 if (__predict_false(mmc_debug > 2 || (mmc_debug > 0 &&
485 req->cmd->error != MMC_ERR_NONE)))
486 device_printf(sc->dev, "CMD%d RESULT: %d\n",
487 req->cmd->opcode, req->cmd->error);
488 return (0);
489 }
490
491 static int
mmc_wait_for_request(device_t busdev,device_t dev,struct mmc_request * req)492 mmc_wait_for_request(device_t busdev, device_t dev, struct mmc_request *req)
493 {
494 struct mmc_softc *sc;
495 struct mmc_ivars *ivar;
496 int err, i;
497 enum mmc_retune_req retune_req;
498
499 sc = device_get_softc(busdev);
500 KASSERT(sc->owner != NULL,
501 ("%s: Request from %s without bus being acquired.", __func__,
502 device_get_nameunit(dev)));
503
504 /*
505 * Unless no device is selected or re-tuning is already ongoing,
506 * execute re-tuning if a) the bridge is requesting to do so and
507 * re-tuning hasn't been otherwise paused, or b) if a child asked
508 * to be re-tuned prior to pausing (see also mmc_retune_pause()).
509 */
510 if (__predict_false(sc->last_rca != 0 && sc->retune_ongoing == 0 &&
511 (((retune_req = mmcbr_get_retune_req(busdev)) != retune_req_none &&
512 sc->retune_paused == 0) || sc->retune_needed == 1))) {
513 if (__predict_false(mmc_debug > 1)) {
514 device_printf(busdev,
515 "Re-tuning with%s circuit reset required\n",
516 retune_req == retune_req_reset ? "" : "out");
517 }
518 if (device_get_parent(dev) == busdev)
519 ivar = device_get_ivars(dev);
520 else {
521 for (i = 0; i < sc->child_count; i++) {
522 ivar = device_get_ivars(sc->child_list[i]);
523 if (ivar->rca == sc->last_rca)
524 break;
525 }
526 if (ivar->rca != sc->last_rca)
527 return (EINVAL);
528 }
529 sc->retune_ongoing = 1;
530 err = mmc_retune(busdev, dev, retune_req == retune_req_reset);
531 sc->retune_ongoing = 0;
532 switch (err) {
533 case MMC_ERR_NONE:
534 case MMC_ERR_FAILED: /* Re-tune error but still might work */
535 break;
536 case MMC_ERR_BADCRC: /* Switch failure on HS400 recovery */
537 return (ENXIO);
538 case MMC_ERR_INVALID: /* Driver implementation b0rken */
539 default: /* Unknown error, should not happen */
540 return (EINVAL);
541 }
542 sc->retune_needed = 0;
543 }
544 return (mmc_wait_for_req(sc, req));
545 }
546
547 static int
mmc_wait_for_command(struct mmc_softc * sc,uint32_t opcode,uint32_t arg,uint32_t flags,uint32_t * resp,int retries)548 mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode,
549 uint32_t arg, uint32_t flags, uint32_t *resp, int retries)
550 {
551 struct mmc_command cmd;
552 int err;
553
554 memset(&cmd, 0, sizeof(cmd));
555 cmd.opcode = opcode;
556 cmd.arg = arg;
557 cmd.flags = flags;
558 cmd.data = NULL;
559 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, retries);
560 if (err)
561 return (err);
562 if (resp) {
563 if (flags & MMC_RSP_136)
564 memcpy(resp, cmd.resp, 4 * sizeof(uint32_t));
565 else
566 *resp = cmd.resp[0];
567 }
568 return (0);
569 }
570
571 static void
mmc_idle_cards(struct mmc_softc * sc)572 mmc_idle_cards(struct mmc_softc *sc)
573 {
574 device_t dev;
575 struct mmc_command cmd;
576
577 dev = sc->dev;
578 mmcbr_set_chip_select(dev, cs_high);
579 mmcbr_update_ios(dev);
580 mmc_ms_delay(1);
581
582 memset(&cmd, 0, sizeof(cmd));
583 cmd.opcode = MMC_GO_IDLE_STATE;
584 cmd.arg = 0;
585 cmd.flags = MMC_RSP_NONE | MMC_CMD_BC;
586 cmd.data = NULL;
587 mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
588 mmc_ms_delay(1);
589
590 mmcbr_set_chip_select(dev, cs_dontcare);
591 mmcbr_update_ios(dev);
592 mmc_ms_delay(1);
593 }
594
595 static int
mmc_send_app_op_cond(struct mmc_softc * sc,uint32_t ocr,uint32_t * rocr)596 mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr)
597 {
598 struct mmc_command cmd;
599 int err = MMC_ERR_NONE, i;
600
601 memset(&cmd, 0, sizeof(cmd));
602 cmd.opcode = ACMD_SD_SEND_OP_COND;
603 cmd.arg = ocr;
604 cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR;
605 cmd.data = NULL;
606
607 for (i = 0; i < 1000; i++) {
608 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, 0, &cmd,
609 CMD_RETRIES);
610 if (err != MMC_ERR_NONE)
611 break;
612 if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) ||
613 (ocr & MMC_OCR_VOLTAGE) == 0)
614 break;
615 err = MMC_ERR_TIMEOUT;
616 mmc_ms_delay(10);
617 }
618 if (rocr && err == MMC_ERR_NONE)
619 *rocr = cmd.resp[0];
620 return (err);
621 }
622
623 static int
mmc_send_op_cond(struct mmc_softc * sc,uint32_t ocr,uint32_t * rocr)624 mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr)
625 {
626 struct mmc_command cmd;
627 int err = MMC_ERR_NONE, i;
628
629 memset(&cmd, 0, sizeof(cmd));
630 cmd.opcode = MMC_SEND_OP_COND;
631 cmd.arg = ocr;
632 cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR;
633 cmd.data = NULL;
634
635 for (i = 0; i < 1000; i++) {
636 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
637 if (err != MMC_ERR_NONE)
638 break;
639 if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) ||
640 (ocr & MMC_OCR_VOLTAGE) == 0)
641 break;
642 err = MMC_ERR_TIMEOUT;
643 mmc_ms_delay(10);
644 }
645 if (rocr && err == MMC_ERR_NONE)
646 *rocr = cmd.resp[0];
647 return (err);
648 }
649
650 static int
mmc_send_if_cond(struct mmc_softc * sc,uint8_t vhs)651 mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs)
652 {
653 struct mmc_command cmd;
654 int err;
655
656 memset(&cmd, 0, sizeof(cmd));
657 cmd.opcode = SD_SEND_IF_COND;
658 cmd.arg = (vhs << 8) + 0xAA;
659 cmd.flags = MMC_RSP_R7 | MMC_CMD_BCR;
660 cmd.data = NULL;
661
662 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
663 return (err);
664 }
665
666 static void
mmc_power_up(struct mmc_softc * sc)667 mmc_power_up(struct mmc_softc *sc)
668 {
669 device_t dev;
670 enum mmc_vccq vccq;
671
672 dev = sc->dev;
673 mmcbr_set_vdd(dev, mmc_highest_voltage(mmcbr_get_host_ocr(dev)));
674 mmcbr_set_bus_mode(dev, opendrain);
675 mmcbr_set_chip_select(dev, cs_dontcare);
676 mmcbr_set_bus_width(dev, bus_width_1);
677 mmcbr_set_power_mode(dev, power_up);
678 mmcbr_set_clock(dev, 0);
679 mmcbr_update_ios(dev);
680 for (vccq = vccq_330; ; vccq--) {
681 mmcbr_set_vccq(dev, vccq);
682 if (mmcbr_switch_vccq(dev) == 0 || vccq == vccq_120)
683 break;
684 }
685 mmc_ms_delay(1);
686
687 mmcbr_set_clock(dev, SD_MMC_CARD_ID_FREQUENCY);
688 mmcbr_set_timing(dev, bus_timing_normal);
689 mmcbr_set_power_mode(dev, power_on);
690 mmcbr_update_ios(dev);
691 mmc_ms_delay(2);
692 }
693
694 static void
mmc_power_down(struct mmc_softc * sc)695 mmc_power_down(struct mmc_softc *sc)
696 {
697 device_t dev = sc->dev;
698
699 mmcbr_set_bus_mode(dev, opendrain);
700 mmcbr_set_chip_select(dev, cs_dontcare);
701 mmcbr_set_bus_width(dev, bus_width_1);
702 mmcbr_set_power_mode(dev, power_off);
703 mmcbr_set_clock(dev, 0);
704 mmcbr_set_timing(dev, bus_timing_normal);
705 mmcbr_update_ios(dev);
706 }
707
708 static int
mmc_select_card(struct mmc_softc * sc,uint16_t rca)709 mmc_select_card(struct mmc_softc *sc, uint16_t rca)
710 {
711 int err, flags;
712
713 flags = (rca ? MMC_RSP_R1B : MMC_RSP_NONE) | MMC_CMD_AC;
714 sc->retune_paused++;
715 err = mmc_wait_for_command(sc, MMC_SELECT_CARD, (uint32_t)rca << 16,
716 flags, NULL, CMD_RETRIES);
717 sc->retune_paused--;
718 return (err);
719 }
720
721 static int
mmc_sd_switch(struct mmc_softc * sc,uint8_t mode,uint8_t grp,uint8_t value,uint8_t * res)722 mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp, uint8_t value,
723 uint8_t *res)
724 {
725 int err;
726 struct mmc_command cmd;
727 struct mmc_data data;
728
729 memset(&cmd, 0, sizeof(cmd));
730 memset(&data, 0, sizeof(data));
731 memset(res, 0, 64);
732
733 cmd.opcode = SD_SWITCH_FUNC;
734 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
735 cmd.arg = mode << 31; /* 0 - check, 1 - set */
736 cmd.arg |= 0x00FFFFFF;
737 cmd.arg &= ~(0xF << (grp * 4));
738 cmd.arg |= value << (grp * 4);
739 cmd.data = &data;
740
741 data.data = res;
742 data.len = 64;
743 data.flags = MMC_DATA_READ;
744
745 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
746 return (err);
747 }
748
749 static int
mmc_set_card_bus_width(struct mmc_softc * sc,struct mmc_ivars * ivar,enum mmc_bus_timing timing)750 mmc_set_card_bus_width(struct mmc_softc *sc, struct mmc_ivars *ivar,
751 enum mmc_bus_timing timing)
752 {
753 struct mmc_command cmd;
754 int err;
755 uint8_t value;
756
757 if (mmcbr_get_mode(sc->dev) == mode_sd) {
758 memset(&cmd, 0, sizeof(cmd));
759 cmd.opcode = ACMD_SET_CLR_CARD_DETECT;
760 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
761 cmd.arg = SD_CLR_CARD_DETECT;
762 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, ivar->rca, &cmd,
763 CMD_RETRIES);
764 if (err != 0)
765 return (err);
766 memset(&cmd, 0, sizeof(cmd));
767 cmd.opcode = ACMD_SET_BUS_WIDTH;
768 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
769 switch (ivar->bus_width) {
770 case bus_width_1:
771 cmd.arg = SD_BUS_WIDTH_1;
772 break;
773 case bus_width_4:
774 cmd.arg = SD_BUS_WIDTH_4;
775 break;
776 default:
777 return (MMC_ERR_INVALID);
778 }
779 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, ivar->rca, &cmd,
780 CMD_RETRIES);
781 } else {
782 switch (ivar->bus_width) {
783 case bus_width_1:
784 if (timing == bus_timing_mmc_hs400 ||
785 timing == bus_timing_mmc_hs400es)
786 return (MMC_ERR_INVALID);
787 value = EXT_CSD_BUS_WIDTH_1;
788 break;
789 case bus_width_4:
790 switch (timing) {
791 case bus_timing_mmc_ddr52:
792 value = EXT_CSD_BUS_WIDTH_4_DDR;
793 break;
794 case bus_timing_mmc_hs400:
795 case bus_timing_mmc_hs400es:
796 return (MMC_ERR_INVALID);
797 default:
798 value = EXT_CSD_BUS_WIDTH_4;
799 break;
800 }
801 break;
802 case bus_width_8:
803 value = 0;
804 switch (timing) {
805 case bus_timing_mmc_hs400es:
806 value = EXT_CSD_BUS_WIDTH_ES;
807 /* FALLTHROUGH */
808 case bus_timing_mmc_ddr52:
809 case bus_timing_mmc_hs400:
810 value |= EXT_CSD_BUS_WIDTH_8_DDR;
811 break;
812 default:
813 value = EXT_CSD_BUS_WIDTH_8;
814 break;
815 }
816 break;
817 default:
818 return (MMC_ERR_INVALID);
819 }
820 err = mmc_switch(sc->dev, sc->dev, ivar->rca,
821 EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, value,
822 ivar->cmd6_time, true);
823 }
824 return (err);
825 }
826
827 static int
mmc_set_power_class(struct mmc_softc * sc,struct mmc_ivars * ivar)828 mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar)
829 {
830 device_t dev;
831 const uint8_t *ext_csd;
832 uint32_t clock;
833 uint8_t value;
834 enum mmc_bus_timing timing;
835 enum mmc_bus_width bus_width;
836
837 dev = sc->dev;
838 timing = mmcbr_get_timing(dev);
839 bus_width = ivar->bus_width;
840 if (mmcbr_get_mode(dev) != mode_mmc || ivar->csd.spec_vers < 4 ||
841 timing == bus_timing_normal || bus_width == bus_width_1)
842 return (MMC_ERR_NONE);
843
844 value = 0;
845 ext_csd = ivar->raw_ext_csd;
846 clock = mmcbr_get_clock(dev);
847 switch (1 << mmcbr_get_vdd(dev)) {
848 case MMC_OCR_LOW_VOLTAGE:
849 if (clock <= MMC_TYPE_HS_26_MAX)
850 value = ext_csd[EXT_CSD_PWR_CL_26_195];
851 else if (clock <= MMC_TYPE_HS_52_MAX) {
852 if (timing >= bus_timing_mmc_ddr52 &&
853 bus_width >= bus_width_4)
854 value = ext_csd[EXT_CSD_PWR_CL_52_195_DDR];
855 else
856 value = ext_csd[EXT_CSD_PWR_CL_52_195];
857 } else if (clock <= MMC_TYPE_HS200_HS400ES_MAX)
858 value = ext_csd[EXT_CSD_PWR_CL_200_195];
859 break;
860 case MMC_OCR_270_280:
861 case MMC_OCR_280_290:
862 case MMC_OCR_290_300:
863 case MMC_OCR_300_310:
864 case MMC_OCR_310_320:
865 case MMC_OCR_320_330:
866 case MMC_OCR_330_340:
867 case MMC_OCR_340_350:
868 case MMC_OCR_350_360:
869 if (clock <= MMC_TYPE_HS_26_MAX)
870 value = ext_csd[EXT_CSD_PWR_CL_26_360];
871 else if (clock <= MMC_TYPE_HS_52_MAX) {
872 if (timing == bus_timing_mmc_ddr52 &&
873 bus_width >= bus_width_4)
874 value = ext_csd[EXT_CSD_PWR_CL_52_360_DDR];
875 else
876 value = ext_csd[EXT_CSD_PWR_CL_52_360];
877 } else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) {
878 if (bus_width == bus_width_8)
879 value = ext_csd[EXT_CSD_PWR_CL_200_360_DDR];
880 else
881 value = ext_csd[EXT_CSD_PWR_CL_200_360];
882 }
883 break;
884 default:
885 device_printf(dev, "No power class support for VDD 0x%x\n",
886 1 << mmcbr_get_vdd(dev));
887 return (MMC_ERR_INVALID);
888 }
889
890 if (bus_width == bus_width_8)
891 value = (value & EXT_CSD_POWER_CLASS_8BIT_MASK) >>
892 EXT_CSD_POWER_CLASS_8BIT_SHIFT;
893 else
894 value = (value & EXT_CSD_POWER_CLASS_4BIT_MASK) >>
895 EXT_CSD_POWER_CLASS_4BIT_SHIFT;
896
897 if (value == 0)
898 return (MMC_ERR_NONE);
899
900 return (mmc_switch(dev, dev, ivar->rca, EXT_CSD_CMD_SET_NORMAL,
901 EXT_CSD_POWER_CLASS, value, ivar->cmd6_time, true));
902 }
903
904 static int
mmc_set_timing(struct mmc_softc * sc,struct mmc_ivars * ivar,enum mmc_bus_timing timing)905 mmc_set_timing(struct mmc_softc *sc, struct mmc_ivars *ivar,
906 enum mmc_bus_timing timing)
907 {
908 u_char switch_res[64];
909 uint8_t value;
910 int err;
911
912 if (mmcbr_get_mode(sc->dev) == mode_sd) {
913 switch (timing) {
914 case bus_timing_normal:
915 value = SD_SWITCH_NORMAL_MODE;
916 break;
917 case bus_timing_hs:
918 value = SD_SWITCH_HS_MODE;
919 break;
920 default:
921 return (MMC_ERR_INVALID);
922 }
923 err = mmc_sd_switch(sc, SD_SWITCH_MODE_SET, SD_SWITCH_GROUP1,
924 value, switch_res);
925 if (err != MMC_ERR_NONE)
926 return (err);
927 if ((switch_res[16] & 0xf) != value)
928 return (MMC_ERR_FAILED);
929 mmcbr_set_timing(sc->dev, timing);
930 mmcbr_update_ios(sc->dev);
931 } else {
932 switch (timing) {
933 case bus_timing_normal:
934 value = EXT_CSD_HS_TIMING_BC;
935 break;
936 case bus_timing_hs:
937 case bus_timing_mmc_ddr52:
938 value = EXT_CSD_HS_TIMING_HS;
939 break;
940 case bus_timing_mmc_hs200:
941 value = EXT_CSD_HS_TIMING_HS200;
942 break;
943 case bus_timing_mmc_hs400:
944 case bus_timing_mmc_hs400es:
945 value = EXT_CSD_HS_TIMING_HS400;
946 break;
947 default:
948 return (MMC_ERR_INVALID);
949 }
950 err = mmc_switch(sc->dev, sc->dev, ivar->rca,
951 EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, value,
952 ivar->cmd6_time, false);
953 if (err != MMC_ERR_NONE)
954 return (err);
955 mmcbr_set_timing(sc->dev, timing);
956 mmcbr_update_ios(sc->dev);
957 err = mmc_switch_status(sc->dev, sc->dev, ivar->rca,
958 ivar->cmd6_time);
959 }
960 return (err);
961 }
962
963 static int
mmc_set_vccq(struct mmc_softc * sc,struct mmc_ivars * ivar,enum mmc_bus_timing timing)964 mmc_set_vccq(struct mmc_softc *sc, struct mmc_ivars *ivar,
965 enum mmc_bus_timing timing)
966 {
967
968 if (isset(&ivar->vccq_120, timing))
969 mmcbr_set_vccq(sc->dev, vccq_120);
970 else if (isset(&ivar->vccq_180, timing))
971 mmcbr_set_vccq(sc->dev, vccq_180);
972 else
973 mmcbr_set_vccq(sc->dev, vccq_330);
974 if (mmcbr_switch_vccq(sc->dev) != 0)
975 return (MMC_ERR_INVALID);
976 else
977 return (MMC_ERR_NONE);
978 }
979
980 static const uint8_t p8[8] = {
981 0x55, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
982 };
983
984 static const uint8_t p8ok[8] = {
985 0xAA, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
986 };
987
988 static const uint8_t p4[4] = {
989 0x5A, 0x00, 0x00, 0x00
990 };
991
992 static const uint8_t p4ok[4] = {
993 0xA5, 0x00, 0x00, 0x00
994 };
995
996 static int
mmc_test_bus_width(struct mmc_softc * sc)997 mmc_test_bus_width(struct mmc_softc *sc)
998 {
999 struct mmc_command cmd;
1000 struct mmc_data data;
1001 uint8_t buf[8];
1002 int err;
1003
1004 if (mmcbr_get_caps(sc->dev) & MMC_CAP_8_BIT_DATA) {
1005 mmcbr_set_bus_width(sc->dev, bus_width_8);
1006 mmcbr_update_ios(sc->dev);
1007
1008 sc->squelched++; /* Errors are expected, squelch reporting. */
1009 memset(&cmd, 0, sizeof(cmd));
1010 memset(&data, 0, sizeof(data));
1011 cmd.opcode = MMC_BUSTEST_W;
1012 cmd.arg = 0;
1013 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1014 cmd.data = &data;
1015
1016 data.data = __DECONST(void *, p8);
1017 data.len = 8;
1018 data.flags = MMC_DATA_WRITE;
1019 mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0);
1020
1021 memset(&cmd, 0, sizeof(cmd));
1022 memset(&data, 0, sizeof(data));
1023 cmd.opcode = MMC_BUSTEST_R;
1024 cmd.arg = 0;
1025 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1026 cmd.data = &data;
1027
1028 data.data = buf;
1029 data.len = 8;
1030 data.flags = MMC_DATA_READ;
1031 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0);
1032 sc->squelched--;
1033
1034 mmcbr_set_bus_width(sc->dev, bus_width_1);
1035 mmcbr_update_ios(sc->dev);
1036
1037 if (err == MMC_ERR_NONE && memcmp(buf, p8ok, 8) == 0)
1038 return (bus_width_8);
1039 }
1040
1041 if (mmcbr_get_caps(sc->dev) & MMC_CAP_4_BIT_DATA) {
1042 mmcbr_set_bus_width(sc->dev, bus_width_4);
1043 mmcbr_update_ios(sc->dev);
1044
1045 sc->squelched++; /* Errors are expected, squelch reporting. */
1046 memset(&cmd, 0, sizeof(cmd));
1047 memset(&data, 0, sizeof(data));
1048 cmd.opcode = MMC_BUSTEST_W;
1049 cmd.arg = 0;
1050 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1051 cmd.data = &data;
1052
1053 data.data = __DECONST(void *, p4);
1054 data.len = 4;
1055 data.flags = MMC_DATA_WRITE;
1056 mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0);
1057
1058 memset(&cmd, 0, sizeof(cmd));
1059 memset(&data, 0, sizeof(data));
1060 cmd.opcode = MMC_BUSTEST_R;
1061 cmd.arg = 0;
1062 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1063 cmd.data = &data;
1064
1065 data.data = buf;
1066 data.len = 4;
1067 data.flags = MMC_DATA_READ;
1068 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, 0);
1069 sc->squelched--;
1070
1071 mmcbr_set_bus_width(sc->dev, bus_width_1);
1072 mmcbr_update_ios(sc->dev);
1073
1074 if (err == MMC_ERR_NONE && memcmp(buf, p4ok, 4) == 0)
1075 return (bus_width_4);
1076 }
1077 return (bus_width_1);
1078 }
1079
1080 static uint32_t
mmc_get_bits(uint32_t * bits,int bit_len,int start,int size)1081 mmc_get_bits(uint32_t *bits, int bit_len, int start, int size)
1082 {
1083 const int i = (bit_len / 32) - (start / 32) - 1;
1084 const int shift = start & 31;
1085 uint32_t retval = bits[i] >> shift;
1086
1087 if (size + shift > 32)
1088 retval |= bits[i - 1] << (32 - shift);
1089 return (retval & ((1llu << size) - 1));
1090 }
1091
1092 static void
mmc_decode_cid_sd(uint32_t * raw_cid,struct mmc_cid * cid)1093 mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid)
1094 {
1095 int i;
1096
1097 /* There's no version info, so we take it on faith */
1098 memset(cid, 0, sizeof(*cid));
1099 cid->mid = mmc_get_bits(raw_cid, 128, 120, 8);
1100 cid->oid = mmc_get_bits(raw_cid, 128, 104, 16);
1101 for (i = 0; i < 5; i++)
1102 cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8);
1103 cid->pnm[5] = 0;
1104 cid->prv = mmc_get_bits(raw_cid, 128, 56, 8);
1105 cid->psn = mmc_get_bits(raw_cid, 128, 24, 32);
1106 cid->mdt_year = mmc_get_bits(raw_cid, 128, 12, 8) + 2000;
1107 cid->mdt_month = mmc_get_bits(raw_cid, 128, 8, 4);
1108 }
1109
1110 static void
mmc_decode_cid_mmc(uint32_t * raw_cid,struct mmc_cid * cid,bool is_4_41p)1111 mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid, bool is_4_41p)
1112 {
1113 int i;
1114
1115 /* There's no version info, so we take it on faith */
1116 memset(cid, 0, sizeof(*cid));
1117 cid->mid = mmc_get_bits(raw_cid, 128, 120, 8);
1118 cid->oid = mmc_get_bits(raw_cid, 128, 104, 8);
1119 for (i = 0; i < 6; i++)
1120 cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8);
1121 cid->pnm[6] = 0;
1122 cid->prv = mmc_get_bits(raw_cid, 128, 48, 8);
1123 cid->psn = mmc_get_bits(raw_cid, 128, 16, 32);
1124 cid->mdt_month = mmc_get_bits(raw_cid, 128, 12, 4);
1125 cid->mdt_year = mmc_get_bits(raw_cid, 128, 8, 4);
1126 if (is_4_41p)
1127 cid->mdt_year += 2013;
1128 else
1129 cid->mdt_year += 1997;
1130 }
1131
1132 static void
mmc_format_card_id_string(struct mmc_ivars * ivar)1133 mmc_format_card_id_string(struct mmc_ivars *ivar)
1134 {
1135 char oidstr[8];
1136 uint8_t c1;
1137 uint8_t c2;
1138
1139 /*
1140 * Format a card ID string for use by the mmcsd driver, it's what
1141 * appears between the <> in the following:
1142 * mmcsd0: 968MB <SD SD01G 8.0 SN 2686905 MFG 08/2008 by 3 TN> at mmc0
1143 * 22.5MHz/4bit/128-block
1144 *
1145 * Also format just the card serial number, which the mmcsd driver will
1146 * use as the disk->d_ident string.
1147 *
1148 * The card_id_string in mmc_ivars is currently allocated as 64 bytes,
1149 * and our max formatted length is currently 55 bytes if every field
1150 * contains the largest value.
1151 *
1152 * Sometimes the oid is two printable ascii chars; when it's not,
1153 * format it as 0xnnnn instead.
1154 */
1155 c1 = (ivar->cid.oid >> 8) & 0x0ff;
1156 c2 = ivar->cid.oid & 0x0ff;
1157 if (c1 > 0x1f && c1 < 0x7f && c2 > 0x1f && c2 < 0x7f)
1158 snprintf(oidstr, sizeof(oidstr), "%c%c", c1, c2);
1159 else
1160 snprintf(oidstr, sizeof(oidstr), "0x%04x", ivar->cid.oid);
1161 snprintf(ivar->card_sn_string, sizeof(ivar->card_sn_string),
1162 "%08X", ivar->cid.psn);
1163 snprintf(ivar->card_id_string, sizeof(ivar->card_id_string),
1164 "%s%s %s %d.%d SN %08X MFG %02d/%04d by %d %s",
1165 ivar->mode == mode_sd ? "SD" : "MMC", ivar->high_cap ? "HC" : "",
1166 ivar->cid.pnm, ivar->cid.prv >> 4, ivar->cid.prv & 0x0f,
1167 ivar->cid.psn, ivar->cid.mdt_month, ivar->cid.mdt_year,
1168 ivar->cid.mid, oidstr);
1169 }
1170
1171 static const int exp[8] = {
1172 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000
1173 };
1174
1175 static const int mant[16] = {
1176 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80
1177 };
1178
1179 static const int cur_min[8] = {
1180 500, 1000, 5000, 10000, 25000, 35000, 60000, 100000
1181 };
1182
1183 static const int cur_max[8] = {
1184 1000, 5000, 10000, 25000, 35000, 45000, 800000, 200000
1185 };
1186
1187 static int
mmc_decode_csd_sd(uint32_t * raw_csd,struct mmc_csd * csd)1188 mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd)
1189 {
1190 int v;
1191 int m;
1192 int e;
1193
1194 memset(csd, 0, sizeof(*csd));
1195 csd->csd_structure = v = mmc_get_bits(raw_csd, 128, 126, 2);
1196 if (v == 0) {
1197 m = mmc_get_bits(raw_csd, 128, 115, 4);
1198 e = mmc_get_bits(raw_csd, 128, 112, 3);
1199 csd->tacc = (exp[e] * mant[m] + 9) / 10;
1200 csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100;
1201 m = mmc_get_bits(raw_csd, 128, 99, 4);
1202 e = mmc_get_bits(raw_csd, 128, 96, 3);
1203 csd->tran_speed = exp[e] * 10000 * mant[m];
1204 csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12);
1205 csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4);
1206 csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1);
1207 csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1);
1208 csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1);
1209 csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1);
1210 csd->vdd_r_curr_min =
1211 cur_min[mmc_get_bits(raw_csd, 128, 59, 3)];
1212 csd->vdd_r_curr_max =
1213 cur_max[mmc_get_bits(raw_csd, 128, 56, 3)];
1214 csd->vdd_w_curr_min =
1215 cur_min[mmc_get_bits(raw_csd, 128, 53, 3)];
1216 csd->vdd_w_curr_max =
1217 cur_max[mmc_get_bits(raw_csd, 128, 50, 3)];
1218 m = mmc_get_bits(raw_csd, 128, 62, 12);
1219 e = mmc_get_bits(raw_csd, 128, 47, 3);
1220 csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len;
1221 csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1);
1222 csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1;
1223 csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7);
1224 csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1);
1225 csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3);
1226 csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4);
1227 csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1);
1228 return (MMC_ERR_NONE);
1229 } else if (v == 1) {
1230 m = mmc_get_bits(raw_csd, 128, 115, 4);
1231 e = mmc_get_bits(raw_csd, 128, 112, 3);
1232 csd->tacc = (exp[e] * mant[m] + 9) / 10;
1233 csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100;
1234 m = mmc_get_bits(raw_csd, 128, 99, 4);
1235 e = mmc_get_bits(raw_csd, 128, 96, 3);
1236 csd->tran_speed = exp[e] * 10000 * mant[m];
1237 csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12);
1238 csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4);
1239 csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1);
1240 csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1);
1241 csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1);
1242 csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1);
1243 csd->capacity = ((uint64_t)mmc_get_bits(raw_csd, 128, 48, 22) +
1244 1) * 512 * 1024;
1245 csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1);
1246 csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1;
1247 csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7);
1248 csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1);
1249 csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3);
1250 csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4);
1251 csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1);
1252 return (MMC_ERR_NONE);
1253 }
1254 return (MMC_ERR_INVALID);
1255 }
1256
1257 static void
mmc_decode_csd_mmc(uint32_t * raw_csd,struct mmc_csd * csd)1258 mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd)
1259 {
1260 int m;
1261 int e;
1262
1263 memset(csd, 0, sizeof(*csd));
1264 csd->csd_structure = mmc_get_bits(raw_csd, 128, 126, 2);
1265 csd->spec_vers = mmc_get_bits(raw_csd, 128, 122, 4);
1266 m = mmc_get_bits(raw_csd, 128, 115, 4);
1267 e = mmc_get_bits(raw_csd, 128, 112, 3);
1268 csd->tacc = exp[e] * mant[m] + 9 / 10;
1269 csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100;
1270 m = mmc_get_bits(raw_csd, 128, 99, 4);
1271 e = mmc_get_bits(raw_csd, 128, 96, 3);
1272 csd->tran_speed = exp[e] * 10000 * mant[m];
1273 csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12);
1274 csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4);
1275 csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1);
1276 csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1);
1277 csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1);
1278 csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1);
1279 csd->vdd_r_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 59, 3)];
1280 csd->vdd_r_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 56, 3)];
1281 csd->vdd_w_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 53, 3)];
1282 csd->vdd_w_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 50, 3)];
1283 m = mmc_get_bits(raw_csd, 128, 62, 12);
1284 e = mmc_get_bits(raw_csd, 128, 47, 3);
1285 csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len;
1286 csd->erase_blk_en = 0;
1287 csd->erase_sector = (mmc_get_bits(raw_csd, 128, 42, 5) + 1) *
1288 (mmc_get_bits(raw_csd, 128, 37, 5) + 1);
1289 csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 5);
1290 csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1);
1291 csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3);
1292 csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4);
1293 csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1);
1294 }
1295
1296 static void
mmc_app_decode_scr(uint32_t * raw_scr,struct mmc_scr * scr)1297 mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr)
1298 {
1299 unsigned int scr_struct;
1300
1301 memset(scr, 0, sizeof(*scr));
1302
1303 scr_struct = mmc_get_bits(raw_scr, 64, 60, 4);
1304 if (scr_struct != 0) {
1305 printf("Unrecognised SCR structure version %d\n",
1306 scr_struct);
1307 return;
1308 }
1309 scr->sda_vsn = mmc_get_bits(raw_scr, 64, 56, 4);
1310 scr->bus_widths = mmc_get_bits(raw_scr, 64, 48, 4);
1311 }
1312
1313 static void
mmc_app_decode_sd_status(uint32_t * raw_sd_status,struct mmc_sd_status * sd_status)1314 mmc_app_decode_sd_status(uint32_t *raw_sd_status,
1315 struct mmc_sd_status *sd_status)
1316 {
1317
1318 memset(sd_status, 0, sizeof(*sd_status));
1319
1320 sd_status->bus_width = mmc_get_bits(raw_sd_status, 512, 510, 2);
1321 sd_status->secured_mode = mmc_get_bits(raw_sd_status, 512, 509, 1);
1322 sd_status->card_type = mmc_get_bits(raw_sd_status, 512, 480, 16);
1323 sd_status->prot_area = mmc_get_bits(raw_sd_status, 512, 448, 12);
1324 sd_status->speed_class = mmc_get_bits(raw_sd_status, 512, 440, 8);
1325 sd_status->perf_move = mmc_get_bits(raw_sd_status, 512, 432, 8);
1326 sd_status->au_size = mmc_get_bits(raw_sd_status, 512, 428, 4);
1327 sd_status->erase_size = mmc_get_bits(raw_sd_status, 512, 408, 16);
1328 sd_status->erase_timeout = mmc_get_bits(raw_sd_status, 512, 402, 6);
1329 sd_status->erase_offset = mmc_get_bits(raw_sd_status, 512, 400, 2);
1330 }
1331
1332 static int
mmc_all_send_cid(struct mmc_softc * sc,uint32_t * rawcid)1333 mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid)
1334 {
1335 struct mmc_command cmd;
1336 int err;
1337
1338 memset(&cmd, 0, sizeof(cmd));
1339 cmd.opcode = MMC_ALL_SEND_CID;
1340 cmd.arg = 0;
1341 cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR;
1342 cmd.data = NULL;
1343 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
1344 memcpy(rawcid, cmd.resp, 4 * sizeof(uint32_t));
1345 return (err);
1346 }
1347
1348 static int
mmc_send_csd(struct mmc_softc * sc,uint16_t rca,uint32_t * rawcsd)1349 mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd)
1350 {
1351 struct mmc_command cmd;
1352 int err;
1353
1354 memset(&cmd, 0, sizeof(cmd));
1355 cmd.opcode = MMC_SEND_CSD;
1356 cmd.arg = rca << 16;
1357 cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR;
1358 cmd.data = NULL;
1359 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
1360 memcpy(rawcsd, cmd.resp, 4 * sizeof(uint32_t));
1361 return (err);
1362 }
1363
1364 static int
mmc_app_send_scr(struct mmc_softc * sc,uint16_t rca,uint32_t * rawscr)1365 mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, uint32_t *rawscr)
1366 {
1367 int err;
1368 struct mmc_command cmd;
1369 struct mmc_data data;
1370
1371 memset(&cmd, 0, sizeof(cmd));
1372 memset(&data, 0, sizeof(data));
1373
1374 memset(rawscr, 0, 8);
1375 cmd.opcode = ACMD_SEND_SCR;
1376 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1377 cmd.arg = 0;
1378 cmd.data = &data;
1379
1380 data.data = rawscr;
1381 data.len = 8;
1382 data.flags = MMC_DATA_READ;
1383
1384 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, rca, &cmd, CMD_RETRIES);
1385 rawscr[0] = be32toh(rawscr[0]);
1386 rawscr[1] = be32toh(rawscr[1]);
1387 return (err);
1388 }
1389
1390 static int
mmc_app_sd_status(struct mmc_softc * sc,uint16_t rca,uint32_t * rawsdstatus)1391 mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus)
1392 {
1393 struct mmc_command cmd;
1394 struct mmc_data data;
1395 int err, i;
1396
1397 memset(&cmd, 0, sizeof(cmd));
1398 memset(&data, 0, sizeof(data));
1399
1400 memset(rawsdstatus, 0, 64);
1401 cmd.opcode = ACMD_SD_STATUS;
1402 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1403 cmd.arg = 0;
1404 cmd.data = &data;
1405
1406 data.data = rawsdstatus;
1407 data.len = 64;
1408 data.flags = MMC_DATA_READ;
1409
1410 err = mmc_wait_for_app_cmd(sc->dev, sc->dev, rca, &cmd, CMD_RETRIES);
1411 for (i = 0; i < 16; i++)
1412 rawsdstatus[i] = be32toh(rawsdstatus[i]);
1413 return (err);
1414 }
1415
1416 static int
mmc_set_relative_addr(struct mmc_softc * sc,uint16_t resp)1417 mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp)
1418 {
1419 struct mmc_command cmd;
1420 int err;
1421
1422 memset(&cmd, 0, sizeof(cmd));
1423 cmd.opcode = MMC_SET_RELATIVE_ADDR;
1424 cmd.arg = resp << 16;
1425 cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR;
1426 cmd.data = NULL;
1427 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
1428 return (err);
1429 }
1430
1431 static int
mmc_send_relative_addr(struct mmc_softc * sc,uint32_t * resp)1432 mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp)
1433 {
1434 struct mmc_command cmd;
1435 int err;
1436
1437 memset(&cmd, 0, sizeof(cmd));
1438 cmd.opcode = SD_SEND_RELATIVE_ADDR;
1439 cmd.arg = 0;
1440 cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR;
1441 cmd.data = NULL;
1442 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
1443 *resp = cmd.resp[0];
1444 return (err);
1445 }
1446
1447 static int
mmc_set_blocklen(struct mmc_softc * sc,uint32_t len)1448 mmc_set_blocklen(struct mmc_softc *sc, uint32_t len)
1449 {
1450 struct mmc_command cmd;
1451 int err;
1452
1453 memset(&cmd, 0, sizeof(cmd));
1454 cmd.opcode = MMC_SET_BLOCKLEN;
1455 cmd.arg = len;
1456 cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
1457 cmd.data = NULL;
1458 err = mmc_wait_for_cmd(sc->dev, sc->dev, &cmd, CMD_RETRIES);
1459 return (err);
1460 }
1461
1462 static uint32_t
mmc_timing_to_dtr(struct mmc_ivars * ivar,enum mmc_bus_timing timing)1463 mmc_timing_to_dtr(struct mmc_ivars *ivar, enum mmc_bus_timing timing)
1464 {
1465
1466 switch (timing) {
1467 case bus_timing_normal:
1468 return (ivar->tran_speed);
1469 case bus_timing_hs:
1470 return (ivar->hs_tran_speed);
1471 case bus_timing_uhs_sdr12:
1472 return (SD_SDR12_MAX);
1473 case bus_timing_uhs_sdr25:
1474 return (SD_SDR25_MAX);
1475 case bus_timing_uhs_ddr50:
1476 return (SD_DDR50_MAX);
1477 case bus_timing_uhs_sdr50:
1478 return (SD_SDR50_MAX);
1479 case bus_timing_uhs_sdr104:
1480 return (SD_SDR104_MAX);
1481 case bus_timing_mmc_ddr52:
1482 return (MMC_TYPE_DDR52_MAX);
1483 case bus_timing_mmc_hs200:
1484 case bus_timing_mmc_hs400:
1485 case bus_timing_mmc_hs400es:
1486 return (MMC_TYPE_HS200_HS400ES_MAX);
1487 }
1488 return (0);
1489 }
1490
1491 static const char *
mmc_timing_to_string(enum mmc_bus_timing timing)1492 mmc_timing_to_string(enum mmc_bus_timing timing)
1493 {
1494
1495 switch (timing) {
1496 case bus_timing_normal:
1497 return ("normal speed");
1498 case bus_timing_hs:
1499 return ("high speed");
1500 case bus_timing_uhs_sdr12:
1501 case bus_timing_uhs_sdr25:
1502 case bus_timing_uhs_sdr50:
1503 case bus_timing_uhs_sdr104:
1504 return ("single data rate");
1505 case bus_timing_uhs_ddr50:
1506 case bus_timing_mmc_ddr52:
1507 return ("dual data rate");
1508 case bus_timing_mmc_hs200:
1509 return ("HS200");
1510 case bus_timing_mmc_hs400:
1511 return ("HS400");
1512 case bus_timing_mmc_hs400es:
1513 return ("HS400 with enhanced strobe");
1514 }
1515 return ("");
1516 }
1517
1518 static bool
mmc_host_timing(device_t dev,enum mmc_bus_timing timing)1519 mmc_host_timing(device_t dev, enum mmc_bus_timing timing)
1520 {
1521 int host_caps;
1522
1523 host_caps = mmcbr_get_caps(dev);
1524
1525 #define HOST_TIMING_CAP(host_caps, cap) ({ \
1526 bool retval; \
1527 if (((host_caps) & (cap)) == (cap)) \
1528 retval = true; \
1529 else \
1530 retval = false; \
1531 retval; \
1532 })
1533
1534 switch (timing) {
1535 case bus_timing_normal:
1536 return (true);
1537 case bus_timing_hs:
1538 return (HOST_TIMING_CAP(host_caps, MMC_CAP_HSPEED));
1539 case bus_timing_uhs_sdr12:
1540 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR12));
1541 case bus_timing_uhs_sdr25:
1542 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR25));
1543 case bus_timing_uhs_ddr50:
1544 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_DDR50));
1545 case bus_timing_uhs_sdr50:
1546 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR50));
1547 case bus_timing_uhs_sdr104:
1548 return (HOST_TIMING_CAP(host_caps, MMC_CAP_UHS_SDR104));
1549 case bus_timing_mmc_ddr52:
1550 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_DDR52));
1551 case bus_timing_mmc_hs200:
1552 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS200_120) ||
1553 HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS200_180));
1554 case bus_timing_mmc_hs400:
1555 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400_120) ||
1556 HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400_180));
1557 case bus_timing_mmc_hs400es:
1558 return (HOST_TIMING_CAP(host_caps, MMC_CAP_MMC_HS400 |
1559 MMC_CAP_MMC_ENH_STROBE));
1560 }
1561
1562 #undef HOST_TIMING_CAP
1563
1564 return (false);
1565 }
1566
1567 static void
mmc_log_card(device_t dev,struct mmc_ivars * ivar,int newcard)1568 mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard)
1569 {
1570 enum mmc_bus_timing timing;
1571
1572 device_printf(dev, "Card at relative address 0x%04x%s:\n",
1573 ivar->rca, newcard ? " added" : "");
1574 device_printf(dev, " card: %s\n", ivar->card_id_string);
1575 for (timing = bus_timing_max; timing > bus_timing_normal; timing--) {
1576 if (isset(&ivar->timings, timing))
1577 break;
1578 }
1579 device_printf(dev, " quirks: %b\n", ivar->quirks, MMC_QUIRKS_FMT);
1580 device_printf(dev, " bus: %ubit, %uMHz (%s timing)\n",
1581 (ivar->bus_width == bus_width_1 ? 1 :
1582 (ivar->bus_width == bus_width_4 ? 4 : 8)),
1583 mmc_timing_to_dtr(ivar, timing) / 1000000,
1584 mmc_timing_to_string(timing));
1585 device_printf(dev, " memory: %u blocks, erase sector %u blocks%s\n",
1586 ivar->sec_count, ivar->erase_sector,
1587 ivar->read_only ? ", read-only" : "");
1588 }
1589
1590 static void
mmc_discover_cards(struct mmc_softc * sc)1591 mmc_discover_cards(struct mmc_softc *sc)
1592 {
1593 u_char switch_res[64];
1594 uint32_t raw_cid[4];
1595 struct mmc_ivars *ivar = NULL;
1596 const struct mmc_quirk *quirk;
1597 const uint8_t *ext_csd;
1598 device_t child;
1599 int err, host_caps, i, newcard;
1600 uint32_t resp, sec_count, status;
1601 uint16_t rca = 2;
1602 int16_t rev;
1603 uint8_t card_type;
1604
1605 host_caps = mmcbr_get_caps(sc->dev);
1606 if (bootverbose || mmc_debug)
1607 device_printf(sc->dev, "Probing cards\n");
1608 while (1) {
1609 child = NULL;
1610 sc->squelched++; /* Errors are expected, squelch reporting. */
1611 err = mmc_all_send_cid(sc, raw_cid);
1612 sc->squelched--;
1613 if (err == MMC_ERR_TIMEOUT)
1614 break;
1615 if (err != MMC_ERR_NONE) {
1616 device_printf(sc->dev, "Error reading CID %d\n", err);
1617 break;
1618 }
1619 newcard = 1;
1620 for (i = 0; i < sc->child_count; i++) {
1621 ivar = device_get_ivars(sc->child_list[i]);
1622 if (memcmp(ivar->raw_cid, raw_cid, sizeof(raw_cid)) ==
1623 0) {
1624 newcard = 0;
1625 break;
1626 }
1627 }
1628 if (bootverbose || mmc_debug) {
1629 device_printf(sc->dev,
1630 "%sard detected (CID %08x%08x%08x%08x)\n",
1631 newcard ? "New c" : "C",
1632 raw_cid[0], raw_cid[1], raw_cid[2], raw_cid[3]);
1633 }
1634 if (newcard) {
1635 ivar = malloc(sizeof(struct mmc_ivars), M_DEVBUF,
1636 M_WAITOK | M_ZERO);
1637 memcpy(ivar->raw_cid, raw_cid, sizeof(raw_cid));
1638 }
1639 if (mmcbr_get_ro(sc->dev))
1640 ivar->read_only = 1;
1641 ivar->bus_width = bus_width_1;
1642 setbit(&ivar->timings, bus_timing_normal);
1643 ivar->mode = mmcbr_get_mode(sc->dev);
1644 if (ivar->mode == mode_sd) {
1645 mmc_decode_cid_sd(ivar->raw_cid, &ivar->cid);
1646 err = mmc_send_relative_addr(sc, &resp);
1647 if (err != MMC_ERR_NONE) {
1648 device_printf(sc->dev,
1649 "Error getting RCA %d\n", err);
1650 goto free_ivar;
1651 }
1652 ivar->rca = resp >> 16;
1653 /* Get card CSD. */
1654 err = mmc_send_csd(sc, ivar->rca, ivar->raw_csd);
1655 if (err != MMC_ERR_NONE) {
1656 device_printf(sc->dev,
1657 "Error getting CSD %d\n", err);
1658 goto free_ivar;
1659 }
1660 if (bootverbose || mmc_debug)
1661 device_printf(sc->dev,
1662 "%sard detected (CSD %08x%08x%08x%08x)\n",
1663 newcard ? "New c" : "C", ivar->raw_csd[0],
1664 ivar->raw_csd[1], ivar->raw_csd[2],
1665 ivar->raw_csd[3]);
1666 err = mmc_decode_csd_sd(ivar->raw_csd, &ivar->csd);
1667 if (err != MMC_ERR_NONE) {
1668 device_printf(sc->dev, "Error decoding CSD\n");
1669 goto free_ivar;
1670 }
1671 ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE;
1672 if (ivar->csd.csd_structure > 0)
1673 ivar->high_cap = 1;
1674 ivar->tran_speed = ivar->csd.tran_speed;
1675 ivar->erase_sector = ivar->csd.erase_sector *
1676 ivar->csd.write_bl_len / MMC_SECTOR_SIZE;
1677
1678 err = mmc_send_status(sc->dev, sc->dev, ivar->rca,
1679 &status);
1680 if (err != MMC_ERR_NONE) {
1681 device_printf(sc->dev,
1682 "Error reading card status %d\n", err);
1683 goto free_ivar;
1684 }
1685 if ((status & R1_CARD_IS_LOCKED) != 0) {
1686 device_printf(sc->dev,
1687 "Card is password protected, skipping\n");
1688 goto free_ivar;
1689 }
1690
1691 /* Get card SCR. Card must be selected to fetch it. */
1692 err = mmc_select_card(sc, ivar->rca);
1693 if (err != MMC_ERR_NONE) {
1694 device_printf(sc->dev,
1695 "Error selecting card %d\n", err);
1696 goto free_ivar;
1697 }
1698 err = mmc_app_send_scr(sc, ivar->rca, ivar->raw_scr);
1699 if (err != MMC_ERR_NONE) {
1700 device_printf(sc->dev,
1701 "Error reading SCR %d\n", err);
1702 goto free_ivar;
1703 }
1704 mmc_app_decode_scr(ivar->raw_scr, &ivar->scr);
1705 /* Get card switch capabilities (command class 10). */
1706 if ((ivar->scr.sda_vsn >= 1) &&
1707 (ivar->csd.ccc & (1 << 10))) {
1708 err = mmc_sd_switch(sc, SD_SWITCH_MODE_CHECK,
1709 SD_SWITCH_GROUP1, SD_SWITCH_NOCHANGE,
1710 switch_res);
1711 if (err == MMC_ERR_NONE &&
1712 switch_res[13] & (1 << SD_SWITCH_HS_MODE)) {
1713 setbit(&ivar->timings, bus_timing_hs);
1714 ivar->hs_tran_speed = SD_HS_MAX;
1715 }
1716 }
1717
1718 /*
1719 * We deselect then reselect the card here. Some cards
1720 * become unselected and timeout with the above two
1721 * commands, although the state tables / diagrams in the
1722 * standard suggest they go back to the transfer state.
1723 * Other cards don't become deselected, and if we
1724 * attempt to blindly re-select them, we get timeout
1725 * errors from some controllers. So we deselect then
1726 * reselect to handle all situations. The only thing we
1727 * use from the sd_status is the erase sector size, but
1728 * it is still nice to get that right.
1729 */
1730 (void)mmc_select_card(sc, 0);
1731 (void)mmc_select_card(sc, ivar->rca);
1732 (void)mmc_app_sd_status(sc, ivar->rca,
1733 ivar->raw_sd_status);
1734 mmc_app_decode_sd_status(ivar->raw_sd_status,
1735 &ivar->sd_status);
1736 if (ivar->sd_status.au_size != 0) {
1737 ivar->erase_sector =
1738 16 << ivar->sd_status.au_size;
1739 }
1740 /* Find maximum supported bus width. */
1741 if ((host_caps & MMC_CAP_4_BIT_DATA) &&
1742 (ivar->scr.bus_widths & SD_SCR_BUS_WIDTH_4))
1743 ivar->bus_width = bus_width_4;
1744
1745 goto child_common;
1746 }
1747 ivar->rca = rca++;
1748 err = mmc_set_relative_addr(sc, ivar->rca);
1749 if (err != MMC_ERR_NONE) {
1750 device_printf(sc->dev, "Error setting RCA %d\n", err);
1751 goto free_ivar;
1752 }
1753 /* Get card CSD. */
1754 err = mmc_send_csd(sc, ivar->rca, ivar->raw_csd);
1755 if (err != MMC_ERR_NONE) {
1756 device_printf(sc->dev, "Error getting CSD %d\n", err);
1757 goto free_ivar;
1758 }
1759 if (bootverbose || mmc_debug)
1760 device_printf(sc->dev,
1761 "%sard detected (CSD %08x%08x%08x%08x)\n",
1762 newcard ? "New c" : "C", ivar->raw_csd[0],
1763 ivar->raw_csd[1], ivar->raw_csd[2],
1764 ivar->raw_csd[3]);
1765
1766 mmc_decode_csd_mmc(ivar->raw_csd, &ivar->csd);
1767 ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE;
1768 ivar->tran_speed = ivar->csd.tran_speed;
1769 ivar->erase_sector = ivar->csd.erase_sector *
1770 ivar->csd.write_bl_len / MMC_SECTOR_SIZE;
1771
1772 err = mmc_send_status(sc->dev, sc->dev, ivar->rca, &status);
1773 if (err != MMC_ERR_NONE) {
1774 device_printf(sc->dev,
1775 "Error reading card status %d\n", err);
1776 goto free_ivar;
1777 }
1778 if ((status & R1_CARD_IS_LOCKED) != 0) {
1779 device_printf(sc->dev,
1780 "Card is password protected, skipping\n");
1781 goto free_ivar;
1782 }
1783
1784 err = mmc_select_card(sc, ivar->rca);
1785 if (err != MMC_ERR_NONE) {
1786 device_printf(sc->dev, "Error selecting card %d\n",
1787 err);
1788 goto free_ivar;
1789 }
1790
1791 rev = -1;
1792 /* Only MMC >= 4.x devices support EXT_CSD. */
1793 if (ivar->csd.spec_vers >= 4) {
1794 err = mmc_send_ext_csd(sc->dev, sc->dev,
1795 ivar->raw_ext_csd);
1796 if (err != MMC_ERR_NONE) {
1797 device_printf(sc->dev,
1798 "Error reading EXT_CSD %d\n", err);
1799 goto free_ivar;
1800 }
1801 ext_csd = ivar->raw_ext_csd;
1802 rev = ext_csd[EXT_CSD_REV];
1803 /* Handle extended capacity from EXT_CSD */
1804 sec_count = le32dec(&ext_csd[EXT_CSD_SEC_CNT]);
1805 if (sec_count != 0) {
1806 ivar->sec_count = sec_count;
1807 ivar->high_cap = 1;
1808 }
1809 /* Find maximum supported bus width. */
1810 ivar->bus_width = mmc_test_bus_width(sc);
1811 /* Get device speeds beyond normal mode. */
1812 card_type = ext_csd[EXT_CSD_CARD_TYPE];
1813 if ((card_type & EXT_CSD_CARD_TYPE_HS_52) != 0) {
1814 setbit(&ivar->timings, bus_timing_hs);
1815 ivar->hs_tran_speed = MMC_TYPE_HS_52_MAX;
1816 } else if ((card_type & EXT_CSD_CARD_TYPE_HS_26) != 0) {
1817 setbit(&ivar->timings, bus_timing_hs);
1818 ivar->hs_tran_speed = MMC_TYPE_HS_26_MAX;
1819 }
1820 if ((card_type & EXT_CSD_CARD_TYPE_DDR_52_1_2V) != 0 &&
1821 (host_caps & MMC_CAP_SIGNALING_120) != 0) {
1822 setbit(&ivar->timings, bus_timing_mmc_ddr52);
1823 setbit(&ivar->vccq_120, bus_timing_mmc_ddr52);
1824 }
1825 if ((card_type & EXT_CSD_CARD_TYPE_DDR_52_1_8V) != 0 &&
1826 (host_caps & MMC_CAP_SIGNALING_180) != 0) {
1827 setbit(&ivar->timings, bus_timing_mmc_ddr52);
1828 setbit(&ivar->vccq_180, bus_timing_mmc_ddr52);
1829 }
1830 if ((card_type & EXT_CSD_CARD_TYPE_HS200_1_2V) != 0 &&
1831 (host_caps & MMC_CAP_SIGNALING_120) != 0) {
1832 setbit(&ivar->timings, bus_timing_mmc_hs200);
1833 setbit(&ivar->vccq_120, bus_timing_mmc_hs200);
1834 }
1835 if ((card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) != 0 &&
1836 (host_caps & MMC_CAP_SIGNALING_180) != 0) {
1837 setbit(&ivar->timings, bus_timing_mmc_hs200);
1838 setbit(&ivar->vccq_180, bus_timing_mmc_hs200);
1839 }
1840 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_2V) != 0 &&
1841 (host_caps & MMC_CAP_SIGNALING_120) != 0 &&
1842 ivar->bus_width == bus_width_8) {
1843 setbit(&ivar->timings, bus_timing_mmc_hs400);
1844 setbit(&ivar->vccq_120, bus_timing_mmc_hs400);
1845 }
1846 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) != 0 &&
1847 (host_caps & MMC_CAP_SIGNALING_180) != 0 &&
1848 ivar->bus_width == bus_width_8) {
1849 setbit(&ivar->timings, bus_timing_mmc_hs400);
1850 setbit(&ivar->vccq_180, bus_timing_mmc_hs400);
1851 }
1852 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_2V) != 0 &&
1853 (ext_csd[EXT_CSD_STROBE_SUPPORT] &
1854 EXT_CSD_STROBE_SUPPORT_EN) != 0 &&
1855 (host_caps & MMC_CAP_SIGNALING_120) != 0 &&
1856 ivar->bus_width == bus_width_8) {
1857 setbit(&ivar->timings, bus_timing_mmc_hs400es);
1858 setbit(&ivar->vccq_120, bus_timing_mmc_hs400es);
1859 }
1860 if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) != 0 &&
1861 (ext_csd[EXT_CSD_STROBE_SUPPORT] &
1862 EXT_CSD_STROBE_SUPPORT_EN) != 0 &&
1863 (host_caps & MMC_CAP_SIGNALING_180) != 0 &&
1864 ivar->bus_width == bus_width_8) {
1865 setbit(&ivar->timings, bus_timing_mmc_hs400es);
1866 setbit(&ivar->vccq_180, bus_timing_mmc_hs400es);
1867 }
1868 /*
1869 * Determine generic switch timeout (provided in
1870 * units of 10 ms), defaulting to 500 ms.
1871 */
1872 ivar->cmd6_time = 500 * 1000;
1873 if (rev >= 6)
1874 ivar->cmd6_time = 10 *
1875 ext_csd[EXT_CSD_GEN_CMD6_TIME];
1876 /* Handle HC erase sector size. */
1877 if (ext_csd[EXT_CSD_ERASE_GRP_SIZE] != 0) {
1878 ivar->erase_sector = 1024 *
1879 ext_csd[EXT_CSD_ERASE_GRP_SIZE];
1880 err = mmc_switch(sc->dev, sc->dev, ivar->rca,
1881 EXT_CSD_CMD_SET_NORMAL,
1882 EXT_CSD_ERASE_GRP_DEF,
1883 EXT_CSD_ERASE_GRP_DEF_EN,
1884 ivar->cmd6_time, true);
1885 if (err != MMC_ERR_NONE) {
1886 device_printf(sc->dev,
1887 "Error setting erase group %d\n",
1888 err);
1889 goto free_ivar;
1890 }
1891 }
1892 }
1893
1894 mmc_decode_cid_mmc(ivar->raw_cid, &ivar->cid, rev >= 5);
1895
1896 child_common:
1897 for (quirk = &mmc_quirks[0]; quirk->mid != 0x0; quirk++) {
1898 if ((quirk->mid == MMC_QUIRK_MID_ANY ||
1899 quirk->mid == ivar->cid.mid) &&
1900 (quirk->oid == MMC_QUIRK_OID_ANY ||
1901 quirk->oid == ivar->cid.oid) &&
1902 strncmp(quirk->pnm, ivar->cid.pnm,
1903 sizeof(ivar->cid.pnm)) == 0) {
1904 ivar->quirks = quirk->quirks;
1905 break;
1906 }
1907 }
1908
1909 /*
1910 * Some cards that report maximum I/O block sizes greater
1911 * than 512 require the block length to be set to 512, even
1912 * though that is supposed to be the default. Example:
1913 *
1914 * Transcend 2GB SDSC card, CID:
1915 * mid=0x1b oid=0x534d pnm="00000" prv=1.0 mdt=00.2000
1916 */
1917 if (ivar->csd.read_bl_len != MMC_SECTOR_SIZE ||
1918 ivar->csd.write_bl_len != MMC_SECTOR_SIZE)
1919 mmc_set_blocklen(sc, MMC_SECTOR_SIZE);
1920
1921 mmc_format_card_id_string(ivar);
1922
1923 if (bootverbose || mmc_debug)
1924 mmc_log_card(sc->dev, ivar, newcard);
1925 if (newcard) {
1926 /* Add device. */
1927 child = device_add_child(sc->dev, NULL, -1);
1928 if (child != NULL) {
1929 device_set_ivars(child, ivar);
1930 sc->child_list = realloc(sc->child_list,
1931 sizeof(device_t) * (sc->child_count + 1),
1932 M_DEVBUF, M_WAITOK);
1933 sc->child_list[sc->child_count++] = child;
1934 } else
1935 device_printf(sc->dev, "Error adding child\n");
1936 }
1937
1938 free_ivar:
1939 if (newcard && child == NULL)
1940 free(ivar, M_DEVBUF);
1941 (void)mmc_select_card(sc, 0);
1942 /*
1943 * Not returning here when one MMC device could no be added
1944 * potentially would mean looping forever when that device
1945 * is broken (in which case it also may impact the remainder
1946 * of the bus anyway, though).
1947 */
1948 if ((newcard && child == NULL) ||
1949 mmcbr_get_mode(sc->dev) == mode_sd)
1950 return;
1951 }
1952 }
1953
1954 static void
mmc_update_child_list(struct mmc_softc * sc)1955 mmc_update_child_list(struct mmc_softc *sc)
1956 {
1957 device_t child;
1958 int i, j;
1959
1960 if (sc->child_count == 0) {
1961 free(sc->child_list, M_DEVBUF);
1962 return;
1963 }
1964 for (i = j = 0; i < sc->child_count; i++) {
1965 for (;;) {
1966 child = sc->child_list[j++];
1967 if (child != NULL)
1968 break;
1969 }
1970 if (i != j)
1971 sc->child_list[i] = child;
1972 }
1973 sc->child_list = realloc(sc->child_list, sizeof(device_t) *
1974 sc->child_count, M_DEVBUF, M_WAITOK);
1975 }
1976
1977 static void
mmc_rescan_cards(struct mmc_softc * sc)1978 mmc_rescan_cards(struct mmc_softc *sc)
1979 {
1980 struct mmc_ivars *ivar;
1981 int err, i, j;
1982
1983 for (i = j = 0; i < sc->child_count; i++) {
1984 ivar = device_get_ivars(sc->child_list[i]);
1985 if (mmc_select_card(sc, ivar->rca) != MMC_ERR_NONE) {
1986 if (bootverbose || mmc_debug)
1987 device_printf(sc->dev,
1988 "Card at relative address %d lost\n",
1989 ivar->rca);
1990 err = device_delete_child(sc->dev, sc->child_list[i]);
1991 if (err != 0) {
1992 j++;
1993 continue;
1994 }
1995 free(ivar, M_DEVBUF);
1996 } else
1997 j++;
1998 }
1999 if (sc->child_count == j)
2000 goto out;
2001 sc->child_count = j;
2002 mmc_update_child_list(sc);
2003 out:
2004 (void)mmc_select_card(sc, 0);
2005 }
2006
2007 static int
mmc_delete_cards(struct mmc_softc * sc,bool final)2008 mmc_delete_cards(struct mmc_softc *sc, bool final)
2009 {
2010 struct mmc_ivars *ivar;
2011 int err, i, j;
2012
2013 err = 0;
2014 for (i = j = 0; i < sc->child_count; i++) {
2015 ivar = device_get_ivars(sc->child_list[i]);
2016 if (bootverbose || mmc_debug)
2017 device_printf(sc->dev,
2018 "Card at relative address %d deleted\n",
2019 ivar->rca);
2020 err = device_delete_child(sc->dev, sc->child_list[i]);
2021 if (err != 0) {
2022 j++;
2023 if (final == false)
2024 continue;
2025 else
2026 break;
2027 }
2028 free(ivar, M_DEVBUF);
2029 }
2030 sc->child_count = j;
2031 mmc_update_child_list(sc);
2032 return (err);
2033 }
2034
2035 static void
mmc_go_discovery(struct mmc_softc * sc)2036 mmc_go_discovery(struct mmc_softc *sc)
2037 {
2038 uint32_t ocr;
2039 device_t dev;
2040 int err;
2041
2042 dev = sc->dev;
2043 if (mmcbr_get_power_mode(dev) != power_on) {
2044 /*
2045 * First, try SD modes
2046 */
2047 sc->squelched++; /* Errors are expected, squelch reporting. */
2048 mmcbr_set_mode(dev, mode_sd);
2049 mmc_power_up(sc);
2050 mmcbr_set_bus_mode(dev, pushpull);
2051 if (bootverbose || mmc_debug)
2052 device_printf(sc->dev, "Probing bus\n");
2053 mmc_idle_cards(sc);
2054 err = mmc_send_if_cond(sc, 1);
2055 if ((bootverbose || mmc_debug) && err == 0)
2056 device_printf(sc->dev,
2057 "SD 2.0 interface conditions: OK\n");
2058 if (mmc_send_app_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) {
2059 if (bootverbose || mmc_debug)
2060 device_printf(sc->dev, "SD probe: failed\n");
2061 /*
2062 * Failed, try MMC
2063 */
2064 mmcbr_set_mode(dev, mode_mmc);
2065 if (mmc_send_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) {
2066 if (bootverbose || mmc_debug)
2067 device_printf(sc->dev,
2068 "MMC probe: failed\n");
2069 ocr = 0; /* Failed both, powerdown. */
2070 } else if (bootverbose || mmc_debug)
2071 device_printf(sc->dev,
2072 "MMC probe: OK (OCR: 0x%08x)\n", ocr);
2073 } else if (bootverbose || mmc_debug)
2074 device_printf(sc->dev, "SD probe: OK (OCR: 0x%08x)\n",
2075 ocr);
2076 sc->squelched--;
2077
2078 mmcbr_set_ocr(dev, mmc_select_vdd(sc, ocr));
2079 if (mmcbr_get_ocr(dev) != 0)
2080 mmc_idle_cards(sc);
2081 } else {
2082 mmcbr_set_bus_mode(dev, opendrain);
2083 mmcbr_set_clock(dev, SD_MMC_CARD_ID_FREQUENCY);
2084 mmcbr_update_ios(dev);
2085 /* XXX recompute vdd based on new cards? */
2086 }
2087 /*
2088 * Make sure that we have a mutually agreeable voltage to at least
2089 * one card on the bus.
2090 */
2091 if (bootverbose || mmc_debug)
2092 device_printf(sc->dev, "Current OCR: 0x%08x\n",
2093 mmcbr_get_ocr(dev));
2094 if (mmcbr_get_ocr(dev) == 0) {
2095 device_printf(sc->dev, "No compatible cards found on bus\n");
2096 (void)mmc_delete_cards(sc, false);
2097 mmc_power_down(sc);
2098 return;
2099 }
2100 /*
2101 * Reselect the cards after we've idled them above.
2102 */
2103 if (mmcbr_get_mode(dev) == mode_sd) {
2104 err = mmc_send_if_cond(sc, 1);
2105 mmc_send_app_op_cond(sc,
2106 (err ? 0 : MMC_OCR_CCS) | mmcbr_get_ocr(dev), NULL);
2107 } else
2108 mmc_send_op_cond(sc, MMC_OCR_CCS | mmcbr_get_ocr(dev), NULL);
2109 mmc_discover_cards(sc);
2110 mmc_rescan_cards(sc);
2111
2112 mmcbr_set_bus_mode(dev, pushpull);
2113 mmcbr_update_ios(dev);
2114 mmc_calculate_clock(sc);
2115 }
2116
2117 static int
mmc_calculate_clock(struct mmc_softc * sc)2118 mmc_calculate_clock(struct mmc_softc *sc)
2119 {
2120 device_t dev;
2121 struct mmc_ivars *ivar;
2122 int i;
2123 uint32_t dtr, max_dtr;
2124 uint16_t rca;
2125 enum mmc_bus_timing max_timing, timing;
2126 bool changed, hs400;
2127
2128 dev = sc->dev;
2129 max_dtr = mmcbr_get_f_max(dev);
2130 max_timing = bus_timing_max;
2131 do {
2132 changed = false;
2133 for (i = 0; i < sc->child_count; i++) {
2134 ivar = device_get_ivars(sc->child_list[i]);
2135 if (isclr(&ivar->timings, max_timing) ||
2136 !mmc_host_timing(dev, max_timing)) {
2137 for (timing = max_timing - 1; timing >=
2138 bus_timing_normal; timing--) {
2139 if (isset(&ivar->timings, timing) &&
2140 mmc_host_timing(dev, timing)) {
2141 max_timing = timing;
2142 break;
2143 }
2144 }
2145 changed = true;
2146 }
2147 dtr = mmc_timing_to_dtr(ivar, max_timing);
2148 if (dtr < max_dtr) {
2149 max_dtr = dtr;
2150 changed = true;
2151 }
2152 }
2153 } while (changed == true);
2154
2155 if (bootverbose || mmc_debug) {
2156 device_printf(dev,
2157 "setting transfer rate to %d.%03dMHz (%s timing)\n",
2158 max_dtr / 1000000, (max_dtr / 1000) % 1000,
2159 mmc_timing_to_string(max_timing));
2160 }
2161
2162 /*
2163 * HS400 must be tuned in HS200 mode, so in case of HS400 we begin
2164 * with HS200 following the sequence as described in "6.6.2.2 HS200
2165 * timing mode selection" of the eMMC specification v5.1, too, and
2166 * switch to max_timing later. HS400ES requires no tuning and, thus,
2167 * can be switch to directly, but requires the same detour via high
2168 * speed mode as does HS400 (see mmc_switch_to_hs400()).
2169 */
2170 hs400 = max_timing == bus_timing_mmc_hs400;
2171 timing = hs400 == true ? bus_timing_mmc_hs200 : max_timing;
2172 for (i = 0; i < sc->child_count; i++) {
2173 ivar = device_get_ivars(sc->child_list[i]);
2174 if ((ivar->timings & ~(1 << bus_timing_normal)) == 0)
2175 goto clock;
2176
2177 rca = ivar->rca;
2178 if (mmc_select_card(sc, rca) != MMC_ERR_NONE) {
2179 device_printf(dev, "Card at relative address %d "
2180 "failed to select\n", rca);
2181 continue;
2182 }
2183
2184 if (timing == bus_timing_mmc_hs200 || /* includes HS400 */
2185 timing == bus_timing_mmc_hs400es) {
2186 if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) {
2187 device_printf(dev, "Failed to set VCCQ for "
2188 "card at relative address %d\n", rca);
2189 continue;
2190 }
2191 }
2192
2193 if (timing == bus_timing_mmc_hs200) { /* includes HS400 */
2194 /* Set bus width (required for initial tuning). */
2195 if (mmc_set_card_bus_width(sc, ivar, timing) !=
2196 MMC_ERR_NONE) {
2197 device_printf(dev, "Card at relative address "
2198 "%d failed to set bus width\n", rca);
2199 continue;
2200 }
2201 mmcbr_set_bus_width(dev, ivar->bus_width);
2202 mmcbr_update_ios(dev);
2203 } else if (timing == bus_timing_mmc_hs400es) {
2204 if (mmc_switch_to_hs400(sc, ivar, max_dtr, timing) !=
2205 MMC_ERR_NONE) {
2206 device_printf(dev, "Card at relative address "
2207 "%d failed to set %s timing\n", rca,
2208 mmc_timing_to_string(timing));
2209 continue;
2210 }
2211 goto power_class;
2212 }
2213
2214 if (mmc_set_timing(sc, ivar, timing) != MMC_ERR_NONE) {
2215 device_printf(dev, "Card at relative address %d "
2216 "failed to set %s timing\n", rca,
2217 mmc_timing_to_string(timing));
2218 continue;
2219 }
2220
2221 if (timing == bus_timing_mmc_ddr52) {
2222 /*
2223 * Set EXT_CSD_BUS_WIDTH_n_DDR in EXT_CSD_BUS_WIDTH
2224 * (must be done after switching to EXT_CSD_HS_TIMING).
2225 */
2226 if (mmc_set_card_bus_width(sc, ivar, timing) !=
2227 MMC_ERR_NONE) {
2228 device_printf(dev, "Card at relative address "
2229 "%d failed to set bus width\n", rca);
2230 continue;
2231 }
2232 mmcbr_set_bus_width(dev, ivar->bus_width);
2233 mmcbr_update_ios(dev);
2234 if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) {
2235 device_printf(dev, "Failed to set VCCQ for "
2236 "card at relative address %d\n", rca);
2237 continue;
2238 }
2239 }
2240
2241 clock:
2242 /* Set clock (must be done before initial tuning). */
2243 mmcbr_set_clock(dev, max_dtr);
2244 mmcbr_update_ios(dev);
2245
2246 if (mmcbr_tune(dev, hs400) != 0) {
2247 device_printf(dev, "Card at relative address %d "
2248 "failed to execute initial tuning\n", rca);
2249 continue;
2250 }
2251
2252 if (hs400 == true && mmc_switch_to_hs400(sc, ivar, max_dtr,
2253 max_timing) != MMC_ERR_NONE) {
2254 device_printf(dev, "Card at relative address %d "
2255 "failed to set %s timing\n", rca,
2256 mmc_timing_to_string(max_timing));
2257 continue;
2258 }
2259
2260 power_class:
2261 if (mmc_set_power_class(sc, ivar) != MMC_ERR_NONE) {
2262 device_printf(dev, "Card at relative address %d "
2263 "failed to set power class\n", rca);
2264 }
2265 }
2266 (void)mmc_select_card(sc, 0);
2267 return (max_dtr);
2268 }
2269
2270 /*
2271 * Switch from HS200 to HS400 (either initially or for re-tuning) or directly
2272 * to HS400ES. This follows the sequences described in "6.6.2.3 HS400 timing
2273 * mode selection" of the eMMC specification v5.1.
2274 */
2275 static int
mmc_switch_to_hs400(struct mmc_softc * sc,struct mmc_ivars * ivar,uint32_t clock,enum mmc_bus_timing max_timing)2276 mmc_switch_to_hs400(struct mmc_softc *sc, struct mmc_ivars *ivar,
2277 uint32_t clock, enum mmc_bus_timing max_timing)
2278 {
2279 device_t dev;
2280 int err;
2281 uint16_t rca;
2282
2283 dev = sc->dev;
2284 rca = ivar->rca;
2285
2286 /*
2287 * Both clock and timing must be set as appropriate for high speed
2288 * before eventually switching to HS400/HS400ES; mmc_set_timing()
2289 * will issue mmcbr_update_ios().
2290 */
2291 mmcbr_set_clock(dev, ivar->hs_tran_speed);
2292 err = mmc_set_timing(sc, ivar, bus_timing_hs);
2293 if (err != MMC_ERR_NONE)
2294 return (err);
2295
2296 /*
2297 * Set EXT_CSD_BUS_WIDTH_8_DDR in EXT_CSD_BUS_WIDTH (and additionally
2298 * EXT_CSD_BUS_WIDTH_ES for HS400ES).
2299 */
2300 err = mmc_set_card_bus_width(sc, ivar, max_timing);
2301 if (err != MMC_ERR_NONE)
2302 return (err);
2303 mmcbr_set_bus_width(dev, ivar->bus_width);
2304 mmcbr_update_ios(dev);
2305
2306 /* Finally, switch to HS400/HS400ES mode. */
2307 err = mmc_set_timing(sc, ivar, max_timing);
2308 if (err != MMC_ERR_NONE)
2309 return (err);
2310 mmcbr_set_clock(dev, clock);
2311 mmcbr_update_ios(dev);
2312 return (MMC_ERR_NONE);
2313 }
2314
2315 /*
2316 * Switch from HS400 to HS200 (for re-tuning).
2317 */
2318 static int
mmc_switch_to_hs200(struct mmc_softc * sc,struct mmc_ivars * ivar,uint32_t clock)2319 mmc_switch_to_hs200(struct mmc_softc *sc, struct mmc_ivars *ivar,
2320 uint32_t clock)
2321 {
2322 device_t dev;
2323 int err;
2324 uint16_t rca;
2325
2326 dev = sc->dev;
2327 rca = ivar->rca;
2328
2329 /*
2330 * Both clock and timing must initially be set as appropriate for
2331 * DDR52 before eventually switching to HS200; mmc_set_timing()
2332 * will issue mmcbr_update_ios().
2333 */
2334 mmcbr_set_clock(dev, ivar->hs_tran_speed);
2335 err = mmc_set_timing(sc, ivar, bus_timing_mmc_ddr52);
2336 if (err != MMC_ERR_NONE)
2337 return (err);
2338
2339 /*
2340 * Next, switch to high speed. Thus, clear EXT_CSD_BUS_WIDTH_n_DDR
2341 * in EXT_CSD_BUS_WIDTH and update bus width and timing in ios.
2342 */
2343 err = mmc_set_card_bus_width(sc, ivar, bus_timing_hs);
2344 if (err != MMC_ERR_NONE)
2345 return (err);
2346 mmcbr_set_bus_width(dev, ivar->bus_width);
2347 mmcbr_set_timing(sc->dev, bus_timing_hs);
2348 mmcbr_update_ios(dev);
2349
2350 /* Finally, switch to HS200 mode. */
2351 err = mmc_set_timing(sc, ivar, bus_timing_mmc_hs200);
2352 if (err != MMC_ERR_NONE)
2353 return (err);
2354 mmcbr_set_clock(dev, clock);
2355 mmcbr_update_ios(dev);
2356 return (MMC_ERR_NONE);
2357 }
2358
2359 static int
mmc_retune(device_t busdev,device_t dev,bool reset)2360 mmc_retune(device_t busdev, device_t dev, bool reset)
2361 {
2362 struct mmc_softc *sc;
2363 struct mmc_ivars *ivar;
2364 int err;
2365 uint32_t clock;
2366 enum mmc_bus_timing timing;
2367
2368 if (device_get_parent(dev) != busdev)
2369 return (MMC_ERR_INVALID);
2370
2371 sc = device_get_softc(busdev);
2372 if (sc->retune_needed != 1 && sc->retune_paused != 0)
2373 return (MMC_ERR_INVALID);
2374
2375 timing = mmcbr_get_timing(busdev);
2376 if (timing == bus_timing_mmc_hs400) {
2377 /*
2378 * Controllers use the data strobe line to latch data from
2379 * the devices in HS400 mode so periodic re-tuning isn't
2380 * expected to be required, i. e. only if a CRC or tuning
2381 * error is signaled to the bridge. In these latter cases
2382 * we are asked to reset the tuning circuit and need to do
2383 * the switch timing dance.
2384 */
2385 if (reset == false)
2386 return (0);
2387 ivar = device_get_ivars(dev);
2388 clock = mmcbr_get_clock(busdev);
2389 if (mmc_switch_to_hs200(sc, ivar, clock) != MMC_ERR_NONE)
2390 return (MMC_ERR_BADCRC);
2391 }
2392 err = mmcbr_retune(busdev, reset);
2393 if (err != 0 && timing == bus_timing_mmc_hs400)
2394 return (MMC_ERR_BADCRC);
2395 switch (err) {
2396 case 0:
2397 break;
2398 case EIO:
2399 return (MMC_ERR_FAILED);
2400 default:
2401 return (MMC_ERR_INVALID);
2402 }
2403 if (timing == bus_timing_mmc_hs400) {
2404 if (mmc_switch_to_hs400(sc, ivar, clock, timing) !=
2405 MMC_ERR_NONE)
2406 return (MMC_ERR_BADCRC);
2407 }
2408 return (MMC_ERR_NONE);
2409 }
2410
2411 static void
mmc_retune_pause(device_t busdev,device_t dev,bool retune)2412 mmc_retune_pause(device_t busdev, device_t dev, bool retune)
2413 {
2414 struct mmc_softc *sc;
2415
2416 sc = device_get_softc(busdev);
2417 KASSERT(device_get_parent(dev) == busdev,
2418 ("%s: %s is not a child of %s", __func__, device_get_nameunit(dev),
2419 device_get_nameunit(busdev)));
2420 KASSERT(sc->owner != NULL,
2421 ("%s: Request from %s without bus being acquired.", __func__,
2422 device_get_nameunit(dev)));
2423
2424 if (retune == true && sc->retune_paused == 0)
2425 sc->retune_needed = 1;
2426 sc->retune_paused++;
2427 }
2428
2429 static void
mmc_retune_unpause(device_t busdev,device_t dev)2430 mmc_retune_unpause(device_t busdev, device_t dev)
2431 {
2432 struct mmc_softc *sc;
2433
2434 sc = device_get_softc(busdev);
2435 KASSERT(device_get_parent(dev) == busdev,
2436 ("%s: %s is not a child of %s", __func__, device_get_nameunit(dev),
2437 device_get_nameunit(busdev)));
2438 KASSERT(sc->owner != NULL,
2439 ("%s: Request from %s without bus being acquired.", __func__,
2440 device_get_nameunit(dev)));
2441 KASSERT(sc->retune_paused != 0,
2442 ("%s: Re-tune pause count already at 0", __func__));
2443
2444 sc->retune_paused--;
2445 }
2446
2447 static void
mmc_scan(struct mmc_softc * sc)2448 mmc_scan(struct mmc_softc *sc)
2449 {
2450 device_t dev = sc->dev;
2451 int err;
2452
2453 err = mmc_acquire_bus(dev, dev);
2454 if (err != 0) {
2455 device_printf(dev, "Failed to acquire bus for scanning\n");
2456 return;
2457 }
2458 mmc_go_discovery(sc);
2459 err = mmc_release_bus(dev, dev);
2460 if (err != 0) {
2461 device_printf(dev, "Failed to release bus after scanning\n");
2462 return;
2463 }
2464 (void)bus_generic_attach(dev);
2465 }
2466
2467 static int
mmc_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)2468 mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
2469 {
2470 struct mmc_ivars *ivar = device_get_ivars(child);
2471
2472 switch (which) {
2473 default:
2474 return (EINVAL);
2475 case MMC_IVAR_SPEC_VERS:
2476 *result = ivar->csd.spec_vers;
2477 break;
2478 case MMC_IVAR_DSR_IMP:
2479 *result = ivar->csd.dsr_imp;
2480 break;
2481 case MMC_IVAR_MEDIA_SIZE:
2482 *result = ivar->sec_count;
2483 break;
2484 case MMC_IVAR_RCA:
2485 *result = ivar->rca;
2486 break;
2487 case MMC_IVAR_SECTOR_SIZE:
2488 *result = MMC_SECTOR_SIZE;
2489 break;
2490 case MMC_IVAR_TRAN_SPEED:
2491 *result = mmcbr_get_clock(bus);
2492 break;
2493 case MMC_IVAR_READ_ONLY:
2494 *result = ivar->read_only;
2495 break;
2496 case MMC_IVAR_HIGH_CAP:
2497 *result = ivar->high_cap;
2498 break;
2499 case MMC_IVAR_CARD_TYPE:
2500 *result = ivar->mode;
2501 break;
2502 case MMC_IVAR_BUS_WIDTH:
2503 *result = ivar->bus_width;
2504 break;
2505 case MMC_IVAR_ERASE_SECTOR:
2506 *result = ivar->erase_sector;
2507 break;
2508 case MMC_IVAR_MAX_DATA:
2509 *result = mmcbr_get_max_data(bus);
2510 break;
2511 case MMC_IVAR_CMD6_TIMEOUT:
2512 *result = ivar->cmd6_time;
2513 break;
2514 case MMC_IVAR_QUIRKS:
2515 *result = ivar->quirks;
2516 break;
2517 case MMC_IVAR_CARD_ID_STRING:
2518 *(char **)result = ivar->card_id_string;
2519 break;
2520 case MMC_IVAR_CARD_SN_STRING:
2521 *(char **)result = ivar->card_sn_string;
2522 break;
2523 }
2524 return (0);
2525 }
2526
2527 static int
mmc_write_ivar(device_t bus,device_t child,int which,uintptr_t value)2528 mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
2529 {
2530
2531 /*
2532 * None are writable ATM
2533 */
2534 return (EINVAL);
2535 }
2536
2537 static void
mmc_delayed_attach(void * xsc)2538 mmc_delayed_attach(void *xsc)
2539 {
2540 struct mmc_softc *sc = xsc;
2541
2542 mmc_scan(sc);
2543 config_intrhook_disestablish(&sc->config_intrhook);
2544 }
2545
2546 static int
mmc_child_location_str(device_t dev,device_t child,char * buf,size_t buflen)2547 mmc_child_location_str(device_t dev, device_t child, char *buf,
2548 size_t buflen)
2549 {
2550
2551 snprintf(buf, buflen, "rca=0x%04x", mmc_get_rca(child));
2552 return (0);
2553 }
2554
2555 static device_method_t mmc_methods[] = {
2556 /* device_if */
2557 DEVMETHOD(device_probe, mmc_probe),
2558 DEVMETHOD(device_attach, mmc_attach),
2559 DEVMETHOD(device_detach, mmc_detach),
2560 DEVMETHOD(device_suspend, mmc_suspend),
2561 DEVMETHOD(device_resume, mmc_resume),
2562
2563 /* Bus interface */
2564 DEVMETHOD(bus_read_ivar, mmc_read_ivar),
2565 DEVMETHOD(bus_write_ivar, mmc_write_ivar),
2566 DEVMETHOD(bus_child_location_str, mmc_child_location_str),
2567
2568 /* MMC Bus interface */
2569 DEVMETHOD(mmcbus_retune_pause, mmc_retune_pause),
2570 DEVMETHOD(mmcbus_retune_unpause, mmc_retune_unpause),
2571 DEVMETHOD(mmcbus_wait_for_request, mmc_wait_for_request),
2572 DEVMETHOD(mmcbus_acquire_bus, mmc_acquire_bus),
2573 DEVMETHOD(mmcbus_release_bus, mmc_release_bus),
2574
2575 DEVMETHOD_END
2576 };
2577
2578 driver_t mmc_driver = {
2579 "mmc",
2580 mmc_methods,
2581 sizeof(struct mmc_softc),
2582 };
2583 devclass_t mmc_devclass;
2584
2585 MODULE_VERSION(mmc, MMC_VERSION);
2586