1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
4 */
5
6 #include <stddef.h>
7 #include <unistd.h>
8 #include <string.h>
9 #include <stdint.h>
10 #include <stdlib.h>
11 #include <errno.h>
12
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
16 #include <rte_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
32
33 #include "mlx5_defs.h"
34 #include "mlx5.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_mr.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
41
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
44
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
47
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
50
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
53
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
56
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
59
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
62
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
65
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
68
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
71
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
74
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
77
78 /*
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
81 */
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
83
84 /*
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
87 */
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
89
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
92
93 /*
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
96 */
97 #define MLX5_TX_DB_NC "tx_db_nc"
98
99 /*
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
102 */
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
104
105 /*
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
108 */
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
110
111 /*
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
114 */
115 #define MLX5_TX_PP "tx_pp"
116
117 /*
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
121 */
122 #define MLX5_TX_SKEW "tx_skew"
123
124 /*
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
127 */
128 #define MLX5_TX_VEC_EN "tx_vec_en"
129
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
132
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
135
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
138
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
141
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
144
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
147
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
150
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
153
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
156
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
159
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
162
163 /*
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
166 */
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
168
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
171
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
176
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
179
180 /** Driver-specific log messages type. */
181 int mlx5_logtype;
182
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
186
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
189 [MLX5_IPOOL_DECAP_ENCAP] = {
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
191 .trunk_size = 64,
192 .grow_trunk = 3,
193 .grow_shift = 2,
194 .need_lock = 1,
195 .release_mem_en = 1,
196 .malloc = mlx5_malloc,
197 .free = mlx5_free,
198 .type = "mlx5_encap_decap_ipool",
199 },
200 [MLX5_IPOOL_PUSH_VLAN] = {
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
202 .trunk_size = 64,
203 .grow_trunk = 3,
204 .grow_shift = 2,
205 .need_lock = 1,
206 .release_mem_en = 1,
207 .malloc = mlx5_malloc,
208 .free = mlx5_free,
209 .type = "mlx5_push_vlan_ipool",
210 },
211 [MLX5_IPOOL_TAG] = {
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
213 .trunk_size = 64,
214 .grow_trunk = 3,
215 .grow_shift = 2,
216 .need_lock = 1,
217 .release_mem_en = 1,
218 .malloc = mlx5_malloc,
219 .free = mlx5_free,
220 .type = "mlx5_tag_ipool",
221 },
222 [MLX5_IPOOL_PORT_ID] = {
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
224 .trunk_size = 64,
225 .grow_trunk = 3,
226 .grow_shift = 2,
227 .need_lock = 1,
228 .release_mem_en = 1,
229 .malloc = mlx5_malloc,
230 .free = mlx5_free,
231 .type = "mlx5_port_id_ipool",
232 },
233 [MLX5_IPOOL_JUMP] = {
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
235 .trunk_size = 64,
236 .grow_trunk = 3,
237 .grow_shift = 2,
238 .need_lock = 1,
239 .release_mem_en = 1,
240 .malloc = mlx5_malloc,
241 .free = mlx5_free,
242 .type = "mlx5_jump_ipool",
243 },
244 [MLX5_IPOOL_SAMPLE] = {
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
246 .trunk_size = 64,
247 .grow_trunk = 3,
248 .grow_shift = 2,
249 .need_lock = 1,
250 .release_mem_en = 1,
251 .malloc = mlx5_malloc,
252 .free = mlx5_free,
253 .type = "mlx5_sample_ipool",
254 },
255 [MLX5_IPOOL_DEST_ARRAY] = {
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
257 .trunk_size = 64,
258 .grow_trunk = 3,
259 .grow_shift = 2,
260 .need_lock = 1,
261 .release_mem_en = 1,
262 .malloc = mlx5_malloc,
263 .free = mlx5_free,
264 .type = "mlx5_dest_array_ipool",
265 },
266 [MLX5_IPOOL_TUNNEL_ID] = {
267 .size = sizeof(struct mlx5_flow_tunnel),
268 .need_lock = 1,
269 .release_mem_en = 1,
270 .type = "mlx5_tunnel_offload",
271 },
272 [MLX5_IPOOL_TNL_TBL_ID] = {
273 .size = 0,
274 .need_lock = 1,
275 .type = "mlx5_flow_tnl_tbl_ipool",
276 },
277 #endif
278 [MLX5_IPOOL_MTR] = {
279 .size = sizeof(struct mlx5_flow_meter),
280 .trunk_size = 64,
281 .grow_trunk = 3,
282 .grow_shift = 2,
283 .need_lock = 1,
284 .release_mem_en = 1,
285 .malloc = mlx5_malloc,
286 .free = mlx5_free,
287 .type = "mlx5_meter_ipool",
288 },
289 [MLX5_IPOOL_MCP] = {
290 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
291 .trunk_size = 64,
292 .grow_trunk = 3,
293 .grow_shift = 2,
294 .need_lock = 1,
295 .release_mem_en = 1,
296 .malloc = mlx5_malloc,
297 .free = mlx5_free,
298 .type = "mlx5_mcp_ipool",
299 },
300 [MLX5_IPOOL_HRXQ] = {
301 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
302 .trunk_size = 64,
303 .grow_trunk = 3,
304 .grow_shift = 2,
305 .need_lock = 1,
306 .release_mem_en = 1,
307 .malloc = mlx5_malloc,
308 .free = mlx5_free,
309 .type = "mlx5_hrxq_ipool",
310 },
311 [MLX5_IPOOL_MLX5_FLOW] = {
312 /*
313 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
314 * It set in run time according to PCI function configuration.
315 */
316 .size = 0,
317 .trunk_size = 64,
318 .grow_trunk = 3,
319 .grow_shift = 2,
320 .need_lock = 1,
321 .release_mem_en = 1,
322 .malloc = mlx5_malloc,
323 .free = mlx5_free,
324 .type = "mlx5_flow_handle_ipool",
325 },
326 [MLX5_IPOOL_RTE_FLOW] = {
327 .size = sizeof(struct rte_flow),
328 .trunk_size = 4096,
329 .need_lock = 1,
330 .release_mem_en = 1,
331 .malloc = mlx5_malloc,
332 .free = mlx5_free,
333 .type = "rte_flow_ipool",
334 },
335 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
336 .size = 0,
337 .need_lock = 1,
338 .type = "mlx5_flow_rss_id_ipool",
339 },
340 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
341 .size = sizeof(struct mlx5_shared_action_rss),
342 .trunk_size = 64,
343 .grow_trunk = 3,
344 .grow_shift = 2,
345 .need_lock = 1,
346 .release_mem_en = 1,
347 .malloc = mlx5_malloc,
348 .free = mlx5_free,
349 .type = "mlx5_shared_action_rss",
350 },
351 };
352
353
354 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
355 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
356
357 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
358
359 /**
360 * Initialize the ASO aging management structure.
361 *
362 * @param[in] sh
363 * Pointer to mlx5_dev_ctx_shared object to free
364 *
365 * @return
366 * 0 on success, a negative errno value otherwise and rte_errno is set.
367 */
368 int
mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared * sh)369 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
370 {
371 int err;
372
373 if (sh->aso_age_mng)
374 return 0;
375 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
376 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
377 if (!sh->aso_age_mng) {
378 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
379 rte_errno = ENOMEM;
380 return -ENOMEM;
381 }
382 err = mlx5_aso_queue_init(sh);
383 if (err) {
384 mlx5_free(sh->aso_age_mng);
385 return -1;
386 }
387 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
388 rte_spinlock_init(&sh->aso_age_mng->free_sl);
389 LIST_INIT(&sh->aso_age_mng->free);
390 return 0;
391 }
392
393 /**
394 * Close and release all the resources of the ASO aging management structure.
395 *
396 * @param[in] sh
397 * Pointer to mlx5_dev_ctx_shared object to free.
398 */
399 static void
mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared * sh)400 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
401 {
402 int i, j;
403
404 mlx5_aso_queue_stop(sh);
405 mlx5_aso_queue_uninit(sh);
406 if (sh->aso_age_mng->pools) {
407 struct mlx5_aso_age_pool *pool;
408
409 for (i = 0; i < sh->aso_age_mng->next; ++i) {
410 pool = sh->aso_age_mng->pools[i];
411 claim_zero(mlx5_devx_cmd_destroy
412 (pool->flow_hit_aso_obj));
413 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
414 if (pool->actions[j].dr_action)
415 claim_zero
416 (mlx5_glue->destroy_flow_action
417 (pool->actions[j].dr_action));
418 mlx5_free(pool);
419 }
420 mlx5_free(sh->aso_age_mng->pools);
421 }
422 mlx5_free(sh->aso_age_mng);
423 }
424
425 /**
426 * Initialize the shared aging list information per port.
427 *
428 * @param[in] sh
429 * Pointer to mlx5_dev_ctx_shared object.
430 */
431 static void
mlx5_flow_aging_init(struct mlx5_dev_ctx_shared * sh)432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
433 {
434 uint32_t i;
435 struct mlx5_age_info *age_info;
436
437 for (i = 0; i < sh->max_port; i++) {
438 age_info = &sh->port[i].age_info;
439 age_info->flags = 0;
440 TAILQ_INIT(&age_info->aged_counters);
441 LIST_INIT(&age_info->aged_aso);
442 rte_spinlock_init(&age_info->aged_sl);
443 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
444 }
445 }
446
447 /**
448 * Initialize the counters management structure.
449 *
450 * @param[in] sh
451 * Pointer to mlx5_dev_ctx_shared object to free
452 */
453 static void
mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared * sh)454 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
455 {
456 int i;
457
458 memset(&sh->cmng, 0, sizeof(sh->cmng));
459 TAILQ_INIT(&sh->cmng.flow_counters);
460 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
461 sh->cmng.max_id = -1;
462 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
463 rte_spinlock_init(&sh->cmng.pool_update_sl);
464 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
465 TAILQ_INIT(&sh->cmng.counters[i]);
466 rte_spinlock_init(&sh->cmng.csl[i]);
467 }
468 }
469
470 /**
471 * Destroy all the resources allocated for a counter memory management.
472 *
473 * @param[in] mng
474 * Pointer to the memory management structure.
475 */
476 static void
mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng * mng)477 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
478 {
479 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
480
481 LIST_REMOVE(mng, next);
482 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
483 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
484 mlx5_free(mem);
485 }
486
487 /**
488 * Close and release all the resources of the counters management.
489 *
490 * @param[in] sh
491 * Pointer to mlx5_dev_ctx_shared object to free.
492 */
493 static void
mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared * sh)494 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
495 {
496 struct mlx5_counter_stats_mem_mng *mng;
497 int i, j;
498 int retries = 1024;
499
500 rte_errno = 0;
501 while (--retries) {
502 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
503 if (rte_errno != EINPROGRESS)
504 break;
505 rte_pause();
506 }
507
508 if (sh->cmng.pools) {
509 struct mlx5_flow_counter_pool *pool;
510 uint16_t n_valid = sh->cmng.n_valid;
511 bool fallback = sh->cmng.counter_fallback;
512
513 for (i = 0; i < n_valid; ++i) {
514 pool = sh->cmng.pools[i];
515 if (!fallback && pool->min_dcs)
516 claim_zero(mlx5_devx_cmd_destroy
517 (pool->min_dcs));
518 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
519 struct mlx5_flow_counter *cnt =
520 MLX5_POOL_GET_CNT(pool, j);
521
522 if (cnt->action)
523 claim_zero
524 (mlx5_glue->destroy_flow_action
525 (cnt->action));
526 if (fallback && MLX5_POOL_GET_CNT
527 (pool, j)->dcs_when_free)
528 claim_zero(mlx5_devx_cmd_destroy
529 (cnt->dcs_when_free));
530 }
531 mlx5_free(pool);
532 }
533 mlx5_free(sh->cmng.pools);
534 }
535 mng = LIST_FIRST(&sh->cmng.mem_mngs);
536 while (mng) {
537 mlx5_flow_destroy_counter_stat_mem_mng(mng);
538 mng = LIST_FIRST(&sh->cmng.mem_mngs);
539 }
540 memset(&sh->cmng, 0, sizeof(sh->cmng));
541 }
542
543 /* Send FLOW_AGED event if needed. */
544 void
mlx5_age_event_prepare(struct mlx5_dev_ctx_shared * sh)545 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
546 {
547 struct mlx5_age_info *age_info;
548 uint32_t i;
549
550 for (i = 0; i < sh->max_port; i++) {
551 age_info = &sh->port[i].age_info;
552 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
553 continue;
554 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
555 rte_eth_dev_callback_process
556 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
557 RTE_ETH_EVENT_FLOW_AGED, NULL);
558 age_info->flags = 0;
559 }
560 }
561
562 /**
563 * Initialize the flow resources' indexed mempool.
564 *
565 * @param[in] sh
566 * Pointer to mlx5_dev_ctx_shared object.
567 * @param[in] sh
568 * Pointer to user dev config.
569 */
570 static void
mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared * sh,const struct mlx5_dev_config * config)571 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
572 const struct mlx5_dev_config *config)
573 {
574 uint8_t i;
575 struct mlx5_indexed_pool_config cfg;
576
577 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
578 cfg = mlx5_ipool_cfg[i];
579 switch (i) {
580 default:
581 break;
582 /*
583 * Set MLX5_IPOOL_MLX5_FLOW ipool size
584 * according to PCI function flow configuration.
585 */
586 case MLX5_IPOOL_MLX5_FLOW:
587 cfg.size = config->dv_flow_en ?
588 sizeof(struct mlx5_flow_handle) :
589 MLX5_FLOW_HANDLE_VERBS_SIZE;
590 break;
591 }
592 if (config->reclaim_mode)
593 cfg.release_mem_en = 1;
594 sh->ipool[i] = mlx5_ipool_create(&cfg);
595 }
596 }
597
598 /**
599 * Release the flow resources' indexed mempool.
600 *
601 * @param[in] sh
602 * Pointer to mlx5_dev_ctx_shared object.
603 */
604 static void
mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared * sh)605 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
606 {
607 uint8_t i;
608
609 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
610 mlx5_ipool_destroy(sh->ipool[i]);
611 }
612
613 /*
614 * Check if dynamic flex parser for eCPRI already exists.
615 *
616 * @param dev
617 * Pointer to Ethernet device structure.
618 *
619 * @return
620 * true on exists, false on not.
621 */
622 bool
mlx5_flex_parser_ecpri_exist(struct rte_eth_dev * dev)623 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
624 {
625 struct mlx5_priv *priv = dev->data->dev_private;
626 struct mlx5_flex_parser_profiles *prf =
627 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
628
629 return !!prf->obj;
630 }
631
632 /*
633 * Allocation of a flex parser for eCPRI. Once created, this parser related
634 * resources will be held until the device is closed.
635 *
636 * @param dev
637 * Pointer to Ethernet device structure.
638 *
639 * @return
640 * 0 on success, a negative errno value otherwise and rte_errno is set.
641 */
642 int
mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev * dev)643 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
644 {
645 struct mlx5_priv *priv = dev->data->dev_private;
646 struct mlx5_flex_parser_profiles *prf =
647 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
648 struct mlx5_devx_graph_node_attr node = {
649 .modify_field_select = 0,
650 };
651 uint32_t ids[8];
652 int ret;
653
654 if (!priv->config.hca_attr.parse_graph_flex_node) {
655 DRV_LOG(ERR, "Dynamic flex parser is not supported "
656 "for device %s.", priv->dev_data->name);
657 return -ENOTSUP;
658 }
659 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
660 /* 8 bytes now: 4B common header + 4B message body header. */
661 node.header_length_base_value = 0x8;
662 /* After MAC layer: Ether / VLAN. */
663 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
664 /* Type of compared condition should be 0xAEFE in the L2 layer. */
665 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
666 /* Sample #0: type in common header. */
667 node.sample[0].flow_match_sample_en = 1;
668 /* Fixed offset. */
669 node.sample[0].flow_match_sample_offset_mode = 0x0;
670 /* Only the 2nd byte will be used. */
671 node.sample[0].flow_match_sample_field_base_offset = 0x0;
672 /* Sample #1: message payload. */
673 node.sample[1].flow_match_sample_en = 1;
674 /* Fixed offset. */
675 node.sample[1].flow_match_sample_offset_mode = 0x0;
676 /*
677 * Only the first two bytes will be used right now, and its offset will
678 * start after the common header that with the length of a DW(u32).
679 */
680 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
681 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
682 if (!prf->obj) {
683 DRV_LOG(ERR, "Failed to create flex parser node object.");
684 return (rte_errno == 0) ? -ENODEV : -rte_errno;
685 }
686 prf->num = 2;
687 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
688 if (ret) {
689 DRV_LOG(ERR, "Failed to query sample IDs.");
690 return (rte_errno == 0) ? -ENODEV : -rte_errno;
691 }
692 prf->offset[0] = 0x0;
693 prf->offset[1] = sizeof(uint32_t);
694 prf->ids[0] = ids[0];
695 prf->ids[1] = ids[1];
696 return 0;
697 }
698
699 /*
700 * Destroy the flex parser node, including the parser itself, input / output
701 * arcs and DW samples. Resources could be reused then.
702 *
703 * @param dev
704 * Pointer to Ethernet device structure.
705 */
706 static void
mlx5_flex_parser_ecpri_release(struct rte_eth_dev * dev)707 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
708 {
709 struct mlx5_priv *priv = dev->data->dev_private;
710 struct mlx5_flex_parser_profiles *prf =
711 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
712
713 if (prf->obj)
714 mlx5_devx_cmd_destroy(prf->obj);
715 prf->obj = NULL;
716 }
717
718 /*
719 * Allocate Rx and Tx UARs in robust fashion.
720 * This routine handles the following UAR allocation issues:
721 *
722 * - tries to allocate the UAR with the most appropriate memory
723 * mapping type from the ones supported by the host
724 *
725 * - tries to allocate the UAR with non-NULL base address
726 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
727 * UAR base address if UAR was not the first object in the UAR page.
728 * It caused the PMD failure and we should try to get another UAR
729 * till we get the first one with non-NULL base address returned.
730 */
731 static int
mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared * sh,const struct mlx5_dev_config * config)732 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
733 const struct mlx5_dev_config *config)
734 {
735 uint32_t uar_mapping, retry;
736 int err = 0;
737 void *base_addr;
738
739 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
740 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
741 /* Control the mapping type according to the settings. */
742 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
743 MLX5DV_UAR_ALLOC_TYPE_NC :
744 MLX5DV_UAR_ALLOC_TYPE_BF;
745 #else
746 RTE_SET_USED(config);
747 /*
748 * It seems we have no way to control the memory mapping type
749 * for the UAR, the default "Write-Combining" type is supposed.
750 * The UAR initialization on queue creation queries the
751 * actual mapping type done by Verbs/kernel and setups the
752 * PMD datapath accordingly.
753 */
754 uar_mapping = 0;
755 #endif
756 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
757 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
758 if (!sh->tx_uar &&
759 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
760 if (config->dbnc == MLX5_TXDB_CACHED ||
761 config->dbnc == MLX5_TXDB_HEURISTIC)
762 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
763 "is not supported by DevX");
764 /*
765 * In some environments like virtual machine
766 * the Write Combining mapped might be not supported
767 * and UAR allocation fails. We try "Non-Cached"
768 * mapping for the case. The tx_burst routines take
769 * the UAR mapping type into account on UAR setup
770 * on queue creation.
771 */
772 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
773 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
774 sh->tx_uar = mlx5_glue->devx_alloc_uar
775 (sh->ctx, uar_mapping);
776 } else if (!sh->tx_uar &&
777 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
778 if (config->dbnc == MLX5_TXDB_NCACHED)
779 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
780 "is not supported by DevX");
781 /*
782 * If Verbs/kernel does not support "Non-Cached"
783 * try the "Write-Combining".
784 */
785 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
786 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
787 sh->tx_uar = mlx5_glue->devx_alloc_uar
788 (sh->ctx, uar_mapping);
789 }
790 #endif
791 if (!sh->tx_uar) {
792 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
793 err = ENOMEM;
794 goto exit;
795 }
796 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
797 if (base_addr)
798 break;
799 /*
800 * The UARs are allocated by rdma_core within the
801 * IB device context, on context closure all UARs
802 * will be freed, should be no memory/object leakage.
803 */
804 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
805 sh->tx_uar = NULL;
806 }
807 /* Check whether we finally succeeded with valid UAR allocation. */
808 if (!sh->tx_uar) {
809 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
810 err = ENOMEM;
811 goto exit;
812 }
813 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
814 uar_mapping = 0;
815 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
816 (sh->ctx, uar_mapping);
817 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
818 if (!sh->devx_rx_uar &&
819 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
820 /*
821 * Rx UAR is used to control interrupts only,
822 * should be no datapath noticeable impact,
823 * can try "Non-Cached" mapping safely.
824 */
825 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
826 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
827 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
828 (sh->ctx, uar_mapping);
829 }
830 #endif
831 if (!sh->devx_rx_uar) {
832 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
833 err = ENOMEM;
834 goto exit;
835 }
836 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
837 if (base_addr)
838 break;
839 /*
840 * The UARs are allocated by rdma_core within the
841 * IB device context, on context closure all UARs
842 * will be freed, should be no memory/object leakage.
843 */
844 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
845 sh->devx_rx_uar = NULL;
846 }
847 /* Check whether we finally succeeded with valid UAR allocation. */
848 if (!sh->devx_rx_uar) {
849 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
850 err = ENOMEM;
851 }
852 exit:
853 return err;
854 }
855
856 /**
857 * Allocate shared device context. If there is multiport device the
858 * master and representors will share this context, if there is single
859 * port dedicated device, the context will be used by only given
860 * port due to unification.
861 *
862 * Routine first searches the context for the specified device name,
863 * if found the shared context assumed and reference counter is incremented.
864 * If no context found the new one is created and initialized with specified
865 * device context and parameters.
866 *
867 * @param[in] spawn
868 * Pointer to the device attributes (name, port, etc).
869 * @param[in] config
870 * Pointer to device configuration structure.
871 *
872 * @return
873 * Pointer to mlx5_dev_ctx_shared object on success,
874 * otherwise NULL and rte_errno is set.
875 */
876 struct mlx5_dev_ctx_shared *
mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data * spawn,const struct mlx5_dev_config * config)877 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
878 const struct mlx5_dev_config *config)
879 {
880 struct mlx5_dev_ctx_shared *sh;
881 int err = 0;
882 uint32_t i;
883 struct mlx5_devx_tis_attr tis_attr = { 0 };
884
885 MLX5_ASSERT(spawn);
886 /* Secondary process should not create the shared context. */
887 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
888 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
889 /* Search for IB context by device name. */
890 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
891 if (!strcmp(sh->ibdev_name,
892 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
893 sh->refcnt++;
894 goto exit;
895 }
896 }
897 /* No device found, we have to create new shared context. */
898 MLX5_ASSERT(spawn->max_port);
899 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
900 sizeof(struct mlx5_dev_ctx_shared) +
901 spawn->max_port *
902 sizeof(struct mlx5_dev_shared_port),
903 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
904 if (!sh) {
905 DRV_LOG(ERR, "shared context allocation failure");
906 rte_errno = ENOMEM;
907 goto exit;
908 }
909 err = mlx5_os_open_device(spawn, config, sh);
910 if (!sh->ctx)
911 goto error;
912 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
913 if (err) {
914 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
915 goto error;
916 }
917 sh->refcnt = 1;
918 sh->bond_dev = UINT16_MAX;
919 sh->max_port = spawn->max_port;
920 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
921 sizeof(sh->ibdev_name) - 1);
922 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
923 sizeof(sh->ibdev_path) - 1);
924 /*
925 * Setting port_id to max unallowed value means
926 * there is no interrupt subhandler installed for
927 * the given port index i.
928 */
929 for (i = 0; i < sh->max_port; i++) {
930 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
931 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
932 }
933 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
934 if (sh->pd == NULL) {
935 DRV_LOG(ERR, "PD allocation failure");
936 err = ENOMEM;
937 goto error;
938 }
939 if (sh->devx) {
940 /* Query the EQN for this core. */
941 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
942 if (err) {
943 rte_errno = errno;
944 DRV_LOG(ERR, "Failed to query event queue number %d.",
945 rte_errno);
946 goto error;
947 }
948 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
949 if (err) {
950 DRV_LOG(ERR, "Fail to extract pdn from PD");
951 goto error;
952 }
953 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
954 if (!sh->td) {
955 DRV_LOG(ERR, "TD allocation failure");
956 err = ENOMEM;
957 goto error;
958 }
959 tis_attr.transport_domain = sh->td->id;
960 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
961 if (!sh->tis) {
962 DRV_LOG(ERR, "TIS allocation failure");
963 err = ENOMEM;
964 goto error;
965 }
966 err = mlx5_alloc_rxtx_uars(sh, config);
967 if (err)
968 goto error;
969 MLX5_ASSERT(sh->tx_uar);
970 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
971
972 MLX5_ASSERT(sh->devx_rx_uar);
973 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
974 }
975 #ifndef RTE_ARCH_64
976 /* Initialize UAR access locks for 32bit implementations. */
977 rte_spinlock_init(&sh->uar_lock_cq);
978 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
979 rte_spinlock_init(&sh->uar_lock[i]);
980 #endif
981 /*
982 * Once the device is added to the list of memory event
983 * callback, its global MR cache table cannot be expanded
984 * on the fly because of deadlock. If it overflows, lookup
985 * should be done by searching MR list linearly, which is slow.
986 *
987 * At this point the device is not added to the memory
988 * event list yet, context is just being created.
989 */
990 err = mlx5_mr_btree_init(&sh->share_cache.cache,
991 MLX5_MR_BTREE_CACHE_N * 2,
992 spawn->pci_dev->device.numa_node);
993 if (err) {
994 err = rte_errno;
995 goto error;
996 }
997 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
998 &sh->share_cache.dereg_mr_cb);
999 mlx5_os_dev_shared_handler_install(sh);
1000 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1001 if (!sh->cnt_id_tbl) {
1002 err = rte_errno;
1003 goto error;
1004 }
1005 mlx5_flow_aging_init(sh);
1006 mlx5_flow_counters_mng_init(sh);
1007 mlx5_flow_ipool_create(sh, config);
1008 /* Add device to memory callback list. */
1009 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1010 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1011 sh, mem_event_cb);
1012 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1013 /* Add context to the global device list. */
1014 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1015 exit:
1016 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1017 return sh;
1018 error:
1019 pthread_mutex_destroy(&sh->txpp.mutex);
1020 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1021 MLX5_ASSERT(sh);
1022 if (sh->cnt_id_tbl)
1023 mlx5_l3t_destroy(sh->cnt_id_tbl);
1024 if (sh->tis)
1025 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1026 if (sh->td)
1027 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1028 if (sh->devx_rx_uar)
1029 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1030 if (sh->tx_uar)
1031 mlx5_glue->devx_free_uar(sh->tx_uar);
1032 if (sh->pd)
1033 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1034 if (sh->ctx)
1035 claim_zero(mlx5_glue->close_device(sh->ctx));
1036 mlx5_free(sh);
1037 MLX5_ASSERT(err > 0);
1038 rte_errno = err;
1039 return NULL;
1040 }
1041
1042 /**
1043 * Free shared IB device context. Decrement counter and if zero free
1044 * all allocated resources and close handles.
1045 *
1046 * @param[in] sh
1047 * Pointer to mlx5_dev_ctx_shared object to free
1048 */
1049 void
mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared * sh)1050 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1051 {
1052 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1053 #ifdef RTE_LIBRTE_MLX5_DEBUG
1054 /* Check the object presence in the list. */
1055 struct mlx5_dev_ctx_shared *lctx;
1056
1057 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1058 if (lctx == sh)
1059 break;
1060 MLX5_ASSERT(lctx);
1061 if (lctx != sh) {
1062 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1063 goto exit;
1064 }
1065 #endif
1066 MLX5_ASSERT(sh);
1067 MLX5_ASSERT(sh->refcnt);
1068 /* Secondary process should not free the shared context. */
1069 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1070 if (--sh->refcnt)
1071 goto exit;
1072 /* Remove from memory callback device list. */
1073 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1074 LIST_REMOVE(sh, mem_event_cb);
1075 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1076 /* Release created Memory Regions. */
1077 mlx5_mr_release_cache(&sh->share_cache);
1078 /* Remove context from the global device list. */
1079 LIST_REMOVE(sh, next);
1080 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1081 /*
1082 * Ensure there is no async event handler installed.
1083 * Only primary process handles async device events.
1084 **/
1085 mlx5_flow_counters_mng_close(sh);
1086 if (sh->aso_age_mng) {
1087 mlx5_flow_aso_age_mng_close(sh);
1088 sh->aso_age_mng = NULL;
1089 }
1090 mlx5_flow_ipool_destroy(sh);
1091 mlx5_os_dev_shared_handler_uninstall(sh);
1092 if (sh->cnt_id_tbl) {
1093 mlx5_l3t_destroy(sh->cnt_id_tbl);
1094 sh->cnt_id_tbl = NULL;
1095 }
1096 if (sh->tx_uar) {
1097 mlx5_glue->devx_free_uar(sh->tx_uar);
1098 sh->tx_uar = NULL;
1099 }
1100 if (sh->pd)
1101 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1102 if (sh->tis)
1103 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1104 if (sh->td)
1105 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1106 if (sh->devx_rx_uar)
1107 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1108 if (sh->ctx)
1109 claim_zero(mlx5_glue->close_device(sh->ctx));
1110 pthread_mutex_destroy(&sh->txpp.mutex);
1111 mlx5_free(sh);
1112 return;
1113 exit:
1114 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1115 }
1116
1117 /**
1118 * Destroy table hash list.
1119 *
1120 * @param[in] priv
1121 * Pointer to the private device data structure.
1122 */
1123 void
mlx5_free_table_hash_list(struct mlx5_priv * priv)1124 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1125 {
1126 struct mlx5_dev_ctx_shared *sh = priv->sh;
1127
1128 if (!sh->flow_tbls)
1129 return;
1130 mlx5_hlist_destroy(sh->flow_tbls);
1131 }
1132
1133 /**
1134 * Initialize flow table hash list and create the root tables entry
1135 * for each domain.
1136 *
1137 * @param[in] priv
1138 * Pointer to the private device data structure.
1139 *
1140 * @return
1141 * Zero on success, positive error code otherwise.
1142 */
1143 int
mlx5_alloc_table_hash_list(struct mlx5_priv * priv __rte_unused)1144 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1145 {
1146 int err = 0;
1147 /* Tables are only used in DV and DR modes. */
1148 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1149 struct mlx5_dev_ctx_shared *sh = priv->sh;
1150 char s[MLX5_HLIST_NAMESIZE];
1151
1152 MLX5_ASSERT(sh);
1153 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1154 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1155 0, 0, flow_dv_tbl_create_cb, NULL,
1156 flow_dv_tbl_remove_cb);
1157 if (!sh->flow_tbls) {
1158 DRV_LOG(ERR, "flow tables with hash creation failed.");
1159 err = ENOMEM;
1160 return err;
1161 }
1162 sh->flow_tbls->ctx = sh;
1163 #ifndef HAVE_MLX5DV_DR
1164 struct rte_flow_error error;
1165 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1166
1167 /*
1168 * In case we have not DR support, the zero tables should be created
1169 * because DV expect to see them even if they cannot be created by
1170 * RDMA-CORE.
1171 */
1172 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1173 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1174 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1175 err = ENOMEM;
1176 goto error;
1177 }
1178 return err;
1179 error:
1180 mlx5_free_table_hash_list(priv);
1181 #endif /* HAVE_MLX5DV_DR */
1182 #endif
1183 return err;
1184 }
1185
1186 /**
1187 * Retrieve integer value from environment variable.
1188 *
1189 * @param[in] name
1190 * Environment variable name.
1191 *
1192 * @return
1193 * Integer value, 0 if the variable is not set.
1194 */
1195 int
mlx5_getenv_int(const char * name)1196 mlx5_getenv_int(const char *name)
1197 {
1198 const char *val = getenv(name);
1199
1200 if (val == NULL)
1201 return 0;
1202 return atoi(val);
1203 }
1204
1205 /**
1206 * DPDK callback to add udp tunnel port
1207 *
1208 * @param[in] dev
1209 * A pointer to eth_dev
1210 * @param[in] udp_tunnel
1211 * A pointer to udp tunnel
1212 *
1213 * @return
1214 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1215 */
1216 int
mlx5_udp_tunnel_port_add(struct rte_eth_dev * dev __rte_unused,struct rte_eth_udp_tunnel * udp_tunnel)1217 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1218 struct rte_eth_udp_tunnel *udp_tunnel)
1219 {
1220 MLX5_ASSERT(udp_tunnel != NULL);
1221 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1222 udp_tunnel->udp_port == 4789)
1223 return 0;
1224 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1225 udp_tunnel->udp_port == 4790)
1226 return 0;
1227 return -ENOTSUP;
1228 }
1229
1230 /**
1231 * Initialize process private data structure.
1232 *
1233 * @param dev
1234 * Pointer to Ethernet device structure.
1235 *
1236 * @return
1237 * 0 on success, a negative errno value otherwise and rte_errno is set.
1238 */
1239 int
mlx5_proc_priv_init(struct rte_eth_dev * dev)1240 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1241 {
1242 struct mlx5_priv *priv = dev->data->dev_private;
1243 struct mlx5_proc_priv *ppriv;
1244 size_t ppriv_size;
1245
1246 /*
1247 * UAR register table follows the process private structure. BlueFlame
1248 * registers for Tx queues are stored in the table.
1249 */
1250 ppriv_size =
1251 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1252 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1253 dev->device->numa_node);
1254 if (!ppriv) {
1255 rte_errno = ENOMEM;
1256 return -rte_errno;
1257 }
1258 ppriv->uar_table_sz = ppriv_size;
1259 dev->process_private = ppriv;
1260 return 0;
1261 }
1262
1263 /**
1264 * Un-initialize process private data structure.
1265 *
1266 * @param dev
1267 * Pointer to Ethernet device structure.
1268 */
1269 static void
mlx5_proc_priv_uninit(struct rte_eth_dev * dev)1270 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1271 {
1272 if (!dev->process_private)
1273 return;
1274 mlx5_free(dev->process_private);
1275 dev->process_private = NULL;
1276 }
1277
1278 /**
1279 * DPDK callback to close the device.
1280 *
1281 * Destroy all queues and objects, free memory.
1282 *
1283 * @param dev
1284 * Pointer to Ethernet device structure.
1285 */
1286 int
mlx5_dev_close(struct rte_eth_dev * dev)1287 mlx5_dev_close(struct rte_eth_dev *dev)
1288 {
1289 struct mlx5_priv *priv = dev->data->dev_private;
1290 unsigned int i;
1291 int ret;
1292
1293 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1294 /* Check if process_private released. */
1295 if (!dev->process_private)
1296 return 0;
1297 mlx5_tx_uar_uninit_secondary(dev);
1298 mlx5_proc_priv_uninit(dev);
1299 rte_eth_dev_release_port(dev);
1300 return 0;
1301 }
1302 if (!priv->sh)
1303 return 0;
1304 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1305 dev->data->port_id,
1306 ((priv->sh->ctx != NULL) ?
1307 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1308 /*
1309 * If default mreg copy action is removed at the stop stage,
1310 * the search will return none and nothing will be done anymore.
1311 */
1312 mlx5_flow_stop_default(dev);
1313 mlx5_traffic_disable(dev);
1314 /*
1315 * If all the flows are already flushed in the device stop stage,
1316 * then this will return directly without any action.
1317 */
1318 mlx5_flow_list_flush(dev, &priv->flows, true);
1319 mlx5_shared_action_flush(dev);
1320 mlx5_flow_meter_flush(dev, NULL);
1321 /* Prevent crashes when queues are still in use. */
1322 dev->rx_pkt_burst = removed_rx_burst;
1323 dev->tx_pkt_burst = removed_tx_burst;
1324 rte_wmb();
1325 /* Disable datapath on secondary process. */
1326 mlx5_mp_os_req_stop_rxtx(dev);
1327 /* Free the eCPRI flex parser resource. */
1328 mlx5_flex_parser_ecpri_release(dev);
1329 if (priv->rxqs != NULL) {
1330 /* XXX race condition if mlx5_rx_burst() is still running. */
1331 usleep(1000);
1332 for (i = 0; (i != priv->rxqs_n); ++i)
1333 mlx5_rxq_release(dev, i);
1334 priv->rxqs_n = 0;
1335 priv->rxqs = NULL;
1336 }
1337 if (priv->txqs != NULL) {
1338 /* XXX race condition if mlx5_tx_burst() is still running. */
1339 usleep(1000);
1340 for (i = 0; (i != priv->txqs_n); ++i)
1341 mlx5_txq_release(dev, i);
1342 priv->txqs_n = 0;
1343 priv->txqs = NULL;
1344 }
1345 mlx5_proc_priv_uninit(dev);
1346 if (priv->drop_queue.hrxq)
1347 mlx5_drop_action_destroy(dev);
1348 if (priv->mreg_cp_tbl)
1349 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1350 mlx5_mprq_free_mp(dev);
1351 mlx5_os_free_shared_dr(priv);
1352 if (priv->rss_conf.rss_key != NULL)
1353 mlx5_free(priv->rss_conf.rss_key);
1354 if (priv->reta_idx != NULL)
1355 mlx5_free(priv->reta_idx);
1356 if (priv->config.vf)
1357 mlx5_os_mac_addr_flush(dev);
1358 if (priv->nl_socket_route >= 0)
1359 close(priv->nl_socket_route);
1360 if (priv->nl_socket_rdma >= 0)
1361 close(priv->nl_socket_rdma);
1362 if (priv->vmwa_context)
1363 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1364 ret = mlx5_hrxq_verify(dev);
1365 if (ret)
1366 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1367 dev->data->port_id);
1368 ret = mlx5_ind_table_obj_verify(dev);
1369 if (ret)
1370 DRV_LOG(WARNING, "port %u some indirection table still remain",
1371 dev->data->port_id);
1372 ret = mlx5_rxq_obj_verify(dev);
1373 if (ret)
1374 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1375 dev->data->port_id);
1376 ret = mlx5_rxq_verify(dev);
1377 if (ret)
1378 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1379 dev->data->port_id);
1380 ret = mlx5_txq_obj_verify(dev);
1381 if (ret)
1382 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1383 dev->data->port_id);
1384 ret = mlx5_txq_verify(dev);
1385 if (ret)
1386 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1387 dev->data->port_id);
1388 ret = mlx5_flow_verify(dev);
1389 if (ret)
1390 DRV_LOG(WARNING, "port %u some flows still remain",
1391 dev->data->port_id);
1392 mlx5_cache_list_destroy(&priv->hrxqs);
1393 /*
1394 * Free the shared context in last turn, because the cleanup
1395 * routines above may use some shared fields, like
1396 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1397 * ifindex if Netlink fails.
1398 */
1399 mlx5_free_shared_dev_ctx(priv->sh);
1400 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1401 unsigned int c = 0;
1402 uint16_t port_id;
1403
1404 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1405 struct mlx5_priv *opriv =
1406 rte_eth_devices[port_id].data->dev_private;
1407
1408 if (!opriv ||
1409 opriv->domain_id != priv->domain_id ||
1410 &rte_eth_devices[port_id] == dev)
1411 continue;
1412 ++c;
1413 break;
1414 }
1415 if (!c)
1416 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1417 }
1418 memset(priv, 0, sizeof(*priv));
1419 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1420 /*
1421 * Reset mac_addrs to NULL such that it is not freed as part of
1422 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1423 * it is freed when dev_private is freed.
1424 */
1425 dev->data->mac_addrs = NULL;
1426 return 0;
1427 }
1428
1429 /**
1430 * Verify and store value for device argument.
1431 *
1432 * @param[in] key
1433 * Key argument to verify.
1434 * @param[in] val
1435 * Value associated with key.
1436 * @param opaque
1437 * User data.
1438 *
1439 * @return
1440 * 0 on success, a negative errno value otherwise and rte_errno is set.
1441 */
1442 static int
mlx5_args_check(const char * key,const char * val,void * opaque)1443 mlx5_args_check(const char *key, const char *val, void *opaque)
1444 {
1445 struct mlx5_dev_config *config = opaque;
1446 unsigned long mod;
1447 signed long tmp;
1448
1449 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1450 if (!strcmp(MLX5_REPRESENTOR, key))
1451 return 0;
1452 errno = 0;
1453 tmp = strtol(val, NULL, 0);
1454 if (errno) {
1455 rte_errno = errno;
1456 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1457 return -rte_errno;
1458 }
1459 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1460 /* Negative values are acceptable for some keys only. */
1461 rte_errno = EINVAL;
1462 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1463 return -rte_errno;
1464 }
1465 mod = tmp >= 0 ? tmp : -tmp;
1466 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1467 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1468 DRV_LOG(ERR, "invalid CQE compression "
1469 "format parameter");
1470 rte_errno = EINVAL;
1471 return -rte_errno;
1472 }
1473 config->cqe_comp = !!tmp;
1474 config->cqe_comp_fmt = tmp;
1475 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1476 config->cqe_pad = !!tmp;
1477 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1478 config->hw_padding = !!tmp;
1479 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1480 config->mprq.enabled = !!tmp;
1481 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1482 config->mprq.stride_num_n = tmp;
1483 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1484 config->mprq.stride_size_n = tmp;
1485 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1486 config->mprq.max_memcpy_len = tmp;
1487 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1488 config->mprq.min_rxqs_num = tmp;
1489 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1490 DRV_LOG(WARNING, "%s: deprecated parameter,"
1491 " converted to txq_inline_max", key);
1492 config->txq_inline_max = tmp;
1493 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1494 config->txq_inline_max = tmp;
1495 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1496 config->txq_inline_min = tmp;
1497 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1498 config->txq_inline_mpw = tmp;
1499 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1500 config->txqs_inline = tmp;
1501 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1502 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1503 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1504 config->mps = !!tmp;
1505 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1506 if (tmp != MLX5_TXDB_CACHED &&
1507 tmp != MLX5_TXDB_NCACHED &&
1508 tmp != MLX5_TXDB_HEURISTIC) {
1509 DRV_LOG(ERR, "invalid Tx doorbell "
1510 "mapping parameter");
1511 rte_errno = EINVAL;
1512 return -rte_errno;
1513 }
1514 config->dbnc = tmp;
1515 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1516 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1517 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1518 DRV_LOG(WARNING, "%s: deprecated parameter,"
1519 " converted to txq_inline_mpw", key);
1520 config->txq_inline_mpw = tmp;
1521 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1522 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1523 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1524 if (!mod) {
1525 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1526 rte_errno = EINVAL;
1527 return -rte_errno;
1528 }
1529 config->tx_pp = tmp;
1530 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1531 config->tx_skew = tmp;
1532 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1533 config->rx_vec_en = !!tmp;
1534 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1535 config->l3_vxlan_en = !!tmp;
1536 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1537 config->vf_nl_en = !!tmp;
1538 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1539 config->dv_esw_en = !!tmp;
1540 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1541 config->dv_flow_en = !!tmp;
1542 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1543 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1544 tmp != MLX5_XMETA_MODE_META16 &&
1545 tmp != MLX5_XMETA_MODE_META32 &&
1546 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1547 DRV_LOG(ERR, "invalid extensive "
1548 "metadata parameter");
1549 rte_errno = EINVAL;
1550 return -rte_errno;
1551 }
1552 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1553 config->dv_xmeta_en = tmp;
1554 else
1555 config->dv_miss_info = 1;
1556 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1557 config->lacp_by_user = !!tmp;
1558 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1559 config->mr_ext_memseg_en = !!tmp;
1560 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1561 config->max_dump_files_num = tmp;
1562 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1563 config->lro.timeout = tmp;
1564 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1565 DRV_LOG(DEBUG, "class argument is %s.", val);
1566 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1567 config->log_hp_size = tmp;
1568 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1569 if (tmp != MLX5_RCM_NONE &&
1570 tmp != MLX5_RCM_LIGHT &&
1571 tmp != MLX5_RCM_AGGR) {
1572 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1573 rte_errno = EINVAL;
1574 return -rte_errno;
1575 }
1576 config->reclaim_mode = tmp;
1577 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1578 config->sys_mem_en = !!tmp;
1579 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1580 config->decap_en = !!tmp;
1581 } else {
1582 DRV_LOG(WARNING, "%s: unknown parameter", key);
1583 rte_errno = EINVAL;
1584 return -rte_errno;
1585 }
1586 return 0;
1587 }
1588
1589 /**
1590 * Parse device parameters.
1591 *
1592 * @param config
1593 * Pointer to device configuration structure.
1594 * @param devargs
1595 * Device arguments structure.
1596 *
1597 * @return
1598 * 0 on success, a negative errno value otherwise and rte_errno is set.
1599 */
1600 int
mlx5_args(struct mlx5_dev_config * config,struct rte_devargs * devargs)1601 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1602 {
1603 const char **params = (const char *[]){
1604 MLX5_RXQ_CQE_COMP_EN,
1605 MLX5_RXQ_CQE_PAD_EN,
1606 MLX5_RXQ_PKT_PAD_EN,
1607 MLX5_RX_MPRQ_EN,
1608 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1609 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1610 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1611 MLX5_RXQS_MIN_MPRQ,
1612 MLX5_TXQ_INLINE,
1613 MLX5_TXQ_INLINE_MIN,
1614 MLX5_TXQ_INLINE_MAX,
1615 MLX5_TXQ_INLINE_MPW,
1616 MLX5_TXQS_MIN_INLINE,
1617 MLX5_TXQS_MAX_VEC,
1618 MLX5_TXQ_MPW_EN,
1619 MLX5_TXQ_MPW_HDR_DSEG_EN,
1620 MLX5_TXQ_MAX_INLINE_LEN,
1621 MLX5_TX_DB_NC,
1622 MLX5_TX_PP,
1623 MLX5_TX_SKEW,
1624 MLX5_TX_VEC_EN,
1625 MLX5_RX_VEC_EN,
1626 MLX5_L3_VXLAN_EN,
1627 MLX5_VF_NL_EN,
1628 MLX5_DV_ESW_EN,
1629 MLX5_DV_FLOW_EN,
1630 MLX5_DV_XMETA_EN,
1631 MLX5_LACP_BY_USER,
1632 MLX5_MR_EXT_MEMSEG_EN,
1633 MLX5_REPRESENTOR,
1634 MLX5_MAX_DUMP_FILES_NUM,
1635 MLX5_LRO_TIMEOUT_USEC,
1636 MLX5_CLASS_ARG_NAME,
1637 MLX5_HP_BUF_SIZE,
1638 MLX5_RECLAIM_MEM,
1639 MLX5_SYS_MEM_EN,
1640 MLX5_DECAP_EN,
1641 NULL,
1642 };
1643 struct rte_kvargs *kvlist;
1644 int ret = 0;
1645 int i;
1646
1647 if (devargs == NULL)
1648 return 0;
1649 /* Following UGLY cast is done to pass checkpatch. */
1650 kvlist = rte_kvargs_parse(devargs->args, params);
1651 if (kvlist == NULL) {
1652 rte_errno = EINVAL;
1653 return -rte_errno;
1654 }
1655 /* Process parameters. */
1656 for (i = 0; (params[i] != NULL); ++i) {
1657 if (rte_kvargs_count(kvlist, params[i])) {
1658 ret = rte_kvargs_process(kvlist, params[i],
1659 mlx5_args_check, config);
1660 if (ret) {
1661 rte_errno = EINVAL;
1662 rte_kvargs_free(kvlist);
1663 return -rte_errno;
1664 }
1665 }
1666 }
1667 rte_kvargs_free(kvlist);
1668 return 0;
1669 }
1670
1671 /**
1672 * Configures the minimal amount of data to inline into WQE
1673 * while sending packets.
1674 *
1675 * - the txq_inline_min has the maximal priority, if this
1676 * key is specified in devargs
1677 * - if DevX is enabled the inline mode is queried from the
1678 * device (HCA attributes and NIC vport context if needed).
1679 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1680 * and none (0 bytes) for other NICs
1681 *
1682 * @param spawn
1683 * Verbs device parameters (name, port, switch_info) to spawn.
1684 * @param config
1685 * Device configuration parameters.
1686 */
1687 void
mlx5_set_min_inline(struct mlx5_dev_spawn_data * spawn,struct mlx5_dev_config * config)1688 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1689 struct mlx5_dev_config *config)
1690 {
1691 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1692 /* Application defines size of inlined data explicitly. */
1693 switch (spawn->pci_dev->id.device_id) {
1694 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1695 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1696 if (config->txq_inline_min <
1697 (int)MLX5_INLINE_HSIZE_L2) {
1698 DRV_LOG(DEBUG,
1699 "txq_inline_mix aligned to minimal"
1700 " ConnectX-4 required value %d",
1701 (int)MLX5_INLINE_HSIZE_L2);
1702 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1703 }
1704 break;
1705 }
1706 goto exit;
1707 }
1708 if (config->hca_attr.eth_net_offloads) {
1709 /* We have DevX enabled, inline mode queried successfully. */
1710 switch (config->hca_attr.wqe_inline_mode) {
1711 case MLX5_CAP_INLINE_MODE_L2:
1712 /* outer L2 header must be inlined. */
1713 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1714 goto exit;
1715 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1716 /* No inline data are required by NIC. */
1717 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1718 config->hw_vlan_insert =
1719 config->hca_attr.wqe_vlan_insert;
1720 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1721 goto exit;
1722 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1723 /* inline mode is defined by NIC vport context. */
1724 if (!config->hca_attr.eth_virt)
1725 break;
1726 switch (config->hca_attr.vport_inline_mode) {
1727 case MLX5_INLINE_MODE_NONE:
1728 config->txq_inline_min =
1729 MLX5_INLINE_HSIZE_NONE;
1730 goto exit;
1731 case MLX5_INLINE_MODE_L2:
1732 config->txq_inline_min =
1733 MLX5_INLINE_HSIZE_L2;
1734 goto exit;
1735 case MLX5_INLINE_MODE_IP:
1736 config->txq_inline_min =
1737 MLX5_INLINE_HSIZE_L3;
1738 goto exit;
1739 case MLX5_INLINE_MODE_TCP_UDP:
1740 config->txq_inline_min =
1741 MLX5_INLINE_HSIZE_L4;
1742 goto exit;
1743 case MLX5_INLINE_MODE_INNER_L2:
1744 config->txq_inline_min =
1745 MLX5_INLINE_HSIZE_INNER_L2;
1746 goto exit;
1747 case MLX5_INLINE_MODE_INNER_IP:
1748 config->txq_inline_min =
1749 MLX5_INLINE_HSIZE_INNER_L3;
1750 goto exit;
1751 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1752 config->txq_inline_min =
1753 MLX5_INLINE_HSIZE_INNER_L4;
1754 goto exit;
1755 }
1756 }
1757 }
1758 /*
1759 * We get here if we are unable to deduce
1760 * inline data size with DevX. Try PCI ID
1761 * to determine old NICs.
1762 */
1763 switch (spawn->pci_dev->id.device_id) {
1764 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1765 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1766 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1767 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1768 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1769 config->hw_vlan_insert = 0;
1770 break;
1771 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1772 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1773 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1774 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1775 /*
1776 * These NICs support VLAN insertion from WQE and
1777 * report the wqe_vlan_insert flag. But there is the bug
1778 * and PFC control may be broken, so disable feature.
1779 */
1780 config->hw_vlan_insert = 0;
1781 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1782 break;
1783 default:
1784 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1785 break;
1786 }
1787 exit:
1788 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1789 }
1790
1791 /**
1792 * Configures the metadata mask fields in the shared context.
1793 *
1794 * @param [in] dev
1795 * Pointer to Ethernet device.
1796 */
1797 void
mlx5_set_metadata_mask(struct rte_eth_dev * dev)1798 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1799 {
1800 struct mlx5_priv *priv = dev->data->dev_private;
1801 struct mlx5_dev_ctx_shared *sh = priv->sh;
1802 uint32_t meta, mark, reg_c0;
1803
1804 reg_c0 = ~priv->vport_meta_mask;
1805 switch (priv->config.dv_xmeta_en) {
1806 case MLX5_XMETA_MODE_LEGACY:
1807 meta = UINT32_MAX;
1808 mark = MLX5_FLOW_MARK_MASK;
1809 break;
1810 case MLX5_XMETA_MODE_META16:
1811 meta = reg_c0 >> rte_bsf32(reg_c0);
1812 mark = MLX5_FLOW_MARK_MASK;
1813 break;
1814 case MLX5_XMETA_MODE_META32:
1815 meta = UINT32_MAX;
1816 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1817 break;
1818 default:
1819 meta = 0;
1820 mark = 0;
1821 MLX5_ASSERT(false);
1822 break;
1823 }
1824 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1825 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1826 sh->dv_mark_mask, mark);
1827 else
1828 sh->dv_mark_mask = mark;
1829 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1830 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1831 sh->dv_meta_mask, meta);
1832 else
1833 sh->dv_meta_mask = meta;
1834 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1835 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1836 sh->dv_meta_mask, reg_c0);
1837 else
1838 sh->dv_regc0_mask = reg_c0;
1839 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1840 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1841 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1842 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1843 }
1844
1845 int
rte_pmd_mlx5_get_dyn_flag_names(char * names[],unsigned int n)1846 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1847 {
1848 static const char *const dynf_names[] = {
1849 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1850 RTE_MBUF_DYNFLAG_METADATA_NAME,
1851 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1852 };
1853 unsigned int i;
1854
1855 if (n < RTE_DIM(dynf_names))
1856 return -ENOMEM;
1857 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1858 if (names[i] == NULL)
1859 return -EINVAL;
1860 strcpy(names[i], dynf_names[i]);
1861 }
1862 return RTE_DIM(dynf_names);
1863 }
1864
1865 /**
1866 * Comparison callback to sort device data.
1867 *
1868 * This is meant to be used with qsort().
1869 *
1870 * @param a[in]
1871 * Pointer to pointer to first data object.
1872 * @param b[in]
1873 * Pointer to pointer to second data object.
1874 *
1875 * @return
1876 * 0 if both objects are equal, less than 0 if the first argument is less
1877 * than the second, greater than 0 otherwise.
1878 */
1879 int
mlx5_dev_check_sibling_config(struct mlx5_priv * priv,struct mlx5_dev_config * config)1880 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1881 struct mlx5_dev_config *config)
1882 {
1883 struct mlx5_dev_ctx_shared *sh = priv->sh;
1884 struct mlx5_dev_config *sh_conf = NULL;
1885 uint16_t port_id;
1886
1887 MLX5_ASSERT(sh);
1888 /* Nothing to compare for the single/first device. */
1889 if (sh->refcnt == 1)
1890 return 0;
1891 /* Find the device with shared context. */
1892 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1893 struct mlx5_priv *opriv =
1894 rte_eth_devices[port_id].data->dev_private;
1895
1896 if (opriv && opriv != priv && opriv->sh == sh) {
1897 sh_conf = &opriv->config;
1898 break;
1899 }
1900 }
1901 if (!sh_conf)
1902 return 0;
1903 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1904 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1905 " for shared %s context", sh->ibdev_name);
1906 rte_errno = EINVAL;
1907 return rte_errno;
1908 }
1909 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1910 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1911 " for shared %s context", sh->ibdev_name);
1912 rte_errno = EINVAL;
1913 return rte_errno;
1914 }
1915 return 0;
1916 }
1917
1918 /**
1919 * Look for the ethernet device belonging to mlx5 driver.
1920 *
1921 * @param[in] port_id
1922 * port_id to start looking for device.
1923 * @param[in] pci_dev
1924 * Pointer to the hint PCI device. When device is being probed
1925 * the its siblings (master and preceding representors might
1926 * not have assigned driver yet (because the mlx5_os_pci_probe()
1927 * is not completed yet, for this case match on hint PCI
1928 * device may be used to detect sibling device.
1929 *
1930 * @return
1931 * port_id of found device, RTE_MAX_ETHPORT if not found.
1932 */
1933 uint16_t
mlx5_eth_find_next(uint16_t port_id,struct rte_pci_device * pci_dev)1934 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1935 {
1936 while (port_id < RTE_MAX_ETHPORTS) {
1937 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1938
1939 if (dev->state != RTE_ETH_DEV_UNUSED &&
1940 dev->device &&
1941 (dev->device == &pci_dev->device ||
1942 (dev->device->driver &&
1943 dev->device->driver->name &&
1944 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1945 break;
1946 port_id++;
1947 }
1948 if (port_id >= RTE_MAX_ETHPORTS)
1949 return RTE_MAX_ETHPORTS;
1950 return port_id;
1951 }
1952
1953 /**
1954 * DPDK callback to remove a PCI device.
1955 *
1956 * This function removes all Ethernet devices belong to a given PCI device.
1957 *
1958 * @param[in] pci_dev
1959 * Pointer to the PCI device.
1960 *
1961 * @return
1962 * 0 on success, the function cannot fail.
1963 */
1964 static int
mlx5_pci_remove(struct rte_pci_device * pci_dev)1965 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1966 {
1967 uint16_t port_id;
1968 int ret = 0;
1969
1970 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1971 /*
1972 * mlx5_dev_close() is not registered to secondary process,
1973 * call the close function explicitly for secondary process.
1974 */
1975 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1976 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1977 else
1978 ret |= rte_eth_dev_close(port_id);
1979 }
1980 return ret == 0 ? 0 : -EIO;
1981 }
1982
1983 static const struct rte_pci_id mlx5_pci_id_map[] = {
1984 {
1985 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1986 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1987 },
1988 {
1989 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1990 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1991 },
1992 {
1993 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1994 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1995 },
1996 {
1997 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1998 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1999 },
2000 {
2001 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2002 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2003 },
2004 {
2005 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2006 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2007 },
2008 {
2009 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2010 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2011 },
2012 {
2013 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2014 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2015 },
2016 {
2017 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2018 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2019 },
2020 {
2021 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2022 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2023 },
2024 {
2025 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2026 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2027 },
2028 {
2029 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2030 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2031 },
2032 {
2033 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2034 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2035 },
2036 {
2037 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2038 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2039 },
2040 {
2041 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2042 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2043 },
2044 {
2045 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2046 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2047 },
2048 {
2049 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2050 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2051 },
2052 {
2053 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2054 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2055 },
2056 {
2057 .vendor_id = 0
2058 }
2059 };
2060
2061 static struct mlx5_pci_driver mlx5_driver = {
2062 .driver_class = MLX5_CLASS_NET,
2063 .pci_driver = {
2064 .driver = {
2065 .name = MLX5_DRIVER_NAME,
2066 },
2067 .id_table = mlx5_pci_id_map,
2068 .probe = mlx5_os_pci_probe,
2069 .remove = mlx5_pci_remove,
2070 .dma_map = mlx5_dma_map,
2071 .dma_unmap = mlx5_dma_unmap,
2072 .drv_flags = PCI_DRV_FLAGS,
2073 },
2074 };
2075
2076 /* Initialize driver log type. */
2077 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2078
2079 /**
2080 * Driver initialization routine.
2081 */
RTE_INIT(rte_mlx5_pmd_init)2082 RTE_INIT(rte_mlx5_pmd_init)
2083 {
2084 mlx5_common_init();
2085 /* Build the static tables for Verbs conversion. */
2086 mlx5_set_ptype_table();
2087 mlx5_set_cksum_table();
2088 mlx5_set_swp_types_table();
2089 if (mlx5_glue)
2090 mlx5_pci_driver_register(&mlx5_driver);
2091 }
2092
2093 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2094 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2095 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
2096