1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 Adrian Chadd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include "opt_ddb.h"
33
34 #include <sys/param.h>
35 #include <sys/conf.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cons.h>
40 #include <sys/kdb.h>
41 #include <sys/reboot.h>
42
43 #include <vm/vm.h>
44 #include <vm/vm_page.h>
45
46 #include <net/ethernet.h>
47
48 #include <machine/clock.h>
49 #include <machine/cpu.h>
50 #include <machine/cpuregs.h>
51 #include <machine/hwfunc.h>
52 #include <machine/md_var.h>
53 #include <machine/trap.h>
54 #include <machine/vmparam.h>
55
56 #include <mips/atheros/ar71xxreg.h>
57 #include <mips/atheros/ar71xx_chip.h>
58 #include <mips/atheros/ar71xx_cpudef.h>
59
60 /* XXX these should replace the current definitions in ar71xxreg.h */
61 /* XXX perhaps an ar71xx_chip.h header file? */
62 #define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
63 #define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04
64 #define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10
65 #define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
66
67 #define AR71XX_PLL_DIV_SHIFT 3
68 #define AR71XX_PLL_DIV_MASK 0x1f
69 #define AR71XX_CPU_DIV_SHIFT 16
70 #define AR71XX_CPU_DIV_MASK 0x3
71 #define AR71XX_DDR_DIV_SHIFT 18
72 #define AR71XX_DDR_DIV_MASK 0x3
73 #define AR71XX_AHB_DIV_SHIFT 20
74 #define AR71XX_AHB_DIV_MASK 0x7
75
76 /* XXX these shouldn't be in here - this file is a per-chip file */
77 /* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
78 uint32_t u_ar71xx_cpu_freq;
79 uint32_t u_ar71xx_ahb_freq;
80 uint32_t u_ar71xx_ddr_freq;
81 uint32_t u_ar71xx_uart_freq;
82 uint32_t u_ar71xx_wdt_freq;
83 uint32_t u_ar71xx_refclk;
84 uint32_t u_ar71xx_mdio_freq;
85
86 static void
ar71xx_chip_detect_mem_size(void)87 ar71xx_chip_detect_mem_size(void)
88 {
89 }
90
91 static void
ar71xx_chip_detect_sys_frequency(void)92 ar71xx_chip_detect_sys_frequency(void)
93 {
94 uint32_t pll;
95 uint32_t freq;
96 uint32_t div;
97
98 u_ar71xx_mdio_freq = u_ar71xx_refclk = AR71XX_BASE_FREQ;
99
100 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
101
102 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
103 freq = div * AR71XX_BASE_FREQ;
104
105 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
106 u_ar71xx_cpu_freq = freq / div;
107
108 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
109 u_ar71xx_ddr_freq = freq / div;
110
111 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
112 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
113 u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
114 u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
115 }
116
117 /*
118 * This does not lock the CPU whilst doing the work!
119 */
120 static void
ar71xx_chip_device_stop(uint32_t mask)121 ar71xx_chip_device_stop(uint32_t mask)
122 {
123 uint32_t reg;
124
125 reg = ATH_READ_REG(AR71XX_RST_RESET);
126 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
127 }
128
129 static void
ar71xx_chip_device_start(uint32_t mask)130 ar71xx_chip_device_start(uint32_t mask)
131 {
132 uint32_t reg;
133
134 reg = ATH_READ_REG(AR71XX_RST_RESET);
135 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
136 }
137
138 static int
ar71xx_chip_device_stopped(uint32_t mask)139 ar71xx_chip_device_stopped(uint32_t mask)
140 {
141 uint32_t reg;
142
143 reg = ATH_READ_REG(AR71XX_RST_RESET);
144 return ((reg & mask) == mask);
145 }
146
147 void
ar71xx_chip_set_mii_speed(uint32_t unit,uint32_t speed)148 ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed)
149 {
150 uint32_t val, reg, ctrl;
151
152 switch (unit) {
153 case 0:
154 reg = AR71XX_MII0_CTRL;
155 break;
156 case 1:
157 reg = AR71XX_MII1_CTRL;
158 break;
159 default:
160 printf("%s: invalid MII unit set for arge unit: %d\n",
161 __func__, unit);
162 return;
163 }
164
165 switch (speed) {
166 case 10:
167 ctrl = MII_CTRL_SPEED_10;
168 break;
169 case 100:
170 ctrl = MII_CTRL_SPEED_100;
171 break;
172 case 1000:
173 ctrl = MII_CTRL_SPEED_1000;
174 break;
175 default:
176 printf("%s: invalid MII speed (%d) set for arge unit: %d\n",
177 __func__, speed, unit);
178 return;
179 }
180
181 val = ATH_READ_REG(reg);
182 val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
183 val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
184 ATH_WRITE_REG(reg, val);
185 }
186
187 void
ar71xx_chip_set_mii_if(uint32_t unit,uint32_t mii_mode)188 ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
189 {
190 uint32_t val, reg, mii_if;
191
192 switch (unit) {
193 case 0:
194 reg = AR71XX_MII0_CTRL;
195 if (mii_mode == AR71XX_MII_MODE_GMII)
196 mii_if = MII0_CTRL_IF_GMII;
197 else if (mii_mode == AR71XX_MII_MODE_MII)
198 mii_if = MII0_CTRL_IF_MII;
199 else if (mii_mode == AR71XX_MII_MODE_RGMII)
200 mii_if = MII0_CTRL_IF_RGMII;
201 else if (mii_mode == AR71XX_MII_MODE_RMII)
202 mii_if = MII0_CTRL_IF_RMII;
203 else {
204 printf("%s: invalid MII mode (%d) for unit %d\n",
205 __func__, mii_mode, unit);
206 return;
207 }
208 break;
209 case 1:
210 reg = AR71XX_MII1_CTRL;
211 if (mii_mode == AR71XX_MII_MODE_RGMII)
212 mii_if = MII1_CTRL_IF_RGMII;
213 else if (mii_mode == AR71XX_MII_MODE_RMII)
214 mii_if = MII1_CTRL_IF_RMII;
215 else {
216 printf("%s: invalid MII mode (%d) for unit %d\n",
217 __func__, mii_mode, unit);
218 return;
219 }
220 break;
221 default:
222 printf("%s: invalid MII unit set for arge unit: %d\n",
223 __func__, unit);
224 return;
225 }
226
227 val = ATH_READ_REG(reg);
228 val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT);
229 val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT;
230 ATH_WRITE_REG(reg, val);
231 }
232
233 /* Speed is either 10, 100 or 1000 */
234 static void
ar71xx_chip_set_pll_ge(int unit,int speed,uint32_t pll)235 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
236 {
237
238 switch (unit) {
239 case 0:
240 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
241 AR71XX_PLL_ETH_INT0_CLK, pll,
242 AR71XX_PLL_ETH0_SHIFT);
243 break;
244 case 1:
245 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
246 AR71XX_PLL_ETH_INT1_CLK, pll,
247 AR71XX_PLL_ETH1_SHIFT);
248 break;
249 default:
250 printf("%s: invalid PLL set for arge unit: %d\n",
251 __func__, unit);
252 return;
253 }
254 }
255
256 static void
ar71xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)257 ar71xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
258 {
259
260 switch (id) {
261 case AR71XX_CPU_DDR_FLUSH_GE0:
262 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
263 break;
264 case AR71XX_CPU_DDR_FLUSH_GE1:
265 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
266 break;
267 case AR71XX_CPU_DDR_FLUSH_USB:
268 ar71xx_ddr_flush(AR71XX_WB_FLUSH_USB);
269 break;
270 case AR71XX_CPU_DDR_FLUSH_PCIE:
271 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
272 break;
273 default:
274 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
275 break;
276 }
277 }
278
279 static uint32_t
ar71xx_chip_get_eth_pll(unsigned int mac,int speed)280 ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
281 {
282 uint32_t pll;
283
284 switch (speed) {
285 case 10:
286 pll = PLL_ETH_INT_CLK_10;
287 break;
288 case 100:
289 pll = PLL_ETH_INT_CLK_100;
290 break;
291 case 1000:
292 pll = PLL_ETH_INT_CLK_1000;
293 break;
294 default:
295 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
296 pll = 0;
297 }
298
299 return (pll);
300 }
301
302 static void
ar71xx_chip_init_usb_peripheral(void)303 ar71xx_chip_init_usb_peripheral(void)
304 {
305
306 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL |
307 RST_RESET_USB_HOST | RST_RESET_USB_PHY);
308 DELAY(1000);
309
310 ar71xx_device_start(RST_RESET_USB_OHCI_DLL |
311 RST_RESET_USB_HOST | RST_RESET_USB_PHY);
312 DELAY(1000);
313
314 ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
315 USB_CTRL_CONFIG_OHCI_DES_SWAP |
316 USB_CTRL_CONFIG_OHCI_BUF_SWAP |
317 USB_CTRL_CONFIG_EHCI_DES_SWAP |
318 USB_CTRL_CONFIG_EHCI_BUF_SWAP);
319
320 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
321 (32 << USB_CTRL_FLADJ_HOST_SHIFT) |
322 (3 << USB_CTRL_FLADJ_A5_SHIFT));
323
324 DELAY(1000);
325 }
326
327 struct ar71xx_cpu_def ar71xx_chip_def = {
328 &ar71xx_chip_detect_mem_size,
329 &ar71xx_chip_detect_sys_frequency,
330 &ar71xx_chip_device_stop,
331 &ar71xx_chip_device_start,
332 &ar71xx_chip_device_stopped,
333 &ar71xx_chip_set_pll_ge,
334 &ar71xx_chip_set_mii_speed,
335 &ar71xx_chip_set_mii_if,
336 &ar71xx_chip_get_eth_pll,
337 &ar71xx_chip_ddr_flush,
338 &ar71xx_chip_init_usb_peripheral,
339 };
340