1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _GIC_V3_VAR_H_ 33 #define _GIC_V3_VAR_H_ 34 35 #include <arm/arm/gic_common.h> 36 37 #define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0" 38 39 DECLARE_CLASS(gic_v3_driver); 40 41 struct gic_v3_irqsrc; 42 43 struct redist_pcpu { 44 struct resource res; /* mem resource for redist */ 45 vm_offset_t pend_base; 46 bool lpi_enabled; /* redist LPI configured? */ 47 }; 48 49 struct gic_redists { 50 /* 51 * Re-Distributor region description. 52 * We will have few of those depending 53 * on the #redistributor-regions property in FDT. 54 */ 55 struct resource ** regions; 56 /* Number of Re-Distributor regions */ 57 u_int nregions; 58 /* Per-CPU Re-Distributor data */ 59 struct redist_pcpu *pcpu[MAXCPU]; 60 }; 61 62 struct gic_v3_softc { 63 device_t dev; 64 struct resource ** gic_res; 65 struct mtx gic_mtx; 66 /* Distributor */ 67 struct resource * gic_dist; 68 /* Re-Distributors */ 69 struct gic_redists gic_redists; 70 71 /* Message Based Interrupts */ 72 u_int gic_mbi_start; 73 u_int gic_mbi_end; 74 struct mtx gic_mbi_mtx; 75 76 uint32_t gic_pidr2; 77 u_int gic_bus; 78 79 u_int gic_nirqs; 80 u_int gic_idbits; 81 82 boolean_t gic_registered; 83 84 int gic_nchildren; 85 device_t *gic_children; 86 struct intr_pic *gic_pic; 87 struct gic_v3_irqsrc *gic_irqs; 88 }; 89 90 struct gic_v3_devinfo { 91 int gic_domain; 92 int msi_xref; 93 }; 94 95 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) 96 97 MALLOC_DECLARE(M_GIC_V3); 98 99 /* ivars */ 100 #define GICV3_IVAR_NIRQS 1000 101 /* 1001 was GICV3_IVAR_REDIST_VADDR */ 102 #define GICV3_IVAR_REDIST 1002 103 104 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int); 105 __BUS_ACCESSOR(gicv3, redist, GICV3, REDIST, void *); 106 107 /* Device methods */ 108 int gic_v3_attach(device_t dev); 109 int gic_v3_detach(device_t dev); 110 int arm_gic_v3_intr(void *); 111 112 uint32_t gic_r_read_4(device_t, bus_size_t); 113 uint64_t gic_r_read_8(device_t, bus_size_t); 114 void gic_r_write_4(device_t, bus_size_t, uint32_t var); 115 void gic_r_write_8(device_t, bus_size_t, uint64_t var); 116 117 /* 118 * GIC Distributor accessors. 119 * Notice that only GIC sofc can be passed. 120 */ 121 #define gic_d_read(sc, len, reg) \ 122 ({ \ 123 bus_read_##len(sc->gic_dist, reg); \ 124 }) 125 126 #define gic_d_write(sc, len, reg, val) \ 127 ({ \ 128 bus_write_##len(sc->gic_dist, reg, val);\ 129 }) 130 131 /* GIC Re-Distributor accessors (per-CPU) */ 132 #define gic_r_read(sc, len, reg) \ 133 ({ \ 134 u_int cpu = PCPU_GET(cpuid); \ 135 \ 136 bus_read_##len( \ 137 &sc->gic_redists.pcpu[cpu]->res, \ 138 reg); \ 139 }) 140 141 #define gic_r_write(sc, len, reg, val) \ 142 ({ \ 143 u_int cpu = PCPU_GET(cpuid); \ 144 \ 145 bus_write_##len( \ 146 &sc->gic_redists.pcpu[cpu]->res, \ 147 reg, val); \ 148 }) 149 150 #endif /* _GIC_V3_VAR_H_ */ 151