1 /***********************license start***************
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3 * reserved.
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37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
39
40
41
42
43
44
45
46 /**
47 * @file
48 *
49 * Support library for the SPI4000 card
50 *
51 * <hr>$Revision: 70030 $<hr>
52 */
53 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
54 #include <linux/module.h>
55 #include <asm/octeon/cvmx.h>
56 #include <asm/octeon/cvmx-spi.h>
57 #include <asm/octeon/cvmx-twsi.h>
58 #include <asm/octeon/cvmx-gmxx-defs.h>
59 #else
60 #include "cvmx.h"
61 #include "cvmx-spi.h"
62 #include "cvmx-twsi.h"
63 #endif
64
65 /* If someone is using an old config, make the SPI4000 act like RGMII for backpressure */
66 #ifndef CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE
67 #ifndef CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
68 #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
69 #endif
70 #define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
71 #endif
72
73 #define SPI4000_READ_ADDRESS_HIGH 0xf0
74 #define SPI4000_READ_ADDRESS_LOW 0xf1
75 #define SPI4000_WRITE_ADDRESS_HIGH 0xf2
76 #define SPI4000_WRITE_ADDRESS_LOW 0xf3
77 #define SPI4000_READ_DATA0 0xf4 /* High byte */
78 #define SPI4000_READ_DATA1 0xf5
79 #define SPI4000_READ_DATA2 0xf6
80 #define SPI4000_READ_DATA3 0xf7 /* Low byte */
81 #define SPI4000_WRITE_DATA0 0xf8 /* High byte */
82 #define SPI4000_WRITE_DATA1 0xf9
83 #define SPI4000_WRITE_DATA2 0xfa
84 #define SPI4000_WRITE_DATA3 0xfb /* Low byte */
85 #define SPI4000_DO_READ 0xfc /* Issue a read, returns read status */
86 #define SPI4000_GET_READ_STATUS 0xfd /* 0xff: initial state, 2: Read failed, 1: Read pending, 0: Read success */
87 #define SPI4000_DO_WRITE 0xfe /* Issue a write, returns write status */
88 #define SPI4000_GET_WRITE_STATUS 0xff /* 0xff: initial state, 6: Write failed, 5: Write pending, 4: Write success */
89 #define SPI4000_TWSI_ID(interface) (0x66 + interface)
90
91 /* MDI Single Command (register 0x680) */
92 typedef union
93 {
94 uint32_t u32;
95 struct
96 {
97 uint32_t reserved_21_31 : 11;
98 uint32_t mdi_command : 1; /**< Performs an MDIO access. When set, this bit
99 self clears upon completion of the access. */
100 uint32_t reserved_18_19 : 2;
101 uint32_t op_code : 2; /**< MDIO Op Code
102 00 = Reserved
103 01 = Write Access
104 10 = Read Access
105 11 = Reserved */
106 uint32_t reserved_13_15 : 3;
107 uint32_t phy_address : 5; /**< Address of external PHY device */
108 uint32_t reserved_5_7 : 3;
109 uint32_t reg_address : 5; /**< Address of register within external PHY */
110 } s;
111 } mdio_single_command_t;
112
113
114 static CVMX_SHARED int interface_is_spi4000[2] = {0,0};
115
116
117 /**
118 * @INTERNAL
119 * Write data to the specified SPI4000 address
120 *
121 * @param interface Interface the SPI4000 is on. (0 or 1)
122 * @param address Address to write to
123 * @param data Data to write
124 */
__cvmx_spi4000_write(int interface,int address,uint32_t data)125 static void __cvmx_spi4000_write(int interface, int address, uint32_t data)
126 {
127 int status;
128 cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 2, 1, address);
129 cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_DATA0, 4, 1, data);
130
131 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_WRITE);
132 while ((status == 5) || (status == 0xff))
133 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_WRITE_STATUS);
134
135 if (status != 4)
136 cvmx_dprintf("SPI4000: write failed with status=0x%x\n", status);
137 }
138
139
140 /**
141 * @INTERNAL
142 * Read data from the SPI4000.
143 *
144 * @param interface Interface the SPI4000 is on. (0 or 1)
145 * @param address Address to read from
146 *
147 * @return Value at the specified address
148 */
__cvmx_spi4000_read(int interface,int address)149 static uint32_t __cvmx_spi4000_read(int interface, int address)
150 {
151 int status;
152 uint64_t data;
153
154 cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_ADDRESS_HIGH, 2, 1, address);
155
156 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_READ);
157 while ((status == 1) || (status == 0xff))
158 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_READ_STATUS);
159
160 if (status)
161 {
162 cvmx_dprintf("SPI4000: read failed with %d\n", status);
163 return 0;
164 }
165
166 status = cvmx_twsix_read_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_DATA0, 4, 1, &data);
167 if (status != 4)
168 {
169 cvmx_dprintf("SPI4000: read failed with %d\n", status);
170 return 0;
171 }
172
173 return data;
174 }
175
176
177 /**
178 * @INTERNAL
179 * Write to a PHY using MDIO on the SPI4000
180 *
181 * @param interface Interface the SPI4000 is on. (0 or 1)
182 * @param port SPI4000 RGMII port to write to. (0-9)
183 * @param location MDIO register to write
184 * @param val Value to write
185 */
__cvmx_spi4000_mdio_write(int interface,int port,int location,int val)186 static void __cvmx_spi4000_mdio_write(int interface, int port, int location, int val)
187 {
188 static int last_value=-1;
189 mdio_single_command_t mdio;
190
191 mdio.u32 = 0;
192 mdio.s.mdi_command = 1;
193 mdio.s.op_code = 1;
194 mdio.s.phy_address = port;
195 mdio.s.reg_address = location;
196
197 /* Since the TWSI accesses are very slow, don't update the write value
198 if it is the same as the last value */
199 if (val != last_value)
200 {
201 last_value = val;
202 __cvmx_spi4000_write(interface, 0x0681, val);
203 }
204
205 __cvmx_spi4000_write(interface, 0x0680, mdio.u32);
206 }
207
208
209 /**
210 * @INTERNAL
211 * Read from a PHY using MDIO on the SPI4000
212 *
213 * @param interface Interface the SPI4000 is on. (0 or 1)
214 * @param port SPI4000 RGMII port to read from. (0-9)
215 * @param location MDIO register to read
216 * @return The MDI read result
217 */
__cvmx_spi4000_mdio_read(int interface,int port,int location)218 static int __cvmx_spi4000_mdio_read(int interface, int port, int location)
219 {
220 mdio_single_command_t mdio;
221
222 mdio.u32 = 0;
223 mdio.s.mdi_command = 1;
224 mdio.s.op_code = 2;
225 mdio.s.phy_address = port;
226 mdio.s.reg_address = location;
227 __cvmx_spi4000_write(interface, 0x0680, mdio.u32);
228
229 do
230 {
231 mdio.u32 = __cvmx_spi4000_read(interface, 0x0680);
232 } while (mdio.s.mdi_command);
233
234 return __cvmx_spi4000_read(interface, 0x0681) >> 16;
235 }
236
237
238 /**
239 * @INTERNAL
240 * Configure the SPI4000 MACs
241 */
__cvmx_spi4000_configure_mac(int interface)242 static void __cvmx_spi4000_configure_mac(int interface)
243 {
244 int port;
245 // IXF1010 configuration
246 // ---------------------
247 //
248 // Step 1: Apply soft reset to TxFIFO and MAC
249 // MAC soft reset register. address=0x505
250 // TxFIFO soft reset. address=0x620
251 __cvmx_spi4000_write(interface, 0x0505, 0x3ff); // reset all the MACs
252 __cvmx_spi4000_write(interface, 0x0620, 0x3ff); // reset the TX FIFOs
253
254 // Global address and Configuration Register. address=0x500
255 //
256 // Step 2: Apply soft reset to RxFIFO and SPI.
257 __cvmx_spi4000_write(interface, 0x059e, 0x3ff); // reset the RX FIFOs
258
259 // Step 3a: Take the MAC out of softreset
260 // MAC soft reset register. address=0x505
261 __cvmx_spi4000_write(interface, 0x0505, 0x0); // reset all the MACs
262
263 // Step 3b: De-assert port enables.
264 // Global address and Configuration Register. address=0x500
265 __cvmx_spi4000_write(interface, 0x0500, 0x0); // disable all ports
266
267 // Step 4: Assert Clock mode change En.
268 // Clock and interface mode Change En. address=Serdes base + 0x14
269 // Serdes (Serializer/de-serializer). address=0x780
270 // [Can't find this one]
271
272 for (port=0; port < 10; port++)
273 {
274 int port_offset = port << 7;
275
276 // Step 5: Set MAC interface mode GMII speed.
277 // MAC interface mode and RGMII speed register.
278 // address=port_index+0x10
279 //
280 // OUT port_index+0x10, 0x07 //RGMII 1000 Mbps operation.
281 __cvmx_spi4000_write(interface, port_offset | 0x0010, 0x3);
282
283 // Set the max packet size to 16383 bytes, including the CRC
284 __cvmx_spi4000_write(interface, port_offset | 0x000f, 0x3fff);
285
286 // Step 6: Change Interface to Copper mode
287 // Interface mode register. address=0x501
288 // [Can't find this]
289
290 // Step 7: MAC configuration
291 // Station address configuration.
292 // Source MAC address low register. Source MAC address 31-0.
293 // address=port_index+0x00
294 // Source MAC address high register. Source MAC address 47-32.
295 // address=port_index+0x01
296 // where Port index is 0x0 to 0x5.
297 // This address is inserted in the source address filed when
298 // transmitting pause frames, and is also used to compare against
299 // unicast pause frames at the receiving side.
300 //
301 // OUT port_index+0x00, source MAC address low.
302 __cvmx_spi4000_write(interface, port_offset | 0x0000, 0x0000);
303 // OUT port_index+0x01, source MAC address high.
304 __cvmx_spi4000_write(interface, port_offset | 0x0001, 0x0000);
305
306 // Step 8: Set desired duplex mode
307 // Desired duplex register. address=port_index+0x02
308 // [Reserved]
309
310 // Step 9: Other configuration.
311 // FC Enable Register. address=port_index+0x12
312 // Discard Unknown Control Frame. address=port_index+0x15
313 // Diverse config write register. address=port_index+0x18
314 // RX Packet Filter register. address=port_index+0x19
315 //
316 // Step 9a: Tx FD FC Enabled / Rx FD FC Enabled
317 if (CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE)
318 __cvmx_spi4000_write(interface, port_offset | 0x0012, 0);
319 else
320 __cvmx_spi4000_write(interface, port_offset | 0x0012, 0x7);
321
322 // Step 9b: Discard unknown control frames
323 __cvmx_spi4000_write(interface, port_offset | 0x0015, 0x1);
324
325 // Step 9c: Enable auto-CRC and auto-padding
326 __cvmx_spi4000_write(interface, port_offset | 0x0018, 0x11cd); //??
327
328 // Step 9d: Drop bad CRC / Drop Pause / No DAF
329 __cvmx_spi4000_write(interface, port_offset | 0x0019, 0x00);
330 }
331
332 // Step 9d: Drop frames
333 __cvmx_spi4000_write(interface, 0x059f, 0x03ff);
334
335 for (port=0; port < 10; port++)
336 {
337 // Step 9e: Set the TX FIFO marks
338 __cvmx_spi4000_write(interface, port + 0x0600, 0x0900); // TXFIFO High watermark
339 __cvmx_spi4000_write(interface, port + 0x060a, 0x0800); // TXFIFO Low watermark
340 __cvmx_spi4000_write(interface, port + 0x0614, 0x0380); // TXFIFO threshold
341 }
342
343 // Step 12: De-assert RxFIFO and SPI Rx/Tx reset
344 __cvmx_spi4000_write(interface, 0x059e, 0x0); // reset the RX FIFOs
345
346 // Step 13: De-assert TxFIFO and MAC reset
347 __cvmx_spi4000_write(interface, 0x0620, 0x0); // reset the TX FIFOs
348
349 // Step 14: Assert port enable
350 // Global address and Configuration Register. address=0x500
351 __cvmx_spi4000_write(interface, 0x0500, 0x03ff); // enable all ports
352
353 // Step 15: Disable loopback
354 // [Can't find this one]
355 }
356
357
358 /**
359 * @INTERNAL
360 * Configure the SPI4000 PHYs
361 */
__cvmx_spi4000_configure_phy(int interface)362 static void __cvmx_spi4000_configure_phy(int interface)
363 {
364 int port;
365
366 /* We use separate loops below since it allows us to save a write
367 to the SPI4000 for each repeated value. This adds up to a couple
368 of seconds */
369
370 /* Update the link state before resets. It takes a while for the links to
371 come back after the resets. Most likely they'll come back the same as
372 they are now */
373 for (port=0; port < 10; port++)
374 cvmx_spi4000_check_speed(interface, port);
375 /* Enable RGMII DELAYS for TX_CLK and RX_CLK (see spec) */
376 for (port=0; port < 10; port++)
377 __cvmx_spi4000_mdio_write(interface, port, 0x14, 0x00e2);
378 /* Advertise pause and 100 Full Duplex. Don't advertise half duplex or 10Mbpa */
379 for (port=0; port < 10; port++)
380 __cvmx_spi4000_mdio_write(interface, port, 0x4, 0x0d01);
381 /* Enable PHY reset */
382 for (port=0; port < 10; port++)
383 __cvmx_spi4000_mdio_write(interface, port, 0x0, 0x9140);
384 }
385
386
387 /**
388 * Poll all the SPI4000 port and check its speed
389 *
390 * @param interface Interface the SPI4000 is on
391 * @param port Port to poll (0-9)
392 * @return Status of the port. 0=down. All other values the port is up.
393 */
cvmx_spi4000_check_speed(int interface,int port)394 cvmx_gmxx_rxx_rx_inbnd_t cvmx_spi4000_check_speed(int interface, int port)
395 {
396 static int phy_status[10] = {0,};
397 cvmx_gmxx_rxx_rx_inbnd_t link;
398 int read_status;
399
400 link.u64 = 0;
401
402 if (!interface_is_spi4000[interface])
403 return link;
404 if (port>=10)
405 return link;
406
407 /* Register 0x11: PHY Specific Status Register
408 Register Function Setting Mode HW Rst SW Rst Notes
409 RO 00 Retain note
410 17.15:14 Speed 11 = Reserved
411 17.a
412 10 = 1000 Mbps
413 01 = 100 Mbps
414 00 = 10 Mbps
415 17.13 Duplex 1 = Full-duplex RO 0 Retain note
416 0 = Half-duplex 17.a
417 17.12 Page Received 1 = Page received RO, LH 0 0
418 0 = Page not received
419 1 = Resolved RO 0 0 note
420 17.11 Speed and
421 0 = Not resolved 17.a
422 Duplex
423 Resolved
424 17.10 Link (real time) 1 = Link up RO 0 0
425 0 = Link down
426 RO 000 000 note
427 000 = < 50m
428 17.9:7 Cable Length
429 001 = 50 - 80m 17.b
430 (100/1000
431 010 = 80 - 110m
432 modes only)
433 011 = 110 - 140m
434 100 = >140m
435 17.6 MDI Crossover 1 = MDIX RO 0 0 note
436 Status 0 = MDI 17.a
437 17.5 Downshift Sta- 1 = Downshift RO 0 0
438 tus 0 = No Downshift
439 17.4 Energy Detect 1 = Sleep RO 0 0
440 Status 0 = Active
441 17.3 Transmit Pause 1 = Transmit pause enabled RO 0 0 note17.
442 Enabled 0 = Transmit pause disabled a, 17.c
443 17.2 Receive Pause 1 = Receive pause enabled RO 0 0 note17.
444 Enabled 0 = Receive pause disabled a, 17.c
445 17.1 Polarity (real 1 = Reversed RO 0 0
446 time) 0 = Normal
447 17.0 Jabber (real 1 = Jabber RO 0 Retain
448 time) 0 = No jabber
449 */
450 read_status = __cvmx_spi4000_mdio_read(interface, port, 0x11);
451 if ((read_status & (1<<10)) == 0)
452 read_status = 0; /* If the link is down, force zero */
453 else
454 read_status &= 0xe400; /* Strip off all the don't care bits */
455 if (read_status != phy_status[port])
456 {
457 phy_status[port] = read_status;
458 if (read_status & (1<<10))
459 {
460 /* If the link is up, we need to set the speed based on the PHY status */
461 if (read_status & (1<<15))
462 __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
463 else
464 __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x1); /* 100Mbps */
465 }
466 else
467 {
468 /* If the link is down, force 1Gbps so TX traffic dumps fast */
469 __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
470 }
471 }
472
473 if (read_status & (1<<10))
474 {
475 link.s.status = 1; /* Link up */
476 if (read_status & (1<<15))
477 link.s.speed = 2;
478 else
479 link.s.speed = 1;
480 }
481 else
482 {
483 link.s.speed = 2; /* Use 1Gbps when down */
484 link.s.status = 0; /* Link Down */
485 }
486 link.s.duplex = ((read_status & (1<<13)) != 0);
487
488 return link;
489 }
490 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
491 EXPORT_SYMBOL(cvmx_spi4000_check_speed);
492 #endif
493
494
495 /**
496 * Return non-zero if the SPI interface has a SPI4000 attached
497 *
498 * @param interface SPI interface the SPI4000 is connected to
499 *
500 * @return
501 */
cvmx_spi4000_is_present(int interface)502 int cvmx_spi4000_is_present(int interface)
503 {
504 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
505 return 0;
506 // Check for the presence of a SPI4000. If it isn't there,
507 // these writes will timeout.
508 if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 0))
509 return 0;
510 if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_LOW, 0))
511 return 0;
512 interface_is_spi4000[interface] = 1;
513 return 1;
514 }
515
516
517 /**
518 * Initialize the SPI4000 for use
519 *
520 * @param interface SPI interface the SPI4000 is connected to
521 */
cvmx_spi4000_initialize(int interface)522 int cvmx_spi4000_initialize(int interface)
523 {
524 if (!cvmx_spi4000_is_present(interface))
525 return -1;
526
527 __cvmx_spi4000_configure_mac(interface);
528 __cvmx_spi4000_configure_phy(interface);
529 return 0;
530 }
531
532