1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
3 */
4
5 #ifndef _HNS3_RXTX_H_
6 #define _HNS3_RXTX_H_
7
8 #include <stdint.h>
9 #include <rte_mbuf_core.h>
10
11 #define HNS3_MIN_RING_DESC 64
12 #define HNS3_MAX_RING_DESC 32768
13 #define HNS3_DEFAULT_RING_DESC 1024
14 #define HNS3_ALIGN_RING_DESC 32
15 #define HNS3_RING_BASE_ALIGN 128
16 #define HNS3_BULK_ALLOC_MBUF_NUM 32
17
18 #define HNS3_DEFAULT_RX_FREE_THRESH 32
19 #define HNS3_DEFAULT_TX_FREE_THRESH 32
20 #define HNS3_DEFAULT_TX_RS_THRESH 32
21 #define HNS3_TX_FAST_FREE_AHEAD 64
22
23 #define HNS3_DEFAULT_RX_BURST 32
24 #if (HNS3_DEFAULT_RX_BURST > 64)
25 #error "PMD HNS3: HNS3_DEFAULT_RX_BURST must <= 64\n"
26 #endif
27 #define HNS3_DEFAULT_DESCS_PER_LOOP 4
28 #define HNS3_SVE_DEFAULT_DESCS_PER_LOOP 8
29 #if (HNS3_DEFAULT_DESCS_PER_LOOP > HNS3_SVE_DEFAULT_DESCS_PER_LOOP)
30 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_DEFAULT_DESCS_PER_LOOP
31 #else
32 #define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_SVE_DEFAULT_DESCS_PER_LOOP
33 #endif
34 #define HNS3_DEFAULT_RXQ_REARM_THRESH 64
35 #define HNS3_UINT8_BIT 8
36 #define HNS3_UINT16_BIT 16
37 #define HNS3_UINT32_BIT 32
38
39 #define HNS3_512_BD_BUF_SIZE 512
40 #define HNS3_1K_BD_BUF_SIZE 1024
41 #define HNS3_2K_BD_BUF_SIZE 2048
42 #define HNS3_4K_BD_BUF_SIZE 4096
43
44 #define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
45 #define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
46
47 #define HNS3_BD_SIZE_512_TYPE 0
48 #define HNS3_BD_SIZE_1024_TYPE 1
49 #define HNS3_BD_SIZE_2048_TYPE 2
50 #define HNS3_BD_SIZE_4096_TYPE 3
51
52 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
53 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
54 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
55 #define HNS3_RX_FLAG_L4ID_UDP 0x0
56 #define HNS3_RX_FLAG_L4ID_TCP 0x1
57
58 #define HNS3_RXD_DMAC_S 0
59 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
60 #define HNS3_RXD_VLAN_S 2
61 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
62 #define HNS3_RXD_L3ID_S 4
63 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
64 #define HNS3_RXD_L4ID_S 8
65 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
66 #define HNS3_RXD_FRAG_B 12
67 #define HNS3_RXD_STRP_TAGP_S 13
68 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
69
70 #define HNS3_RXD_L2E_B 16
71 #define HNS3_RXD_L3E_B 17
72 #define HNS3_RXD_L4E_B 18
73 #define HNS3_RXD_TRUNCATE_B 19
74 #define HNS3_RXD_HOI_B 20
75 #define HNS3_RXD_DOI_B 21
76 #define HNS3_RXD_OL3E_B 22
77 #define HNS3_RXD_OL4E_B 23
78 #define HNS3_RXD_GRO_COUNT_S 24
79 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
80 #define HNS3_RXD_GRO_FIXID_B 30
81 #define HNS3_RXD_GRO_ECN_B 31
82
83 #define HNS3_RXD_ODMAC_S 0
84 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
85 #define HNS3_RXD_OVLAN_S 2
86 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
87 #define HNS3_RXD_OL3ID_S 4
88 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
89 #define HNS3_RXD_OL4ID_S 8
90 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
91 #define HNS3_RXD_FBHI_S 12
92 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
93 #define HNS3_RXD_FBLI_S 14
94 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
95
96 #define HNS3_RXD_BDTYPE_S 0
97 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
98 #define HNS3_RXD_VLD_B 4
99 #define HNS3_RXD_UDP0_B 5
100 #define HNS3_RXD_EXTEND_B 7
101 #define HNS3_RXD_FE_B 8
102 #define HNS3_RXD_LUM_B 9
103 #define HNS3_RXD_CRCP_B 10
104 #define HNS3_RXD_L3L4P_B 11
105 #define HNS3_RXD_TSIND_S 12
106 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
107 #define HNS3_RXD_LKBK_B 15
108 #define HNS3_RXD_GRO_SIZE_S 16
109 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
110
111 #define HNS3_TXD_L3T_S 0
112 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
113 #define HNS3_TXD_L4T_S 2
114 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
115 #define HNS3_TXD_L3CS_B 4
116 #define HNS3_TXD_L4CS_B 5
117 #define HNS3_TXD_VLAN_B 6
118 #define HNS3_TXD_TSO_B 7
119
120 #define HNS3_TXD_L2LEN_S 8
121 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
122 #define HNS3_TXD_L3LEN_S 16
123 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
124 #define HNS3_TXD_L4LEN_S 24
125 #define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
126
127 #define HNS3_TXD_OL3T_S 0
128 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
129 #define HNS3_TXD_OVLAN_B 2
130 #define HNS3_TXD_MACSEC_B 3
131 #define HNS3_TXD_TUNTYPE_S 4
132 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
133
134 #define HNS3_TXD_BDTYPE_S 0
135 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
136 #define HNS3_TXD_FE_B 4
137 #define HNS3_TXD_SC_S 5
138 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
139 #define HNS3_TXD_EXTEND_B 7
140 #define HNS3_TXD_VLD_B 8
141 #define HNS3_TXD_RI_B 9
142 #define HNS3_TXD_RA_B 10
143 #define HNS3_TXD_TSYN_B 11
144 #define HNS3_TXD_DECTTL_S 12
145 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
146
147 #define HNS3_TXD_MSS_S 0
148 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
149
150 #define HNS3_L2_LEN_UNIT 1UL
151 #define HNS3_L3_LEN_UNIT 2UL
152 #define HNS3_L4_LEN_UNIT 2UL
153
154 #define HNS3_TXD_DEFAULT_BDTYPE 0
155 #define HNS3_TXD_VLD_CMD (0x1 << HNS3_TXD_VLD_B)
156 #define HNS3_TXD_FE_CMD (0x1 << HNS3_TXD_FE_B)
157 #define HNS3_TXD_DEFAULT_VLD_FE_BDTYPE \
158 (HNS3_TXD_VLD_CMD | HNS3_TXD_FE_CMD | HNS3_TXD_DEFAULT_BDTYPE)
159 #define HNS3_TXD_SEND_SIZE_SHIFT 16
160
161 enum hns3_pkt_l2t_type {
162 HNS3_L2_TYPE_UNICAST,
163 HNS3_L2_TYPE_MULTICAST,
164 HNS3_L2_TYPE_BROADCAST,
165 HNS3_L2_TYPE_INVALID,
166 };
167
168 enum hns3_pkt_l3t_type {
169 HNS3_L3T_NONE,
170 HNS3_L3T_IPV6,
171 HNS3_L3T_IPV4,
172 HNS3_L3T_RESERVED
173 };
174
175 enum hns3_pkt_l4t_type {
176 HNS3_L4T_UNKNOWN,
177 HNS3_L4T_TCP,
178 HNS3_L4T_UDP,
179 HNS3_L4T_SCTP
180 };
181
182 enum hns3_pkt_ol3t_type {
183 HNS3_OL3T_NONE,
184 HNS3_OL3T_IPV6,
185 HNS3_OL3T_IPV4_NO_CSUM,
186 HNS3_OL3T_IPV4_CSUM
187 };
188
189 enum hns3_pkt_tun_type {
190 HNS3_TUN_NONE,
191 HNS3_TUN_MAC_IN_UDP,
192 HNS3_TUN_NVGRE,
193 HNS3_TUN_OTHER
194 };
195
196 /* hardware spec ring buffer format */
197 struct hns3_desc {
198 union {
199 uint64_t addr;
200 struct {
201 uint32_t addr0;
202 uint32_t addr1;
203 };
204 };
205 union {
206 struct {
207 uint16_t vlan_tag;
208 uint16_t send_size;
209 union {
210 /*
211 * L3T | L4T | L3CS | L4CS | VLAN | TSO |
212 * L2_LEN
213 */
214 uint32_t type_cs_vlan_tso_len;
215 struct {
216 uint8_t type_cs_vlan_tso;
217 uint8_t l2_len;
218 uint8_t l3_len;
219 uint8_t l4_len;
220 };
221 };
222 uint16_t outer_vlan_tag;
223 uint16_t tv;
224 union {
225 /* OL3T | OVALAN | MACSEC */
226 uint32_t ol_type_vlan_len_msec;
227 struct {
228 uint8_t ol_type_vlan_msec;
229 uint8_t ol2_len;
230 uint8_t ol3_len;
231 uint8_t ol4_len;
232 };
233 };
234
235 uint32_t paylen;
236 uint16_t tp_fe_sc_vld_ra_ri;
237 uint16_t mss;
238 } tx;
239
240 struct {
241 uint32_t l234_info;
242 uint16_t pkt_len;
243 uint16_t size;
244 uint32_t rss_hash;
245 uint16_t fd_id;
246 uint16_t vlan_tag;
247 union {
248 uint32_t ol_info;
249 struct {
250 uint16_t o_dm_vlan_id_fb;
251 uint16_t ot_vlan_tag;
252 };
253 };
254 union {
255 uint32_t bd_base_info;
256 struct {
257 uint16_t bdtype_vld_udp0;
258 uint16_t fe_lum_crcp_l3l4p;
259 };
260 };
261 } rx;
262 };
263 } __rte_packed;
264
265 struct hns3_entry {
266 struct rte_mbuf *mbuf;
267 };
268
269 struct hns3_rx_queue {
270 void *io_base;
271 volatile void *io_head_reg;
272 struct hns3_adapter *hns;
273 struct hns3_ptype_table *ptype_tbl;
274 struct rte_mempool *mb_pool;
275 struct hns3_desc *rx_ring;
276 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
277 const struct rte_memzone *mz;
278 struct hns3_entry *sw_ring;
279 struct rte_mbuf *pkt_first_seg;
280 struct rte_mbuf *pkt_last_seg;
281
282 uint16_t queue_id;
283 uint16_t port_id;
284 uint16_t nb_rx_desc;
285 uint16_t rx_buf_len;
286 /*
287 * threshold for the number of BDs waited to passed to hardware. If the
288 * number exceeds the threshold, driver will pass these BDs to hardware.
289 */
290 uint16_t rx_free_thresh;
291 uint16_t next_to_use; /* index of next BD to be polled */
292 uint16_t rx_free_hold; /* num of BDs waited to passed to hardware */
293 uint16_t rx_rearm_start; /* index of BD that driver re-arming from */
294 uint16_t rx_rearm_nb; /* number of remaining BDs to be re-armed */
295
296 /* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
297 uint8_t crc_len;
298
299 bool rx_deferred_start; /* don't start this queue in dev start */
300 bool configured; /* indicate if rx queue has been configured */
301 /*
302 * Indicate whether ignore the outer VLAN field in the Rx BD reported
303 * by the Hardware. Because the outer VLAN is the PVID if the PVID is
304 * set for some version of hardware network engine whose vlan mode is
305 * HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920. And this VLAN
306 * should not be transitted to the upper-layer application. For hardware
307 * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,
308 * such as kunpeng 930, PVID will not be reported to the BDs. So, PMD
309 * driver does not need to perform PVID-related operation in Rx. At this
310 * point, the pvid_sw_discard_en will be false.
311 */
312 bool pvid_sw_discard_en;
313 bool enabled; /* indicate if Rx queue has been enabled */
314
315 uint64_t l2_errors;
316 uint64_t pkt_len_errors;
317 uint64_t l3_csum_errors;
318 uint64_t l4_csum_errors;
319 uint64_t ol3_csum_errors;
320 uint64_t ol4_csum_errors;
321
322 struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
323 uint16_t bulk_mbuf_num;
324
325 /* offset_table: used for vector, to solve execute re-order problem */
326 uint8_t offset_table[HNS3_VECTOR_RX_OFFSET_TABLE_LEN + 1];
327 uint64_t mbuf_initializer; /* value to init mbufs used with vector rx */
328 struct rte_mbuf fake_mbuf; /* fake mbuf used with vector rx */
329 };
330
331 struct hns3_tx_queue {
332 void *io_base;
333 volatile void *io_tail_reg;
334 struct hns3_adapter *hns;
335 struct hns3_desc *tx_ring;
336 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
337 const struct rte_memzone *mz;
338 struct hns3_entry *sw_ring;
339
340 uint16_t queue_id;
341 uint16_t port_id;
342 uint16_t nb_tx_desc;
343 /*
344 * index of next BD whose corresponding rte_mbuf can be released by
345 * driver.
346 */
347 uint16_t next_to_clean;
348 /* index of next BD to be filled by driver to send packet */
349 uint16_t next_to_use;
350 /* num of remaining BDs ready to be filled by driver to send packet */
351 uint16_t tx_bd_ready;
352
353 /* threshold for free tx buffer if available BDs less than this value */
354 uint16_t tx_free_thresh;
355
356 /*
357 * For better performance in tx datapath, releasing mbuf in batches is
358 * required.
359 * Only checking the VLD bit of the last descriptor in a batch of the
360 * thresh descriptors does not mean that these descriptors are all sent
361 * by hardware successfully. So we need to check that the VLD bits of
362 * all descriptors are cleared. and then free all mbufs in the batch.
363 * - tx_rs_thresh
364 * Number of mbufs released at a time.
365 *
366 * - free
367 * Tx mbuf free array used for preserving temporarily address of mbuf
368 * released back to mempool, when releasing mbuf in batches.
369 */
370 uint16_t tx_rs_thresh;
371 struct rte_mbuf **free;
372
373 /*
374 * tso mode.
375 * value range:
376 * HNS3_TSO_SW_CAL_PSEUDO_H_CSUM/HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
377 *
378 * - HNS3_TSO_SW_CAL_PSEUDO_H_CSUM
379 * In this mode, because of the hardware constraint, network driver
380 * software need erase the L4 len value of the TCP pseudo header
381 * and recalculate the TCP pseudo header checksum of packets that
382 * need TSO.
383 *
384 * - HNS3_TSO_HW_CAL_PSEUDO_H_CSUM
385 * In this mode, hardware support recalculate the TCP pseudo header
386 * checksum of packets that need TSO, so network driver software
387 * not need to recalculate it.
388 */
389 uint8_t tso_mode;
390 /*
391 * The minimum length of the packet supported by hardware in the Tx
392 * direction.
393 */
394 uint32_t min_tx_pkt_len;
395
396 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
397 bool tx_deferred_start; /* don't start this queue in dev start */
398 bool configured; /* indicate if tx queue has been configured */
399 /*
400 * Indicate whether add the vlan_tci of the mbuf to the inner VLAN field
401 * of Tx BD. Because the outer VLAN will always be the PVID when the
402 * PVID is set and for some version of hardware network engine whose
403 * vlan mode is HNS3_SW_SHIFT_AND_DISCARD_MODE, such as kunpeng 920, the
404 * PVID will overwrite the outer VLAN field of Tx BD. For the hardware
405 * network engine whose vlan mode is HNS3_HW_SHIFT_AND_DISCARD_MODE,
406 * such as kunpeng 930, if the PVID is set, the hardware will shift the
407 * VLAN field automatically. So, PMD driver does not need to do
408 * PVID-related operations in Tx. And pvid_sw_shift_en will be false at
409 * this point.
410 */
411 bool pvid_sw_shift_en;
412 bool enabled; /* indicate if Tx queue has been enabled */
413
414 /*
415 * The following items are used for the abnormal errors statistics in
416 * the Tx datapath. When upper level application calls the
417 * rte_eth_tx_burst API function to send multiple packets at a time with
418 * burst mode based on hns3 network engine, there are some abnormal
419 * conditions that cause the driver to fail to operate the hardware to
420 * send packets correctly.
421 * Note: When using burst mode to call the rte_eth_tx_burst API function
422 * to send multiple packets at a time. When the first abnormal error is
423 * detected, add one to the relevant error statistics item, and then
424 * exit the loop of sending multiple packets of the function. That is to
425 * say, even if there are multiple packets in which abnormal errors may
426 * be detected in the burst, the relevant error statistics in the driver
427 * will only be increased by one.
428 * The detail description of the Tx abnormal errors statistic items as
429 * below:
430 * - over_length_pkt_cnt
431 * Total number of greater than HNS3_MAX_FRAME_LEN the driver
432 * supported.
433 *
434 * - exceed_limit_bd_pkt_cnt
435 * Total number of exceeding the hardware limited bd which process
436 * a packet needed bd numbers.
437 *
438 * - exceed_limit_bd_reassem_fail
439 * Total number of exceeding the hardware limited bd fail which
440 * process a packet needed bd numbers and reassemble fail.
441 *
442 * - unsupported_tunnel_pkt_cnt
443 * Total number of unsupported tunnel packet. The unsupported tunnel
444 * type: vxlan_gpe, gtp, ipip and MPLSINUDP, MPLSINUDP is a packet
445 * with MPLS-in-UDP RFC 7510 header.
446 *
447 * - queue_full_cnt
448 * Total count which the available bd numbers in current bd queue is
449 * less than the bd numbers with the pkt process needed.
450 *
451 * - pkt_padding_fail_cnt
452 * Total count which the packet length is less than minimum packet
453 * length(struct hns3_tx_queue::min_tx_pkt_len) supported by
454 * hardware in Tx direction and fail to be appended with 0.
455 */
456 uint64_t over_length_pkt_cnt;
457 uint64_t exceed_limit_bd_pkt_cnt;
458 uint64_t exceed_limit_bd_reassem_fail;
459 uint64_t unsupported_tunnel_pkt_cnt;
460 uint64_t queue_full_cnt;
461 uint64_t pkt_padding_fail_cnt;
462 };
463
464 #define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
465 ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
466
467 struct hns3_queue_info {
468 const char *type; /* point to queue memory name */
469 const char *ring_name; /* point to hardware ring name */
470 uint16_t idx;
471 uint16_t nb_desc;
472 unsigned int socket_id;
473 };
474
475 #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
476 PKT_TX_OUTER_IP_CKSUM | \
477 PKT_TX_IP_CKSUM | \
478 PKT_TX_TCP_SEG | \
479 PKT_TX_L4_MASK)
480
481 enum hns3_cksum_status {
482 HNS3_CKSUM_NONE = 0,
483 HNS3_L3_CKSUM_ERR = 1,
484 HNS3_L4_CKSUM_ERR = 2,
485 HNS3_OUTER_L3_CKSUM_ERR = 4,
486 HNS3_OUTER_L4_CKSUM_ERR = 8
487 };
488
489 static inline int
hns3_handle_bdinfo(struct hns3_rx_queue * rxq,struct rte_mbuf * rxm,uint32_t bd_base_info,uint32_t l234_info,uint32_t * cksum_err)490 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
491 uint32_t bd_base_info, uint32_t l234_info,
492 uint32_t *cksum_err)
493 {
494 #define L2E_TRUNC_ERR_FLAG (BIT(HNS3_RXD_L2E_B) | \
495 BIT(HNS3_RXD_TRUNCATE_B))
496 #define CHECKSUM_ERR_FLAG (BIT(HNS3_RXD_L3E_B) | \
497 BIT(HNS3_RXD_L4E_B) | \
498 BIT(HNS3_RXD_OL3E_B) | \
499 BIT(HNS3_RXD_OL4E_B))
500
501 uint32_t tmp = 0;
502
503 /*
504 * If packet len bigger than mtu when recv with no-scattered algorithm,
505 * the first n bd will without FE bit, we need process this sisution.
506 * Note: we don't need add statistic counter because latest BD which
507 * with FE bit will mark HNS3_RXD_L2E_B bit.
508 */
509 if (unlikely((bd_base_info & BIT(HNS3_RXD_FE_B)) == 0))
510 return -EINVAL;
511
512 if (unlikely((l234_info & L2E_TRUNC_ERR_FLAG) || rxm->pkt_len == 0)) {
513 if (l234_info & BIT(HNS3_RXD_L2E_B))
514 rxq->l2_errors++;
515 else
516 rxq->pkt_len_errors++;
517 return -EINVAL;
518 }
519
520 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
521 if (likely((l234_info & CHECKSUM_ERR_FLAG) == 0)) {
522 *cksum_err = 0;
523 return 0;
524 }
525
526 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
527 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
528 rxq->l3_csum_errors++;
529 tmp |= HNS3_L3_CKSUM_ERR;
530 }
531
532 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
533 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
534 rxq->l4_csum_errors++;
535 tmp |= HNS3_L4_CKSUM_ERR;
536 }
537
538 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
539 rxq->ol3_csum_errors++;
540 tmp |= HNS3_OUTER_L3_CKSUM_ERR;
541 }
542
543 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
544 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
545 rxq->ol4_csum_errors++;
546 tmp |= HNS3_OUTER_L4_CKSUM_ERR;
547 }
548 }
549 *cksum_err = tmp;
550
551 return 0;
552 }
553
554 static inline void
hns3_rx_set_cksum_flag(struct rte_mbuf * rxm,const uint64_t packet_type,const uint32_t cksum_err)555 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, const uint64_t packet_type,
556 const uint32_t cksum_err)
557 {
558 if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
559 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
560 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
561 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
562 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
563 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
564 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
565 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
566 (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
567 rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
568 } else {
569 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
570 (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
571 rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
572 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
573 (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
574 rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
575 }
576 }
577
578 static inline uint32_t
hns3_rx_calc_ptype(struct hns3_rx_queue * rxq,const uint32_t l234_info,const uint32_t ol_info)579 hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,
580 const uint32_t ol_info)
581 {
582 const struct hns3_ptype_table * const ptype_tbl = rxq->ptype_tbl;
583 uint32_t l2id, l3id, l4id;
584 uint32_t ol3id, ol4id, ol2id;
585
586 ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
587 ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
588 ol2id = hns3_get_field(ol_info, HNS3_RXD_OVLAN_M, HNS3_RXD_OVLAN_S);
589 l2id = hns3_get_field(l234_info, HNS3_RXD_VLAN_M, HNS3_RXD_VLAN_S);
590 l3id = hns3_get_field(l234_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
591 l4id = hns3_get_field(l234_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
592
593 if (unlikely(ptype_tbl->ol4table[ol4id]))
594 return ptype_tbl->inner_l2table[l2id] |
595 ptype_tbl->inner_l3table[l3id] |
596 ptype_tbl->inner_l4table[l4id] |
597 ptype_tbl->ol3table[ol3id] |
598 ptype_tbl->ol4table[ol4id] | ptype_tbl->ol2table[ol2id];
599 else
600 return ptype_tbl->l2l3table[l2id][l3id] |
601 ptype_tbl->l4table[l4id];
602 }
603
604 void hns3_dev_rx_queue_release(void *queue);
605 void hns3_dev_tx_queue_release(void *queue);
606 void hns3_free_all_queues(struct rte_eth_dev *dev);
607 int hns3_reset_all_tqps(struct hns3_adapter *hns);
608 void hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en);
609 int hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
610 int hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
611 void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
612 int hns3_init_queues(struct hns3_adapter *hns, bool reset_queue);
613 void hns3_start_tqps(struct hns3_hw *hw);
614 void hns3_stop_tqps(struct hns3_hw *hw);
615 int hns3_rxq_iterate(struct rte_eth_dev *dev,
616 int (*callback)(struct hns3_rx_queue *, void *), void *arg);
617 void hns3_dev_release_mbufs(struct hns3_adapter *hns);
618 int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
619 unsigned int socket, const struct rte_eth_rxconf *conf,
620 struct rte_mempool *mp);
621 int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
622 unsigned int socket, const struct rte_eth_txconf *conf);
623 uint32_t hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
624 int hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
625 int hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
626 int hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
627 int hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
628 uint16_t hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
629 uint16_t nb_pkts);
630 uint16_t hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
631 uint16_t nb_pkts);
632 uint16_t hns3_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
633 uint16_t nb_pkts);
634 uint16_t hns3_recv_pkts_vec_sve(void *rx_queue, struct rte_mbuf **rx_pkts,
635 uint16_t nb_pkts);
636 int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
637 __rte_unused uint16_t queue_id,
638 struct rte_eth_burst_mode *mode);
639 int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
640 uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
641 uint16_t nb_pkts);
642 uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
643 uint16_t nb_pkts);
644 uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
645 uint16_t nb_pkts);
646 uint16_t hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
647 uint16_t nb_pkts);
648 uint16_t hns3_xmit_pkts_vec_sve(void *tx_queue, struct rte_mbuf **tx_pkts,
649 uint16_t nb_pkts);
650 int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
651 __rte_unused uint16_t queue_id,
652 struct rte_eth_burst_mode *mode);
653 const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
654 void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
655 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
656 void hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
657 uint8_t gl_idx, uint16_t gl_value);
658 void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id,
659 uint16_t rl_value);
660 void hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id,
661 uint16_t ql_value);
662 int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
663 uint16_t nb_tx_q);
664 int hns3_config_gro(struct hns3_hw *hw, bool en);
665 int hns3_restore_gro_conf(struct hns3_hw *hw);
666 void hns3_update_all_queues_pvid_proc_en(struct hns3_hw *hw);
667 void hns3_rx_scattered_reset(struct rte_eth_dev *dev);
668 void hns3_rx_scattered_calc(struct rte_eth_dev *dev);
669 int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
670 int hns3_tx_check_vec_support(struct rte_eth_dev *dev);
671 void hns3_rxq_vec_setup(struct hns3_rx_queue *rxq);
672 void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
673 struct rte_eth_rxq_info *qinfo);
674 void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
675 struct rte_eth_txq_info *qinfo);
676 uint32_t hns3_get_tqp_reg_offset(uint16_t idx);
677 int hns3_start_all_txqs(struct rte_eth_dev *dev);
678 int hns3_start_all_rxqs(struct rte_eth_dev *dev);
679 void hns3_stop_all_txqs(struct rte_eth_dev *dev);
680 void hns3_restore_tqp_enable_state(struct hns3_hw *hw);
681
682 #endif /* _HNS3_RXTX_H_ */
683