1 /* $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $ */
2 /* tracked to 1.38 */
3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Copyright (c) 1988 University of Utah.
7 * Copyright (c) 1992, 1993
8 * The Regents of the University of California. All rights reserved.
9 *
10 * This code is derived from software contributed to Berkeley by
11 * the Systems Programming Group of the University of Utah Computer
12 * Science Department, The Mach Operating System project at
13 * Carnegie-Mellon University and Ralph Campbell.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
40 * Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp
41 * JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49
42 */
43
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
46
47 #include "opt_ddb.h"
48 #include "opt_md.h"
49
50 #include <sys/param.h>
51 #include <sys/proc.h>
52 #include <sys/systm.h>
53 #include <sys/buf.h>
54 #include <sys/bus.h>
55 #include <sys/conf.h>
56 #include <sys/cpu.h>
57 #include <sys/kernel.h>
58 #include <sys/linker.h>
59 #include <sys/malloc.h>
60 #include <sys/mbuf.h>
61 #include <sys/msgbuf.h>
62 #include <sys/reboot.h>
63 #include <sys/rwlock.h>
64 #include <sys/sched.h>
65 #include <sys/sysctl.h>
66 #include <sys/sysproto.h>
67 #include <sys/vmmeter.h>
68
69 #include <vm/vm.h>
70 #include <vm/vm_kern.h>
71 #include <vm/vm_object.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_phys.h>
74 #include <vm/pmap.h>
75 #include <vm/vm_map.h>
76 #include <vm/vm_pager.h>
77 #include <vm/vm_extern.h>
78 #include <sys/socket.h>
79
80 #include <sys/user.h>
81 #include <sys/interrupt.h>
82 #include <sys/cons.h>
83 #include <sys/syslog.h>
84 #include <machine/asm.h>
85 #include <machine/bootinfo.h>
86 #include <machine/cache.h>
87 #include <machine/clock.h>
88 #include <machine/cpu.h>
89 #include <machine/cpuregs.h>
90 #include <machine/elf.h>
91 #include <machine/hwfunc.h>
92 #include <machine/intr_machdep.h>
93 #include <machine/md_var.h>
94 #include <machine/tlb.h>
95 #ifdef DDB
96 #include <sys/kdb.h>
97 #include <ddb/ddb.h>
98 #endif
99
100 #include <sys/random.h>
101 #include <net/if.h>
102
103 #define BOOTINFO_DEBUG 0
104
105 char machine[] = "mips";
106 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class");
107
108 char cpu_model[80];
109 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model");
110
111 char cpu_board[80];
112 SYSCTL_STRING(_hw, OID_AUTO, board, CTLFLAG_RD, cpu_board, 0, "Machine board");
113
114 int cold = 1;
115 long realmem = 0;
116 long Maxmem = 0;
117 int cpu_clock = MIPS_DEFAULT_HZ;
118 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
119 &cpu_clock, 0, "CPU instruction clock rate");
120 int clocks_running = 0;
121
122 vm_offset_t kstack0;
123
124 /*
125 * Each entry in the pcpu_space[] array is laid out in the following manner:
126 * struct pcpu for cpu 'n' pcpu_space[n]
127 * boot stack for cpu 'n' pcpu_space[n] + PAGE_SIZE * 2 - CALLFRAME_SIZ
128 *
129 * Note that the boot stack grows downwards and we assume that we never
130 * use enough stack space to trample over the 'struct pcpu' that is at
131 * the beginning of the array.
132 *
133 * The array is aligned on a (PAGE_SIZE * 2) boundary so that the 'struct pcpu'
134 * is always in the even page frame of the wired TLB entry on SMP kernels.
135 *
136 * The array is in the .data section so that the stack does not get zeroed out
137 * when the .bss section is zeroed.
138 */
139 char pcpu_space[MAXCPU][PAGE_SIZE * 2] \
140 __aligned(PAGE_SIZE * 2) __section(".data");
141
142 struct pcpu *pcpup = (struct pcpu *)pcpu_space;
143
144 vm_paddr_t physmem_desc[PHYS_AVAIL_COUNT];
145
146 #ifdef UNIMPLEMENTED
147 struct platform platform;
148 #endif
149
150 static void cpu_startup(void *);
151 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
152
153 struct kva_md_info kmi;
154
155 int cpucfg; /* Value of processor config register */
156 int num_tlbentries = 64; /* Size of the CPU tlb */
157 int cputype;
158
159 extern char MipsException[], MipsExceptionEnd[];
160
161 /* TLB miss handler address and end */
162 extern char MipsTLBMiss[], MipsTLBMissEnd[];
163
164 /* Cache error handler */
165 extern char MipsCache[], MipsCacheEnd[];
166
167 /* MIPS wait skip region */
168 extern char MipsWaitStart[], MipsWaitEnd[];
169
170 extern char edata[], end[];
171
172 u_int32_t bootdev;
173 struct bootinfo bootinfo;
174 /*
175 * First kseg0 address available for use. By default it's equal to &end.
176 * But in some cases there might be additional data placed right after
177 * _end by loader or ELF trampoline.
178 */
179 vm_offset_t kernel_kseg0_end = (vm_offset_t)&end;
180
181 static void
cpu_startup(void * dummy)182 cpu_startup(void *dummy)
183 {
184
185 if (boothowto & RB_VERBOSE)
186 bootverbose++;
187
188 cpu_identify();
189
190 printf("real memory = %ju (%juK bytes)\n", ptoa((uintmax_t)realmem),
191 ptoa((uintmax_t)realmem) / 1024);
192
193 /*
194 * Display any holes after the first chunk of extended memory.
195 */
196 if (bootverbose) {
197 int indx;
198
199 printf("Physical memory chunk(s):\n");
200 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
201 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
202
203 printf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
204 (uintmax_t)phys_avail[indx],
205 (uintmax_t)phys_avail[indx + 1] - 1,
206 (uintmax_t)size1,
207 (uintmax_t)size1 / PAGE_SIZE);
208 }
209 }
210
211 vm_ksubmap_init(&kmi);
212
213 printf("avail memory = %ju (%juMB)\n",
214 ptoa((uintmax_t)vm_free_count()),
215 ptoa((uintmax_t)vm_free_count()) / 1048576);
216 cpu_init_interrupts();
217
218 /*
219 * Set up buffers, so they can be used to read disk labels.
220 */
221 bufinit();
222 vm_pager_bufferinit();
223 }
224
225 /*
226 * Shutdown the CPU as much as possible
227 */
228 void
cpu_reset(void)229 cpu_reset(void)
230 {
231
232 platform_reset();
233 }
234
235 /*
236 * Flush the D-cache for non-DMA I/O so that the I-cache can
237 * be made coherent later.
238 */
239 void
cpu_flush_dcache(void * ptr,size_t len)240 cpu_flush_dcache(void *ptr, size_t len)
241 {
242 /* TBD */
243 }
244
245 /* Get current clock frequency for the given cpu id. */
246 int
cpu_est_clockrate(int cpu_id,uint64_t * rate)247 cpu_est_clockrate(int cpu_id, uint64_t *rate)
248 {
249
250 return (ENXIO);
251 }
252
253 /*
254 * Shutdown the CPU as much as possible
255 */
256 void
cpu_halt(void)257 cpu_halt(void)
258 {
259 for (;;)
260 ;
261 }
262
263 SYSCTL_STRUCT(_machdep, OID_AUTO, bootinfo, CTLFLAG_RD, &bootinfo,
264 bootinfo, "Bootinfo struct: kernel filename, BIOS harddisk geometry, etc");
265
266 /*
267 * Initialize per cpu data structures, include curthread.
268 */
269 void
mips_pcpu0_init()270 mips_pcpu0_init()
271 {
272 /* Initialize pcpu info of cpu-zero */
273 pcpu_init(PCPU_ADDR(0), 0, sizeof(struct pcpu));
274 PCPU_SET(curthread, &thread0);
275 }
276
277 /*
278 * Initialize mips and configure to run kernel
279 */
280 void
mips_proc0_init(void)281 mips_proc0_init(void)
282 {
283 #ifdef SMP
284 if (platform_processor_id() != 0)
285 panic("BSP must be processor number 0");
286 #endif
287 proc_linkup0(&proc0, &thread0);
288
289 KASSERT((kstack0 & PAGE_MASK) == 0,
290 ("kstack0 is not aligned on a page boundary: 0x%0lx",
291 (long)kstack0));
292 thread0.td_kstack = kstack0;
293 thread0.td_kstack_pages = KSTACK_PAGES;
294 /*
295 * Do not use cpu_thread_alloc to initialize these fields
296 * thread0 is the only thread that has kstack located in KSEG0
297 * while cpu_thread_alloc handles kstack allocated in KSEG2.
298 */
299 thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
300 thread0.td_kstack_pages * PAGE_SIZE) - 1;
301 thread0.td_frame = &thread0.td_pcb->pcb_regs;
302
303 /* Steal memory for the dynamic per-cpu area. */
304 dpcpu_init((void *)pmap_steal_memory(DPCPU_SIZE), 0);
305
306 PCPU_SET(curpcb, thread0.td_pcb);
307 /*
308 * There is no need to initialize md_upte array for thread0 as it's
309 * located in .bss section and should be explicitly zeroed during
310 * kernel initialization.
311 */
312 }
313
314 void
cpu_initclocks(void)315 cpu_initclocks(void)
316 {
317
318 platform_initclocks();
319 cpu_initclocks_bsp();
320 }
321
322 /*
323 * Initialize the hardware exception vectors, and the jump table used to
324 * call locore cache and TLB management functions, based on the kind
325 * of CPU the kernel is running on.
326 */
327 void
mips_vector_init(void)328 mips_vector_init(void)
329 {
330 /*
331 * Make sure that the Wait region logic is not been
332 * changed
333 */
334 if (MipsWaitEnd - MipsWaitStart != 16)
335 panic("startup: MIPS wait region not correct");
336 /*
337 * Copy down exception vector code.
338 */
339 if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
340 panic("startup: UTLB code too large");
341
342 if (MipsCacheEnd - MipsCache > 0x80)
343 panic("startup: Cache error code too large");
344
345 bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
346 MipsTLBMissEnd - MipsTLBMiss);
347
348 /*
349 * XXXRW: Why don't we install the XTLB handler for all 64-bit
350 * architectures?
351 */
352 #if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) || defined(CPU_BERI)
353 /* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
354 bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
355 MipsTLBMissEnd - MipsTLBMiss);
356 #endif
357
358 bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
359 MipsExceptionEnd - MipsException);
360
361 bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
362 MipsCacheEnd - MipsCache);
363
364 /*
365 * Clear out the I and D caches.
366 */
367 mips_icache_sync_all();
368 mips_dcache_wbinv_all();
369
370 /*
371 * Mask all interrupts. Each interrupt will be enabled
372 * when handler is installed for it
373 */
374 set_intr_mask(0);
375
376 /* Clear BEV in SR so we start handling our own exceptions */
377 mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
378 }
379
380 /*
381 * Fix kernel_kseg0_end address in case trampoline placed debug sympols
382 * data there
383 */
384 void
mips_postboot_fixup(void)385 mips_postboot_fixup(void)
386 {
387 /*
388 * We store u_long sized objects into the reload area, so the array
389 * must be so aligned. The standard allows any alignment for char data.
390 */
391 _Alignas(_Alignof(u_long)) static char fake_preload[256];
392 caddr_t preload_ptr = (caddr_t)&fake_preload[0];
393 size_t size = 0;
394
395 #define PRELOAD_PUSH_VALUE(type, value) do { \
396 *(type *)(preload_ptr + size) = (value); \
397 size += sizeof(type); \
398 } while (0);
399
400 /*
401 * Provide kernel module file information
402 */
403 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_NAME);
404 PRELOAD_PUSH_VALUE(uint32_t, strlen("kernel") + 1);
405 strcpy((char*)(preload_ptr + size), "kernel");
406 size += strlen("kernel") + 1;
407 size = roundup(size, sizeof(u_long));
408
409 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_TYPE);
410 PRELOAD_PUSH_VALUE(uint32_t, strlen("elf kernel") + 1);
411 strcpy((char*)(preload_ptr + size), "elf kernel");
412 size += strlen("elf kernel") + 1;
413 size = roundup(size, sizeof(u_long));
414
415 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_ADDR);
416 PRELOAD_PUSH_VALUE(uint32_t, sizeof(vm_offset_t));
417 PRELOAD_PUSH_VALUE(vm_offset_t, KERNLOADADDR);
418 size = roundup(size, sizeof(u_long));
419
420 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_SIZE);
421 PRELOAD_PUSH_VALUE(uint32_t, sizeof(size_t));
422 PRELOAD_PUSH_VALUE(size_t, (size_t)&end - KERNLOADADDR);
423 size = roundup(size, sizeof(u_long));
424
425 /* End marker */
426 PRELOAD_PUSH_VALUE(uint32_t, 0);
427 PRELOAD_PUSH_VALUE(uint32_t, 0);
428
429 #undef PRELOAD_PUSH_VALUE
430
431 KASSERT((size < sizeof(fake_preload)),
432 ("fake preload size is more thenallocated"));
433
434 preload_metadata = (void *)fake_preload;
435
436 #ifdef DDB
437 Elf_Size *trampoline_data = (Elf_Size*)kernel_kseg0_end;
438 Elf_Size symtabsize = 0;
439 vm_offset_t ksym_start;
440 vm_offset_t ksym_end;
441
442 if (trampoline_data[0] == SYMTAB_MAGIC) {
443 symtabsize = trampoline_data[1];
444 kernel_kseg0_end += 2 * sizeof(Elf_Size);
445 /* start of .symtab */
446 ksym_start = kernel_kseg0_end;
447 kernel_kseg0_end += symtabsize;
448 /* end of .strtab */
449 ksym_end = kernel_kseg0_end;
450 db_fetch_ksymtab(ksym_start, ksym_end, 0);
451 }
452 #endif
453 }
454
455 #ifdef SMP
456 void
mips_pcpu_tlb_init(struct pcpu * pcpu)457 mips_pcpu_tlb_init(struct pcpu *pcpu)
458 {
459 vm_paddr_t pa;
460 pt_entry_t pte;
461
462 /*
463 * Map the pcpu structure at the virtual address 'pcpup'.
464 * We use a wired tlb index to do this one-time mapping.
465 */
466 pa = vtophys(pcpu);
467 pte = PTE_D | PTE_V | PTE_G | PTE_C_CACHE;
468 tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup,
469 TLBLO_PA_TO_PFN(pa) | pte,
470 TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte);
471 }
472 #endif
473
474 /*
475 * Initialise a struct pcpu.
476 */
477 void
cpu_pcpu_init(struct pcpu * pcpu,int cpuid,size_t size)478 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
479 {
480
481 pcpu->pc_next_asid = 1;
482 pcpu->pc_asid_generation = 1;
483 pcpu->pc_self = pcpu;
484 #ifdef SMP
485 if ((vm_offset_t)pcpup >= VM_MIN_KERNEL_ADDRESS &&
486 (vm_offset_t)pcpup <= VM_MAX_KERNEL_ADDRESS) {
487 mips_pcpu_tlb_init(pcpu);
488 }
489 #endif
490 }
491
492 int
fill_dbregs(struct thread * td,struct dbreg * dbregs)493 fill_dbregs(struct thread *td, struct dbreg *dbregs)
494 {
495
496 /* No debug registers on mips */
497 return (ENOSYS);
498 }
499
500 int
set_dbregs(struct thread * td,struct dbreg * dbregs)501 set_dbregs(struct thread *td, struct dbreg *dbregs)
502 {
503
504 /* No debug registers on mips */
505 return (ENOSYS);
506 }
507
508 void
spinlock_enter(void)509 spinlock_enter(void)
510 {
511 struct thread *td;
512 register_t intr;
513
514 td = curthread;
515 if (td->td_md.md_spinlock_count == 0) {
516 intr = intr_disable();
517 td->td_md.md_spinlock_count = 1;
518 td->td_md.md_saved_intr = intr;
519 critical_enter();
520 } else
521 td->td_md.md_spinlock_count++;
522 }
523
524 void
spinlock_exit(void)525 spinlock_exit(void)
526 {
527 struct thread *td;
528 register_t intr;
529
530 td = curthread;
531 intr = td->td_md.md_saved_intr;
532 td->td_md.md_spinlock_count--;
533 if (td->td_md.md_spinlock_count == 0) {
534 critical_exit();
535 intr_restore(intr);
536 }
537 }
538
539 /*
540 * call platform specific code to halt (until next interrupt) for the idle loop
541 */
542 void
cpu_idle(int busy)543 cpu_idle(int busy)
544 {
545 KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0,
546 ("interrupts disabled in idle process."));
547 KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0,
548 ("all interrupts masked in idle process."));
549
550 if (!busy) {
551 critical_enter();
552 cpu_idleclock();
553 }
554 mips_wait();
555 if (!busy) {
556 cpu_activeclock();
557 critical_exit();
558 }
559 }
560
561 int
cpu_idle_wakeup(int cpu)562 cpu_idle_wakeup(int cpu)
563 {
564
565 return (0);
566 }
567
568 int
is_cacheable_mem(vm_paddr_t pa)569 is_cacheable_mem(vm_paddr_t pa)
570 {
571 int i;
572
573 for (i = 0; physmem_desc[i + 1] != 0; i += 2) {
574 if (pa >= physmem_desc[i] && pa < physmem_desc[i + 1])
575 return (1);
576 }
577
578 return (0);
579 }
580