1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the X86 specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H 15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H 16 17 #include "X86FrameLowering.h" 18 #include "X86ISelLowering.h" 19 #include "X86InstrInfo.h" 20 #include "X86SelectionDAGInfo.h" 21 #include "llvm/ADT/StringRef.h" 22 #include "llvm/ADT/Triple.h" 23 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 24 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 25 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 26 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 27 #include "llvm/CodeGen/TargetSubtargetInfo.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/Target/TargetMachine.h" 30 #include <climits> 31 #include <memory> 32 33 #define GET_SUBTARGETINFO_HEADER 34 #include "X86GenSubtargetInfo.inc" 35 36 namespace llvm { 37 38 class GlobalValue; 39 40 /// The X86 backend supports a number of different styles of PIC. 41 /// 42 namespace PICStyles { 43 44 enum Style { 45 StubPIC, // Used on i386-darwin in pic mode. 46 GOT, // Used on 32 bit elf on when in pic mode. 47 RIPRel, // Used on X86-64 when in pic mode. 48 None // Set when not in pic mode. 49 }; 50 51 } // end namespace PICStyles 52 53 class X86Subtarget final : public X86GenSubtargetInfo { 54 public: 55 // NOTE: Do not add anything new to this list. Coarse, CPU name based flags 56 // are not a good idea. We should be migrating away from these. 57 enum X86ProcFamilyEnum { 58 Others, 59 IntelAtom, 60 IntelSLM, 61 IntelGLM, 62 IntelGLP, 63 IntelTRM 64 }; 65 66 protected: 67 enum X86SSEEnum { 68 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 69 }; 70 71 enum X863DNowEnum { 72 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA 73 }; 74 75 /// X86 processor family: Intel Atom, and others 76 X86ProcFamilyEnum X86ProcFamily = Others; 77 78 /// Which PIC style to use 79 PICStyles::Style PICStyle; 80 81 const TargetMachine &TM; 82 83 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. 84 X86SSEEnum X86SSELevel = NoSSE; 85 86 /// MMX, 3DNow, 3DNow Athlon, or none supported. 87 X863DNowEnum X863DNowLevel = NoThreeDNow; 88 89 /// True if the processor supports X87 instructions. 90 bool HasX87 = false; 91 92 /// True if this processor has NOPL instruction 93 /// (generally pentium pro+). 94 bool HasNOPL = false; 95 96 /// True if this processor has conditional move instructions 97 /// (generally pentium pro+). 98 bool HasCMov = false; 99 100 /// True if the processor supports X86-64 instructions. 101 bool HasX86_64 = false; 102 103 /// True if the processor supports POPCNT. 104 bool HasPOPCNT = false; 105 106 /// True if the processor supports SSE4A instructions. 107 bool HasSSE4A = false; 108 109 /// Target has AES instructions 110 bool HasAES = false; 111 bool HasVAES = false; 112 113 /// Target has FXSAVE/FXRESTOR instructions 114 bool HasFXSR = false; 115 116 /// Target has XSAVE instructions 117 bool HasXSAVE = false; 118 119 /// Target has XSAVEOPT instructions 120 bool HasXSAVEOPT = false; 121 122 /// Target has XSAVEC instructions 123 bool HasXSAVEC = false; 124 125 /// Target has XSAVES instructions 126 bool HasXSAVES = false; 127 128 /// Target has carry-less multiplication 129 bool HasPCLMUL = false; 130 bool HasVPCLMULQDQ = false; 131 132 /// Target has Galois Field Arithmetic instructions 133 bool HasGFNI = false; 134 135 /// Target has 3-operand fused multiply-add 136 bool HasFMA = false; 137 138 /// Target has 4-operand fused multiply-add 139 bool HasFMA4 = false; 140 141 /// Target has XOP instructions 142 bool HasXOP = false; 143 144 /// Target has TBM instructions. 145 bool HasTBM = false; 146 147 /// Target has LWP instructions 148 bool HasLWP = false; 149 150 /// True if the processor has the MOVBE instruction. 151 bool HasMOVBE = false; 152 153 /// True if the processor has the RDRAND instruction. 154 bool HasRDRAND = false; 155 156 /// Processor has 16-bit floating point conversion instructions. 157 bool HasF16C = false; 158 159 /// Processor has FS/GS base insturctions. 160 bool HasFSGSBase = false; 161 162 /// Processor has LZCNT instruction. 163 bool HasLZCNT = false; 164 165 /// Processor has BMI1 instructions. 166 bool HasBMI = false; 167 168 /// Processor has BMI2 instructions. 169 bool HasBMI2 = false; 170 171 /// Processor has VBMI instructions. 172 bool HasVBMI = false; 173 174 /// Processor has VBMI2 instructions. 175 bool HasVBMI2 = false; 176 177 /// Processor has Integer Fused Multiply Add 178 bool HasIFMA = false; 179 180 /// Processor has RTM instructions. 181 bool HasRTM = false; 182 183 /// Processor has ADX instructions. 184 bool HasADX = false; 185 186 /// Processor has SHA instructions. 187 bool HasSHA = false; 188 189 /// Processor has PRFCHW instructions. 190 bool HasPRFCHW = false; 191 192 /// Processor has RDSEED instructions. 193 bool HasRDSEED = false; 194 195 /// Processor has LAHF/SAHF instructions. 196 bool HasLAHFSAHF = false; 197 198 /// Processor has MONITORX/MWAITX instructions. 199 bool HasMWAITX = false; 200 201 /// Processor has Cache Line Zero instruction 202 bool HasCLZERO = false; 203 204 /// Processor has Cache Line Demote instruction 205 bool HasCLDEMOTE = false; 206 207 /// Processor has MOVDIRI instruction (direct store integer). 208 bool HasMOVDIRI = false; 209 210 /// Processor has MOVDIR64B instruction (direct store 64 bytes). 211 bool HasMOVDIR64B = false; 212 213 /// Processor has ptwrite instruction. 214 bool HasPTWRITE = false; 215 216 /// Processor has Prefetch with intent to Write instruction 217 bool HasPREFETCHWT1 = false; 218 219 /// True if SHLD instructions are slow. 220 bool IsSHLDSlow = false; 221 222 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and 223 // PMULUDQ. 224 bool IsPMULLDSlow = false; 225 226 /// True if the PMADDWD instruction is slow compared to PMULLD. 227 bool IsPMADDWDSlow = false; 228 229 /// True if unaligned memory accesses of 16-bytes are slow. 230 bool IsUAMem16Slow = false; 231 232 /// True if unaligned memory accesses of 32-bytes are slow. 233 bool IsUAMem32Slow = false; 234 235 /// True if SSE operations can have unaligned memory operands. 236 /// This may require setting a configuration bit in the processor. 237 bool HasSSEUnalignedMem = false; 238 239 /// True if this processor has the CMPXCHG16B instruction; 240 /// this is true for most x86-64 chips, but not the first AMD chips. 241 bool HasCmpxchg16b = false; 242 243 /// True if the LEA instruction should be used for adjusting 244 /// the stack pointer. This is an optimization for Intel Atom processors. 245 bool UseLeaForSP = false; 246 247 /// True if POPCNT instruction has a false dependency on the destination register. 248 bool HasPOPCNTFalseDeps = false; 249 250 /// True if LZCNT/TZCNT instructions have a false dependency on the destination register. 251 bool HasLZCNTFalseDeps = false; 252 253 /// True if its preferable to combine to a single shuffle using a variable 254 /// mask over multiple fixed shuffles. 255 bool HasFastVariableShuffle = false; 256 257 /// True if there is no performance penalty to writing only the lower parts 258 /// of a YMM or ZMM register without clearing the upper part. 259 bool HasFastPartialYMMorZMMWrite = false; 260 261 /// True if there is no performance penalty for writing NOPs with up to 262 /// 11 bytes. 263 bool HasFast11ByteNOP = false; 264 265 /// True if there is no performance penalty for writing NOPs with up to 266 /// 15 bytes. 267 bool HasFast15ByteNOP = false; 268 269 /// True if gather is reasonably fast. This is true for Skylake client and 270 /// all AVX-512 CPUs. 271 bool HasFastGather = false; 272 273 /// True if hardware SQRTSS instruction is at least as fast (latency) as 274 /// RSQRTSS followed by a Newton-Raphson iteration. 275 bool HasFastScalarFSQRT = false; 276 277 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast 278 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. 279 bool HasFastVectorFSQRT = false; 280 281 /// True if 8-bit divisions are significantly faster than 282 /// 32-bit divisions and should be used when possible. 283 bool HasSlowDivide32 = false; 284 285 /// True if 32-bit divides are significantly faster than 286 /// 64-bit divisions and should be used when possible. 287 bool HasSlowDivide64 = false; 288 289 /// True if LZCNT instruction is fast. 290 bool HasFastLZCNT = false; 291 292 /// True if SHLD based rotate is fast. 293 bool HasFastSHLDRotate = false; 294 295 /// True if the processor supports macrofusion. 296 bool HasMacroFusion = false; 297 298 /// True if the processor has enhanced REP MOVSB/STOSB. 299 bool HasERMSB = false; 300 301 /// True if the short functions should be padded to prevent 302 /// a stall when returning too early. 303 bool PadShortFunctions = false; 304 305 /// True if two memory operand instructions should use a temporary register 306 /// instead. 307 bool SlowTwoMemOps = false; 308 309 /// True if the LEA instruction inputs have to be ready at address generation 310 /// (AG) time. 311 bool LEAUsesAG = false; 312 313 /// True if the LEA instruction with certain arguments is slow 314 bool SlowLEA = false; 315 316 /// True if the LEA instruction has all three source operands: base, index, 317 /// and offset or if the LEA instruction uses base and index registers where 318 /// the base is EBP, RBP,or R13 319 bool Slow3OpsLEA = false; 320 321 /// True if INC and DEC instructions are slow when writing to flags 322 bool SlowIncDec = false; 323 324 /// Processor has AVX-512 PreFetch Instructions 325 bool HasPFI = false; 326 327 /// Processor has AVX-512 Exponential and Reciprocal Instructions 328 bool HasERI = false; 329 330 /// Processor has AVX-512 Conflict Detection Instructions 331 bool HasCDI = false; 332 333 /// Processor has AVX-512 population count Instructions 334 bool HasVPOPCNTDQ = false; 335 336 /// Processor has AVX-512 Doubleword and Quadword instructions 337 bool HasDQI = false; 338 339 /// Processor has AVX-512 Byte and Word instructions 340 bool HasBWI = false; 341 342 /// Processor has AVX-512 Vector Length eXtenstions 343 bool HasVLX = false; 344 345 /// Processor has PKU extenstions 346 bool HasPKU = false; 347 348 /// Processor has AVX-512 Vector Neural Network Instructions 349 bool HasVNNI = false; 350 351 /// Processor has AVX-512 Bit Algorithms instructions 352 bool HasBITALG = false; 353 354 /// Processor supports MPX - Memory Protection Extensions 355 bool HasMPX = false; 356 357 /// Processor supports CET SHSTK - Control-Flow Enforcement Technology 358 /// using Shadow Stack 359 bool HasSHSTK = false; 360 361 /// Processor supports Invalidate Process-Context Identifier 362 bool HasINVPCID = false; 363 364 /// Processor has Software Guard Extensions 365 bool HasSGX = false; 366 367 /// Processor supports Flush Cache Line instruction 368 bool HasCLFLUSHOPT = false; 369 370 /// Processor supports Cache Line Write Back instruction 371 bool HasCLWB = false; 372 373 /// Processor supports Write Back No Invalidate instruction 374 bool HasWBNOINVD = false; 375 376 /// Processor support RDPID instruction 377 bool HasRDPID = false; 378 379 /// Processor supports WaitPKG instructions 380 bool HasWAITPKG = false; 381 382 /// Processor supports PCONFIG instruction 383 bool HasPCONFIG = false; 384 385 /// Processor has a single uop BEXTR implementation. 386 bool HasFastBEXTR = false; 387 388 /// Try harder to combine to horizontal vector ops if they are fast. 389 bool HasFastHorizontalOps = false; 390 391 /// Use a retpoline thunk rather than indirect calls to block speculative 392 /// execution. 393 bool UseRetpolineIndirectCalls = false; 394 395 /// Use a retpoline thunk or remove any indirect branch to block speculative 396 /// execution. 397 bool UseRetpolineIndirectBranches = false; 398 399 /// Deprecated flag, query `UseRetpolineIndirectCalls` and 400 /// `UseRetpolineIndirectBranches` instead. 401 bool DeprecatedUseRetpoline = false; 402 403 /// When using a retpoline thunk, call an externally provided thunk rather 404 /// than emitting one inside the compiler. 405 bool UseRetpolineExternalThunk = false; 406 407 /// Use software floating point for code generation. 408 bool UseSoftFloat = false; 409 410 /// The minimum alignment known to hold of the stack frame on 411 /// entry to the function and which must be maintained by every function. 412 unsigned stackAlignment = 4; 413 414 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. 415 /// 416 // FIXME: this is a known good value for Yonah. How about others? 417 unsigned MaxInlineSizeThreshold = 128; 418 419 /// Indicates target prefers 256 bit instructions. 420 bool Prefer256Bit = false; 421 422 /// Threeway branch is profitable in this subtarget. 423 bool ThreewayBranchProfitable = false; 424 425 /// What processor and OS we're targeting. 426 Triple TargetTriple; 427 428 /// GlobalISel related APIs. 429 std::unique_ptr<CallLowering> CallLoweringInfo; 430 std::unique_ptr<LegalizerInfo> Legalizer; 431 std::unique_ptr<RegisterBankInfo> RegBankInfo; 432 std::unique_ptr<InstructionSelector> InstSelector; 433 434 private: 435 /// Override the stack alignment. 436 unsigned StackAlignOverride; 437 438 /// Preferred vector width from function attribute. 439 unsigned PreferVectorWidthOverride; 440 441 /// Resolved preferred vector width from function attribute and subtarget 442 /// features. 443 unsigned PreferVectorWidth = UINT32_MAX; 444 445 /// Required vector width from function attribute. 446 unsigned RequiredVectorWidth; 447 448 /// True if compiling for 64-bit, false for 16-bit or 32-bit. 449 bool In64BitMode; 450 451 /// True if compiling for 32-bit, false for 16-bit or 64-bit. 452 bool In32BitMode; 453 454 /// True if compiling for 16-bit, false for 32-bit or 64-bit. 455 bool In16BitMode; 456 457 /// Contains the Overhead of gather\scatter instructions 458 int GatherOverhead = 1024; 459 int ScatterOverhead = 1024; 460 461 X86SelectionDAGInfo TSInfo; 462 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which 463 // X86TargetLowering needs. 464 X86InstrInfo InstrInfo; 465 X86TargetLowering TLInfo; 466 X86FrameLowering FrameLowering; 467 468 public: 469 /// This constructor initializes the data members to match that 470 /// of the specified triple. 471 /// 472 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, 473 const X86TargetMachine &TM, unsigned StackAlignOverride, 474 unsigned PreferVectorWidthOverride, 475 unsigned RequiredVectorWidth); 476 getTargetLowering()477 const X86TargetLowering *getTargetLowering() const override { 478 return &TLInfo; 479 } 480 getInstrInfo()481 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; } 482 getFrameLowering()483 const X86FrameLowering *getFrameLowering() const override { 484 return &FrameLowering; 485 } 486 getSelectionDAGInfo()487 const X86SelectionDAGInfo *getSelectionDAGInfo() const override { 488 return &TSInfo; 489 } 490 getRegisterInfo()491 const X86RegisterInfo *getRegisterInfo() const override { 492 return &getInstrInfo()->getRegisterInfo(); 493 } 494 495 /// Returns the minimum alignment known to hold of the 496 /// stack frame on entry to the function and which must be maintained by every 497 /// function for this subtarget. getStackAlignment()498 unsigned getStackAlignment() const { return stackAlignment; } 499 500 /// Returns the maximum memset / memcpy size 501 /// that still makes it profitable to inline the call. getMaxInlineSizeThreshold()502 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } 503 504 /// ParseSubtargetFeatures - Parses features string setting specified 505 /// subtarget options. Definition of function is auto generated by tblgen. 506 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 507 508 /// Methods used by Global ISel 509 const CallLowering *getCallLowering() const override; 510 const InstructionSelector *getInstructionSelector() const override; 511 const LegalizerInfo *getLegalizerInfo() const override; 512 const RegisterBankInfo *getRegBankInfo() const override; 513 514 private: 515 /// Initialize the full set of dependencies so we can use an initializer 516 /// list for X86Subtarget. 517 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 518 void initSubtargetFeatures(StringRef CPU, StringRef FS); 519 520 public: 521 /// Is this x86_64? (disregarding specific ABI / programming model) is64Bit()522 bool is64Bit() const { 523 return In64BitMode; 524 } 525 is32Bit()526 bool is32Bit() const { 527 return In32BitMode; 528 } 529 is16Bit()530 bool is16Bit() const { 531 return In16BitMode; 532 } 533 534 /// Is this x86_64 with the ILP32 programming model (x32 ABI)? isTarget64BitILP32()535 bool isTarget64BitILP32() const { 536 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 || 537 TargetTriple.isOSNaCl()); 538 } 539 540 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? isTarget64BitLP64()541 bool isTarget64BitLP64() const { 542 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 && 543 !TargetTriple.isOSNaCl()); 544 } 545 getPICStyle()546 PICStyles::Style getPICStyle() const { return PICStyle; } setPICStyle(PICStyles::Style Style)547 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } 548 hasX87()549 bool hasX87() const { return HasX87; } hasNOPL()550 bool hasNOPL() const { return HasNOPL; } 551 // SSE codegen depends on cmovs, and all SSE1+ processors support them. 552 // All 64-bit processors support cmov. hasCMov()553 bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); } hasSSE1()554 bool hasSSE1() const { return X86SSELevel >= SSE1; } hasSSE2()555 bool hasSSE2() const { return X86SSELevel >= SSE2; } hasSSE3()556 bool hasSSE3() const { return X86SSELevel >= SSE3; } hasSSSE3()557 bool hasSSSE3() const { return X86SSELevel >= SSSE3; } hasSSE41()558 bool hasSSE41() const { return X86SSELevel >= SSE41; } hasSSE42()559 bool hasSSE42() const { return X86SSELevel >= SSE42; } hasAVX()560 bool hasAVX() const { return X86SSELevel >= AVX; } hasAVX2()561 bool hasAVX2() const { return X86SSELevel >= AVX2; } hasAVX512()562 bool hasAVX512() const { return X86SSELevel >= AVX512F; } hasInt256()563 bool hasInt256() const { return hasAVX2(); } hasSSE4A()564 bool hasSSE4A() const { return HasSSE4A; } hasMMX()565 bool hasMMX() const { return X863DNowLevel >= MMX; } has3DNow()566 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } has3DNowA()567 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } hasPOPCNT()568 bool hasPOPCNT() const { return HasPOPCNT; } hasAES()569 bool hasAES() const { return HasAES; } hasVAES()570 bool hasVAES() const { return HasVAES; } hasFXSR()571 bool hasFXSR() const { return HasFXSR; } hasXSAVE()572 bool hasXSAVE() const { return HasXSAVE; } hasXSAVEOPT()573 bool hasXSAVEOPT() const { return HasXSAVEOPT; } hasXSAVEC()574 bool hasXSAVEC() const { return HasXSAVEC; } hasXSAVES()575 bool hasXSAVES() const { return HasXSAVES; } hasPCLMUL()576 bool hasPCLMUL() const { return HasPCLMUL; } hasVPCLMULQDQ()577 bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; } hasGFNI()578 bool hasGFNI() const { return HasGFNI; } 579 // Prefer FMA4 to FMA - its better for commutation/memory folding and 580 // has equal or better performance on all supported targets. hasFMA()581 bool hasFMA() const { return HasFMA; } hasFMA4()582 bool hasFMA4() const { return HasFMA4; } hasAnyFMA()583 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); } hasXOP()584 bool hasXOP() const { return HasXOP; } hasTBM()585 bool hasTBM() const { return HasTBM; } hasLWP()586 bool hasLWP() const { return HasLWP; } hasMOVBE()587 bool hasMOVBE() const { return HasMOVBE; } hasRDRAND()588 bool hasRDRAND() const { return HasRDRAND; } hasF16C()589 bool hasF16C() const { return HasF16C; } hasFSGSBase()590 bool hasFSGSBase() const { return HasFSGSBase; } hasLZCNT()591 bool hasLZCNT() const { return HasLZCNT; } hasBMI()592 bool hasBMI() const { return HasBMI; } hasBMI2()593 bool hasBMI2() const { return HasBMI2; } hasVBMI()594 bool hasVBMI() const { return HasVBMI; } hasVBMI2()595 bool hasVBMI2() const { return HasVBMI2; } hasIFMA()596 bool hasIFMA() const { return HasIFMA; } hasRTM()597 bool hasRTM() const { return HasRTM; } hasADX()598 bool hasADX() const { return HasADX; } hasSHA()599 bool hasSHA() const { return HasSHA; } hasPRFCHW()600 bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; } hasPREFETCHWT1()601 bool hasPREFETCHWT1() const { return HasPREFETCHWT1; } hasSSEPrefetch()602 bool hasSSEPrefetch() const { 603 // We implicitly enable these when we have a write prefix supporting cache 604 // level OR if we have prfchw, but don't already have a read prefetch from 605 // 3dnow. 606 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1(); 607 } hasRDSEED()608 bool hasRDSEED() const { return HasRDSEED; } hasLAHFSAHF()609 bool hasLAHFSAHF() const { return HasLAHFSAHF; } hasMWAITX()610 bool hasMWAITX() const { return HasMWAITX; } hasCLZERO()611 bool hasCLZERO() const { return HasCLZERO; } hasCLDEMOTE()612 bool hasCLDEMOTE() const { return HasCLDEMOTE; } hasMOVDIRI()613 bool hasMOVDIRI() const { return HasMOVDIRI; } hasMOVDIR64B()614 bool hasMOVDIR64B() const { return HasMOVDIR64B; } hasPTWRITE()615 bool hasPTWRITE() const { return HasPTWRITE; } isSHLDSlow()616 bool isSHLDSlow() const { return IsSHLDSlow; } isPMULLDSlow()617 bool isPMULLDSlow() const { return IsPMULLDSlow; } isPMADDWDSlow()618 bool isPMADDWDSlow() const { return IsPMADDWDSlow; } isUnalignedMem16Slow()619 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } isUnalignedMem32Slow()620 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } getGatherOverhead()621 int getGatherOverhead() const { return GatherOverhead; } getScatterOverhead()622 int getScatterOverhead() const { return ScatterOverhead; } hasSSEUnalignedMem()623 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } hasCmpxchg16b()624 bool hasCmpxchg16b() const { return HasCmpxchg16b; } useLeaForSP()625 bool useLeaForSP() const { return UseLeaForSP; } hasPOPCNTFalseDeps()626 bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; } hasLZCNTFalseDeps()627 bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; } hasFastVariableShuffle()628 bool hasFastVariableShuffle() const { 629 return HasFastVariableShuffle; 630 } hasFastPartialYMMorZMMWrite()631 bool hasFastPartialYMMorZMMWrite() const { 632 return HasFastPartialYMMorZMMWrite; 633 } hasFastGather()634 bool hasFastGather() const { return HasFastGather; } hasFastScalarFSQRT()635 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; } hasFastVectorFSQRT()636 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; } hasFastLZCNT()637 bool hasFastLZCNT() const { return HasFastLZCNT; } hasFastSHLDRotate()638 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; } hasFastBEXTR()639 bool hasFastBEXTR() const { return HasFastBEXTR; } hasFastHorizontalOps()640 bool hasFastHorizontalOps() const { return HasFastHorizontalOps; } hasMacroFusion()641 bool hasMacroFusion() const { return HasMacroFusion; } hasERMSB()642 bool hasERMSB() const { return HasERMSB; } hasSlowDivide32()643 bool hasSlowDivide32() const { return HasSlowDivide32; } hasSlowDivide64()644 bool hasSlowDivide64() const { return HasSlowDivide64; } padShortFunctions()645 bool padShortFunctions() const { return PadShortFunctions; } slowTwoMemOps()646 bool slowTwoMemOps() const { return SlowTwoMemOps; } LEAusesAG()647 bool LEAusesAG() const { return LEAUsesAG; } slowLEA()648 bool slowLEA() const { return SlowLEA; } slow3OpsLEA()649 bool slow3OpsLEA() const { return Slow3OpsLEA; } slowIncDec()650 bool slowIncDec() const { return SlowIncDec; } hasCDI()651 bool hasCDI() const { return HasCDI; } hasVPOPCNTDQ()652 bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; } hasPFI()653 bool hasPFI() const { return HasPFI; } hasERI()654 bool hasERI() const { return HasERI; } hasDQI()655 bool hasDQI() const { return HasDQI; } hasBWI()656 bool hasBWI() const { return HasBWI; } hasVLX()657 bool hasVLX() const { return HasVLX; } hasPKU()658 bool hasPKU() const { return HasPKU; } hasVNNI()659 bool hasVNNI() const { return HasVNNI; } hasBITALG()660 bool hasBITALG() const { return HasBITALG; } hasMPX()661 bool hasMPX() const { return HasMPX; } hasSHSTK()662 bool hasSHSTK() const { return HasSHSTK; } hasCLFLUSHOPT()663 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; } hasCLWB()664 bool hasCLWB() const { return HasCLWB; } hasWBNOINVD()665 bool hasWBNOINVD() const { return HasWBNOINVD; } hasRDPID()666 bool hasRDPID() const { return HasRDPID; } hasWAITPKG()667 bool hasWAITPKG() const { return HasWAITPKG; } hasPCONFIG()668 bool hasPCONFIG() const { return HasPCONFIG; } hasSGX()669 bool hasSGX() const { return HasSGX; } threewayBranchProfitable()670 bool threewayBranchProfitable() const { return ThreewayBranchProfitable; } hasINVPCID()671 bool hasINVPCID() const { return HasINVPCID; } useRetpolineIndirectCalls()672 bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; } useRetpolineIndirectBranches()673 bool useRetpolineIndirectBranches() const { 674 return UseRetpolineIndirectBranches; 675 } useRetpolineExternalThunk()676 bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; } 677 getPreferVectorWidth()678 unsigned getPreferVectorWidth() const { return PreferVectorWidth; } getRequiredVectorWidth()679 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; } 680 681 // Helper functions to determine when we should allow widening to 512-bit 682 // during codegen. 683 // TODO: Currently we're always allowing widening on CPUs without VLX, 684 // because for many cases we don't have a better option. canExtendTo512DQ()685 bool canExtendTo512DQ() const { 686 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512); 687 } canExtendTo512BW()688 bool canExtendTo512BW() const { 689 return hasBWI() && canExtendTo512DQ(); 690 } 691 692 // If there are no 512-bit vectors and we prefer not to use 512-bit registers, 693 // disable them in the legalizer. useAVX512Regs()694 bool useAVX512Regs() const { 695 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256); 696 } 697 useBWIRegs()698 bool useBWIRegs() const { 699 return hasBWI() && useAVX512Regs(); 700 } 701 isXRaySupported()702 bool isXRaySupported() const override { return is64Bit(); } 703 getProcFamily()704 X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; } 705 706 /// TODO: to be removed later and replaced with suitable properties isAtom()707 bool isAtom() const { return X86ProcFamily == IntelAtom; } isSLM()708 bool isSLM() const { return X86ProcFamily == IntelSLM; } isGLM()709 bool isGLM() const { 710 return X86ProcFamily == IntelGLM || 711 X86ProcFamily == IntelGLP || 712 X86ProcFamily == IntelTRM; 713 } useSoftFloat()714 bool useSoftFloat() const { return UseSoftFloat; } 715 716 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 717 /// no-sse2). There isn't any reason to disable it if the target processor 718 /// supports it. hasMFence()719 bool hasMFence() const { return hasSSE2() || is64Bit(); } 720 getTargetTriple()721 const Triple &getTargetTriple() const { return TargetTriple; } 722 isTargetDarwin()723 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } isTargetFreeBSD()724 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); } isTargetDragonFly()725 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); } isTargetSolaris()726 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); } isTargetPS4()727 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); } 728 isTargetELF()729 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } isTargetCOFF()730 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } isTargetMachO()731 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 732 isTargetLinux()733 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } isTargetKFreeBSD()734 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); } isTargetGlibc()735 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); } isTargetAndroid()736 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } isTargetNaCl()737 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } isTargetNaCl32()738 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } isTargetNaCl64()739 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } isTargetMCU()740 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); } isTargetFuchsia()741 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); } 742 isTargetWindowsMSVC()743 bool isTargetWindowsMSVC() const { 744 return TargetTriple.isWindowsMSVCEnvironment(); 745 } 746 isTargetKnownWindowsMSVC()747 bool isTargetKnownWindowsMSVC() const { 748 return TargetTriple.isKnownWindowsMSVCEnvironment(); 749 } 750 isTargetWindowsCoreCLR()751 bool isTargetWindowsCoreCLR() const { 752 return TargetTriple.isWindowsCoreCLREnvironment(); 753 } 754 isTargetWindowsCygwin()755 bool isTargetWindowsCygwin() const { 756 return TargetTriple.isWindowsCygwinEnvironment(); 757 } 758 isTargetWindowsGNU()759 bool isTargetWindowsGNU() const { 760 return TargetTriple.isWindowsGNUEnvironment(); 761 } 762 isTargetWindowsItanium()763 bool isTargetWindowsItanium() const { 764 return TargetTriple.isWindowsItaniumEnvironment(); 765 } 766 isTargetCygMing()767 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } 768 isOSWindows()769 bool isOSWindows() const { return TargetTriple.isOSWindows(); } 770 isTargetWin64()771 bool isTargetWin64() const { return In64BitMode && isOSWindows(); } 772 isTargetWin32()773 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); } 774 isPICStyleGOT()775 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; } isPICStyleRIPRel()776 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; } 777 isPICStyleStubPIC()778 bool isPICStyleStubPIC() const { 779 return PICStyle == PICStyles::StubPIC; 780 } 781 isPositionIndependent()782 bool isPositionIndependent() const { return TM.isPositionIndependent(); } 783 isCallingConvWin64(CallingConv::ID CC)784 bool isCallingConvWin64(CallingConv::ID CC) const { 785 switch (CC) { 786 // On Win64, all these conventions just use the default convention. 787 case CallingConv::C: 788 case CallingConv::Fast: 789 case CallingConv::Swift: 790 case CallingConv::X86_FastCall: 791 case CallingConv::X86_StdCall: 792 case CallingConv::X86_ThisCall: 793 case CallingConv::X86_VectorCall: 794 case CallingConv::Intel_OCL_BI: 795 return isTargetWin64(); 796 // This convention allows using the Win64 convention on other targets. 797 case CallingConv::Win64: 798 return true; 799 // This convention allows using the SysV convention on Windows targets. 800 case CallingConv::X86_64_SysV: 801 return false; 802 // Otherwise, who knows what this is. 803 default: 804 return false; 805 } 806 } 807 808 /// Classify a global variable reference for the current subtarget according 809 /// to how we should reference it in a non-pcrel context. 810 unsigned char classifyLocalReference(const GlobalValue *GV) const; 811 812 unsigned char classifyGlobalReference(const GlobalValue *GV, 813 const Module &M) const; 814 unsigned char classifyGlobalReference(const GlobalValue *GV) const; 815 816 /// Classify a global function reference for the current subtarget. 817 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, 818 const Module &M) const; 819 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const; 820 821 /// Classify a blockaddress reference for the current subtarget according to 822 /// how we should reference it in a non-pcrel context. 823 unsigned char classifyBlockAddressReference() const; 824 825 /// Return true if the subtarget allows calls to immediate address. 826 bool isLegalToCallImmediateAddr() const; 827 828 /// If we are using retpolines, we need to expand indirectbr to avoid it 829 /// lowering to an actual indirect jump. enableIndirectBrExpand()830 bool enableIndirectBrExpand() const override { 831 return useRetpolineIndirectBranches(); 832 } 833 834 /// Enable the MachineScheduler pass for all X86 subtargets. enableMachineScheduler()835 bool enableMachineScheduler() const override { return true; } 836 837 // TODO: Update the regression tests and return true. supportPrintSchedInfo()838 bool supportPrintSchedInfo() const override { return false; } 839 840 bool enableEarlyIfConversion() const override; 841 getAntiDepBreakMode()842 AntiDepBreakMode getAntiDepBreakMode() const override { 843 return TargetSubtargetInfo::ANTIDEP_CRITICAL; 844 } 845 enableAdvancedRASplitCost()846 bool enableAdvancedRASplitCost() const override { return true; } 847 }; 848 849 } // end namespace llvm 850 851 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H 852