1 /*-
2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #ifdef __i386__
31 #include "opt_apic.h"
32 #endif
33 #include "opt_cpu.h"
34 #include "opt_kstack_pages.h"
35 #include "opt_pmap.h"
36 #include "opt_sched.h"
37 #include "opt_smp.h"
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/bus.h>
42 #include <sys/cons.h> /* cngetc() */
43 #include <sys/cpuset.h>
44 #ifdef GPROF
45 #include <sys/gmon.h>
46 #endif
47 #include <sys/kdb.h>
48 #include <sys/kernel.h>
49 #include <sys/ktr.h>
50 #include <sys/lock.h>
51 #include <sys/malloc.h>
52 #include <sys/memrange.h>
53 #include <sys/mutex.h>
54 #include <sys/pcpu.h>
55 #include <sys/proc.h>
56 #include <sys/sched.h>
57 #include <sys/smp.h>
58 #include <sys/sysctl.h>
59
60 #include <vm/vm.h>
61 #include <vm/vm_param.h>
62 #include <vm/pmap.h>
63 #include <vm/vm_kern.h>
64 #include <vm/vm_extern.h>
65 #include <vm/vm_map.h>
66
67 #include <x86/apicreg.h>
68 #include <machine/clock.h>
69 #include <machine/cpu.h>
70 #include <machine/cputypes.h>
71 #include <x86/mca.h>
72 #include <machine/md_var.h>
73 #include <machine/pcb.h>
74 #include <machine/psl.h>
75 #include <machine/smp.h>
76 #include <machine/specialreg.h>
77 #include <x86/ucode.h>
78
79 static MALLOC_DEFINE(M_CPUS, "cpus", "CPU items");
80
81 /* lock region used by kernel profiling */
82 int mcount_lock;
83
84 int mp_naps; /* # of Applications processors */
85 int boot_cpu_id = -1; /* designated BSP */
86
87 /* AP uses this during bootstrap. Do not staticize. */
88 char *bootSTK;
89 int bootAP;
90
91 /* Free these after use */
92 void *bootstacks[MAXCPU];
93 void *dpcpu;
94
95 struct pcb stoppcbs[MAXCPU];
96 struct susppcb **susppcbs;
97
98 #ifdef COUNT_IPIS
99 /* Interrupt counts. */
100 static u_long *ipi_preempt_counts[MAXCPU];
101 static u_long *ipi_ast_counts[MAXCPU];
102 u_long *ipi_invltlb_counts[MAXCPU];
103 u_long *ipi_invlrng_counts[MAXCPU];
104 u_long *ipi_invlpg_counts[MAXCPU];
105 u_long *ipi_invlcache_counts[MAXCPU];
106 u_long *ipi_rendezvous_counts[MAXCPU];
107 static u_long *ipi_hardclock_counts[MAXCPU];
108 #endif
109
110 /* Default cpu_ops implementation. */
111 struct cpu_ops cpu_ops;
112
113 /*
114 * Local data and functions.
115 */
116
117 static volatile cpuset_t ipi_stop_nmi_pending;
118
119 volatile cpuset_t resuming_cpus;
120 volatile cpuset_t toresume_cpus;
121
122 /* used to hold the AP's until we are ready to release them */
123 struct mtx ap_boot_mtx;
124
125 /* Set to 1 once we're ready to let the APs out of the pen. */
126 volatile int aps_ready = 0;
127
128 /*
129 * Store data from cpu_add() until later in the boot when we actually setup
130 * the APs.
131 */
132 struct cpu_info *cpu_info;
133 int *apic_cpuids;
134 int cpu_apic_ids[MAXCPU];
135 _Static_assert(MAXCPU <= MAX_APIC_ID,
136 "MAXCPU cannot be larger that MAX_APIC_ID");
137 _Static_assert(xAPIC_MAX_APIC_ID <= MAX_APIC_ID,
138 "xAPIC_MAX_APIC_ID cannot be larger that MAX_APIC_ID");
139
140 /* Holds pending bitmap based IPIs per CPU */
141 volatile u_int cpu_ipi_pending[MAXCPU];
142
143 static void release_aps(void *dummy);
144 static void cpustop_handler_post(u_int cpu);
145
146 static int hyperthreading_allowed = 1;
147 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_allowed, CTLFLAG_RDTUN,
148 &hyperthreading_allowed, 0, "Use Intel HTT logical CPUs");
149
150 static struct topo_node topo_root;
151
152 static int pkg_id_shift;
153 static int node_id_shift;
154 static int core_id_shift;
155 static int disabled_cpus;
156
157 struct cache_info {
158 int id_shift;
159 int present;
160 } static caches[MAX_CACHE_LEVELS];
161
162 unsigned int boot_address;
163
164 #define MiB(v) (v ## ULL << 20)
165
166 void
mem_range_AP_init(void)167 mem_range_AP_init(void)
168 {
169
170 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
171 mem_range_softc.mr_op->initAP(&mem_range_softc);
172 }
173
174 /*
175 * Round up to the next power of two, if necessary, and then
176 * take log2.
177 * Returns -1 if argument is zero.
178 */
179 static __inline int
mask_width(u_int x)180 mask_width(u_int x)
181 {
182
183 return (fls(x << (1 - powerof2(x))) - 1);
184 }
185
186 /*
187 * Add a cache level to the cache topology description.
188 */
189 static int
add_deterministic_cache(int type,int level,int share_count)190 add_deterministic_cache(int type, int level, int share_count)
191 {
192
193 if (type == 0)
194 return (0);
195 if (type > 3) {
196 printf("unexpected cache type %d\n", type);
197 return (1);
198 }
199 if (type == 2) /* ignore instruction cache */
200 return (1);
201 if (level == 0 || level > MAX_CACHE_LEVELS) {
202 printf("unexpected cache level %d\n", type);
203 return (1);
204 }
205
206 if (caches[level - 1].present) {
207 printf("WARNING: multiple entries for L%u data cache\n", level);
208 printf("%u => %u\n", caches[level - 1].id_shift,
209 mask_width(share_count));
210 }
211 caches[level - 1].id_shift = mask_width(share_count);
212 caches[level - 1].present = 1;
213
214 if (caches[level - 1].id_shift > pkg_id_shift) {
215 printf("WARNING: L%u data cache covers more "
216 "APIC IDs than a package (%u > %u)\n", level,
217 caches[level - 1].id_shift, pkg_id_shift);
218 caches[level - 1].id_shift = pkg_id_shift;
219 }
220 if (caches[level - 1].id_shift < core_id_shift) {
221 printf("WARNING: L%u data cache covers fewer "
222 "APIC IDs than a core (%u < %u)\n", level,
223 caches[level - 1].id_shift, core_id_shift);
224 caches[level - 1].id_shift = core_id_shift;
225 }
226
227 return (1);
228 }
229
230 /*
231 * Determine topology of processing units and caches for AMD CPUs.
232 * See:
233 * - AMD CPUID Specification (Publication # 25481)
234 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
235 * - BKDG For AMD Family 10h Processors (Publication # 31116)
236 * - BKDG For AMD Family 15h Models 00h-0Fh Processors (Publication # 42301)
237 * - BKDG For AMD Family 16h Models 00h-0Fh Processors (Publication # 48751)
238 * - PPR For AMD Family 17h Models 00h-0Fh Processors (Publication # 54945)
239 */
240 static void
topo_probe_amd(void)241 topo_probe_amd(void)
242 {
243 u_int p[4];
244 uint64_t v;
245 int level;
246 int nodes_per_socket;
247 int share_count;
248 int type;
249 int i;
250
251 /* No multi-core capability. */
252 if ((amd_feature2 & AMDID2_CMP) == 0)
253 return;
254
255 /* For families 10h and newer. */
256 pkg_id_shift = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
257 AMDID_COREID_SIZE_SHIFT;
258
259 /* For 0Fh family. */
260 if (pkg_id_shift == 0)
261 pkg_id_shift =
262 mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1);
263
264 /*
265 * Families prior to 16h define the following value as
266 * cores per compute unit and we don't really care about the AMD
267 * compute units at the moment. Perhaps we should treat them as
268 * cores and cores within the compute units as hardware threads,
269 * but that's up for debate.
270 * Later families define the value as threads per compute unit,
271 * so we are following AMD's nomenclature here.
272 */
273 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0 &&
274 CPUID_TO_FAMILY(cpu_id) >= 0x16) {
275 cpuid_count(0x8000001e, 0, p);
276 share_count = ((p[1] >> 8) & 0xff) + 1;
277 core_id_shift = mask_width(share_count);
278
279 /*
280 * For Zen (17h), gather Nodes per Processor. Each node is a
281 * Zeppelin die; TR and EPYC CPUs will have multiple dies per
282 * package. Communication latency between dies is higher than
283 * within them.
284 */
285 nodes_per_socket = ((p[2] >> 8) & 0x7) + 1;
286 node_id_shift = pkg_id_shift - mask_width(nodes_per_socket);
287 }
288
289 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) {
290 for (i = 0; ; i++) {
291 cpuid_count(0x8000001d, i, p);
292 type = p[0] & 0x1f;
293 level = (p[0] >> 5) & 0x7;
294 share_count = 1 + ((p[0] >> 14) & 0xfff);
295
296 if (!add_deterministic_cache(type, level, share_count))
297 break;
298 }
299 } else {
300 if (cpu_exthigh >= 0x80000005) {
301 cpuid_count(0x80000005, 0, p);
302 if (((p[2] >> 24) & 0xff) != 0) {
303 caches[0].id_shift = 0;
304 caches[0].present = 1;
305 }
306 }
307 if (cpu_exthigh >= 0x80000006) {
308 cpuid_count(0x80000006, 0, p);
309 if (((p[2] >> 16) & 0xffff) != 0) {
310 caches[1].id_shift = 0;
311 caches[1].present = 1;
312 }
313 if (((p[3] >> 18) & 0x3fff) != 0) {
314 nodes_per_socket = 1;
315 if ((amd_feature2 & AMDID2_NODE_ID) != 0) {
316 /*
317 * Handle multi-node processors that
318 * have multiple chips, each with its
319 * own L3 cache, on the same die.
320 */
321 v = rdmsr(0xc001100c);
322 nodes_per_socket = 1 + ((v >> 3) & 0x7);
323 }
324 caches[2].id_shift =
325 pkg_id_shift - mask_width(nodes_per_socket);
326 caches[2].present = 1;
327 }
328 }
329 }
330 }
331
332 /*
333 * Determine topology of processing units for Intel CPUs
334 * using CPUID Leaf 1 and Leaf 4, if supported.
335 * See:
336 * - Intel 64 Architecture Processor Topology Enumeration
337 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
338 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
339 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
340 */
341 static void
topo_probe_intel_0x4(void)342 topo_probe_intel_0x4(void)
343 {
344 u_int p[4];
345 int max_cores;
346 int max_logical;
347
348 /* Both zero and one here mean one logical processor per package. */
349 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
350 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
351 if (max_logical <= 1)
352 return;
353
354 if (cpu_high >= 0x4) {
355 cpuid_count(0x04, 0, p);
356 max_cores = ((p[0] >> 26) & 0x3f) + 1;
357 } else
358 max_cores = 1;
359
360 core_id_shift = mask_width(max_logical/max_cores);
361 KASSERT(core_id_shift >= 0,
362 ("intel topo: max_cores > max_logical\n"));
363 pkg_id_shift = core_id_shift + mask_width(max_cores);
364 }
365
366 /*
367 * Determine topology of processing units for Intel CPUs
368 * using CPUID Leaf 11, if supported.
369 * See:
370 * - Intel 64 Architecture Processor Topology Enumeration
371 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
372 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
373 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
374 */
375 static void
topo_probe_intel_0xb(void)376 topo_probe_intel_0xb(void)
377 {
378 u_int p[4];
379 int bits;
380 int type;
381 int i;
382
383 /* Fall back if CPU leaf 11 doesn't really exist. */
384 cpuid_count(0x0b, 0, p);
385 if (p[1] == 0) {
386 topo_probe_intel_0x4();
387 return;
388 }
389
390 /* We only support three levels for now. */
391 for (i = 0; ; i++) {
392 cpuid_count(0x0b, i, p);
393
394 bits = p[0] & 0x1f;
395 type = (p[2] >> 8) & 0xff;
396
397 if (type == 0)
398 break;
399
400 /* TODO: check for duplicate (re-)assignment */
401 if (type == CPUID_TYPE_SMT)
402 core_id_shift = bits;
403 else if (type == CPUID_TYPE_CORE)
404 pkg_id_shift = bits;
405 else
406 printf("unknown CPU level type %d\n", type);
407 }
408
409 if (pkg_id_shift < core_id_shift) {
410 printf("WARNING: core covers more APIC IDs than a package\n");
411 core_id_shift = pkg_id_shift;
412 }
413 }
414
415 /*
416 * Determine topology of caches for Intel CPUs.
417 * See:
418 * - Intel 64 Architecture Processor Topology Enumeration
419 * - Intel 64 and IA-32 Architectures Software Developer’s Manual
420 * Volume 2A: Instruction Set Reference, A-M,
421 * CPUID instruction
422 */
423 static void
topo_probe_intel_caches(void)424 topo_probe_intel_caches(void)
425 {
426 u_int p[4];
427 int level;
428 int share_count;
429 int type;
430 int i;
431
432 if (cpu_high < 0x4) {
433 /*
434 * Available cache level and sizes can be determined
435 * via CPUID leaf 2, but that requires a huge table of hardcoded
436 * values, so for now just assume L1 and L2 caches potentially
437 * shared only by HTT processing units, if HTT is present.
438 */
439 caches[0].id_shift = pkg_id_shift;
440 caches[0].present = 1;
441 caches[1].id_shift = pkg_id_shift;
442 caches[1].present = 1;
443 return;
444 }
445
446 for (i = 0; ; i++) {
447 cpuid_count(0x4, i, p);
448 type = p[0] & 0x1f;
449 level = (p[0] >> 5) & 0x7;
450 share_count = 1 + ((p[0] >> 14) & 0xfff);
451
452 if (!add_deterministic_cache(type, level, share_count))
453 break;
454 }
455 }
456
457 /*
458 * Determine topology of processing units and caches for Intel CPUs.
459 * See:
460 * - Intel 64 Architecture Processor Topology Enumeration
461 */
462 static void
topo_probe_intel(void)463 topo_probe_intel(void)
464 {
465
466 /*
467 * Note that 0x1 <= cpu_high < 4 case should be
468 * compatible with topo_probe_intel_0x4() logic when
469 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
470 * or it should trigger the fallback otherwise.
471 */
472 if (cpu_high >= 0xb)
473 topo_probe_intel_0xb();
474 else if (cpu_high >= 0x1)
475 topo_probe_intel_0x4();
476
477 topo_probe_intel_caches();
478 }
479
480 /*
481 * Topology information is queried only on BSP, on which this
482 * code runs and for which it can query CPUID information.
483 * Then topology is extrapolated on all packages using an
484 * assumption that APIC ID to hardware component ID mapping is
485 * homogenious.
486 * That doesn't necesserily imply that the topology is uniform.
487 */
488 void
topo_probe(void)489 topo_probe(void)
490 {
491 static int cpu_topo_probed = 0;
492 struct x86_topo_layer {
493 int type;
494 int subtype;
495 int id_shift;
496 } topo_layers[MAX_CACHE_LEVELS + 4];
497 struct topo_node *parent;
498 struct topo_node *node;
499 int layer;
500 int nlayers;
501 int node_id;
502 int i;
503
504 if (cpu_topo_probed)
505 return;
506
507 CPU_ZERO(&logical_cpus_mask);
508
509 if (mp_ncpus <= 1)
510 ; /* nothing */
511 else if (cpu_vendor_id == CPU_VENDOR_AMD)
512 topo_probe_amd();
513 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
514 topo_probe_intel();
515
516 KASSERT(pkg_id_shift >= core_id_shift,
517 ("bug in APIC topology discovery"));
518
519 nlayers = 0;
520 bzero(topo_layers, sizeof(topo_layers));
521
522 topo_layers[nlayers].type = TOPO_TYPE_PKG;
523 topo_layers[nlayers].id_shift = pkg_id_shift;
524 if (bootverbose)
525 printf("Package ID shift: %u\n", topo_layers[nlayers].id_shift);
526 nlayers++;
527
528 if (pkg_id_shift > node_id_shift && node_id_shift != 0) {
529 topo_layers[nlayers].type = TOPO_TYPE_GROUP;
530 topo_layers[nlayers].id_shift = node_id_shift;
531 if (bootverbose)
532 printf("Node ID shift: %u\n",
533 topo_layers[nlayers].id_shift);
534 nlayers++;
535 }
536
537 /*
538 * Consider all caches to be within a package/chip
539 * and "in front" of all sub-components like
540 * cores and hardware threads.
541 */
542 for (i = MAX_CACHE_LEVELS - 1; i >= 0; --i) {
543 if (caches[i].present) {
544 if (node_id_shift != 0)
545 KASSERT(caches[i].id_shift <= node_id_shift,
546 ("bug in APIC topology discovery"));
547 KASSERT(caches[i].id_shift <= pkg_id_shift,
548 ("bug in APIC topology discovery"));
549 KASSERT(caches[i].id_shift >= core_id_shift,
550 ("bug in APIC topology discovery"));
551
552 topo_layers[nlayers].type = TOPO_TYPE_CACHE;
553 topo_layers[nlayers].subtype = i + 1;
554 topo_layers[nlayers].id_shift = caches[i].id_shift;
555 if (bootverbose)
556 printf("L%u cache ID shift: %u\n",
557 topo_layers[nlayers].subtype,
558 topo_layers[nlayers].id_shift);
559 nlayers++;
560 }
561 }
562
563 if (pkg_id_shift > core_id_shift) {
564 topo_layers[nlayers].type = TOPO_TYPE_CORE;
565 topo_layers[nlayers].id_shift = core_id_shift;
566 if (bootverbose)
567 printf("Core ID shift: %u\n",
568 topo_layers[nlayers].id_shift);
569 nlayers++;
570 }
571
572 topo_layers[nlayers].type = TOPO_TYPE_PU;
573 topo_layers[nlayers].id_shift = 0;
574 nlayers++;
575
576 topo_init_root(&topo_root);
577 for (i = 0; i <= max_apic_id; ++i) {
578 if (!cpu_info[i].cpu_present)
579 continue;
580
581 parent = &topo_root;
582 for (layer = 0; layer < nlayers; ++layer) {
583 node_id = i >> topo_layers[layer].id_shift;
584 parent = topo_add_node_by_hwid(parent, node_id,
585 topo_layers[layer].type,
586 topo_layers[layer].subtype);
587 }
588 }
589
590 parent = &topo_root;
591 for (layer = 0; layer < nlayers; ++layer) {
592 node_id = boot_cpu_id >> topo_layers[layer].id_shift;
593 node = topo_find_node_by_hwid(parent, node_id,
594 topo_layers[layer].type,
595 topo_layers[layer].subtype);
596 topo_promote_child(node);
597 parent = node;
598 }
599
600 cpu_topo_probed = 1;
601 }
602
603 /*
604 * Assign logical CPU IDs to local APICs.
605 */
606 void
assign_cpu_ids(void)607 assign_cpu_ids(void)
608 {
609 struct topo_node *node;
610 u_int smt_mask;
611
612 smt_mask = (1u << core_id_shift) - 1;
613
614 /*
615 * Assign CPU IDs to local APIC IDs and disable any CPUs
616 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
617 */
618 mp_ncpus = 0;
619 TOPO_FOREACH(node, &topo_root) {
620 if (node->type != TOPO_TYPE_PU)
621 continue;
622
623 if ((node->hwid & smt_mask) != (boot_cpu_id & smt_mask))
624 cpu_info[node->hwid].cpu_hyperthread = 1;
625
626 if (resource_disabled("lapic", node->hwid)) {
627 if (node->hwid != boot_cpu_id)
628 cpu_info[node->hwid].cpu_disabled = 1;
629 else
630 printf("Cannot disable BSP, APIC ID = %d\n",
631 node->hwid);
632 }
633
634 if (!hyperthreading_allowed &&
635 cpu_info[node->hwid].cpu_hyperthread)
636 cpu_info[node->hwid].cpu_disabled = 1;
637
638 if (mp_ncpus >= MAXCPU)
639 cpu_info[node->hwid].cpu_disabled = 1;
640
641 if (cpu_info[node->hwid].cpu_disabled) {
642 disabled_cpus++;
643 continue;
644 }
645
646 cpu_apic_ids[mp_ncpus] = node->hwid;
647 apic_cpuids[node->hwid] = mp_ncpus;
648 topo_set_pu_id(node, mp_ncpus);
649 mp_ncpus++;
650 }
651
652 KASSERT(mp_maxid >= mp_ncpus - 1,
653 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
654 mp_ncpus));
655 }
656
657 /*
658 * Print various information about the SMP system hardware and setup.
659 */
660 void
cpu_mp_announce(void)661 cpu_mp_announce(void)
662 {
663 struct topo_node *node;
664 const char *hyperthread;
665 struct topo_analysis topology;
666
667 printf("FreeBSD/SMP: ");
668 if (topo_analyze(&topo_root, 1, &topology)) {
669 printf("%d package(s)", topology.entities[TOPO_LEVEL_PKG]);
670 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
671 printf(" x %d groups",
672 topology.entities[TOPO_LEVEL_GROUP]);
673 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
674 printf(" x %d cache groups",
675 topology.entities[TOPO_LEVEL_CACHEGROUP]);
676 if (topology.entities[TOPO_LEVEL_CORE] > 0)
677 printf(" x %d core(s)",
678 topology.entities[TOPO_LEVEL_CORE]);
679 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
680 printf(" x %d hardware threads",
681 topology.entities[TOPO_LEVEL_THREAD]);
682 } else {
683 printf("Non-uniform topology");
684 }
685 printf("\n");
686
687 if (disabled_cpus) {
688 printf("FreeBSD/SMP Online: ");
689 if (topo_analyze(&topo_root, 0, &topology)) {
690 printf("%d package(s)",
691 topology.entities[TOPO_LEVEL_PKG]);
692 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
693 printf(" x %d groups",
694 topology.entities[TOPO_LEVEL_GROUP]);
695 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
696 printf(" x %d cache groups",
697 topology.entities[TOPO_LEVEL_CACHEGROUP]);
698 if (topology.entities[TOPO_LEVEL_CORE] > 0)
699 printf(" x %d core(s)",
700 topology.entities[TOPO_LEVEL_CORE]);
701 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
702 printf(" x %d hardware threads",
703 topology.entities[TOPO_LEVEL_THREAD]);
704 } else {
705 printf("Non-uniform topology");
706 }
707 printf("\n");
708 }
709
710 if (!bootverbose)
711 return;
712
713 TOPO_FOREACH(node, &topo_root) {
714 switch (node->type) {
715 case TOPO_TYPE_PKG:
716 printf("Package HW ID = %u\n", node->hwid);
717 break;
718 case TOPO_TYPE_CORE:
719 printf("\tCore HW ID = %u\n", node->hwid);
720 break;
721 case TOPO_TYPE_PU:
722 if (cpu_info[node->hwid].cpu_hyperthread)
723 hyperthread = "/HT";
724 else
725 hyperthread = "";
726
727 if (node->subtype == 0)
728 printf("\t\tCPU (AP%s): APIC ID: %u"
729 "(disabled)\n", hyperthread, node->hwid);
730 else if (node->id == 0)
731 printf("\t\tCPU0 (BSP): APIC ID: %u\n",
732 node->hwid);
733 else
734 printf("\t\tCPU%u (AP%s): APIC ID: %u\n",
735 node->id, hyperthread, node->hwid);
736 break;
737 default:
738 /* ignored */
739 break;
740 }
741 }
742 }
743
744 /*
745 * Add a scheduling group, a group of logical processors sharing
746 * a particular cache (and, thus having an affinity), to the scheduling
747 * topology.
748 * This function recursively works on lower level caches.
749 */
750 static void
x86topo_add_sched_group(struct topo_node * root,struct cpu_group * cg_root)751 x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
752 {
753 struct topo_node *node;
754 int nchildren;
755 int ncores;
756 int i;
757
758 KASSERT(root->type == TOPO_TYPE_SYSTEM || root->type == TOPO_TYPE_CACHE ||
759 root->type == TOPO_TYPE_GROUP,
760 ("x86topo_add_sched_group: bad type: %u", root->type));
761 CPU_COPY(&root->cpuset, &cg_root->cg_mask);
762 cg_root->cg_count = root->cpu_count;
763 if (root->type == TOPO_TYPE_SYSTEM)
764 cg_root->cg_level = CG_SHARE_NONE;
765 else
766 cg_root->cg_level = root->subtype;
767
768 /*
769 * Check how many core nodes we have under the given root node.
770 * If we have multiple logical processors, but not multiple
771 * cores, then those processors must be hardware threads.
772 */
773 ncores = 0;
774 node = root;
775 while (node != NULL) {
776 if (node->type != TOPO_TYPE_CORE) {
777 node = topo_next_node(root, node);
778 continue;
779 }
780
781 ncores++;
782 node = topo_next_nonchild_node(root, node);
783 }
784
785 if (cg_root->cg_level != CG_SHARE_NONE &&
786 root->cpu_count > 1 && ncores < 2)
787 cg_root->cg_flags = CG_FLAG_SMT;
788
789 /*
790 * Find out how many cache nodes we have under the given root node.
791 * We ignore cache nodes that cover all the same processors as the
792 * root node. Also, we do not descend below found cache nodes.
793 * That is, we count top-level "non-redundant" caches under the root
794 * node.
795 */
796 nchildren = 0;
797 node = root;
798 while (node != NULL) {
799 if ((node->type != TOPO_TYPE_GROUP &&
800 node->type != TOPO_TYPE_CACHE) ||
801 (root->type != TOPO_TYPE_SYSTEM &&
802 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
803 node = topo_next_node(root, node);
804 continue;
805 }
806 nchildren++;
807 node = topo_next_nonchild_node(root, node);
808 }
809
810 cg_root->cg_child = smp_topo_alloc(nchildren);
811 cg_root->cg_children = nchildren;
812
813 /*
814 * Now find again the same cache nodes as above and recursively
815 * build scheduling topologies for them.
816 */
817 node = root;
818 i = 0;
819 while (node != NULL) {
820 if ((node->type != TOPO_TYPE_GROUP &&
821 node->type != TOPO_TYPE_CACHE) ||
822 (root->type != TOPO_TYPE_SYSTEM &&
823 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
824 node = topo_next_node(root, node);
825 continue;
826 }
827 cg_root->cg_child[i].cg_parent = cg_root;
828 x86topo_add_sched_group(node, &cg_root->cg_child[i]);
829 i++;
830 node = topo_next_nonchild_node(root, node);
831 }
832 }
833
834 /*
835 * Build the MI scheduling topology from the discovered hardware topology.
836 */
837 struct cpu_group *
cpu_topo(void)838 cpu_topo(void)
839 {
840 struct cpu_group *cg_root;
841
842 if (mp_ncpus <= 1)
843 return (smp_topo_none());
844
845 cg_root = smp_topo_alloc(1);
846 x86topo_add_sched_group(&topo_root, cg_root);
847 return (cg_root);
848 }
849
850 static void
cpu_alloc(void * dummy __unused)851 cpu_alloc(void *dummy __unused)
852 {
853 /*
854 * Dynamically allocate the arrays that depend on the
855 * maximum APIC ID.
856 */
857 cpu_info = malloc(sizeof(*cpu_info) * (max_apic_id + 1), M_CPUS,
858 M_WAITOK | M_ZERO);
859 apic_cpuids = malloc(sizeof(*apic_cpuids) * (max_apic_id + 1), M_CPUS,
860 M_WAITOK | M_ZERO);
861 }
862 SYSINIT(cpu_alloc, SI_SUB_CPU, SI_ORDER_FIRST, cpu_alloc, NULL);
863
864 /*
865 * Add a logical CPU to the topology.
866 */
867 void
cpu_add(u_int apic_id,char boot_cpu)868 cpu_add(u_int apic_id, char boot_cpu)
869 {
870
871 if (apic_id > max_apic_id) {
872 panic("SMP: APIC ID %d too high", apic_id);
873 return;
874 }
875 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %u added twice",
876 apic_id));
877 cpu_info[apic_id].cpu_present = 1;
878 if (boot_cpu) {
879 KASSERT(boot_cpu_id == -1,
880 ("CPU %u claims to be BSP, but CPU %u already is", apic_id,
881 boot_cpu_id));
882 boot_cpu_id = apic_id;
883 cpu_info[apic_id].cpu_bsp = 1;
884 }
885 if (bootverbose)
886 printf("SMP: Added CPU %u (%s)\n", apic_id, boot_cpu ? "BSP" :
887 "AP");
888 }
889
890 void
cpu_mp_setmaxid(void)891 cpu_mp_setmaxid(void)
892 {
893
894 /*
895 * mp_ncpus and mp_maxid should be already set by calls to cpu_add().
896 * If there were no calls to cpu_add() assume this is a UP system.
897 */
898 if (mp_ncpus == 0)
899 mp_ncpus = 1;
900 }
901
902 int
cpu_mp_probe(void)903 cpu_mp_probe(void)
904 {
905
906 /*
907 * Always record BSP in CPU map so that the mbuf init code works
908 * correctly.
909 */
910 CPU_SETOF(0, &all_cpus);
911 return (mp_ncpus > 1);
912 }
913
914 /* Allocate memory for the AP trampoline. */
915 void
alloc_ap_trampoline(vm_paddr_t * physmap,unsigned int * physmap_idx)916 alloc_ap_trampoline(vm_paddr_t *physmap, unsigned int *physmap_idx)
917 {
918 unsigned int i;
919 bool allocated;
920
921 allocated = false;
922 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
923 /*
924 * Find a memory region big enough and below the 1MB boundary
925 * for the trampoline code.
926 * NB: needs to be page aligned.
927 */
928 if (physmap[i] >= MiB(1) ||
929 (trunc_page(physmap[i + 1]) - round_page(physmap[i])) <
930 round_page(bootMP_size))
931 continue;
932
933 allocated = true;
934 /*
935 * Try to steal from the end of the region to mimic previous
936 * behaviour, else fallback to steal from the start.
937 */
938 if (physmap[i + 1] < MiB(1)) {
939 boot_address = trunc_page(physmap[i + 1]);
940 if ((physmap[i + 1] - boot_address) < bootMP_size)
941 boot_address -= round_page(bootMP_size);
942 physmap[i + 1] = boot_address;
943 } else {
944 boot_address = round_page(physmap[i]);
945 physmap[i] = boot_address + round_page(bootMP_size);
946 }
947 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
948 memmove(&physmap[i], &physmap[i + 2],
949 sizeof(*physmap) * (*physmap_idx - i + 2));
950 *physmap_idx -= 2;
951 }
952 break;
953 }
954
955 if (!allocated) {
956 boot_address = basemem * 1024 - bootMP_size;
957 if (bootverbose)
958 printf(
959 "Cannot find enough space for the boot trampoline, placing it at %#x",
960 boot_address);
961 }
962 }
963
964 /*
965 * AP CPU's call this to initialize themselves.
966 */
967 void
init_secondary_tail(void)968 init_secondary_tail(void)
969 {
970 u_int cpuid;
971
972 pmap_activate_boot(vmspace_pmap(proc0.p_vmspace));
973
974 /*
975 * On real hardware, switch to x2apic mode if possible. Do it
976 * after aps_ready was signalled, to avoid manipulating the
977 * mode while BSP might still want to send some IPI to us
978 * (second startup IPI is ignored on modern hardware etc).
979 */
980 lapic_xapic_mode();
981
982 /* Initialize the PAT MSR. */
983 pmap_init_pat();
984
985 /* set up CPU registers and state */
986 cpu_setregs();
987
988 /* set up SSE/NX */
989 initializecpu();
990
991 /* set up FPU state on the AP */
992 #ifdef __amd64__
993 fpuinit();
994 #else
995 npxinit(false);
996 #endif
997
998 if (cpu_ops.cpu_init)
999 cpu_ops.cpu_init();
1000
1001 /* A quick check from sanity claus */
1002 cpuid = PCPU_GET(cpuid);
1003 if (PCPU_GET(apic_id) != lapic_id()) {
1004 printf("SMP: cpuid = %d\n", cpuid);
1005 printf("SMP: actual apic_id = %d\n", lapic_id());
1006 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
1007 panic("cpuid mismatch! boom!!");
1008 }
1009
1010 /* Initialize curthread. */
1011 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
1012 PCPU_SET(curthread, PCPU_GET(idlethread));
1013
1014 mtx_lock_spin(&ap_boot_mtx);
1015
1016 mca_init();
1017
1018 /* Init local apic for irq's */
1019 lapic_setup(1);
1020
1021 /* Set memory range attributes for this CPU to match the BSP */
1022 mem_range_AP_init();
1023
1024 smp_cpus++;
1025
1026 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
1027 if (bootverbose)
1028 printf("SMP: AP CPU #%d Launched!\n", cpuid);
1029 else
1030 printf("%s%d%s", smp_cpus == 2 ? "Launching APs: " : "",
1031 cpuid, smp_cpus == mp_ncpus ? "\n" : " ");
1032
1033 /* Determine if we are a logical CPU. */
1034 if (cpu_info[PCPU_GET(apic_id)].cpu_hyperthread)
1035 CPU_SET(cpuid, &logical_cpus_mask);
1036
1037 if (bootverbose)
1038 lapic_dump("AP");
1039
1040 if (smp_cpus == mp_ncpus) {
1041 /* enable IPI's, tlb shootdown, freezes etc */
1042 atomic_store_rel_int(&smp_started, 1);
1043 }
1044
1045 #ifdef __amd64__
1046 /*
1047 * Enable global pages TLB extension
1048 * This also implicitly flushes the TLB
1049 */
1050 load_cr4(rcr4() | CR4_PGE);
1051 if (pmap_pcid_enabled)
1052 load_cr4(rcr4() | CR4_PCIDE);
1053 load_ds(_udatasel);
1054 load_es(_udatasel);
1055 load_fs(_ufssel);
1056 #endif
1057
1058 mtx_unlock_spin(&ap_boot_mtx);
1059
1060 /* Wait until all the AP's are up. */
1061 while (atomic_load_acq_int(&smp_started) == 0)
1062 ia32_pause();
1063
1064 #ifndef EARLY_AP_STARTUP
1065 /* Start per-CPU event timers. */
1066 cpu_initclocks_ap();
1067 #endif
1068
1069 sched_throw(NULL);
1070
1071 panic("scheduler returned us to %s", __func__);
1072 /* NOTREACHED */
1073 }
1074
1075 static void
smp_after_idle_runnable(void * arg __unused)1076 smp_after_idle_runnable(void *arg __unused)
1077 {
1078 struct thread *idle_td;
1079 int cpu;
1080
1081 for (cpu = 1; cpu < mp_ncpus; cpu++) {
1082 idle_td = pcpu_find(cpu)->pc_idlethread;
1083 while (idle_td->td_lastcpu == NOCPU &&
1084 idle_td->td_oncpu == NOCPU)
1085 cpu_spinwait();
1086 kmem_free((vm_offset_t)bootstacks[cpu], kstack_pages *
1087 PAGE_SIZE);
1088 }
1089 }
1090 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
1091 smp_after_idle_runnable, NULL);
1092
1093 /*
1094 * We tell the I/O APIC code about all the CPUs we want to receive
1095 * interrupts. If we don't want certain CPUs to receive IRQs we
1096 * can simply not tell the I/O APIC code about them in this function.
1097 * We also do not tell it about the BSP since it tells itself about
1098 * the BSP internally to work with UP kernels and on UP machines.
1099 */
1100 void
set_interrupt_apic_ids(void)1101 set_interrupt_apic_ids(void)
1102 {
1103 u_int i, apic_id;
1104
1105 for (i = 0; i < MAXCPU; i++) {
1106 apic_id = cpu_apic_ids[i];
1107 if (apic_id == -1)
1108 continue;
1109 if (cpu_info[apic_id].cpu_bsp)
1110 continue;
1111 if (cpu_info[apic_id].cpu_disabled)
1112 continue;
1113
1114 /* Don't let hyperthreads service interrupts. */
1115 if (cpu_info[apic_id].cpu_hyperthread)
1116 continue;
1117
1118 intr_add_cpu(i);
1119 }
1120 }
1121
1122
1123 #ifdef COUNT_XINVLTLB_HITS
1124 u_int xhits_gbl[MAXCPU];
1125 u_int xhits_pg[MAXCPU];
1126 u_int xhits_rng[MAXCPU];
1127 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1128 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1129 sizeof(xhits_gbl), "IU", "");
1130 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1131 sizeof(xhits_pg), "IU", "");
1132 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1133 sizeof(xhits_rng), "IU", "");
1134
1135 u_int ipi_global;
1136 u_int ipi_page;
1137 u_int ipi_range;
1138 u_int ipi_range_size;
1139 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1140 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1141 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1142 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1143 0, "");
1144 #endif /* COUNT_XINVLTLB_HITS */
1145
1146 /*
1147 * Init and startup IPI.
1148 */
1149 void
ipi_startup(int apic_id,int vector)1150 ipi_startup(int apic_id, int vector)
1151 {
1152
1153 /*
1154 * This attempts to follow the algorithm described in the
1155 * Intel Multiprocessor Specification v1.4 in section B.4.
1156 * For each IPI, we allow the local APIC ~20us to deliver the
1157 * IPI. If that times out, we panic.
1158 */
1159
1160 /*
1161 * first we do an INIT IPI: this INIT IPI might be run, resetting
1162 * and running the target CPU. OR this INIT IPI might be latched (P5
1163 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1164 * ignored.
1165 */
1166 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1167 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1168 lapic_ipi_wait(100);
1169
1170 /* Explicitly deassert the INIT IPI. */
1171 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1172 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1173 apic_id);
1174
1175 DELAY(10000); /* wait ~10mS */
1176
1177 /*
1178 * next we do a STARTUP IPI: the previous INIT IPI might still be
1179 * latched, (P5 bug) this 1st STARTUP would then terminate
1180 * immediately, and the previously started INIT IPI would continue. OR
1181 * the previous INIT IPI has already run. and this STARTUP IPI will
1182 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1183 * will run.
1184 */
1185 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1186 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1187 vector, apic_id);
1188 if (!lapic_ipi_wait(100))
1189 panic("Failed to deliver first STARTUP IPI to APIC %d",
1190 apic_id);
1191 DELAY(200); /* wait ~200uS */
1192
1193 /*
1194 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1195 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1196 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1197 * recognized after hardware RESET or INIT IPI.
1198 */
1199 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1200 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1201 vector, apic_id);
1202 if (!lapic_ipi_wait(100))
1203 panic("Failed to deliver second STARTUP IPI to APIC %d",
1204 apic_id);
1205
1206 DELAY(200); /* wait ~200uS */
1207 }
1208
1209 /*
1210 * Send an IPI to specified CPU handling the bitmap logic.
1211 */
1212 void
ipi_send_cpu(int cpu,u_int ipi)1213 ipi_send_cpu(int cpu, u_int ipi)
1214 {
1215 u_int bitmap, old_pending, new_pending;
1216
1217 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1218
1219 if (IPI_IS_BITMAPED(ipi)) {
1220 bitmap = 1 << ipi;
1221 ipi = IPI_BITMAP_VECTOR;
1222 do {
1223 old_pending = cpu_ipi_pending[cpu];
1224 new_pending = old_pending | bitmap;
1225 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1226 old_pending, new_pending));
1227 if (old_pending)
1228 return;
1229 }
1230 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1231 }
1232
1233 void
ipi_bitmap_handler(struct trapframe frame)1234 ipi_bitmap_handler(struct trapframe frame)
1235 {
1236 struct trapframe *oldframe;
1237 struct thread *td;
1238 int cpu = PCPU_GET(cpuid);
1239 u_int ipi_bitmap;
1240
1241 critical_enter();
1242 td = curthread;
1243 td->td_intr_nesting_level++;
1244 oldframe = td->td_intr_frame;
1245 td->td_intr_frame = &frame;
1246 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1247 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1248 #ifdef COUNT_IPIS
1249 (*ipi_preempt_counts[cpu])++;
1250 #endif
1251 sched_preempt(td);
1252 }
1253 if (ipi_bitmap & (1 << IPI_AST)) {
1254 #ifdef COUNT_IPIS
1255 (*ipi_ast_counts[cpu])++;
1256 #endif
1257 /* Nothing to do for AST */
1258 }
1259 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1260 #ifdef COUNT_IPIS
1261 (*ipi_hardclock_counts[cpu])++;
1262 #endif
1263 hardclockintr();
1264 }
1265 td->td_intr_frame = oldframe;
1266 td->td_intr_nesting_level--;
1267 critical_exit();
1268 }
1269
1270 /*
1271 * send an IPI to a set of cpus.
1272 */
1273 void
ipi_selected(cpuset_t cpus,u_int ipi)1274 ipi_selected(cpuset_t cpus, u_int ipi)
1275 {
1276 int cpu;
1277
1278 /*
1279 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1280 * of help in order to understand what is the source.
1281 * Set the mask of receiving CPUs for this purpose.
1282 */
1283 if (ipi == IPI_STOP_HARD)
1284 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &cpus);
1285
1286 while ((cpu = CPU_FFS(&cpus)) != 0) {
1287 cpu--;
1288 CPU_CLR(cpu, &cpus);
1289 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1290 ipi_send_cpu(cpu, ipi);
1291 }
1292 }
1293
1294 /*
1295 * send an IPI to a specific CPU.
1296 */
1297 void
ipi_cpu(int cpu,u_int ipi)1298 ipi_cpu(int cpu, u_int ipi)
1299 {
1300
1301 /*
1302 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1303 * of help in order to understand what is the source.
1304 * Set the mask of receiving CPUs for this purpose.
1305 */
1306 if (ipi == IPI_STOP_HARD)
1307 CPU_SET_ATOMIC(cpu, &ipi_stop_nmi_pending);
1308
1309 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1310 ipi_send_cpu(cpu, ipi);
1311 }
1312
1313 /*
1314 * send an IPI to all CPUs EXCEPT myself
1315 */
1316 void
ipi_all_but_self(u_int ipi)1317 ipi_all_but_self(u_int ipi)
1318 {
1319 cpuset_t other_cpus;
1320
1321 other_cpus = all_cpus;
1322 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1323 if (IPI_IS_BITMAPED(ipi)) {
1324 ipi_selected(other_cpus, ipi);
1325 return;
1326 }
1327
1328 /*
1329 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1330 * of help in order to understand what is the source.
1331 * Set the mask of receiving CPUs for this purpose.
1332 */
1333 if (ipi == IPI_STOP_HARD)
1334 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &other_cpus);
1335
1336 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1337 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1338 }
1339
1340 int
ipi_nmi_handler(void)1341 ipi_nmi_handler(void)
1342 {
1343 u_int cpuid;
1344
1345 /*
1346 * As long as there is not a simple way to know about a NMI's
1347 * source, if the bitmask for the current CPU is present in
1348 * the global pending bitword an IPI_STOP_HARD has been issued
1349 * and should be handled.
1350 */
1351 cpuid = PCPU_GET(cpuid);
1352 if (!CPU_ISSET(cpuid, &ipi_stop_nmi_pending))
1353 return (1);
1354
1355 CPU_CLR_ATOMIC(cpuid, &ipi_stop_nmi_pending);
1356 cpustop_handler();
1357 return (0);
1358 }
1359
1360 int nmi_kdb_lock;
1361
1362 void
nmi_call_kdb_smp(u_int type,struct trapframe * frame)1363 nmi_call_kdb_smp(u_int type, struct trapframe *frame)
1364 {
1365 int cpu;
1366 bool call_post;
1367
1368 cpu = PCPU_GET(cpuid);
1369 if (atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1)) {
1370 nmi_call_kdb(cpu, type, frame);
1371 call_post = false;
1372 } else {
1373 savectx(&stoppcbs[cpu]);
1374 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1375 while (!atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1))
1376 ia32_pause();
1377 call_post = true;
1378 }
1379 atomic_store_rel_int(&nmi_kdb_lock, 0);
1380 if (call_post)
1381 cpustop_handler_post(cpu);
1382 }
1383
1384 /*
1385 * Handle an IPI_STOP by saving our current context and spinning until we
1386 * are resumed.
1387 */
1388 void
cpustop_handler(void)1389 cpustop_handler(void)
1390 {
1391 u_int cpu;
1392
1393 cpu = PCPU_GET(cpuid);
1394
1395 savectx(&stoppcbs[cpu]);
1396
1397 /* Indicate that we are stopped */
1398 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1399
1400 /* Wait for restart */
1401 while (!CPU_ISSET(cpu, &started_cpus))
1402 ia32_pause();
1403
1404 cpustop_handler_post(cpu);
1405 }
1406
1407 static void
cpustop_handler_post(u_int cpu)1408 cpustop_handler_post(u_int cpu)
1409 {
1410
1411 CPU_CLR_ATOMIC(cpu, &started_cpus);
1412 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1413
1414 /*
1415 * We don't broadcast TLB invalidations to other CPUs when they are
1416 * stopped. Hence, we clear the TLB before resuming.
1417 */
1418 invltlb_glob();
1419
1420 #if defined(__amd64__) && defined(DDB)
1421 amd64_db_resume_dbreg();
1422 #endif
1423
1424 if (cpu == 0 && cpustop_restartfunc != NULL) {
1425 cpustop_restartfunc();
1426 cpustop_restartfunc = NULL;
1427 }
1428 }
1429
1430 /*
1431 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1432 * are resumed.
1433 */
1434 void
cpususpend_handler(void)1435 cpususpend_handler(void)
1436 {
1437 u_int cpu;
1438
1439 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1440
1441 cpu = PCPU_GET(cpuid);
1442 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1443 #ifdef __amd64__
1444 fpususpend(susppcbs[cpu]->sp_fpususpend);
1445 #else
1446 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1447 #endif
1448 /*
1449 * suspended_cpus is cleared shortly after each AP is restarted
1450 * by a Startup IPI, so that the BSP can proceed to restarting
1451 * the next AP.
1452 *
1453 * resuming_cpus gets cleared when the AP completes
1454 * initialization after having been released by the BSP.
1455 * resuming_cpus is probably not the best name for the
1456 * variable, because it is actually a set of processors that
1457 * haven't resumed yet and haven't necessarily started resuming.
1458 *
1459 * Note that suspended_cpus is meaningful only for ACPI suspend
1460 * as it's not really used for Xen suspend since the APs are
1461 * automatically restored to the running state and the correct
1462 * context. For the same reason resumectx is never called in
1463 * that case.
1464 */
1465 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1466 CPU_SET_ATOMIC(cpu, &resuming_cpus);
1467
1468 /*
1469 * Invalidate the cache after setting the global status bits.
1470 * The last AP to set its bit may end up being an Owner of the
1471 * corresponding cache line in MOESI protocol. The AP may be
1472 * stopped before the cache line is written to the main memory.
1473 */
1474 wbinvd();
1475 } else {
1476 #ifdef __amd64__
1477 fpuresume(susppcbs[cpu]->sp_fpususpend);
1478 #else
1479 npxresume(susppcbs[cpu]->sp_fpususpend);
1480 #endif
1481 pmap_init_pat();
1482 initializecpu();
1483 PCPU_SET(switchtime, 0);
1484 PCPU_SET(switchticks, ticks);
1485
1486 /* Indicate that we have restarted and restored the context. */
1487 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1488 }
1489
1490 /* Wait for resume directive */
1491 while (!CPU_ISSET(cpu, &toresume_cpus))
1492 ia32_pause();
1493
1494 /* Re-apply microcode updates. */
1495 ucode_reload();
1496
1497 #ifdef __i386__
1498 /* Finish removing the identity mapping of low memory for this AP. */
1499 invltlb_glob();
1500 #endif
1501
1502 if (cpu_ops.cpu_resume)
1503 cpu_ops.cpu_resume();
1504 #ifdef __amd64__
1505 if (vmm_resume_p)
1506 vmm_resume_p();
1507 #endif
1508
1509 /* Resume MCA and local APIC */
1510 lapic_xapic_mode();
1511 mca_resume();
1512 lapic_setup(0);
1513
1514 /* Indicate that we are resumed */
1515 CPU_CLR_ATOMIC(cpu, &resuming_cpus);
1516 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1517 CPU_CLR_ATOMIC(cpu, &toresume_cpus);
1518 }
1519
1520
1521 void
invlcache_handler(void)1522 invlcache_handler(void)
1523 {
1524 uint32_t generation;
1525
1526 #ifdef COUNT_IPIS
1527 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1528 #endif /* COUNT_IPIS */
1529
1530 /*
1531 * Reading the generation here allows greater parallelism
1532 * since wbinvd is a serializing instruction. Without the
1533 * temporary, we'd wait for wbinvd to complete, then the read
1534 * would execute, then the dependent write, which must then
1535 * complete before return from interrupt.
1536 */
1537 generation = smp_tlb_generation;
1538 wbinvd();
1539 PCPU_SET(smp_tlb_done, generation);
1540 }
1541
1542 /*
1543 * This is called once the rest of the system is up and running and we're
1544 * ready to let the AP's out of the pen.
1545 */
1546 static void
release_aps(void * dummy __unused)1547 release_aps(void *dummy __unused)
1548 {
1549
1550 if (mp_ncpus == 1)
1551 return;
1552 atomic_store_rel_int(&aps_ready, 1);
1553 while (smp_started == 0)
1554 ia32_pause();
1555 }
1556 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1557
1558 #ifdef COUNT_IPIS
1559 /*
1560 * Setup interrupt counters for IPI handlers.
1561 */
1562 static void
mp_ipi_intrcnt(void * dummy)1563 mp_ipi_intrcnt(void *dummy)
1564 {
1565 char buf[64];
1566 int i;
1567
1568 CPU_FOREACH(i) {
1569 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1570 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1571 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1572 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1573 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1574 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1575 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1576 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1577 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1578 intrcnt_add(buf, &ipi_preempt_counts[i]);
1579 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1580 intrcnt_add(buf, &ipi_ast_counts[i]);
1581 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1582 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1583 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1584 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1585 }
1586 }
1587 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1588 #endif
1589
1590 /*
1591 * Flush the TLB on other CPU's
1592 */
1593
1594 /* Variables needed for SMP tlb shootdown. */
1595 vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
1596 pmap_t smp_tlb_pmap;
1597 volatile uint32_t smp_tlb_generation;
1598
1599 #ifdef __amd64__
1600 #define read_eflags() read_rflags()
1601 #endif
1602
1603 static void
smp_targeted_tlb_shootdown(cpuset_t mask,u_int vector,pmap_t pmap,vm_offset_t addr1,vm_offset_t addr2)1604 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1605 vm_offset_t addr1, vm_offset_t addr2)
1606 {
1607 cpuset_t other_cpus;
1608 volatile uint32_t *p_cpudone;
1609 uint32_t generation;
1610 int cpu;
1611
1612 /* It is not necessary to signal other CPUs while in the debugger. */
1613 if (kdb_active || panicstr != NULL)
1614 return;
1615
1616 /*
1617 * Check for other cpus. Return if none.
1618 */
1619 if (CPU_ISFULLSET(&mask)) {
1620 if (mp_ncpus <= 1)
1621 return;
1622 } else {
1623 CPU_CLR(PCPU_GET(cpuid), &mask);
1624 if (CPU_EMPTY(&mask))
1625 return;
1626 }
1627
1628 if (!(read_eflags() & PSL_I))
1629 panic("%s: interrupts disabled", __func__);
1630 mtx_lock_spin(&smp_ipi_mtx);
1631 smp_tlb_addr1 = addr1;
1632 smp_tlb_addr2 = addr2;
1633 smp_tlb_pmap = pmap;
1634 generation = ++smp_tlb_generation;
1635 if (CPU_ISFULLSET(&mask)) {
1636 ipi_all_but_self(vector);
1637 other_cpus = all_cpus;
1638 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1639 } else {
1640 other_cpus = mask;
1641 while ((cpu = CPU_FFS(&mask)) != 0) {
1642 cpu--;
1643 CPU_CLR(cpu, &mask);
1644 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1645 cpu, vector);
1646 ipi_send_cpu(cpu, vector);
1647 }
1648 }
1649 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
1650 cpu--;
1651 CPU_CLR(cpu, &other_cpus);
1652 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
1653 while (*p_cpudone != generation)
1654 ia32_pause();
1655 }
1656 mtx_unlock_spin(&smp_ipi_mtx);
1657 }
1658
1659 void
smp_masked_invltlb(cpuset_t mask,pmap_t pmap)1660 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1661 {
1662
1663 if (smp_started) {
1664 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1665 #ifdef COUNT_XINVLTLB_HITS
1666 ipi_global++;
1667 #endif
1668 }
1669 }
1670
1671 void
smp_masked_invlpg(cpuset_t mask,vm_offset_t addr,pmap_t pmap)1672 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, pmap_t pmap)
1673 {
1674
1675 if (smp_started) {
1676 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0);
1677 #ifdef COUNT_XINVLTLB_HITS
1678 ipi_page++;
1679 #endif
1680 }
1681 }
1682
1683 void
smp_masked_invlpg_range(cpuset_t mask,vm_offset_t addr1,vm_offset_t addr2,pmap_t pmap)1684 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2,
1685 pmap_t pmap)
1686 {
1687
1688 if (smp_started) {
1689 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap,
1690 addr1, addr2);
1691 #ifdef COUNT_XINVLTLB_HITS
1692 ipi_range++;
1693 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1694 #endif
1695 }
1696 }
1697
1698 void
smp_cache_flush(void)1699 smp_cache_flush(void)
1700 {
1701
1702 if (smp_started) {
1703 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
1704 0, 0);
1705 }
1706 }
1707
1708 /*
1709 * Handlers for TLB related IPIs
1710 */
1711 void
invltlb_handler(void)1712 invltlb_handler(void)
1713 {
1714 uint32_t generation;
1715
1716 #ifdef COUNT_XINVLTLB_HITS
1717 xhits_gbl[PCPU_GET(cpuid)]++;
1718 #endif /* COUNT_XINVLTLB_HITS */
1719 #ifdef COUNT_IPIS
1720 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1721 #endif /* COUNT_IPIS */
1722
1723 /*
1724 * Reading the generation here allows greater parallelism
1725 * since invalidating the TLB is a serializing operation.
1726 */
1727 generation = smp_tlb_generation;
1728 if (smp_tlb_pmap == kernel_pmap)
1729 invltlb_glob();
1730 #ifdef __amd64__
1731 else
1732 invltlb();
1733 #endif
1734 PCPU_SET(smp_tlb_done, generation);
1735 }
1736
1737 void
invlpg_handler(void)1738 invlpg_handler(void)
1739 {
1740 uint32_t generation;
1741
1742 #ifdef COUNT_XINVLTLB_HITS
1743 xhits_pg[PCPU_GET(cpuid)]++;
1744 #endif /* COUNT_XINVLTLB_HITS */
1745 #ifdef COUNT_IPIS
1746 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1747 #endif /* COUNT_IPIS */
1748
1749 generation = smp_tlb_generation; /* Overlap with serialization */
1750 #ifdef __i386__
1751 if (smp_tlb_pmap == kernel_pmap)
1752 #endif
1753 invlpg(smp_tlb_addr1);
1754 PCPU_SET(smp_tlb_done, generation);
1755 }
1756
1757 void
invlrng_handler(void)1758 invlrng_handler(void)
1759 {
1760 vm_offset_t addr, addr2;
1761 uint32_t generation;
1762
1763 #ifdef COUNT_XINVLTLB_HITS
1764 xhits_rng[PCPU_GET(cpuid)]++;
1765 #endif /* COUNT_XINVLTLB_HITS */
1766 #ifdef COUNT_IPIS
1767 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1768 #endif /* COUNT_IPIS */
1769
1770 addr = smp_tlb_addr1;
1771 addr2 = smp_tlb_addr2;
1772 generation = smp_tlb_generation; /* Overlap with serialization */
1773 #ifdef __i386__
1774 if (smp_tlb_pmap == kernel_pmap)
1775 #endif
1776 do {
1777 invlpg(addr);
1778 addr += PAGE_SIZE;
1779 } while (addr < addr2);
1780
1781 PCPU_SET(smp_tlb_done, generation);
1782 }
1783