1 /*-
2 * Copyright (C) 2012 Intel Corporation
3 * All rights reserved.
4 * Copyright (C) 2018 Alexander Motin <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include "opt_ddb.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/domainset.h>
38 #include <sys/fail.h>
39 #include <sys/ioccom.h>
40 #include <sys/kernel.h>
41 #include <sys/ktr.h>
42 #include <sys/lock.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/rman.h>
47 #include <sys/sbuf.h>
48 #include <sys/smp.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
51 #include <sys/time.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/stdarg.h>
57
58 #ifdef DDB
59 #include <ddb/ddb.h>
60 #endif
61
62 #include "ioat.h"
63 #include "ioat_hw.h"
64 #include "ioat_internal.h"
65
66 #ifndef BUS_SPACE_MAXADDR_40BIT
67 #define BUS_SPACE_MAXADDR_40BIT MIN(BUS_SPACE_MAXADDR, 0xFFFFFFFFFFULL)
68 #endif
69 #ifndef BUS_SPACE_MAXADDR_46BIT
70 #define BUS_SPACE_MAXADDR_46BIT MIN(BUS_SPACE_MAXADDR, 0x3FFFFFFFFFFFULL)
71 #endif
72
73 static int ioat_modevent(module_t mod, int type, void *data);
74 static int ioat_probe(device_t device);
75 static int ioat_attach(device_t device);
76 static int ioat_detach(device_t device);
77 static int ioat_setup_intr(struct ioat_softc *ioat);
78 static int ioat_teardown_intr(struct ioat_softc *ioat);
79 static int ioat3_attach(device_t device);
80 static int ioat_start_channel(struct ioat_softc *ioat);
81 static int ioat_map_pci_bar(struct ioat_softc *ioat);
82 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg,
83 int error);
84 static void ioat_interrupt_handler(void *arg);
85 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat);
86 static int chanerr_to_errno(uint32_t);
87 static void ioat_process_events(struct ioat_softc *ioat, boolean_t intr);
88 static inline uint32_t ioat_get_active(struct ioat_softc *ioat);
89 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat);
90 static void ioat_free_ring(struct ioat_softc *, uint32_t size,
91 struct ioat_descriptor *);
92 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags);
93 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *,
94 uint32_t index);
95 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *,
96 uint32_t index);
97 static void ioat_halted_debug(struct ioat_softc *, uint32_t);
98 static void ioat_poll_timer_callback(void *arg);
99 static void dump_descriptor(void *hw_desc);
100 static void ioat_submit_single(struct ioat_softc *ioat);
101 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg,
102 int error);
103 static int ioat_reset_hw(struct ioat_softc *ioat);
104 static void ioat_reset_hw_task(void *, int);
105 static void ioat_setup_sysctl(device_t device);
106 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS);
107 static void ioat_get(struct ioat_softc *);
108 static void ioat_put(struct ioat_softc *);
109 static void ioat_drain_locked(struct ioat_softc *);
110
111 #define ioat_log_message(v, ...) do { \
112 if ((v) <= g_ioat_debug_level) { \
113 device_printf(ioat->device, __VA_ARGS__); \
114 } \
115 } while (0)
116
117 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations");
118 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
119 "ioat node");
120
121 static int g_force_legacy_interrupts;
122 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN,
123 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled");
124
125 int g_ioat_debug_level = 0;
126 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level,
127 0, "Set log level (0-3) for ioat(4). Higher is more verbose.");
128
129 unsigned g_ioat_ring_order = 13;
130 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order,
131 0, "Set IOAT ring order. (1 << this) == ring size.");
132
133 /*
134 * OS <-> Driver interface structures
135 */
136 static device_method_t ioat_pci_methods[] = {
137 /* Device interface */
138 DEVMETHOD(device_probe, ioat_probe),
139 DEVMETHOD(device_attach, ioat_attach),
140 DEVMETHOD(device_detach, ioat_detach),
141 DEVMETHOD_END
142 };
143
144 static driver_t ioat_pci_driver = {
145 "ioat",
146 ioat_pci_methods,
147 sizeof(struct ioat_softc),
148 };
149
150 static devclass_t ioat_devclass;
151 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, ioat_modevent, NULL);
152 MODULE_VERSION(ioat, 1);
153
154 /*
155 * Private data structures
156 */
157 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS];
158 static unsigned ioat_channel_index = 0;
159 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0,
160 "Number of IOAT channels attached");
161 static struct mtx ioat_list_mtx;
162 MTX_SYSINIT(ioat_list_mtx, &ioat_list_mtx, "ioat list mtx", MTX_DEF);
163
164 static struct _pcsid
165 {
166 u_int32_t type;
167 const char *desc;
168 } pci_ids[] = {
169 { 0x34308086, "TBG IOAT Ch0" },
170 { 0x34318086, "TBG IOAT Ch1" },
171 { 0x34328086, "TBG IOAT Ch2" },
172 { 0x34338086, "TBG IOAT Ch3" },
173 { 0x34298086, "TBG IOAT Ch4" },
174 { 0x342a8086, "TBG IOAT Ch5" },
175 { 0x342b8086, "TBG IOAT Ch6" },
176 { 0x342c8086, "TBG IOAT Ch7" },
177
178 { 0x37108086, "JSF IOAT Ch0" },
179 { 0x37118086, "JSF IOAT Ch1" },
180 { 0x37128086, "JSF IOAT Ch2" },
181 { 0x37138086, "JSF IOAT Ch3" },
182 { 0x37148086, "JSF IOAT Ch4" },
183 { 0x37158086, "JSF IOAT Ch5" },
184 { 0x37168086, "JSF IOAT Ch6" },
185 { 0x37178086, "JSF IOAT Ch7" },
186 { 0x37188086, "JSF IOAT Ch0 (RAID)" },
187 { 0x37198086, "JSF IOAT Ch1 (RAID)" },
188
189 { 0x3c208086, "SNB IOAT Ch0" },
190 { 0x3c218086, "SNB IOAT Ch1" },
191 { 0x3c228086, "SNB IOAT Ch2" },
192 { 0x3c238086, "SNB IOAT Ch3" },
193 { 0x3c248086, "SNB IOAT Ch4" },
194 { 0x3c258086, "SNB IOAT Ch5" },
195 { 0x3c268086, "SNB IOAT Ch6" },
196 { 0x3c278086, "SNB IOAT Ch7" },
197 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" },
198 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" },
199
200 { 0x0e208086, "IVB IOAT Ch0" },
201 { 0x0e218086, "IVB IOAT Ch1" },
202 { 0x0e228086, "IVB IOAT Ch2" },
203 { 0x0e238086, "IVB IOAT Ch3" },
204 { 0x0e248086, "IVB IOAT Ch4" },
205 { 0x0e258086, "IVB IOAT Ch5" },
206 { 0x0e268086, "IVB IOAT Ch6" },
207 { 0x0e278086, "IVB IOAT Ch7" },
208 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" },
209 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" },
210
211 { 0x2f208086, "HSW IOAT Ch0" },
212 { 0x2f218086, "HSW IOAT Ch1" },
213 { 0x2f228086, "HSW IOAT Ch2" },
214 { 0x2f238086, "HSW IOAT Ch3" },
215 { 0x2f248086, "HSW IOAT Ch4" },
216 { 0x2f258086, "HSW IOAT Ch5" },
217 { 0x2f268086, "HSW IOAT Ch6" },
218 { 0x2f278086, "HSW IOAT Ch7" },
219 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" },
220 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" },
221
222 { 0x0c508086, "BWD IOAT Ch0" },
223 { 0x0c518086, "BWD IOAT Ch1" },
224 { 0x0c528086, "BWD IOAT Ch2" },
225 { 0x0c538086, "BWD IOAT Ch3" },
226
227 { 0x6f508086, "BDXDE IOAT Ch0" },
228 { 0x6f518086, "BDXDE IOAT Ch1" },
229 { 0x6f528086, "BDXDE IOAT Ch2" },
230 { 0x6f538086, "BDXDE IOAT Ch3" },
231
232 { 0x6f208086, "BDX IOAT Ch0" },
233 { 0x6f218086, "BDX IOAT Ch1" },
234 { 0x6f228086, "BDX IOAT Ch2" },
235 { 0x6f238086, "BDX IOAT Ch3" },
236 { 0x6f248086, "BDX IOAT Ch4" },
237 { 0x6f258086, "BDX IOAT Ch5" },
238 { 0x6f268086, "BDX IOAT Ch6" },
239 { 0x6f278086, "BDX IOAT Ch7" },
240 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" },
241 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" },
242
243 { 0x20218086, "SKX IOAT" },
244 };
245
246 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids,
247 nitems(pci_ids));
248
249 /*
250 * OS <-> Driver linkage functions
251 */
252 static int
ioat_modevent(module_t mod __unused,int type,void * data __unused)253 ioat_modevent(module_t mod __unused, int type, void *data __unused)
254 {
255 switch(type) {
256 case MOD_LOAD:
257 break;
258
259 case MOD_UNLOAD:
260 ioat_test_detach();
261 break;
262
263 case MOD_SHUTDOWN:
264 break;
265
266 default:
267 return (EOPNOTSUPP);
268 }
269
270 return (0);
271 }
272
273 static int
ioat_probe(device_t device)274 ioat_probe(device_t device)
275 {
276 struct _pcsid *ep;
277 u_int32_t type;
278
279 type = pci_get_devid(device);
280 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) {
281 if (ep->type == type) {
282 device_set_desc(device, ep->desc);
283 return (0);
284 }
285 }
286 return (ENXIO);
287 }
288
289 static int
ioat_attach(device_t device)290 ioat_attach(device_t device)
291 {
292 struct ioat_softc *ioat;
293 int error, i;
294
295 ioat = DEVICE2SOFTC(device);
296 ioat->device = device;
297 if (bus_get_domain(device, &ioat->domain) != 0)
298 ioat->domain = 0;
299 ioat->cpu = CPU_FFS(&cpuset_domain[ioat->domain]) - 1;
300 if (ioat->cpu < 0)
301 ioat->cpu = CPU_FIRST();
302
303 error = ioat_map_pci_bar(ioat);
304 if (error != 0)
305 goto err;
306
307 ioat->version = ioat_read_cbver(ioat);
308 if (ioat->version < IOAT_VER_3_0) {
309 error = ENODEV;
310 goto err;
311 }
312
313 error = ioat3_attach(device);
314 if (error != 0)
315 goto err;
316
317 error = pci_enable_busmaster(device);
318 if (error != 0)
319 goto err;
320
321 error = ioat_setup_intr(ioat);
322 if (error != 0)
323 goto err;
324
325 error = ioat_reset_hw(ioat);
326 if (error != 0)
327 goto err;
328
329 ioat_process_events(ioat, FALSE);
330 ioat_setup_sysctl(device);
331
332 mtx_lock(&ioat_list_mtx);
333 for (i = 0; i < IOAT_MAX_CHANNELS; i++) {
334 if (ioat_channel[i] == NULL)
335 break;
336 }
337 if (i >= IOAT_MAX_CHANNELS) {
338 mtx_unlock(&ioat_list_mtx);
339 device_printf(device, "Too many I/OAT devices in system\n");
340 error = ENXIO;
341 goto err;
342 }
343 ioat->chan_idx = i;
344 ioat_channel[i] = ioat;
345 if (i >= ioat_channel_index)
346 ioat_channel_index = i + 1;
347 mtx_unlock(&ioat_list_mtx);
348
349 ioat_test_attach();
350
351 err:
352 if (error != 0)
353 ioat_detach(device);
354 return (error);
355 }
356
357 static inline int
ioat_bus_dmamap_destroy(struct ioat_softc * ioat,const char * func,bus_dma_tag_t dmat,bus_dmamap_t map)358 ioat_bus_dmamap_destroy(struct ioat_softc *ioat, const char *func,
359 bus_dma_tag_t dmat, bus_dmamap_t map)
360 {
361 int error;
362
363 error = bus_dmamap_destroy(dmat, map);
364 if (error != 0) {
365 ioat_log_message(0,
366 "%s: bus_dmamap_destroy failed %d\n", func, error);
367 }
368
369 return (error);
370 }
371
372 static int
ioat_detach(device_t device)373 ioat_detach(device_t device)
374 {
375 struct ioat_softc *ioat;
376 int i, error;
377
378 ioat = DEVICE2SOFTC(device);
379
380 mtx_lock(&ioat_list_mtx);
381 ioat_channel[ioat->chan_idx] = NULL;
382 while (ioat_channel_index > 0 &&
383 ioat_channel[ioat_channel_index - 1] == NULL)
384 ioat_channel_index--;
385 mtx_unlock(&ioat_list_mtx);
386
387 taskqueue_drain(taskqueue_thread, &ioat->reset_task);
388
389 mtx_lock(&ioat->submit_lock);
390 ioat->quiescing = TRUE;
391 ioat->destroying = TRUE;
392 wakeup(&ioat->quiescing);
393 wakeup(&ioat->resetting);
394
395 ioat_drain_locked(ioat);
396 mtx_unlock(&ioat->submit_lock);
397 mtx_lock(&ioat->cleanup_lock);
398 while (ioat_get_active(ioat) > 0)
399 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1);
400 mtx_unlock(&ioat->cleanup_lock);
401
402 ioat_teardown_intr(ioat);
403 callout_drain(&ioat->poll_timer);
404
405 pci_disable_busmaster(device);
406
407 if (ioat->pci_resource != NULL)
408 bus_release_resource(device, SYS_RES_MEMORY,
409 ioat->pci_resource_id, ioat->pci_resource);
410
411 if (ioat->data_tag != NULL) {
412 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
413 error = ioat_bus_dmamap_destroy(ioat, __func__,
414 ioat->data_tag, ioat->ring[i].src_dmamap);
415 if (error != 0)
416 return (error);
417 }
418 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
419 error = ioat_bus_dmamap_destroy(ioat, __func__,
420 ioat->data_tag, ioat->ring[i].dst_dmamap);
421 if (error != 0)
422 return (error);
423 }
424
425 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
426 error = ioat_bus_dmamap_destroy(ioat, __func__,
427 ioat->data_tag, ioat->ring[i].src2_dmamap);
428 if (error != 0)
429 return (error);
430 }
431 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
432 error = ioat_bus_dmamap_destroy(ioat, __func__,
433 ioat->data_tag, ioat->ring[i].dst2_dmamap);
434 if (error != 0)
435 return (error);
436 }
437
438 bus_dma_tag_destroy(ioat->data_tag);
439 }
440
441 if (ioat->ring != NULL)
442 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring);
443
444 if (ioat->comp_update != NULL) {
445 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map);
446 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update,
447 ioat->comp_update_map);
448 bus_dma_tag_destroy(ioat->comp_update_tag);
449 }
450
451 if (ioat->hw_desc_ring != NULL) {
452 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map);
453 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring,
454 ioat->hw_desc_map);
455 bus_dma_tag_destroy(ioat->hw_desc_tag);
456 }
457
458 return (0);
459 }
460
461 static int
ioat_teardown_intr(struct ioat_softc * ioat)462 ioat_teardown_intr(struct ioat_softc *ioat)
463 {
464
465 if (ioat->tag != NULL)
466 bus_teardown_intr(ioat->device, ioat->res, ioat->tag);
467
468 if (ioat->res != NULL)
469 bus_release_resource(ioat->device, SYS_RES_IRQ,
470 rman_get_rid(ioat->res), ioat->res);
471
472 pci_release_msi(ioat->device);
473 return (0);
474 }
475
476 static int
ioat_start_channel(struct ioat_softc * ioat)477 ioat_start_channel(struct ioat_softc *ioat)
478 {
479 struct ioat_dma_hw_descriptor *hw_desc;
480 struct ioat_descriptor *desc;
481 struct bus_dmadesc *dmadesc;
482 uint64_t status;
483 uint32_t chanerr;
484 int i;
485
486 ioat_acquire(&ioat->dmaengine);
487
488 /* Submit 'NULL' operation manually to avoid quiescing flag */
489 desc = ioat_get_ring_entry(ioat, ioat->head);
490 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma;
491 dmadesc = &desc->bus_dmadesc;
492
493 dmadesc->callback_fn = NULL;
494 dmadesc->callback_arg = NULL;
495
496 hw_desc->u.control_raw = 0;
497 hw_desc->u.control_generic.op = IOAT_OP_COPY;
498 hw_desc->u.control_generic.completion_update = 1;
499 hw_desc->size = 8;
500 hw_desc->src_addr = 0;
501 hw_desc->dest_addr = 0;
502 hw_desc->u.control.null = 1;
503
504 ioat_submit_single(ioat);
505 ioat_release(&ioat->dmaengine);
506
507 for (i = 0; i < 100; i++) {
508 DELAY(1);
509 status = ioat_get_chansts(ioat);
510 if (is_ioat_idle(status))
511 return (0);
512 }
513
514 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
515 ioat_log_message(0, "could not start channel: "
516 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr,
517 IOAT_CHANERR_STR);
518 return (ENXIO);
519 }
520
521 /*
522 * Initialize Hardware
523 */
524 static int
ioat3_attach(device_t device)525 ioat3_attach(device_t device)
526 {
527 struct ioat_softc *ioat;
528 struct ioat_descriptor *ring;
529 struct ioat_dma_hw_descriptor *dma_hw_desc;
530 void *hw_desc;
531 bus_addr_t lowaddr;
532 size_t ringsz;
533 int i, num_descriptors;
534 int error;
535 uint8_t xfercap;
536
537 error = 0;
538 ioat = DEVICE2SOFTC(device);
539 ioat->capabilities = ioat_read_dmacapability(ioat);
540
541 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities,
542 IOAT_DMACAP_STR);
543
544 xfercap = ioat_read_xfercap(ioat);
545 ioat->max_xfer_size = 1 << xfercap;
546
547 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) &
548 IOAT_INTRDELAY_SUPPORTED) != 0;
549 if (ioat->intrdelay_supported)
550 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK;
551
552 /* TODO: need to check DCA here if we ever do XOR/PQ */
553
554 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF);
555 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF);
556 callout_init(&ioat->poll_timer, 1);
557 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat);
558
559 /* Establish lock order for Witness */
560 mtx_lock(&ioat->cleanup_lock);
561 mtx_lock(&ioat->submit_lock);
562 mtx_unlock(&ioat->submit_lock);
563 mtx_unlock(&ioat->cleanup_lock);
564
565 ioat->is_submitter_processing = FALSE;
566
567 if (ioat->version >= IOAT_VER_3_3)
568 lowaddr = BUS_SPACE_MAXADDR_48BIT;
569 else if (ioat->version >= IOAT_VER_3_2)
570 lowaddr = BUS_SPACE_MAXADDR_46BIT;
571 else
572 lowaddr = BUS_SPACE_MAXADDR_40BIT;
573
574 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
575 sizeof(uint64_t), 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
576 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
577 &ioat->comp_update_tag);
578 if (error != 0)
579 return (error);
580
581 error = bus_dmamem_alloc(ioat->comp_update_tag,
582 (void **)&ioat->comp_update, BUS_DMA_ZERO | BUS_DMA_WAITOK,
583 &ioat->comp_update_map);
584 if (error != 0)
585 return (error);
586
587 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
588 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
589 BUS_DMA_NOWAIT);
590 if (error != 0)
591 return (error);
592
593 ioat->ring_size_order = g_ioat_ring_order;
594 num_descriptors = 1 << ioat->ring_size_order;
595 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors;
596
597 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
598 2 * 1024 * 1024, 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
599 ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag);
600 if (error != 0)
601 return (error);
602
603 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc,
604 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map);
605 if (error != 0)
606 return (error);
607
608 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc,
609 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_NOWAIT);
610 if (error)
611 return (error);
612
613 ioat->hw_desc_ring = hw_desc;
614
615 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
616 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
617 ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL,
618 &ioat->data_tag);
619 if (error != 0)
620 return (error);
621 ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT,
622 DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK);
623
624 ring = ioat->ring;
625 for (i = 0; i < num_descriptors; i++) {
626 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc));
627 ring[i].id = i;
628 error = bus_dmamap_create(ioat->data_tag, 0,
629 &ring[i].src_dmamap);
630 if (error != 0) {
631 ioat_log_message(0,
632 "%s: bus_dmamap_create failed %d\n", __func__,
633 error);
634 return (error);
635 }
636 error = bus_dmamap_create(ioat->data_tag, 0,
637 &ring[i].dst_dmamap);
638 if (error != 0) {
639 ioat_log_message(0,
640 "%s: bus_dmamap_create failed %d\n", __func__,
641 error);
642 return (error);
643 }
644 error = bus_dmamap_create(ioat->data_tag, 0,
645 &ring[i].src2_dmamap);
646 if (error != 0) {
647 ioat_log_message(0,
648 "%s: bus_dmamap_create failed %d\n", __func__,
649 error);
650 return (error);
651 }
652 error = bus_dmamap_create(ioat->data_tag, 0,
653 &ring[i].dst2_dmamap);
654 if (error != 0) {
655 ioat_log_message(0,
656 "%s: bus_dmamap_create failed %d\n", __func__,
657 error);
658 return (error);
659 }
660 }
661
662 for (i = 0; i < num_descriptors; i++) {
663 dma_hw_desc = &ioat->hw_desc_ring[i].dma;
664 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1);
665 }
666
667 ioat->tail = ioat->head = 0;
668 *ioat->comp_update = ioat->last_seen =
669 RING_PHYS_ADDR(ioat, ioat->tail - 1);
670 return (0);
671 }
672
673 static int
ioat_map_pci_bar(struct ioat_softc * ioat)674 ioat_map_pci_bar(struct ioat_softc *ioat)
675 {
676
677 ioat->pci_resource_id = PCIR_BAR(0);
678 ioat->pci_resource = bus_alloc_resource_any(ioat->device,
679 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE);
680
681 if (ioat->pci_resource == NULL) {
682 ioat_log_message(0, "unable to allocate pci resource\n");
683 return (ENODEV);
684 }
685
686 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource);
687 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource);
688 return (0);
689 }
690
691 static void
ioat_comp_update_map(void * arg,bus_dma_segment_t * seg,int nseg,int error)692 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
693 {
694 struct ioat_softc *ioat = arg;
695
696 KASSERT(error == 0, ("%s: error:%d", __func__, error));
697 ioat->comp_update_bus_addr = seg[0].ds_addr;
698 }
699
700 static void
ioat_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)701 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
702 {
703 bus_addr_t *baddr;
704
705 KASSERT(error == 0, ("%s: error:%d", __func__, error));
706 baddr = arg;
707 *baddr = segs->ds_addr;
708 }
709
710 /*
711 * Interrupt setup and handlers
712 */
713 static int
ioat_setup_intr(struct ioat_softc * ioat)714 ioat_setup_intr(struct ioat_softc *ioat)
715 {
716 uint32_t num_vectors;
717 int error;
718 boolean_t use_msix;
719 boolean_t force_legacy_interrupts;
720
721 use_msix = FALSE;
722 force_legacy_interrupts = FALSE;
723
724 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) {
725 num_vectors = 1;
726 pci_alloc_msix(ioat->device, &num_vectors);
727 if (num_vectors == 1)
728 use_msix = TRUE;
729 }
730
731 if (use_msix) {
732 ioat->rid = 1;
733 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
734 &ioat->rid, RF_ACTIVE);
735 } else {
736 ioat->rid = 0;
737 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
738 &ioat->rid, RF_SHAREABLE | RF_ACTIVE);
739 }
740 if (ioat->res == NULL) {
741 ioat_log_message(0, "bus_alloc_resource failed\n");
742 return (ENOMEM);
743 }
744
745 ioat->tag = NULL;
746 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE |
747 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag);
748 if (error != 0) {
749 ioat_log_message(0, "bus_setup_intr failed\n");
750 return (error);
751 }
752
753 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN);
754 return (0);
755 }
756
757 static boolean_t
ioat_model_resets_msix(struct ioat_softc * ioat)758 ioat_model_resets_msix(struct ioat_softc *ioat)
759 {
760 u_int32_t pciid;
761
762 pciid = pci_get_devid(ioat->device);
763 switch (pciid) {
764 /* BWD: */
765 case 0x0c508086:
766 case 0x0c518086:
767 case 0x0c528086:
768 case 0x0c538086:
769 /* BDXDE: */
770 case 0x6f508086:
771 case 0x6f518086:
772 case 0x6f528086:
773 case 0x6f538086:
774 return (TRUE);
775 }
776
777 return (FALSE);
778 }
779
780 static void
ioat_interrupt_handler(void * arg)781 ioat_interrupt_handler(void *arg)
782 {
783 struct ioat_softc *ioat = arg;
784
785 ioat->stats.interrupts++;
786 ioat_process_events(ioat, TRUE);
787 }
788
789 static int
chanerr_to_errno(uint32_t chanerr)790 chanerr_to_errno(uint32_t chanerr)
791 {
792
793 if (chanerr == 0)
794 return (0);
795 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0)
796 return (EFAULT);
797 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0)
798 return (EIO);
799 /* This one is probably our fault: */
800 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0)
801 return (EIO);
802 return (EIO);
803 }
804
805 static void
ioat_process_events(struct ioat_softc * ioat,boolean_t intr)806 ioat_process_events(struct ioat_softc *ioat, boolean_t intr)
807 {
808 struct ioat_descriptor *desc;
809 struct bus_dmadesc *dmadesc;
810 uint64_t comp_update, status;
811 uint32_t completed, chanerr;
812 int error;
813
814 if (intr) {
815 mtx_lock(&ioat->cleanup_lock);
816 } else {
817 if (!mtx_trylock(&ioat->cleanup_lock))
818 return;
819 }
820
821 /*
822 * Don't run while the hardware is being reset. Reset is responsible
823 * for blocking new work and draining & completing existing work, so
824 * there is nothing to do until new work is queued after reset anyway.
825 */
826 if (ioat->resetting_cleanup) {
827 mtx_unlock(&ioat->cleanup_lock);
828 return;
829 }
830
831 completed = 0;
832 comp_update = *ioat->comp_update;
833 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK;
834
835 if (status < ioat->hw_desc_bus_addr ||
836 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) *
837 sizeof(struct ioat_generic_hw_descriptor))
838 panic("Bogus completion address %jx (channel %u)",
839 (uintmax_t)status, ioat->chan_idx);
840
841 if (status == ioat->last_seen) {
842 /*
843 * If we landed in process_events and nothing has been
844 * completed, check for a timeout due to channel halt.
845 */
846 goto out;
847 }
848 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx",
849 __func__, ioat->chan_idx, comp_update, ioat->last_seen);
850
851 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) {
852 desc = ioat_get_ring_entry(ioat, ioat->tail);
853 dmadesc = &desc->bus_dmadesc;
854 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)",
855 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
856 dmadesc->callback_arg);
857
858 bus_dmamap_unload(ioat->data_tag, desc->src_dmamap);
859 bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap);
860 bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap);
861 bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap);
862
863 if (dmadesc->callback_fn != NULL)
864 dmadesc->callback_fn(dmadesc->callback_arg, 0);
865
866 completed++;
867 ioat->tail++;
868 }
869 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
870 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
871
872 if (completed != 0) {
873 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1);
874 ioat->stats.descriptors_processed += completed;
875 wakeup(&ioat->tail);
876 }
877
878 out:
879 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
880 mtx_unlock(&ioat->cleanup_lock);
881
882 /*
883 * The device doesn't seem to reliably push suspend/halt statuses to
884 * the channel completion memory address, so poll the device register
885 * here. For performance reasons skip it on interrupts, do it only
886 * on much more rare polling events.
887 */
888 if (!intr)
889 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
890 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update))
891 return;
892
893 ioat->stats.channel_halts++;
894
895 /*
896 * Fatal programming error on this DMA channel. Flush any outstanding
897 * work with error status and restart the engine.
898 */
899 mtx_lock(&ioat->submit_lock);
900 ioat->quiescing = TRUE;
901 mtx_unlock(&ioat->submit_lock);
902
903 /*
904 * This is safe to do here because the submit queue is quiesced. We
905 * know that we will drain all outstanding events, so ioat_reset_hw
906 * can't deadlock. It is necessary to protect other ioat_process_event
907 * threads from racing ioat_reset_hw, reading an indeterminate hw
908 * state, and attempting to continue issuing completions.
909 */
910 mtx_lock(&ioat->cleanup_lock);
911 ioat->resetting_cleanup = TRUE;
912
913 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
914 if (1 <= g_ioat_debug_level)
915 ioat_halted_debug(ioat, chanerr);
916 ioat->stats.last_halt_chanerr = chanerr;
917
918 while (ioat_get_active(ioat) > 0) {
919 desc = ioat_get_ring_entry(ioat, ioat->tail);
920 dmadesc = &desc->bus_dmadesc;
921 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)",
922 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
923 dmadesc->callback_arg);
924
925 if (dmadesc->callback_fn != NULL)
926 dmadesc->callback_fn(dmadesc->callback_arg,
927 chanerr_to_errno(chanerr));
928
929 ioat->tail++;
930 ioat->stats.descriptors_processed++;
931 ioat->stats.descriptors_error++;
932 }
933 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
934 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
935
936 /* Clear error status */
937 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
938
939 mtx_unlock(&ioat->cleanup_lock);
940
941 ioat_log_message(0, "Resetting channel to recover from error\n");
942 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task);
943 KASSERT(error == 0,
944 ("%s: taskqueue_enqueue failed: %d", __func__, error));
945 }
946
947 static void
ioat_reset_hw_task(void * ctx,int pending __unused)948 ioat_reset_hw_task(void *ctx, int pending __unused)
949 {
950 struct ioat_softc *ioat;
951 int error;
952
953 ioat = ctx;
954 ioat_log_message(1, "%s: Resetting channel\n", __func__);
955
956 error = ioat_reset_hw(ioat);
957 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error));
958 (void)error;
959 }
960
961 /*
962 * User API functions
963 */
964 unsigned
ioat_get_nchannels(void)965 ioat_get_nchannels(void)
966 {
967
968 return (ioat_channel_index);
969 }
970
971 bus_dmaengine_t
ioat_get_dmaengine(uint32_t index,int flags)972 ioat_get_dmaengine(uint32_t index, int flags)
973 {
974 struct ioat_softc *ioat;
975
976 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0,
977 ("invalid flags: 0x%08x", flags));
978 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK),
979 ("invalid wait | nowait"));
980
981 mtx_lock(&ioat_list_mtx);
982 if (index >= ioat_channel_index ||
983 (ioat = ioat_channel[index]) == NULL) {
984 mtx_unlock(&ioat_list_mtx);
985 return (NULL);
986 }
987 mtx_lock(&ioat->submit_lock);
988 mtx_unlock(&ioat_list_mtx);
989
990 if (ioat->destroying) {
991 mtx_unlock(&ioat->submit_lock);
992 return (NULL);
993 }
994
995 ioat_get(ioat);
996 if (ioat->quiescing) {
997 if ((flags & M_NOWAIT) != 0) {
998 ioat_put(ioat);
999 mtx_unlock(&ioat->submit_lock);
1000 return (NULL);
1001 }
1002
1003 while (ioat->quiescing && !ioat->destroying)
1004 msleep(&ioat->quiescing, &ioat->submit_lock, 0, "getdma", 0);
1005
1006 if (ioat->destroying) {
1007 ioat_put(ioat);
1008 mtx_unlock(&ioat->submit_lock);
1009 return (NULL);
1010 }
1011 }
1012 mtx_unlock(&ioat->submit_lock);
1013 return (&ioat->dmaengine);
1014 }
1015
1016 void
ioat_put_dmaengine(bus_dmaengine_t dmaengine)1017 ioat_put_dmaengine(bus_dmaengine_t dmaengine)
1018 {
1019 struct ioat_softc *ioat;
1020
1021 ioat = to_ioat_softc(dmaengine);
1022 mtx_lock(&ioat->submit_lock);
1023 ioat_put(ioat);
1024 mtx_unlock(&ioat->submit_lock);
1025 }
1026
1027 int
ioat_get_hwversion(bus_dmaengine_t dmaengine)1028 ioat_get_hwversion(bus_dmaengine_t dmaengine)
1029 {
1030 struct ioat_softc *ioat;
1031
1032 ioat = to_ioat_softc(dmaengine);
1033 return (ioat->version);
1034 }
1035
1036 size_t
ioat_get_max_io_size(bus_dmaengine_t dmaengine)1037 ioat_get_max_io_size(bus_dmaengine_t dmaengine)
1038 {
1039 struct ioat_softc *ioat;
1040
1041 ioat = to_ioat_softc(dmaengine);
1042 return (ioat->max_xfer_size);
1043 }
1044
1045 uint32_t
ioat_get_capabilities(bus_dmaengine_t dmaengine)1046 ioat_get_capabilities(bus_dmaengine_t dmaengine)
1047 {
1048 struct ioat_softc *ioat;
1049
1050 ioat = to_ioat_softc(dmaengine);
1051 return (ioat->capabilities);
1052 }
1053
1054 int
ioat_get_domain(bus_dmaengine_t dmaengine,int * domain)1055 ioat_get_domain(bus_dmaengine_t dmaengine, int *domain)
1056 {
1057 struct ioat_softc *ioat;
1058
1059 ioat = to_ioat_softc(dmaengine);
1060 return (bus_get_domain(ioat->device, domain));
1061 }
1062
1063 int
ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine,uint16_t delay)1064 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay)
1065 {
1066 struct ioat_softc *ioat;
1067
1068 ioat = to_ioat_softc(dmaengine);
1069 if (!ioat->intrdelay_supported)
1070 return (ENODEV);
1071 if (delay > ioat->intrdelay_max)
1072 return (ERANGE);
1073
1074 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay);
1075 ioat->cached_intrdelay =
1076 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK;
1077 return (0);
1078 }
1079
1080 uint16_t
ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)1081 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)
1082 {
1083 struct ioat_softc *ioat;
1084
1085 ioat = to_ioat_softc(dmaengine);
1086 return (ioat->intrdelay_max);
1087 }
1088
1089 void
ioat_acquire(bus_dmaengine_t dmaengine)1090 ioat_acquire(bus_dmaengine_t dmaengine)
1091 {
1092 struct ioat_softc *ioat;
1093
1094 ioat = to_ioat_softc(dmaengine);
1095 mtx_lock(&ioat->submit_lock);
1096 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1097 ioat->acq_head = ioat->head;
1098 }
1099
1100 int
ioat_acquire_reserve(bus_dmaengine_t dmaengine,unsigned n,int mflags)1101 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags)
1102 {
1103 struct ioat_softc *ioat;
1104 int error;
1105
1106 ioat = to_ioat_softc(dmaengine);
1107 ioat_acquire(dmaengine);
1108
1109 error = ioat_reserve_space(ioat, n, mflags);
1110 if (error != 0)
1111 ioat_release(dmaengine);
1112 return (error);
1113 }
1114
1115 void
ioat_release(bus_dmaengine_t dmaengine)1116 ioat_release(bus_dmaengine_t dmaengine)
1117 {
1118 struct ioat_softc *ioat;
1119
1120 ioat = to_ioat_softc(dmaengine);
1121 CTR3(KTR_IOAT, "%s channel=%u dispatch1 head=%u", __func__,
1122 ioat->chan_idx, ioat->head);
1123 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */);
1124 CTR3(KTR_IOAT, "%s channel=%u dispatch2 head=%u", __func__,
1125 ioat->chan_idx, ioat->head);
1126
1127 if (ioat->acq_head != ioat->head) {
1128 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET,
1129 (uint16_t)ioat->head);
1130
1131 if (!callout_pending(&ioat->poll_timer)) {
1132 callout_reset_on(&ioat->poll_timer, 1,
1133 ioat_poll_timer_callback, ioat, ioat->cpu);
1134 }
1135 }
1136 mtx_unlock(&ioat->submit_lock);
1137 }
1138
1139 static struct ioat_descriptor *
ioat_op_generic(struct ioat_softc * ioat,uint8_t op,uint32_t size,uint64_t src,uint64_t dst,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1140 ioat_op_generic(struct ioat_softc *ioat, uint8_t op,
1141 uint32_t size, uint64_t src, uint64_t dst,
1142 bus_dmaengine_callback_t callback_fn, void *callback_arg,
1143 uint32_t flags)
1144 {
1145 struct ioat_generic_hw_descriptor *hw_desc;
1146 struct ioat_descriptor *desc;
1147 bus_dma_segment_t seg;
1148 int mflags, nseg, error;
1149
1150 mtx_assert(&ioat->submit_lock, MA_OWNED);
1151
1152 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0,
1153 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS));
1154 KASSERT(size <= ioat->max_xfer_size, ("%s: size too big (%u > %u)",
1155 __func__, (unsigned)size, ioat->max_xfer_size));
1156
1157 if ((flags & DMA_NO_WAIT) != 0)
1158 mflags = M_NOWAIT;
1159 else
1160 mflags = M_WAITOK;
1161
1162 if (ioat_reserve_space(ioat, 1, mflags) != 0)
1163 return (NULL);
1164
1165 desc = ioat_get_ring_entry(ioat, ioat->head);
1166 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic;
1167
1168 hw_desc->u.control_raw = 0;
1169 hw_desc->u.control_generic.op = op;
1170 hw_desc->u.control_generic.completion_update = 1;
1171
1172 if ((flags & DMA_INT_EN) != 0)
1173 hw_desc->u.control_generic.int_enable = 1;
1174 if ((flags & DMA_FENCE) != 0)
1175 hw_desc->u.control_generic.fence = 1;
1176
1177 hw_desc->size = size;
1178
1179 if (src != 0) {
1180 nseg = -1;
1181 error = _bus_dmamap_load_phys(ioat->data_tag, desc->src_dmamap,
1182 src, size, 0, &seg, &nseg);
1183 if (error != 0) {
1184 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1185 " failed %d\n", __func__, error);
1186 return (NULL);
1187 }
1188 hw_desc->src_addr = seg.ds_addr;
1189 }
1190
1191 if (dst != 0) {
1192 nseg = -1;
1193 error = _bus_dmamap_load_phys(ioat->data_tag, desc->dst_dmamap,
1194 dst, size, 0, &seg, &nseg);
1195 if (error != 0) {
1196 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1197 " failed %d\n", __func__, error);
1198 return (NULL);
1199 }
1200 hw_desc->dest_addr = seg.ds_addr;
1201 }
1202
1203 desc->bus_dmadesc.callback_fn = callback_fn;
1204 desc->bus_dmadesc.callback_arg = callback_arg;
1205 return (desc);
1206 }
1207
1208 struct bus_dmadesc *
ioat_null(bus_dmaengine_t dmaengine,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1209 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn,
1210 void *callback_arg, uint32_t flags)
1211 {
1212 struct ioat_dma_hw_descriptor *hw_desc;
1213 struct ioat_descriptor *desc;
1214 struct ioat_softc *ioat;
1215
1216 ioat = to_ioat_softc(dmaengine);
1217 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1218
1219 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn,
1220 callback_arg, flags);
1221 if (desc == NULL)
1222 return (NULL);
1223
1224 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1225 hw_desc->u.control.null = 1;
1226 ioat_submit_single(ioat);
1227 return (&desc->bus_dmadesc);
1228 }
1229
1230 struct bus_dmadesc *
ioat_copy(bus_dmaengine_t dmaengine,bus_addr_t dst,bus_addr_t src,bus_size_t len,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1231 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
1232 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
1233 void *callback_arg, uint32_t flags)
1234 {
1235 struct ioat_dma_hw_descriptor *hw_desc;
1236 struct ioat_descriptor *desc;
1237 struct ioat_softc *ioat;
1238
1239 ioat = to_ioat_softc(dmaengine);
1240 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn,
1241 callback_arg, flags);
1242 if (desc == NULL)
1243 return (NULL);
1244
1245 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1246 if (g_ioat_debug_level >= 3)
1247 dump_descriptor(hw_desc);
1248
1249 ioat_submit_single(ioat);
1250 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx",
1251 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len);
1252 return (&desc->bus_dmadesc);
1253 }
1254
1255 struct bus_dmadesc *
ioat_copy_8k_aligned(bus_dmaengine_t dmaengine,bus_addr_t dst1,bus_addr_t dst2,bus_addr_t src1,bus_addr_t src2,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1256 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
1257 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
1258 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1259 {
1260 struct ioat_dma_hw_descriptor *hw_desc;
1261 struct ioat_descriptor *desc;
1262 struct ioat_softc *ioat;
1263 bus_size_t src1_len, dst1_len;
1264 bus_dma_segment_t seg;
1265 int nseg, error;
1266
1267 ioat = to_ioat_softc(dmaengine);
1268 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1269
1270 KASSERT(((src1 | src2 | dst1 | dst2) & PAGE_MASK) == 0,
1271 ("%s: addresses are not page-aligned", __func__));
1272
1273 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, 0, 0,
1274 callback_fn, callback_arg, flags);
1275 if (desc == NULL)
1276 return (NULL);
1277
1278 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1279
1280 src1_len = (src2 != src1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE;
1281 nseg = -1;
1282 error = _bus_dmamap_load_phys(ioat->data_tag,
1283 desc->src_dmamap, src1, src1_len, 0, &seg, &nseg);
1284 if (error != 0) {
1285 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1286 " failed %d\n", __func__, error);
1287 return (NULL);
1288 }
1289 hw_desc->src_addr = seg.ds_addr;
1290 if (src1_len != 2 * PAGE_SIZE) {
1291 hw_desc->u.control.src_page_break = 1;
1292 nseg = -1;
1293 error = _bus_dmamap_load_phys(ioat->data_tag,
1294 desc->src2_dmamap, src2, PAGE_SIZE, 0, &seg, &nseg);
1295 if (error != 0) {
1296 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1297 " failed %d\n", __func__, error);
1298 return (NULL);
1299 }
1300 hw_desc->next_src_addr = seg.ds_addr;
1301 }
1302
1303 dst1_len = (dst2 != dst1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE;
1304 nseg = -1;
1305 error = _bus_dmamap_load_phys(ioat->data_tag,
1306 desc->dst_dmamap, dst1, dst1_len, 0, &seg, &nseg);
1307 if (error != 0) {
1308 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1309 " failed %d\n", __func__, error);
1310 return (NULL);
1311 }
1312 hw_desc->dest_addr = seg.ds_addr;
1313 if (dst1_len != 2 * PAGE_SIZE) {
1314 hw_desc->u.control.dest_page_break = 1;
1315 nseg = -1;
1316 error = _bus_dmamap_load_phys(ioat->data_tag,
1317 desc->dst2_dmamap, dst2, PAGE_SIZE, 0, &seg, &nseg);
1318 if (error != 0) {
1319 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1320 " failed %d\n", __func__, error);
1321 return (NULL);
1322 }
1323 hw_desc->next_dest_addr = seg.ds_addr;
1324 }
1325
1326 if (g_ioat_debug_level >= 3)
1327 dump_descriptor(hw_desc);
1328
1329 ioat_submit_single(ioat);
1330 return (&desc->bus_dmadesc);
1331 }
1332
1333 struct bus_dmadesc *
ioat_copy_crc(bus_dmaengine_t dmaengine,bus_addr_t dst,bus_addr_t src,bus_size_t len,uint32_t * initialseed,bus_addr_t crcptr,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1334 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
1335 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
1336 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1337 {
1338 struct ioat_crc32_hw_descriptor *hw_desc;
1339 struct ioat_descriptor *desc;
1340 struct ioat_softc *ioat;
1341 uint32_t teststore;
1342 uint8_t op;
1343 bus_dma_segment_t seg;
1344 int nseg, error;
1345
1346 ioat = to_ioat_softc(dmaengine);
1347 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1348
1349 KASSERT((ioat->capabilities & IOAT_DMACAP_MOVECRC) != 0,
1350 ("%s: device lacks MOVECRC capability", __func__));
1351 teststore = (flags & _DMA_CRC_TESTSTORE);
1352 KASSERT(teststore != _DMA_CRC_TESTSTORE,
1353 ("%s: TEST and STORE invalid", __func__));
1354 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0,
1355 ("%s: INLINE invalid without TEST or STORE", __func__));
1356
1357 switch (teststore) {
1358 case DMA_CRC_STORE:
1359 op = IOAT_OP_MOVECRC_STORE;
1360 break;
1361 case DMA_CRC_TEST:
1362 op = IOAT_OP_MOVECRC_TEST;
1363 break;
1364 default:
1365 KASSERT(teststore == 0, ("bogus"));
1366 op = IOAT_OP_MOVECRC;
1367 break;
1368 }
1369
1370 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
1371 callback_arg, flags & ~_DMA_CRC_FLAGS);
1372 if (desc == NULL)
1373 return (NULL);
1374
1375 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1376
1377 if ((flags & DMA_CRC_INLINE) == 0) {
1378 nseg = -1;
1379 error = _bus_dmamap_load_phys(ioat->data_tag,
1380 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
1381 &seg, &nseg);
1382 if (error != 0) {
1383 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1384 " failed %d\n", __func__, error);
1385 return (NULL);
1386 }
1387 hw_desc->crc_address = seg.ds_addr;
1388 } else
1389 hw_desc->u.control.crc_location = 1;
1390
1391 if (initialseed != NULL) {
1392 hw_desc->u.control.use_seed = 1;
1393 hw_desc->seed = *initialseed;
1394 }
1395
1396 if (g_ioat_debug_level >= 3)
1397 dump_descriptor(hw_desc);
1398
1399 ioat_submit_single(ioat);
1400 return (&desc->bus_dmadesc);
1401 }
1402
1403 struct bus_dmadesc *
ioat_crc(bus_dmaengine_t dmaengine,bus_addr_t src,bus_size_t len,uint32_t * initialseed,bus_addr_t crcptr,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1404 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
1405 uint32_t *initialseed, bus_addr_t crcptr,
1406 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1407 {
1408 struct ioat_crc32_hw_descriptor *hw_desc;
1409 struct ioat_descriptor *desc;
1410 struct ioat_softc *ioat;
1411 uint32_t teststore;
1412 uint8_t op;
1413 bus_dma_segment_t seg;
1414 int nseg, error;
1415
1416 ioat = to_ioat_softc(dmaengine);
1417 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1418
1419 KASSERT((ioat->capabilities & IOAT_DMACAP_CRC) != 0,
1420 ("%s: device lacks CRC capability", __func__));
1421 teststore = (flags & _DMA_CRC_TESTSTORE);
1422 KASSERT(teststore != _DMA_CRC_TESTSTORE,
1423 ("%s: TEST and STORE invalid", __func__));
1424 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0,
1425 ("%s: INLINE invalid without TEST or STORE", __func__));
1426
1427 switch (teststore) {
1428 case DMA_CRC_STORE:
1429 op = IOAT_OP_CRC_STORE;
1430 break;
1431 case DMA_CRC_TEST:
1432 op = IOAT_OP_CRC_TEST;
1433 break;
1434 default:
1435 KASSERT(teststore == 0, ("bogus"));
1436 op = IOAT_OP_CRC;
1437 break;
1438 }
1439
1440 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
1441 callback_arg, flags & ~_DMA_CRC_FLAGS);
1442 if (desc == NULL)
1443 return (NULL);
1444
1445 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1446
1447 if ((flags & DMA_CRC_INLINE) == 0) {
1448 nseg = -1;
1449 error = _bus_dmamap_load_phys(ioat->data_tag,
1450 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
1451 &seg, &nseg);
1452 if (error != 0) {
1453 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1454 " failed %d\n", __func__, error);
1455 return (NULL);
1456 }
1457 hw_desc->crc_address = seg.ds_addr;
1458 } else
1459 hw_desc->u.control.crc_location = 1;
1460
1461 if (initialseed != NULL) {
1462 hw_desc->u.control.use_seed = 1;
1463 hw_desc->seed = *initialseed;
1464 }
1465
1466 if (g_ioat_debug_level >= 3)
1467 dump_descriptor(hw_desc);
1468
1469 ioat_submit_single(ioat);
1470 return (&desc->bus_dmadesc);
1471 }
1472
1473 struct bus_dmadesc *
ioat_blockfill(bus_dmaengine_t dmaengine,bus_addr_t dst,uint64_t fillpattern,bus_size_t len,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1474 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
1475 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg,
1476 uint32_t flags)
1477 {
1478 struct ioat_fill_hw_descriptor *hw_desc;
1479 struct ioat_descriptor *desc;
1480 struct ioat_softc *ioat;
1481
1482 ioat = to_ioat_softc(dmaengine);
1483 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1484
1485 KASSERT((ioat->capabilities & IOAT_DMACAP_BFILL) != 0,
1486 ("%s: device lacks BFILL capability", __func__));
1487
1488 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst,
1489 callback_fn, callback_arg, flags);
1490 if (desc == NULL)
1491 return (NULL);
1492
1493 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill;
1494 hw_desc->src_data = fillpattern;
1495 if (g_ioat_debug_level >= 3)
1496 dump_descriptor(hw_desc);
1497
1498 ioat_submit_single(ioat);
1499 return (&desc->bus_dmadesc);
1500 }
1501
1502 /*
1503 * Ring Management
1504 */
1505 static inline uint32_t
ioat_get_active(struct ioat_softc * ioat)1506 ioat_get_active(struct ioat_softc *ioat)
1507 {
1508
1509 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1));
1510 }
1511
1512 static inline uint32_t
ioat_get_ring_space(struct ioat_softc * ioat)1513 ioat_get_ring_space(struct ioat_softc *ioat)
1514 {
1515
1516 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1);
1517 }
1518
1519 /*
1520 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain
1521 * for 'num_descs'.
1522 *
1523 * If mflags contains M_WAITOK, blocks until enough space is available.
1524 *
1525 * Returns zero on success, or an errno on error. If num_descs is beyond the
1526 * maximum ring size, returns EINVAl; if allocation would block and mflags
1527 * contains M_NOWAIT, returns EAGAIN.
1528 *
1529 * Must be called with the submit_lock held; returns with the lock held. The
1530 * lock may be dropped to allocate the ring.
1531 *
1532 * (The submit_lock is needed to add any entries to the ring, so callers are
1533 * assured enough room is available.)
1534 */
1535 static int
ioat_reserve_space(struct ioat_softc * ioat,uint32_t num_descs,int mflags)1536 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags)
1537 {
1538 boolean_t dug;
1539 int error;
1540
1541 mtx_assert(&ioat->submit_lock, MA_OWNED);
1542 error = 0;
1543 dug = FALSE;
1544
1545 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) {
1546 error = EINVAL;
1547 goto out;
1548 }
1549
1550 for (;;) {
1551 if (ioat->quiescing) {
1552 error = ENXIO;
1553 goto out;
1554 }
1555
1556 if (ioat_get_ring_space(ioat) >= num_descs)
1557 goto out;
1558
1559 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__,
1560 ioat->chan_idx, num_descs);
1561
1562 if (!dug && !ioat->is_submitter_processing) {
1563 ioat->is_submitter_processing = TRUE;
1564 mtx_unlock(&ioat->submit_lock);
1565
1566 CTR2(KTR_IOAT, "%s channel=%u attempting to process events",
1567 __func__, ioat->chan_idx);
1568 ioat_process_events(ioat, FALSE);
1569
1570 mtx_lock(&ioat->submit_lock);
1571 dug = TRUE;
1572 KASSERT(ioat->is_submitter_processing == TRUE,
1573 ("is_submitter_processing"));
1574 ioat->is_submitter_processing = FALSE;
1575 wakeup(&ioat->tail);
1576 continue;
1577 }
1578
1579 if ((mflags & M_WAITOK) == 0) {
1580 error = EAGAIN;
1581 break;
1582 }
1583 CTR2(KTR_IOAT, "%s channel=%u blocking on completions",
1584 __func__, ioat->chan_idx);
1585 msleep(&ioat->tail, &ioat->submit_lock, 0,
1586 "ioat_full", 0);
1587 continue;
1588 }
1589
1590 out:
1591 mtx_assert(&ioat->submit_lock, MA_OWNED);
1592 KASSERT(!ioat->quiescing || error == ENXIO,
1593 ("reserved during quiesce"));
1594 return (error);
1595 }
1596
1597 static void
ioat_free_ring(struct ioat_softc * ioat,uint32_t size,struct ioat_descriptor * ring)1598 ioat_free_ring(struct ioat_softc *ioat, uint32_t size,
1599 struct ioat_descriptor *ring)
1600 {
1601
1602 free(ring, M_IOAT);
1603 }
1604
1605 static struct ioat_descriptor *
ioat_get_ring_entry(struct ioat_softc * ioat,uint32_t index)1606 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index)
1607 {
1608
1609 return (&ioat->ring[index % (1 << ioat->ring_size_order)]);
1610 }
1611
1612 static union ioat_hw_descriptor *
ioat_get_descriptor(struct ioat_softc * ioat,uint32_t index)1613 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index)
1614 {
1615
1616 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]);
1617 }
1618
1619 static void
ioat_halted_debug(struct ioat_softc * ioat,uint32_t chanerr)1620 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr)
1621 {
1622 union ioat_hw_descriptor *desc;
1623
1624 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr,
1625 IOAT_CHANERR_STR);
1626 if (chanerr == 0)
1627 return;
1628
1629 mtx_assert(&ioat->cleanup_lock, MA_OWNED);
1630
1631 desc = ioat_get_descriptor(ioat, ioat->tail + 0);
1632 dump_descriptor(desc);
1633
1634 desc = ioat_get_descriptor(ioat, ioat->tail + 1);
1635 dump_descriptor(desc);
1636 }
1637
1638 static void
ioat_poll_timer_callback(void * arg)1639 ioat_poll_timer_callback(void *arg)
1640 {
1641 struct ioat_softc *ioat;
1642
1643 ioat = arg;
1644 CTR1(KTR_IOAT, "%s", __func__);
1645
1646 ioat_process_events(ioat, FALSE);
1647
1648 mtx_lock(&ioat->submit_lock);
1649 if (ioat_get_active(ioat) > 0)
1650 callout_schedule(&ioat->poll_timer, 1);
1651 mtx_unlock(&ioat->submit_lock);
1652 }
1653
1654 /*
1655 * Support Functions
1656 */
1657 static void
ioat_submit_single(struct ioat_softc * ioat)1658 ioat_submit_single(struct ioat_softc *ioat)
1659 {
1660
1661 mtx_assert(&ioat->submit_lock, MA_OWNED);
1662
1663 ioat->head++;
1664 CTR4(KTR_IOAT, "%s channel=%u head=%u tail=%u", __func__,
1665 ioat->chan_idx, ioat->head, ioat->tail);
1666
1667 ioat->stats.descriptors_submitted++;
1668 }
1669
1670 static int
ioat_reset_hw(struct ioat_softc * ioat)1671 ioat_reset_hw(struct ioat_softc *ioat)
1672 {
1673 uint64_t status;
1674 uint32_t chanerr;
1675 unsigned timeout;
1676 int error;
1677
1678 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1679
1680 mtx_lock(&ioat->submit_lock);
1681 while (ioat->resetting && !ioat->destroying)
1682 msleep(&ioat->resetting, &ioat->submit_lock, 0, "IRH_drain", 0);
1683 if (ioat->destroying) {
1684 mtx_unlock(&ioat->submit_lock);
1685 return (ENXIO);
1686 }
1687 ioat->resetting = TRUE;
1688 ioat->quiescing = TRUE;
1689 mtx_unlock(&ioat->submit_lock);
1690 mtx_lock(&ioat->cleanup_lock);
1691 while (ioat_get_active(ioat) > 0)
1692 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1);
1693
1694 /*
1695 * Suspend ioat_process_events while the hardware and softc are in an
1696 * indeterminate state.
1697 */
1698 ioat->resetting_cleanup = TRUE;
1699 mtx_unlock(&ioat->cleanup_lock);
1700
1701 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__,
1702 ioat->chan_idx);
1703
1704 status = ioat_get_chansts(ioat);
1705 if (is_ioat_active(status) || is_ioat_idle(status))
1706 ioat_suspend(ioat);
1707
1708 /* Wait at most 20 ms */
1709 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) &&
1710 timeout < 20; timeout++) {
1711 DELAY(1000);
1712 status = ioat_get_chansts(ioat);
1713 }
1714 if (timeout == 20) {
1715 error = ETIMEDOUT;
1716 goto out;
1717 }
1718
1719 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce"));
1720
1721 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1722 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
1723
1724 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__,
1725 ioat->chan_idx);
1726
1727 /*
1728 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors
1729 * that can cause stability issues for IOAT v3.
1730 */
1731 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07,
1732 4);
1733 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4);
1734 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4);
1735
1736 /*
1737 * BDXDE and BWD models reset MSI-X registers on device reset.
1738 * Save/restore their contents manually.
1739 */
1740 if (ioat_model_resets_msix(ioat)) {
1741 ioat_log_message(1, "device resets MSI-X registers; saving\n");
1742 pci_save_state(ioat->device);
1743 }
1744
1745 ioat_reset(ioat);
1746 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__,
1747 ioat->chan_idx);
1748
1749 /* Wait at most 20 ms */
1750 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++)
1751 DELAY(1000);
1752 if (timeout == 20) {
1753 error = ETIMEDOUT;
1754 goto out;
1755 }
1756
1757 if (ioat_model_resets_msix(ioat)) {
1758 ioat_log_message(1, "device resets registers; restored\n");
1759 pci_restore_state(ioat->device);
1760 }
1761
1762 /* Reset attempts to return the hardware to "halted." */
1763 status = ioat_get_chansts(ioat);
1764 if (is_ioat_active(status) || is_ioat_idle(status)) {
1765 /* So this really shouldn't happen... */
1766 ioat_log_message(0, "Device is active after a reset?\n");
1767 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1768 error = 0;
1769 goto out;
1770 }
1771
1772 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1773 if (chanerr != 0) {
1774 mtx_lock(&ioat->cleanup_lock);
1775 ioat_halted_debug(ioat, chanerr);
1776 mtx_unlock(&ioat->cleanup_lock);
1777 error = EIO;
1778 goto out;
1779 }
1780
1781 /*
1782 * Bring device back online after reset. Writing CHAINADDR brings the
1783 * device back to active.
1784 *
1785 * The internal ring counter resets to zero, so we have to start over
1786 * at zero as well.
1787 */
1788 ioat->tail = ioat->head = 0;
1789 *ioat->comp_update = ioat->last_seen =
1790 RING_PHYS_ADDR(ioat, ioat->tail - 1);
1791
1792 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1793 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr);
1794 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0));
1795 error = 0;
1796 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__,
1797 ioat->chan_idx);
1798
1799 out:
1800 /* Enqueues a null operation and ensures it completes. */
1801 if (error == 0) {
1802 error = ioat_start_channel(ioat);
1803 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__,
1804 ioat->chan_idx);
1805 }
1806
1807 /*
1808 * Resume completions now that ring state is consistent.
1809 */
1810 mtx_lock(&ioat->cleanup_lock);
1811 ioat->resetting_cleanup = FALSE;
1812 mtx_unlock(&ioat->cleanup_lock);
1813
1814 /* Unblock submission of new work */
1815 mtx_lock(&ioat->submit_lock);
1816 ioat->quiescing = FALSE;
1817 wakeup(&ioat->quiescing);
1818
1819 ioat->resetting = FALSE;
1820 wakeup(&ioat->resetting);
1821
1822 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx);
1823 mtx_unlock(&ioat->submit_lock);
1824
1825 return (error);
1826 }
1827
1828 static int
sysctl_handle_chansts(SYSCTL_HANDLER_ARGS)1829 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS)
1830 {
1831 struct ioat_softc *ioat;
1832 struct sbuf sb;
1833 uint64_t status;
1834 int error;
1835
1836 ioat = arg1;
1837
1838 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
1839
1840 sbuf_new_for_sysctl(&sb, NULL, 256, req);
1841 switch (status) {
1842 case IOAT_CHANSTS_ACTIVE:
1843 sbuf_printf(&sb, "ACTIVE");
1844 break;
1845 case IOAT_CHANSTS_IDLE:
1846 sbuf_printf(&sb, "IDLE");
1847 break;
1848 case IOAT_CHANSTS_SUSPENDED:
1849 sbuf_printf(&sb, "SUSPENDED");
1850 break;
1851 case IOAT_CHANSTS_HALTED:
1852 sbuf_printf(&sb, "HALTED");
1853 break;
1854 case IOAT_CHANSTS_ARMED:
1855 sbuf_printf(&sb, "ARMED");
1856 break;
1857 default:
1858 sbuf_printf(&sb, "UNKNOWN");
1859 break;
1860 }
1861 error = sbuf_finish(&sb);
1862 sbuf_delete(&sb);
1863
1864 if (error != 0 || req->newptr == NULL)
1865 return (error);
1866 return (EINVAL);
1867 }
1868
1869 static int
sysctl_handle_dpi(SYSCTL_HANDLER_ARGS)1870 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS)
1871 {
1872 struct ioat_softc *ioat;
1873 struct sbuf sb;
1874 #define PRECISION "1"
1875 const uintmax_t factor = 10;
1876 uintmax_t rate;
1877 int error;
1878
1879 ioat = arg1;
1880 sbuf_new_for_sysctl(&sb, NULL, 16, req);
1881
1882 if (ioat->stats.interrupts == 0) {
1883 sbuf_printf(&sb, "NaN");
1884 goto out;
1885 }
1886 rate = ioat->stats.descriptors_processed * factor /
1887 ioat->stats.interrupts;
1888 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor,
1889 rate % factor);
1890 #undef PRECISION
1891 out:
1892 error = sbuf_finish(&sb);
1893 sbuf_delete(&sb);
1894 if (error != 0 || req->newptr == NULL)
1895 return (error);
1896 return (EINVAL);
1897 }
1898
1899 static int
sysctl_handle_reset(SYSCTL_HANDLER_ARGS)1900 sysctl_handle_reset(SYSCTL_HANDLER_ARGS)
1901 {
1902 struct ioat_softc *ioat;
1903 int error, arg;
1904
1905 ioat = arg1;
1906
1907 arg = 0;
1908 error = SYSCTL_OUT(req, &arg, sizeof(arg));
1909 if (error != 0 || req->newptr == NULL)
1910 return (error);
1911
1912 error = SYSCTL_IN(req, &arg, sizeof(arg));
1913 if (error != 0)
1914 return (error);
1915
1916 if (arg != 0)
1917 error = ioat_reset_hw(ioat);
1918
1919 return (error);
1920 }
1921
1922 static void
dump_descriptor(void * hw_desc)1923 dump_descriptor(void *hw_desc)
1924 {
1925 int i, j;
1926
1927 for (i = 0; i < 2; i++) {
1928 for (j = 0; j < 8; j++)
1929 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]);
1930 printf("\n");
1931 }
1932 }
1933
1934 static void
ioat_setup_sysctl(device_t device)1935 ioat_setup_sysctl(device_t device)
1936 {
1937 struct sysctl_oid_list *par, *statpar, *state, *hammer;
1938 struct sysctl_ctx_list *ctx;
1939 struct sysctl_oid *tree, *tmp;
1940 struct ioat_softc *ioat;
1941
1942 ioat = DEVICE2SOFTC(device);
1943 ctx = device_get_sysctl_ctx(device);
1944 tree = device_get_sysctl_tree(device);
1945 par = SYSCTL_CHILDREN(tree);
1946
1947 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD,
1948 &ioat->version, 0, "HW version (0xMM form)");
1949 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD,
1950 &ioat->max_xfer_size, 0, "HW maximum transfer size");
1951 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD,
1952 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported");
1953 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD,
1954 &ioat->intrdelay_max, 0,
1955 "Maximum configurable INTRDELAY on this channel (microseconds)");
1956
1957 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state",
1958 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IOAT channel internal state");
1959 state = SYSCTL_CHILDREN(tmp);
1960
1961 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD,
1962 &ioat->ring_size_order, 0, "SW descriptor ring size order");
1963 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head,
1964 0, "SW descriptor head pointer index");
1965 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail,
1966 0, "SW descriptor tail pointer index");
1967
1968 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD,
1969 ioat->comp_update, "HW addr of last completion");
1970
1971 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing",
1972 CTLFLAG_RD, &ioat->is_submitter_processing, 0,
1973 "submitter processing");
1974
1975 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts",
1976 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, ioat, 0,
1977 sysctl_handle_chansts, "A", "String of the channel status");
1978
1979 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD,
1980 &ioat->cached_intrdelay, 0,
1981 "Current INTRDELAY on this channel (cached, microseconds)");
1982
1983 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer",
1984 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1985 "Big hammers (mostly for testing)");
1986 hammer = SYSCTL_CHILDREN(tmp);
1987
1988 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset",
1989 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, ioat, 0,
1990 sysctl_handle_reset, "I", "Set to non-zero to reset the hardware");
1991
1992 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats",
1993 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IOAT channel statistics");
1994 statpar = SYSCTL_CHILDREN(tmp);
1995
1996 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts",
1997 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.interrupts,
1998 "Number of interrupts processed on this channel");
1999 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors",
2000 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_processed,
2001 "Number of descriptors processed on this channel");
2002 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted",
2003 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_submitted,
2004 "Number of descriptors submitted to this channel");
2005 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored",
2006 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_error,
2007 "Number of descriptors failed by channel errors");
2008 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts",
2009 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.channel_halts, 0,
2010 "Number of times the channel has halted");
2011 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr",
2012 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.last_halt_chanerr, 0,
2013 "The raw CHANERR when the channel was last halted");
2014
2015 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt",
2016 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, ioat, 0,
2017 sysctl_handle_dpi, "A", "Descriptors per interrupt");
2018 }
2019
2020 static void
ioat_get(struct ioat_softc * ioat)2021 ioat_get(struct ioat_softc *ioat)
2022 {
2023
2024 mtx_assert(&ioat->submit_lock, MA_OWNED);
2025 KASSERT(ioat->refcnt < UINT32_MAX, ("refcnt overflow"));
2026
2027 ioat->refcnt++;
2028 }
2029
2030 static void
ioat_put(struct ioat_softc * ioat)2031 ioat_put(struct ioat_softc *ioat)
2032 {
2033
2034 mtx_assert(&ioat->submit_lock, MA_OWNED);
2035 KASSERT(ioat->refcnt >= 1, ("refcnt error"));
2036
2037 if (--ioat->refcnt == 0)
2038 wakeup(&ioat->refcnt);
2039 }
2040
2041 static void
ioat_drain_locked(struct ioat_softc * ioat)2042 ioat_drain_locked(struct ioat_softc *ioat)
2043 {
2044
2045 mtx_assert(&ioat->submit_lock, MA_OWNED);
2046
2047 while (ioat->refcnt > 0)
2048 msleep(&ioat->refcnt, &ioat->submit_lock, 0, "ioat_drain", 0);
2049 }
2050
2051 #ifdef DDB
2052 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo)
2053 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object)
DB_SHOW_COMMAND(ioat,db_show_ioat)2054 DB_SHOW_COMMAND(ioat, db_show_ioat)
2055 {
2056 struct ioat_softc *sc;
2057 unsigned idx;
2058
2059 if (!have_addr)
2060 goto usage;
2061 idx = (unsigned)addr;
2062 if (idx >= ioat_channel_index)
2063 goto usage;
2064
2065 sc = ioat_channel[idx];
2066 db_printf("ioat softc at %p\n", sc);
2067 if (sc == NULL)
2068 return;
2069
2070 db_printf(" version: %d\n", sc->version);
2071 db_printf(" chan_idx: %u\n", sc->chan_idx);
2072 db_printf(" submit_lock: ");
2073 db_show_lock(&sc->submit_lock);
2074
2075 db_printf(" capabilities: %b\n", (int)sc->capabilities,
2076 IOAT_DMACAP_STR);
2077 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay);
2078 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update);
2079
2080 db_printf(" poll_timer:\n");
2081 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time);
2082 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg);
2083 db_printf(" c_func: %p\n", sc->poll_timer.c_func);
2084 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock);
2085 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags);
2086
2087 db_printf(" quiescing: %d\n", (int)sc->quiescing);
2088 db_printf(" destroying: %d\n", (int)sc->destroying);
2089 db_printf(" is_submitter_processing: %d\n",
2090 (int)sc->is_submitter_processing);
2091 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported);
2092 db_printf(" resetting: %d\n", (int)sc->resetting);
2093
2094 db_printf(" head: %u\n", sc->head);
2095 db_printf(" tail: %u\n", sc->tail);
2096 db_printf(" ring_size_order: %u\n", sc->ring_size_order);
2097 db_printf(" last_seen: 0x%lx\n", sc->last_seen);
2098 db_printf(" ring: %p\n", sc->ring);
2099 db_printf(" descriptors: %p\n", sc->hw_desc_ring);
2100 db_printf(" descriptors (phys): 0x%jx\n",
2101 (uintmax_t)sc->hw_desc_bus_addr);
2102
2103 db_printf(" ring[%u] (tail):\n", sc->tail %
2104 (1 << sc->ring_size_order));
2105 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id);
2106 db_printf(" addr: 0x%lx\n",
2107 RING_PHYS_ADDR(sc, sc->tail));
2108 db_printf(" next: 0x%lx\n",
2109 ioat_get_descriptor(sc, sc->tail)->generic.next);
2110
2111 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) %
2112 (1 << sc->ring_size_order));
2113 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id);
2114 db_printf(" addr: 0x%lx\n",
2115 RING_PHYS_ADDR(sc, sc->head - 1));
2116 db_printf(" next: 0x%lx\n",
2117 ioat_get_descriptor(sc, sc->head - 1)->generic.next);
2118
2119 db_printf(" ring[%u] (head):\n", (sc->head) %
2120 (1 << sc->ring_size_order));
2121 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id);
2122 db_printf(" addr: 0x%lx\n",
2123 RING_PHYS_ADDR(sc, sc->head));
2124 db_printf(" next: 0x%lx\n",
2125 ioat_get_descriptor(sc, sc->head)->generic.next);
2126
2127 for (idx = 0; idx < (1 << sc->ring_size_order); idx++)
2128 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK)
2129 == RING_PHYS_ADDR(sc, idx))
2130 db_printf(" ring[%u] == hardware tail\n", idx);
2131
2132 db_printf(" cleanup_lock: ");
2133 db_show_lock(&sc->cleanup_lock);
2134
2135 db_printf(" refcnt: %u\n", sc->refcnt);
2136 db_printf(" stats:\n");
2137 db_printf(" interrupts: %lu\n", sc->stats.interrupts);
2138 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed);
2139 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error);
2140 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted);
2141
2142 db_printf(" channel_halts: %u\n", sc->stats.channel_halts);
2143 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr);
2144
2145 if (db_pager_quit)
2146 return;
2147
2148 db_printf(" hw status:\n");
2149 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc));
2150 db_printf(" chanctrl: 0x%x\n",
2151 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET));
2152 db_printf(" chancmd: 0x%x\n",
2153 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET));
2154 db_printf(" dmacount: 0x%x\n",
2155 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET));
2156 db_printf(" chainaddr: 0x%lx\n",
2157 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW));
2158 db_printf(" chancmp: 0x%lx\n",
2159 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW));
2160 db_printf(" chanerr: %b\n",
2161 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR);
2162 return;
2163 usage:
2164 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index);
2165 return;
2166 }
2167 #endif /* DDB */
2168