1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 #include "igc_api.h"
6
7 /**
8 * igc_get_i2c_data - Reads the I2C SDA data bit
9 * @i2cctl: Current value of I2CCTL register
10 *
11 * Returns the I2C data bit value
12 **/
igc_get_i2c_data(u32 * i2cctl)13 static bool igc_get_i2c_data(u32 *i2cctl)
14 {
15 bool data;
16
17 DEBUGFUNC("igc_get_i2c_data");
18
19 if (*i2cctl & IGC_I2C_DATA_IN)
20 data = 1;
21 else
22 data = 0;
23
24 return data;
25 }
26
27 /**
28 * igc_set_i2c_data - Sets the I2C data bit
29 * @hw: pointer to hardware structure
30 * @i2cctl: Current value of I2CCTL register
31 * @data: I2C data value (0 or 1) to set
32 *
33 * Sets the I2C data bit
34 **/
igc_set_i2c_data(struct igc_hw * hw,u32 * i2cctl,bool data)35 static s32 igc_set_i2c_data(struct igc_hw *hw, u32 *i2cctl, bool data)
36 {
37 s32 status = IGC_SUCCESS;
38
39 DEBUGFUNC("igc_set_i2c_data");
40
41 if (data)
42 *i2cctl |= IGC_I2C_DATA_OUT;
43 else
44 *i2cctl &= ~IGC_I2C_DATA_OUT;
45
46 *i2cctl &= ~IGC_I2C_DATA_OE_N;
47 *i2cctl |= IGC_I2C_CLK_OE_N;
48 IGC_WRITE_REG(hw, IGC_I2CPARAMS, *i2cctl);
49 IGC_WRITE_FLUSH(hw);
50
51 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
52 usec_delay(IGC_I2C_T_RISE + IGC_I2C_T_FALL + IGC_I2C_T_SU_DATA);
53
54 *i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
55 if (data != igc_get_i2c_data(i2cctl)) {
56 status = IGC_ERR_I2C;
57 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
58 }
59
60 return status;
61 }
62
63 /**
64 * igc_raise_i2c_clk - Raises the I2C SCL clock
65 * @hw: pointer to hardware structure
66 * @i2cctl: Current value of I2CCTL register
67 *
68 * Raises the I2C clock line '0'->'1'
69 **/
igc_raise_i2c_clk(struct igc_hw * hw,u32 * i2cctl)70 static void igc_raise_i2c_clk(struct igc_hw *hw, u32 *i2cctl)
71 {
72 DEBUGFUNC("igc_raise_i2c_clk");
73
74 *i2cctl |= IGC_I2C_CLK_OUT;
75 *i2cctl &= ~IGC_I2C_CLK_OE_N;
76 IGC_WRITE_REG(hw, IGC_I2CPARAMS, *i2cctl);
77 IGC_WRITE_FLUSH(hw);
78
79 /* SCL rise time (1000ns) */
80 usec_delay(IGC_I2C_T_RISE);
81 }
82
83 /**
84 * igc_lower_i2c_clk - Lowers the I2C SCL clock
85 * @hw: pointer to hardware structure
86 * @i2cctl: Current value of I2CCTL register
87 *
88 * Lowers the I2C clock line '1'->'0'
89 **/
igc_lower_i2c_clk(struct igc_hw * hw,u32 * i2cctl)90 static void igc_lower_i2c_clk(struct igc_hw *hw, u32 *i2cctl)
91 {
92 DEBUGFUNC("igc_lower_i2c_clk");
93
94 *i2cctl &= ~IGC_I2C_CLK_OUT;
95 *i2cctl &= ~IGC_I2C_CLK_OE_N;
96 IGC_WRITE_REG(hw, IGC_I2CPARAMS, *i2cctl);
97 IGC_WRITE_FLUSH(hw);
98
99 /* SCL fall time (300ns) */
100 usec_delay(IGC_I2C_T_FALL);
101 }
102
103 /**
104 * igc_i2c_start - Sets I2C start condition
105 * @hw: pointer to hardware structure
106 *
107 * Sets I2C start condition (High -> Low on SDA while SCL is High)
108 **/
igc_i2c_start(struct igc_hw * hw)109 static void igc_i2c_start(struct igc_hw *hw)
110 {
111 u32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
112
113 DEBUGFUNC("igc_i2c_start");
114
115 /* Start condition must begin with data and clock high */
116 igc_set_i2c_data(hw, &i2cctl, 1);
117 igc_raise_i2c_clk(hw, &i2cctl);
118
119 /* Setup time for start condition (4.7us) */
120 usec_delay(IGC_I2C_T_SU_STA);
121
122 igc_set_i2c_data(hw, &i2cctl, 0);
123
124 /* Hold time for start condition (4us) */
125 usec_delay(IGC_I2C_T_HD_STA);
126
127 igc_lower_i2c_clk(hw, &i2cctl);
128
129 /* Minimum low period of clock is 4.7 us */
130 usec_delay(IGC_I2C_T_LOW);
131 }
132
133 /**
134 * igc_i2c_stop - Sets I2C stop condition
135 * @hw: pointer to hardware structure
136 *
137 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
138 **/
igc_i2c_stop(struct igc_hw * hw)139 static void igc_i2c_stop(struct igc_hw *hw)
140 {
141 u32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
142
143 DEBUGFUNC("igc_i2c_stop");
144
145 /* Stop condition must begin with data low and clock high */
146 igc_set_i2c_data(hw, &i2cctl, 0);
147 igc_raise_i2c_clk(hw, &i2cctl);
148
149 /* Setup time for stop condition (4us) */
150 usec_delay(IGC_I2C_T_SU_STO);
151
152 igc_set_i2c_data(hw, &i2cctl, 1);
153
154 /* bus free time between stop and start (4.7us)*/
155 usec_delay(IGC_I2C_T_BUF);
156 }
157
158 /**
159 * igc_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
160 * @hw: pointer to hardware structure
161 * @data: read data value
162 *
163 * Clocks in one bit via I2C data/clock
164 **/
igc_clock_in_i2c_bit(struct igc_hw * hw,bool * data)165 static void igc_clock_in_i2c_bit(struct igc_hw *hw, bool *data)
166 {
167 u32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
168
169 DEBUGFUNC("igc_clock_in_i2c_bit");
170
171 igc_raise_i2c_clk(hw, &i2cctl);
172
173 /* Minimum high period of clock is 4us */
174 usec_delay(IGC_I2C_T_HIGH);
175
176 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
177 *data = igc_get_i2c_data(&i2cctl);
178
179 igc_lower_i2c_clk(hw, &i2cctl);
180
181 /* Minimum low period of clock is 4.7 us */
182 usec_delay(IGC_I2C_T_LOW);
183 }
184
185 /**
186 * igc_clock_in_i2c_byte - Clocks in one byte via I2C
187 * @hw: pointer to hardware structure
188 * @data: data byte to clock in
189 *
190 * Clocks in one byte data via I2C data/clock
191 **/
igc_clock_in_i2c_byte(struct igc_hw * hw,u8 * data)192 static void igc_clock_in_i2c_byte(struct igc_hw *hw, u8 *data)
193 {
194 s32 i;
195 bool bit = 0;
196
197 DEBUGFUNC("igc_clock_in_i2c_byte");
198
199 *data = 0;
200 for (i = 7; i >= 0; i--) {
201 igc_clock_in_i2c_bit(hw, &bit);
202 *data |= bit << i;
203 }
204 }
205
206 /**
207 * igc_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
208 * @hw: pointer to hardware structure
209 * @data: data value to write
210 *
211 * Clocks out one bit via I2C data/clock
212 **/
igc_clock_out_i2c_bit(struct igc_hw * hw,bool data)213 static s32 igc_clock_out_i2c_bit(struct igc_hw *hw, bool data)
214 {
215 s32 status;
216 u32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
217
218 DEBUGFUNC("igc_clock_out_i2c_bit");
219
220 status = igc_set_i2c_data(hw, &i2cctl, data);
221 if (status == IGC_SUCCESS) {
222 igc_raise_i2c_clk(hw, &i2cctl);
223
224 /* Minimum high period of clock is 4us */
225 usec_delay(IGC_I2C_T_HIGH);
226
227 igc_lower_i2c_clk(hw, &i2cctl);
228
229 /* Minimum low period of clock is 4.7 us.
230 * This also takes care of the data hold time.
231 */
232 usec_delay(IGC_I2C_T_LOW);
233 } else {
234 status = IGC_ERR_I2C;
235 DEBUGOUT1("I2C data was not set to %X\n", data);
236 }
237
238 return status;
239 }
240
241 /**
242 * igc_clock_out_i2c_byte - Clocks out one byte via I2C
243 * @hw: pointer to hardware structure
244 * @data: data byte clocked out
245 *
246 * Clocks out one byte data via I2C data/clock
247 **/
igc_clock_out_i2c_byte(struct igc_hw * hw,u8 data)248 static s32 igc_clock_out_i2c_byte(struct igc_hw *hw, u8 data)
249 {
250 s32 status = IGC_SUCCESS;
251 s32 i;
252 u32 i2cctl;
253 bool bit = 0;
254
255 DEBUGFUNC("igc_clock_out_i2c_byte");
256
257 for (i = 7; i >= 0; i--) {
258 bit = (data >> i) & 0x1;
259 status = igc_clock_out_i2c_bit(hw, bit);
260
261 if (status != IGC_SUCCESS)
262 break;
263 }
264
265 /* Release SDA line (set high) */
266 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
267
268 i2cctl |= IGC_I2C_DATA_OE_N;
269 IGC_WRITE_REG(hw, IGC_I2CPARAMS, i2cctl);
270 IGC_WRITE_FLUSH(hw);
271
272 return status;
273 }
274
275 /**
276 * igc_get_i2c_ack - Polls for I2C ACK
277 * @hw: pointer to hardware structure
278 *
279 * Clocks in/out one bit via I2C data/clock
280 **/
igc_get_i2c_ack(struct igc_hw * hw)281 static s32 igc_get_i2c_ack(struct igc_hw *hw)
282 {
283 s32 status = IGC_SUCCESS;
284 u32 i = 0;
285 u32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
286 u32 timeout = 10;
287 bool ack = true;
288
289 DEBUGFUNC("igc_get_i2c_ack");
290
291 igc_raise_i2c_clk(hw, &i2cctl);
292
293 /* Minimum high period of clock is 4us */
294 usec_delay(IGC_I2C_T_HIGH);
295
296 /* Wait until SCL returns high */
297 for (i = 0; i < timeout; i++) {
298 usec_delay(1);
299 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
300 if (i2cctl & IGC_I2C_CLK_IN)
301 break;
302 }
303 if (!(i2cctl & IGC_I2C_CLK_IN))
304 return IGC_ERR_I2C;
305
306 ack = igc_get_i2c_data(&i2cctl);
307 if (ack) {
308 DEBUGOUT("I2C ack was not received.\n");
309 status = IGC_ERR_I2C;
310 }
311
312 igc_lower_i2c_clk(hw, &i2cctl);
313
314 /* Minimum low period of clock is 4.7 us */
315 usec_delay(IGC_I2C_T_LOW);
316
317 return status;
318 }
319
320 /**
321 * igc_set_i2c_bb - Enable I2C bit-bang
322 * @hw: pointer to the HW structure
323 *
324 * Enable I2C bit-bang interface
325 *
326 **/
igc_set_i2c_bb(struct igc_hw * hw)327 s32 igc_set_i2c_bb(struct igc_hw *hw)
328 {
329 s32 ret_val = IGC_SUCCESS;
330 u32 ctrl_ext, i2cparams;
331
332 DEBUGFUNC("igc_set_i2c_bb");
333
334 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
335 ctrl_ext |= IGC_CTRL_I2C_ENA;
336 IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext);
337 IGC_WRITE_FLUSH(hw);
338
339 i2cparams = IGC_READ_REG(hw, IGC_I2CPARAMS);
340 i2cparams |= IGC_I2CBB_EN;
341 i2cparams |= IGC_I2C_DATA_OE_N;
342 i2cparams |= IGC_I2C_CLK_OE_N;
343 IGC_WRITE_REG(hw, IGC_I2CPARAMS, i2cparams);
344 IGC_WRITE_FLUSH(hw);
345
346 return ret_val;
347 }
348
349 /**
350 * igc_read_i2c_byte_generic - Reads 8 bit word over I2C
351 * @hw: pointer to hardware structure
352 * @byte_offset: byte offset to read
353 * @dev_addr: device address
354 * @data: value read
355 *
356 * Performs byte read operation over I2C interface at
357 * a specified device address.
358 **/
igc_read_i2c_byte_generic(struct igc_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)359 s32 igc_read_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,
360 u8 dev_addr, u8 *data)
361 {
362 s32 status = IGC_SUCCESS;
363 u32 max_retry = 10;
364 u32 retry = 1;
365 u16 swfw_mask = 0;
366
367 bool nack = true;
368
369 DEBUGFUNC("igc_read_i2c_byte_generic");
370
371 swfw_mask = IGC_SWFW_PHY0_SM;
372
373 do {
374 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
375 != IGC_SUCCESS) {
376 status = IGC_ERR_SWFW_SYNC;
377 goto read_byte_out;
378 }
379
380 igc_i2c_start(hw);
381
382 /* Device Address and write indication */
383 status = igc_clock_out_i2c_byte(hw, dev_addr);
384 if (status != IGC_SUCCESS)
385 goto fail;
386
387 status = igc_get_i2c_ack(hw);
388 if (status != IGC_SUCCESS)
389 goto fail;
390
391 status = igc_clock_out_i2c_byte(hw, byte_offset);
392 if (status != IGC_SUCCESS)
393 goto fail;
394
395 status = igc_get_i2c_ack(hw);
396 if (status != IGC_SUCCESS)
397 goto fail;
398
399 igc_i2c_start(hw);
400
401 /* Device Address and read indication */
402 status = igc_clock_out_i2c_byte(hw, (dev_addr | 0x1));
403 if (status != IGC_SUCCESS)
404 goto fail;
405
406 status = igc_get_i2c_ack(hw);
407 if (status != IGC_SUCCESS)
408 goto fail;
409
410 igc_clock_in_i2c_byte(hw, data);
411
412 status = igc_clock_out_i2c_bit(hw, nack);
413 if (status != IGC_SUCCESS)
414 goto fail;
415
416 igc_i2c_stop(hw);
417 break;
418
419 fail:
420 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
421 msec_delay(100);
422 igc_i2c_bus_clear(hw);
423 retry++;
424 if (retry < max_retry)
425 DEBUGOUT("I2C byte read error - Retrying.\n");
426 else
427 DEBUGOUT("I2C byte read error.\n");
428
429 } while (retry < max_retry);
430
431 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
432
433 read_byte_out:
434
435 return status;
436 }
437
438 /**
439 * igc_write_i2c_byte_generic - Writes 8 bit word over I2C
440 * @hw: pointer to hardware structure
441 * @byte_offset: byte offset to write
442 * @dev_addr: device address
443 * @data: value to write
444 *
445 * Performs byte write operation over I2C interface at
446 * a specified device address.
447 **/
igc_write_i2c_byte_generic(struct igc_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)448 s32 igc_write_i2c_byte_generic(struct igc_hw *hw, u8 byte_offset,
449 u8 dev_addr, u8 data)
450 {
451 s32 status = IGC_SUCCESS;
452 u32 max_retry = 1;
453 u32 retry = 0;
454 u16 swfw_mask = 0;
455
456 DEBUGFUNC("igc_write_i2c_byte_generic");
457
458 swfw_mask = IGC_SWFW_PHY0_SM;
459
460 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IGC_SUCCESS) {
461 status = IGC_ERR_SWFW_SYNC;
462 goto write_byte_out;
463 }
464
465 do {
466 igc_i2c_start(hw);
467
468 status = igc_clock_out_i2c_byte(hw, dev_addr);
469 if (status != IGC_SUCCESS)
470 goto fail;
471
472 status = igc_get_i2c_ack(hw);
473 if (status != IGC_SUCCESS)
474 goto fail;
475
476 status = igc_clock_out_i2c_byte(hw, byte_offset);
477 if (status != IGC_SUCCESS)
478 goto fail;
479
480 status = igc_get_i2c_ack(hw);
481 if (status != IGC_SUCCESS)
482 goto fail;
483
484 status = igc_clock_out_i2c_byte(hw, data);
485 if (status != IGC_SUCCESS)
486 goto fail;
487
488 status = igc_get_i2c_ack(hw);
489 if (status != IGC_SUCCESS)
490 goto fail;
491
492 igc_i2c_stop(hw);
493 break;
494
495 fail:
496 igc_i2c_bus_clear(hw);
497 retry++;
498 if (retry < max_retry)
499 DEBUGOUT("I2C byte write error - Retrying.\n");
500 else
501 DEBUGOUT("I2C byte write error.\n");
502 } while (retry < max_retry);
503
504 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
505
506 write_byte_out:
507
508 return status;
509 }
510
511 /**
512 * igc_i2c_bus_clear - Clears the I2C bus
513 * @hw: pointer to hardware structure
514 *
515 * Clears the I2C bus by sending nine clock pulses.
516 * Used when data line is stuck low.
517 **/
igc_i2c_bus_clear(struct igc_hw * hw)518 void igc_i2c_bus_clear(struct igc_hw *hw)
519 {
520 u32 i2cctl = IGC_READ_REG(hw, IGC_I2CPARAMS);
521 u32 i;
522
523 DEBUGFUNC("igc_i2c_bus_clear");
524
525 igc_i2c_start(hw);
526
527 igc_set_i2c_data(hw, &i2cctl, 1);
528
529 for (i = 0; i < 9; i++) {
530 igc_raise_i2c_clk(hw, &i2cctl);
531
532 /* Min high period of clock is 4us */
533 usec_delay(IGC_I2C_T_HIGH);
534
535 igc_lower_i2c_clk(hw, &i2cctl);
536
537 /* Min low period of clock is 4.7us*/
538 usec_delay(IGC_I2C_T_LOW);
539 }
540
541 igc_i2c_start(hw);
542
543 /* Put the i2c bus back to default state */
544 igc_i2c_stop(hw);
545 }
546
547 /**
548 * igc_init_mac_params - Initialize MAC function pointers
549 * @hw: pointer to the HW structure
550 *
551 * This function initializes the function pointers for the MAC
552 * set of functions. Called by drivers or by igc_setup_init_funcs.
553 **/
igc_init_mac_params(struct igc_hw * hw)554 s32 igc_init_mac_params(struct igc_hw *hw)
555 {
556 s32 ret_val = IGC_SUCCESS;
557
558 if (hw->mac.ops.init_params) {
559 ret_val = hw->mac.ops.init_params(hw);
560 if (ret_val) {
561 DEBUGOUT("MAC Initialization Error\n");
562 goto out;
563 }
564 } else {
565 DEBUGOUT("mac.init_mac_params was NULL\n");
566 ret_val = -IGC_ERR_CONFIG;
567 }
568
569 out:
570 return ret_val;
571 }
572
573 /**
574 * igc_init_nvm_params - Initialize NVM function pointers
575 * @hw: pointer to the HW structure
576 *
577 * This function initializes the function pointers for the NVM
578 * set of functions. Called by drivers or by igc_setup_init_funcs.
579 **/
igc_init_nvm_params(struct igc_hw * hw)580 s32 igc_init_nvm_params(struct igc_hw *hw)
581 {
582 s32 ret_val = IGC_SUCCESS;
583
584 if (hw->nvm.ops.init_params) {
585 ret_val = hw->nvm.ops.init_params(hw);
586 if (ret_val) {
587 DEBUGOUT("NVM Initialization Error\n");
588 goto out;
589 }
590 } else {
591 DEBUGOUT("nvm.init_nvm_params was NULL\n");
592 ret_val = -IGC_ERR_CONFIG;
593 }
594
595 out:
596 return ret_val;
597 }
598
599 /**
600 * igc_init_phy_params - Initialize PHY function pointers
601 * @hw: pointer to the HW structure
602 *
603 * This function initializes the function pointers for the PHY
604 * set of functions. Called by drivers or by igc_setup_init_funcs.
605 **/
igc_init_phy_params(struct igc_hw * hw)606 s32 igc_init_phy_params(struct igc_hw *hw)
607 {
608 s32 ret_val = IGC_SUCCESS;
609
610 if (hw->phy.ops.init_params) {
611 ret_val = hw->phy.ops.init_params(hw);
612 if (ret_val) {
613 DEBUGOUT("PHY Initialization Error\n");
614 goto out;
615 }
616 } else {
617 DEBUGOUT("phy.init_phy_params was NULL\n");
618 ret_val = -IGC_ERR_CONFIG;
619 }
620
621 out:
622 return ret_val;
623 }
624
625 /**
626 * igc_init_mbx_params - Initialize mailbox function pointers
627 * @hw: pointer to the HW structure
628 *
629 * This function initializes the function pointers for the PHY
630 * set of functions. Called by drivers or by igc_setup_init_funcs.
631 **/
igc_init_mbx_params(struct igc_hw * hw)632 s32 igc_init_mbx_params(struct igc_hw *hw)
633 {
634 s32 ret_val = IGC_SUCCESS;
635
636 if (hw->mbx.ops.init_params) {
637 ret_val = hw->mbx.ops.init_params(hw);
638 if (ret_val) {
639 DEBUGOUT("Mailbox Initialization Error\n");
640 goto out;
641 }
642 } else {
643 DEBUGOUT("mbx.init_mbx_params was NULL\n");
644 ret_val = -IGC_ERR_CONFIG;
645 }
646
647 out:
648 return ret_val;
649 }
650
651 /**
652 * igc_set_mac_type - Sets MAC type
653 * @hw: pointer to the HW structure
654 *
655 * This function sets the mac type of the adapter based on the
656 * device ID stored in the hw structure.
657 * MUST BE FIRST FUNCTION CALLED (explicitly or through
658 * igc_setup_init_funcs()).
659 **/
igc_set_mac_type(struct igc_hw * hw)660 s32 igc_set_mac_type(struct igc_hw *hw)
661 {
662 struct igc_mac_info *mac = &hw->mac;
663 s32 ret_val = IGC_SUCCESS;
664
665 DEBUGFUNC("igc_set_mac_type");
666
667 switch (hw->device_id) {
668 case IGC_DEV_ID_82542:
669 mac->type = igc_82542;
670 break;
671 case IGC_DEV_ID_82543GC_FIBER:
672 case IGC_DEV_ID_82543GC_COPPER:
673 mac->type = igc_82543;
674 break;
675 case IGC_DEV_ID_82544EI_COPPER:
676 case IGC_DEV_ID_82544EI_FIBER:
677 case IGC_DEV_ID_82544GC_COPPER:
678 case IGC_DEV_ID_82544GC_LOM:
679 mac->type = igc_82544;
680 break;
681 case IGC_DEV_ID_82540EM:
682 case IGC_DEV_ID_82540EM_LOM:
683 case IGC_DEV_ID_82540EP:
684 case IGC_DEV_ID_82540EP_LOM:
685 case IGC_DEV_ID_82540EP_LP:
686 mac->type = igc_82540;
687 break;
688 case IGC_DEV_ID_82545EM_COPPER:
689 case IGC_DEV_ID_82545EM_FIBER:
690 mac->type = igc_82545;
691 break;
692 case IGC_DEV_ID_82545GM_COPPER:
693 case IGC_DEV_ID_82545GM_FIBER:
694 case IGC_DEV_ID_82545GM_SERDES:
695 mac->type = igc_82545_rev_3;
696 break;
697 case IGC_DEV_ID_82546EB_COPPER:
698 case IGC_DEV_ID_82546EB_FIBER:
699 case IGC_DEV_ID_82546EB_QUAD_COPPER:
700 mac->type = igc_82546;
701 break;
702 case IGC_DEV_ID_82546GB_COPPER:
703 case IGC_DEV_ID_82546GB_FIBER:
704 case IGC_DEV_ID_82546GB_SERDES:
705 case IGC_DEV_ID_82546GB_PCIE:
706 case IGC_DEV_ID_82546GB_QUAD_COPPER:
707 case IGC_DEV_ID_82546GB_QUAD_COPPER_KSP3:
708 mac->type = igc_82546_rev_3;
709 break;
710 case IGC_DEV_ID_82541EI:
711 case IGC_DEV_ID_82541EI_MOBILE:
712 case IGC_DEV_ID_82541ER_LOM:
713 mac->type = igc_82541;
714 break;
715 case IGC_DEV_ID_82541ER:
716 case IGC_DEV_ID_82541GI:
717 case IGC_DEV_ID_82541GI_LF:
718 case IGC_DEV_ID_82541GI_MOBILE:
719 mac->type = igc_82541_rev_2;
720 break;
721 case IGC_DEV_ID_82547EI:
722 case IGC_DEV_ID_82547EI_MOBILE:
723 mac->type = igc_82547;
724 break;
725 case IGC_DEV_ID_82547GI:
726 mac->type = igc_82547_rev_2;
727 break;
728 case IGC_DEV_ID_82571EB_COPPER:
729 case IGC_DEV_ID_82571EB_FIBER:
730 case IGC_DEV_ID_82571EB_SERDES:
731 case IGC_DEV_ID_82571EB_SERDES_DUAL:
732 case IGC_DEV_ID_82571EB_SERDES_QUAD:
733 case IGC_DEV_ID_82571EB_QUAD_COPPER:
734 case IGC_DEV_ID_82571PT_QUAD_COPPER:
735 case IGC_DEV_ID_82571EB_QUAD_FIBER:
736 case IGC_DEV_ID_82571EB_QUAD_COPPER_LP:
737 mac->type = igc_82571;
738 break;
739 case IGC_DEV_ID_82572EI:
740 case IGC_DEV_ID_82572EI_COPPER:
741 case IGC_DEV_ID_82572EI_FIBER:
742 case IGC_DEV_ID_82572EI_SERDES:
743 mac->type = igc_82572;
744 break;
745 case IGC_DEV_ID_82573E:
746 case IGC_DEV_ID_82573E_IAMT:
747 case IGC_DEV_ID_82573L:
748 mac->type = igc_82573;
749 break;
750 case IGC_DEV_ID_82574L:
751 case IGC_DEV_ID_82574LA:
752 mac->type = igc_82574;
753 break;
754 case IGC_DEV_ID_82583V:
755 mac->type = igc_82583;
756 break;
757 case IGC_DEV_ID_80003ES2LAN_COPPER_DPT:
758 case IGC_DEV_ID_80003ES2LAN_SERDES_DPT:
759 case IGC_DEV_ID_80003ES2LAN_COPPER_SPT:
760 case IGC_DEV_ID_80003ES2LAN_SERDES_SPT:
761 mac->type = igc_80003es2lan;
762 break;
763 case IGC_DEV_ID_ICH8_IFE:
764 case IGC_DEV_ID_ICH8_IFE_GT:
765 case IGC_DEV_ID_ICH8_IFE_G:
766 case IGC_DEV_ID_ICH8_IGP_M:
767 case IGC_DEV_ID_ICH8_IGP_M_AMT:
768 case IGC_DEV_ID_ICH8_IGP_AMT:
769 case IGC_DEV_ID_ICH8_IGP_C:
770 case IGC_DEV_ID_ICH8_82567V_3:
771 mac->type = igc_ich8lan;
772 break;
773 case IGC_DEV_ID_ICH9_IFE:
774 case IGC_DEV_ID_ICH9_IFE_GT:
775 case IGC_DEV_ID_ICH9_IFE_G:
776 case IGC_DEV_ID_ICH9_IGP_M:
777 case IGC_DEV_ID_ICH9_IGP_M_AMT:
778 case IGC_DEV_ID_ICH9_IGP_M_V:
779 case IGC_DEV_ID_ICH9_IGP_AMT:
780 case IGC_DEV_ID_ICH9_BM:
781 case IGC_DEV_ID_ICH9_IGP_C:
782 case IGC_DEV_ID_ICH10_R_BM_LM:
783 case IGC_DEV_ID_ICH10_R_BM_LF:
784 case IGC_DEV_ID_ICH10_R_BM_V:
785 mac->type = igc_ich9lan;
786 break;
787 case IGC_DEV_ID_ICH10_D_BM_LM:
788 case IGC_DEV_ID_ICH10_D_BM_LF:
789 case IGC_DEV_ID_ICH10_D_BM_V:
790 mac->type = igc_ich10lan;
791 break;
792 case IGC_DEV_ID_PCH_D_HV_DM:
793 case IGC_DEV_ID_PCH_D_HV_DC:
794 case IGC_DEV_ID_PCH_M_HV_LM:
795 case IGC_DEV_ID_PCH_M_HV_LC:
796 mac->type = igc_pchlan;
797 break;
798 case IGC_DEV_ID_PCH2_LV_LM:
799 case IGC_DEV_ID_PCH2_LV_V:
800 mac->type = igc_pch2lan;
801 break;
802 case IGC_DEV_ID_PCH_LPT_I217_LM:
803 case IGC_DEV_ID_PCH_LPT_I217_V:
804 case IGC_DEV_ID_PCH_LPTLP_I218_LM:
805 case IGC_DEV_ID_PCH_LPTLP_I218_V:
806 case IGC_DEV_ID_PCH_I218_LM2:
807 case IGC_DEV_ID_PCH_I218_V2:
808 case IGC_DEV_ID_PCH_I218_LM3:
809 case IGC_DEV_ID_PCH_I218_V3:
810 mac->type = igc_pch_lpt;
811 break;
812 case IGC_DEV_ID_PCH_SPT_I219_LM:
813 case IGC_DEV_ID_PCH_SPT_I219_V:
814 case IGC_DEV_ID_PCH_SPT_I219_LM2:
815 case IGC_DEV_ID_PCH_SPT_I219_V2:
816 case IGC_DEV_ID_PCH_LBG_I219_LM3:
817 case IGC_DEV_ID_PCH_SPT_I219_LM4:
818 case IGC_DEV_ID_PCH_SPT_I219_V4:
819 case IGC_DEV_ID_PCH_SPT_I219_LM5:
820 case IGC_DEV_ID_PCH_SPT_I219_V5:
821 mac->type = igc_pch_spt;
822 break;
823 case IGC_DEV_ID_PCH_CNP_I219_LM6:
824 case IGC_DEV_ID_PCH_CNP_I219_V6:
825 case IGC_DEV_ID_PCH_CNP_I219_LM7:
826 case IGC_DEV_ID_PCH_CNP_I219_V7:
827 case IGC_DEV_ID_PCH_ICP_I219_LM8:
828 case IGC_DEV_ID_PCH_ICP_I219_V8:
829 case IGC_DEV_ID_PCH_ICP_I219_LM9:
830 case IGC_DEV_ID_PCH_ICP_I219_V9:
831 mac->type = igc_pch_cnp;
832 break;
833 case IGC_DEV_ID_82575EB_COPPER:
834 case IGC_DEV_ID_82575EB_FIBER_SERDES:
835 case IGC_DEV_ID_82575GB_QUAD_COPPER:
836 mac->type = igc_82575;
837 break;
838 case IGC_DEV_ID_82576:
839 case IGC_DEV_ID_82576_FIBER:
840 case IGC_DEV_ID_82576_SERDES:
841 case IGC_DEV_ID_82576_QUAD_COPPER:
842 case IGC_DEV_ID_82576_QUAD_COPPER_ET2:
843 case IGC_DEV_ID_82576_NS:
844 case IGC_DEV_ID_82576_NS_SERDES:
845 case IGC_DEV_ID_82576_SERDES_QUAD:
846 mac->type = igc_82576;
847 break;
848 case IGC_DEV_ID_82576_VF:
849 case IGC_DEV_ID_82576_VF_HV:
850 mac->type = igc_vfadapt;
851 break;
852 case IGC_DEV_ID_82580_COPPER:
853 case IGC_DEV_ID_82580_FIBER:
854 case IGC_DEV_ID_82580_SERDES:
855 case IGC_DEV_ID_82580_SGMII:
856 case IGC_DEV_ID_82580_COPPER_DUAL:
857 case IGC_DEV_ID_82580_QUAD_FIBER:
858 case IGC_DEV_ID_DH89XXCC_SGMII:
859 case IGC_DEV_ID_DH89XXCC_SERDES:
860 case IGC_DEV_ID_DH89XXCC_BACKPLANE:
861 case IGC_DEV_ID_DH89XXCC_SFP:
862 mac->type = igc_82580;
863 break;
864 case IGC_DEV_ID_I350_COPPER:
865 case IGC_DEV_ID_I350_FIBER:
866 case IGC_DEV_ID_I350_SERDES:
867 case IGC_DEV_ID_I350_SGMII:
868 case IGC_DEV_ID_I350_DA4:
869 mac->type = igc_i350;
870 break;
871 case IGC_DEV_ID_I210_COPPER_FLASHLESS:
872 case IGC_DEV_ID_I210_SERDES_FLASHLESS:
873 case IGC_DEV_ID_I210_SGMII_FLASHLESS:
874 case IGC_DEV_ID_I210_COPPER:
875 case IGC_DEV_ID_I210_COPPER_OEM1:
876 case IGC_DEV_ID_I210_COPPER_IT:
877 case IGC_DEV_ID_I210_FIBER:
878 case IGC_DEV_ID_I210_SERDES:
879 case IGC_DEV_ID_I210_SGMII:
880 mac->type = igc_i210;
881 break;
882 case IGC_DEV_ID_I211_COPPER:
883 mac->type = igc_i211;
884 break;
885 case IGC_DEV_ID_I225_LM:
886 case IGC_DEV_ID_I225_V:
887 case IGC_DEV_ID_I225_K:
888 case IGC_DEV_ID_I225_I:
889 case IGC_DEV_ID_I220_V:
890 case IGC_DEV_ID_I225_BLANK_NVM:
891 mac->type = igc_i225;
892 break;
893 case IGC_DEV_ID_I350_VF:
894 case IGC_DEV_ID_I350_VF_HV:
895 mac->type = igc_vfadapt_i350;
896 break;
897 case IGC_DEV_ID_I354_BACKPLANE_1GBPS:
898 case IGC_DEV_ID_I354_SGMII:
899 case IGC_DEV_ID_I354_BACKPLANE_2_5GBPS:
900 mac->type = igc_i354;
901 break;
902 default:
903 /* Should never have loaded on this device */
904 ret_val = -IGC_ERR_MAC_INIT;
905 break;
906 }
907
908 return ret_val;
909 }
910
911 /**
912 * igc_setup_init_funcs - Initializes function pointers
913 * @hw: pointer to the HW structure
914 * @init_device: true will initialize the rest of the function pointers
915 * getting the device ready for use. false will only set
916 * MAC type and the function pointers for the other init
917 * functions. Passing false will not generate any hardware
918 * reads or writes.
919 *
920 * This function must be called by a driver in order to use the rest
921 * of the 'shared' code files. Called by drivers only.
922 **/
igc_setup_init_funcs(struct igc_hw * hw,bool init_device)923 s32 igc_setup_init_funcs(struct igc_hw *hw, bool init_device)
924 {
925 s32 ret_val;
926
927 /* Can't do much good without knowing the MAC type. */
928 ret_val = igc_set_mac_type(hw);
929 if (ret_val) {
930 DEBUGOUT("ERROR: MAC type could not be set properly.\n");
931 goto out;
932 }
933
934 if (!hw->hw_addr) {
935 DEBUGOUT("ERROR: Registers not mapped\n");
936 ret_val = -IGC_ERR_CONFIG;
937 goto out;
938 }
939
940 /*
941 * Init function pointers to generic implementations. We do this first
942 * allowing a driver module to override it afterward.
943 */
944 igc_init_mac_ops_generic(hw);
945 igc_init_phy_ops_generic(hw);
946 igc_init_nvm_ops_generic(hw);
947
948 /*
949 * Set up the init function pointers. These are functions within the
950 * adapter family file that sets up function pointers for the rest of
951 * the functions in that family.
952 */
953 switch (hw->mac.type) {
954 case igc_i225:
955 igc_init_function_pointers_i225(hw);
956 break;
957 default:
958 DEBUGOUT("Hardware not supported\n");
959 ret_val = -IGC_ERR_CONFIG;
960 break;
961 }
962
963 /*
964 * Initialize the rest of the function pointers. These require some
965 * register reads/writes in some cases.
966 */
967 if (!(ret_val) && init_device) {
968 ret_val = igc_init_mac_params(hw);
969 if (ret_val)
970 goto out;
971
972 ret_val = igc_init_nvm_params(hw);
973 if (ret_val)
974 goto out;
975
976 ret_val = igc_init_phy_params(hw);
977 if (ret_val)
978 goto out;
979 }
980
981 out:
982 return ret_val;
983 }
984
985 /**
986 * igc_get_bus_info - Obtain bus information for adapter
987 * @hw: pointer to the HW structure
988 *
989 * This will obtain information about the HW bus for which the
990 * adapter is attached and stores it in the hw structure. This is a
991 * function pointer entry point called by drivers.
992 **/
igc_get_bus_info(struct igc_hw * hw)993 s32 igc_get_bus_info(struct igc_hw *hw)
994 {
995 if (hw->mac.ops.get_bus_info)
996 return hw->mac.ops.get_bus_info(hw);
997
998 return IGC_SUCCESS;
999 }
1000
1001 /**
1002 * igc_clear_vfta - Clear VLAN filter table
1003 * @hw: pointer to the HW structure
1004 *
1005 * This clears the VLAN filter table on the adapter. This is a function
1006 * pointer entry point called by drivers.
1007 **/
igc_clear_vfta(struct igc_hw * hw)1008 void igc_clear_vfta(struct igc_hw *hw)
1009 {
1010 if (hw->mac.ops.clear_vfta)
1011 hw->mac.ops.clear_vfta(hw);
1012 }
1013
1014 /**
1015 * igc_write_vfta - Write value to VLAN filter table
1016 * @hw: pointer to the HW structure
1017 * @offset: the 32-bit offset in which to write the value to.
1018 * @value: the 32-bit value to write at location offset.
1019 *
1020 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1021 * table. This is a function pointer entry point called by drivers.
1022 **/
igc_write_vfta(struct igc_hw * hw,u32 offset,u32 value)1023 void igc_write_vfta(struct igc_hw *hw, u32 offset, u32 value)
1024 {
1025 if (hw->mac.ops.write_vfta)
1026 hw->mac.ops.write_vfta(hw, offset, value);
1027 }
1028
1029 /**
1030 * igc_update_mc_addr_list - Update Multicast addresses
1031 * @hw: pointer to the HW structure
1032 * @mc_addr_list: array of multicast addresses to program
1033 * @mc_addr_count: number of multicast addresses to program
1034 *
1035 * Updates the Multicast Table Array.
1036 * The caller must have a packed mc_addr_list of multicast addresses.
1037 **/
igc_update_mc_addr_list(struct igc_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)1038 void igc_update_mc_addr_list(struct igc_hw *hw, u8 *mc_addr_list,
1039 u32 mc_addr_count)
1040 {
1041 if (hw->mac.ops.update_mc_addr_list)
1042 hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
1043 mc_addr_count);
1044 }
1045
1046 /**
1047 * igc_force_mac_fc - Force MAC flow control
1048 * @hw: pointer to the HW structure
1049 *
1050 * Force the MAC's flow control settings. Currently no func pointer exists
1051 * and all implementations are handled in the generic version of this
1052 * function.
1053 **/
igc_force_mac_fc(struct igc_hw * hw)1054 s32 igc_force_mac_fc(struct igc_hw *hw)
1055 {
1056 return igc_force_mac_fc_generic(hw);
1057 }
1058
1059 /**
1060 * igc_check_for_link - Check/Store link connection
1061 * @hw: pointer to the HW structure
1062 *
1063 * This checks the link condition of the adapter and stores the
1064 * results in the hw->mac structure. This is a function pointer entry
1065 * point called by drivers.
1066 **/
igc_check_for_link(struct igc_hw * hw)1067 s32 igc_check_for_link(struct igc_hw *hw)
1068 {
1069 if (hw->mac.ops.check_for_link)
1070 return hw->mac.ops.check_for_link(hw);
1071
1072 return -IGC_ERR_CONFIG;
1073 }
1074
1075 /**
1076 * igc_check_mng_mode - Check management mode
1077 * @hw: pointer to the HW structure
1078 *
1079 * This checks if the adapter has manageability enabled.
1080 * This is a function pointer entry point called by drivers.
1081 **/
igc_check_mng_mode(struct igc_hw * hw)1082 bool igc_check_mng_mode(struct igc_hw *hw)
1083 {
1084 if (hw->mac.ops.check_mng_mode)
1085 return hw->mac.ops.check_mng_mode(hw);
1086
1087 return false;
1088 }
1089
1090 /**
1091 * igc_mng_write_dhcp_info - Writes DHCP info to host interface
1092 * @hw: pointer to the HW structure
1093 * @buffer: pointer to the host interface
1094 * @length: size of the buffer
1095 *
1096 * Writes the DHCP information to the host interface.
1097 **/
igc_mng_write_dhcp_info(struct igc_hw * hw,u8 * buffer,u16 length)1098 s32 igc_mng_write_dhcp_info(struct igc_hw *hw, u8 *buffer, u16 length)
1099 {
1100 return igc_mng_write_dhcp_info_generic(hw, buffer, length);
1101 }
1102
1103 /**
1104 * igc_reset_hw - Reset hardware
1105 * @hw: pointer to the HW structure
1106 *
1107 * This resets the hardware into a known state. This is a function pointer
1108 * entry point called by drivers.
1109 **/
igc_reset_hw(struct igc_hw * hw)1110 s32 igc_reset_hw(struct igc_hw *hw)
1111 {
1112 if (hw->mac.ops.reset_hw)
1113 return hw->mac.ops.reset_hw(hw);
1114
1115 return -IGC_ERR_CONFIG;
1116 }
1117
1118 /**
1119 * igc_init_hw - Initialize hardware
1120 * @hw: pointer to the HW structure
1121 *
1122 * This inits the hardware readying it for operation. This is a function
1123 * pointer entry point called by drivers.
1124 **/
igc_init_hw(struct igc_hw * hw)1125 s32 igc_init_hw(struct igc_hw *hw)
1126 {
1127 if (hw->mac.ops.init_hw)
1128 return hw->mac.ops.init_hw(hw);
1129
1130 return -IGC_ERR_CONFIG;
1131 }
1132
1133 /**
1134 * igc_setup_link - Configures link and flow control
1135 * @hw: pointer to the HW structure
1136 *
1137 * This configures link and flow control settings for the adapter. This
1138 * is a function pointer entry point called by drivers. While modules can
1139 * also call this, they probably call their own version of this function.
1140 **/
igc_setup_link(struct igc_hw * hw)1141 s32 igc_setup_link(struct igc_hw *hw)
1142 {
1143 if (hw->mac.ops.setup_link)
1144 return hw->mac.ops.setup_link(hw);
1145
1146 return -IGC_ERR_CONFIG;
1147 }
1148
1149 /**
1150 * igc_get_speed_and_duplex - Returns current speed and duplex
1151 * @hw: pointer to the HW structure
1152 * @speed: pointer to a 16-bit value to store the speed
1153 * @duplex: pointer to a 16-bit value to store the duplex.
1154 *
1155 * This returns the speed and duplex of the adapter in the two 'out'
1156 * variables passed in. This is a function pointer entry point called
1157 * by drivers.
1158 **/
igc_get_speed_and_duplex(struct igc_hw * hw,u16 * speed,u16 * duplex)1159 s32 igc_get_speed_and_duplex(struct igc_hw *hw, u16 *speed, u16 *duplex)
1160 {
1161 if (hw->mac.ops.get_link_up_info)
1162 return hw->mac.ops.get_link_up_info(hw, speed, duplex);
1163
1164 return -IGC_ERR_CONFIG;
1165 }
1166
1167 /**
1168 * igc_setup_led - Configures SW controllable LED
1169 * @hw: pointer to the HW structure
1170 *
1171 * This prepares the SW controllable LED for use and saves the current state
1172 * of the LED so it can be later restored. This is a function pointer entry
1173 * point called by drivers.
1174 **/
igc_setup_led(struct igc_hw * hw)1175 s32 igc_setup_led(struct igc_hw *hw)
1176 {
1177 if (hw->mac.ops.setup_led)
1178 return hw->mac.ops.setup_led(hw);
1179
1180 return IGC_SUCCESS;
1181 }
1182
1183 /**
1184 * igc_cleanup_led - Restores SW controllable LED
1185 * @hw: pointer to the HW structure
1186 *
1187 * This restores the SW controllable LED to the value saved off by
1188 * igc_setup_led. This is a function pointer entry point called by drivers.
1189 **/
igc_cleanup_led(struct igc_hw * hw)1190 s32 igc_cleanup_led(struct igc_hw *hw)
1191 {
1192 if (hw->mac.ops.cleanup_led)
1193 return hw->mac.ops.cleanup_led(hw);
1194
1195 return IGC_SUCCESS;
1196 }
1197
1198 /**
1199 * igc_blink_led - Blink SW controllable LED
1200 * @hw: pointer to the HW structure
1201 *
1202 * This starts the adapter LED blinking. Request the LED to be setup first
1203 * and cleaned up after. This is a function pointer entry point called by
1204 * drivers.
1205 **/
igc_blink_led(struct igc_hw * hw)1206 s32 igc_blink_led(struct igc_hw *hw)
1207 {
1208 if (hw->mac.ops.blink_led)
1209 return hw->mac.ops.blink_led(hw);
1210
1211 return IGC_SUCCESS;
1212 }
1213
1214 /**
1215 * igc_id_led_init - store LED configurations in SW
1216 * @hw: pointer to the HW structure
1217 *
1218 * Initializes the LED config in SW. This is a function pointer entry point
1219 * called by drivers.
1220 **/
igc_id_led_init(struct igc_hw * hw)1221 s32 igc_id_led_init(struct igc_hw *hw)
1222 {
1223 if (hw->mac.ops.id_led_init)
1224 return hw->mac.ops.id_led_init(hw);
1225
1226 return IGC_SUCCESS;
1227 }
1228
1229 /**
1230 * igc_led_on - Turn on SW controllable LED
1231 * @hw: pointer to the HW structure
1232 *
1233 * Turns the SW defined LED on. This is a function pointer entry point
1234 * called by drivers.
1235 **/
igc_led_on(struct igc_hw * hw)1236 s32 igc_led_on(struct igc_hw *hw)
1237 {
1238 if (hw->mac.ops.led_on)
1239 return hw->mac.ops.led_on(hw);
1240
1241 return IGC_SUCCESS;
1242 }
1243
1244 /**
1245 * igc_led_off - Turn off SW controllable LED
1246 * @hw: pointer to the HW structure
1247 *
1248 * Turns the SW defined LED off. This is a function pointer entry point
1249 * called by drivers.
1250 **/
igc_led_off(struct igc_hw * hw)1251 s32 igc_led_off(struct igc_hw *hw)
1252 {
1253 if (hw->mac.ops.led_off)
1254 return hw->mac.ops.led_off(hw);
1255
1256 return IGC_SUCCESS;
1257 }
1258
1259 /**
1260 * igc_reset_adaptive - Reset adaptive IFS
1261 * @hw: pointer to the HW structure
1262 *
1263 * Resets the adaptive IFS. Currently no func pointer exists and all
1264 * implementations are handled in the generic version of this function.
1265 **/
igc_reset_adaptive(struct igc_hw * hw)1266 void igc_reset_adaptive(struct igc_hw *hw)
1267 {
1268 igc_reset_adaptive_generic(hw);
1269 }
1270
1271 /**
1272 * igc_update_adaptive - Update adaptive IFS
1273 * @hw: pointer to the HW structure
1274 *
1275 * Updates adapter IFS. Currently no func pointer exists and all
1276 * implementations are handled in the generic version of this function.
1277 **/
igc_update_adaptive(struct igc_hw * hw)1278 void igc_update_adaptive(struct igc_hw *hw)
1279 {
1280 igc_update_adaptive_generic(hw);
1281 }
1282
1283 /**
1284 * igc_disable_pcie_master - Disable PCI-Express master access
1285 * @hw: pointer to the HW structure
1286 *
1287 * Disables PCI-Express master access and verifies there are no pending
1288 * requests. Currently no func pointer exists and all implementations are
1289 * handled in the generic version of this function.
1290 **/
igc_disable_pcie_master(struct igc_hw * hw)1291 s32 igc_disable_pcie_master(struct igc_hw *hw)
1292 {
1293 return igc_disable_pcie_master_generic(hw);
1294 }
1295
1296 /**
1297 * igc_config_collision_dist - Configure collision distance
1298 * @hw: pointer to the HW structure
1299 *
1300 * Configures the collision distance to the default value and is used
1301 * during link setup.
1302 **/
igc_config_collision_dist(struct igc_hw * hw)1303 void igc_config_collision_dist(struct igc_hw *hw)
1304 {
1305 if (hw->mac.ops.config_collision_dist)
1306 hw->mac.ops.config_collision_dist(hw);
1307 }
1308
1309 /**
1310 * igc_rar_set - Sets a receive address register
1311 * @hw: pointer to the HW structure
1312 * @addr: address to set the RAR to
1313 * @index: the RAR to set
1314 *
1315 * Sets a Receive Address Register (RAR) to the specified address.
1316 **/
igc_rar_set(struct igc_hw * hw,u8 * addr,u32 index)1317 int igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
1318 {
1319 if (hw->mac.ops.rar_set)
1320 return hw->mac.ops.rar_set(hw, addr, index);
1321
1322 return IGC_SUCCESS;
1323 }
1324
1325 /**
1326 * igc_validate_mdi_setting - Ensures valid MDI/MDIX SW state
1327 * @hw: pointer to the HW structure
1328 *
1329 * Ensures that the MDI/MDIX SW state is valid.
1330 **/
igc_validate_mdi_setting(struct igc_hw * hw)1331 s32 igc_validate_mdi_setting(struct igc_hw *hw)
1332 {
1333 if (hw->mac.ops.validate_mdi_setting)
1334 return hw->mac.ops.validate_mdi_setting(hw);
1335
1336 return IGC_SUCCESS;
1337 }
1338
1339 /**
1340 * igc_hash_mc_addr - Determines address location in multicast table
1341 * @hw: pointer to the HW structure
1342 * @mc_addr: Multicast address to hash.
1343 *
1344 * This hashes an address to determine its location in the multicast
1345 * table. Currently no func pointer exists and all implementations
1346 * are handled in the generic version of this function.
1347 **/
igc_hash_mc_addr(struct igc_hw * hw,u8 * mc_addr)1348 u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)
1349 {
1350 return igc_hash_mc_addr_generic(hw, mc_addr);
1351 }
1352
1353 /**
1354 * igc_enable_tx_pkt_filtering - Enable packet filtering on TX
1355 * @hw: pointer to the HW structure
1356 *
1357 * Enables packet filtering on transmit packets if manageability is enabled
1358 * and host interface is enabled.
1359 * Currently no func pointer exists and all implementations are handled in the
1360 * generic version of this function.
1361 **/
igc_enable_tx_pkt_filtering(struct igc_hw * hw)1362 bool igc_enable_tx_pkt_filtering(struct igc_hw *hw)
1363 {
1364 return igc_enable_tx_pkt_filtering_generic(hw);
1365 }
1366
1367 /**
1368 * igc_mng_host_if_write - Writes to the manageability host interface
1369 * @hw: pointer to the HW structure
1370 * @buffer: pointer to the host interface buffer
1371 * @length: size of the buffer
1372 * @offset: location in the buffer to write to
1373 * @sum: sum of the data (not checksum)
1374 *
1375 * This function writes the buffer content at the offset given on the host if.
1376 * It also does alignment considerations to do the writes in most efficient
1377 * way. Also fills up the sum of the buffer in *buffer parameter.
1378 **/
igc_mng_host_if_write(struct igc_hw * hw,u8 * buffer,u16 length,u16 offset,u8 * sum)1379 s32 igc_mng_host_if_write(struct igc_hw *hw, u8 *buffer, u16 length,
1380 u16 offset, u8 *sum)
1381 {
1382 return igc_mng_host_if_write_generic(hw, buffer, length, offset, sum);
1383 }
1384
1385 /**
1386 * igc_mng_write_cmd_header - Writes manageability command header
1387 * @hw: pointer to the HW structure
1388 * @hdr: pointer to the host interface command header
1389 *
1390 * Writes the command header after does the checksum calculation.
1391 **/
igc_mng_write_cmd_header(struct igc_hw * hw,struct igc_host_mng_command_header * hdr)1392 s32 igc_mng_write_cmd_header(struct igc_hw *hw,
1393 struct igc_host_mng_command_header *hdr)
1394 {
1395 return igc_mng_write_cmd_header_generic(hw, hdr);
1396 }
1397
1398 /**
1399 * igc_mng_enable_host_if - Checks host interface is enabled
1400 * @hw: pointer to the HW structure
1401 *
1402 * Returns IGC_success upon success, else IGC_ERR_HOST_INTERFACE_COMMAND
1403 *
1404 * This function checks whether the HOST IF is enabled for command operation
1405 * and also checks whether the previous command is completed. It busy waits
1406 * in case of previous command is not completed.
1407 **/
igc_mng_enable_host_if(struct igc_hw * hw)1408 s32 igc_mng_enable_host_if(struct igc_hw *hw)
1409 {
1410 return igc_mng_enable_host_if_generic(hw);
1411 }
1412
1413 /**
1414 * igc_check_reset_block - Verifies PHY can be reset
1415 * @hw: pointer to the HW structure
1416 *
1417 * Checks if the PHY is in a state that can be reset or if manageability
1418 * has it tied up. This is a function pointer entry point called by drivers.
1419 **/
igc_check_reset_block(struct igc_hw * hw)1420 s32 igc_check_reset_block(struct igc_hw *hw)
1421 {
1422 if (hw->phy.ops.check_reset_block)
1423 return hw->phy.ops.check_reset_block(hw);
1424
1425 return IGC_SUCCESS;
1426 }
1427
1428 /**
1429 * igc_read_phy_reg - Reads PHY register
1430 * @hw: pointer to the HW structure
1431 * @offset: the register to read
1432 * @data: the buffer to store the 16-bit read.
1433 *
1434 * Reads the PHY register and returns the value in data.
1435 * This is a function pointer entry point called by drivers.
1436 **/
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)1437 s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
1438 {
1439 if (hw->phy.ops.read_reg)
1440 return hw->phy.ops.read_reg(hw, offset, data);
1441
1442 return IGC_SUCCESS;
1443 }
1444
1445 /**
1446 * igc_write_phy_reg - Writes PHY register
1447 * @hw: pointer to the HW structure
1448 * @offset: the register to write
1449 * @data: the value to write.
1450 *
1451 * Writes the PHY register at offset with the value in data.
1452 * This is a function pointer entry point called by drivers.
1453 **/
igc_write_phy_reg(struct igc_hw * hw,u32 offset,u16 data)1454 s32 igc_write_phy_reg(struct igc_hw *hw, u32 offset, u16 data)
1455 {
1456 if (hw->phy.ops.write_reg)
1457 return hw->phy.ops.write_reg(hw, offset, data);
1458
1459 return IGC_SUCCESS;
1460 }
1461
1462 /**
1463 * igc_release_phy - Generic release PHY
1464 * @hw: pointer to the HW structure
1465 *
1466 * Return if silicon family does not require a semaphore when accessing the
1467 * PHY.
1468 **/
igc_release_phy(struct igc_hw * hw)1469 void igc_release_phy(struct igc_hw *hw)
1470 {
1471 if (hw->phy.ops.release)
1472 hw->phy.ops.release(hw);
1473 }
1474
1475 /**
1476 * igc_acquire_phy - Generic acquire PHY
1477 * @hw: pointer to the HW structure
1478 *
1479 * Return success if silicon family does not require a semaphore when
1480 * accessing the PHY.
1481 **/
igc_acquire_phy(struct igc_hw * hw)1482 s32 igc_acquire_phy(struct igc_hw *hw)
1483 {
1484 if (hw->phy.ops.acquire)
1485 return hw->phy.ops.acquire(hw);
1486
1487 return IGC_SUCCESS;
1488 }
1489
1490 /**
1491 * igc_cfg_on_link_up - Configure PHY upon link up
1492 * @hw: pointer to the HW structure
1493 **/
igc_cfg_on_link_up(struct igc_hw * hw)1494 s32 igc_cfg_on_link_up(struct igc_hw *hw)
1495 {
1496 if (hw->phy.ops.cfg_on_link_up)
1497 return hw->phy.ops.cfg_on_link_up(hw);
1498
1499 return IGC_SUCCESS;
1500 }
1501
1502 /**
1503 * igc_read_kmrn_reg - Reads register using Kumeran interface
1504 * @hw: pointer to the HW structure
1505 * @offset: the register to read
1506 * @data: the location to store the 16-bit value read.
1507 *
1508 * Reads a register out of the Kumeran interface. Currently no func pointer
1509 * exists and all implementations are handled in the generic version of
1510 * this function.
1511 **/
igc_read_kmrn_reg(struct igc_hw * hw,u32 offset,u16 * data)1512 s32 igc_read_kmrn_reg(struct igc_hw *hw, u32 offset, u16 *data)
1513 {
1514 return igc_read_kmrn_reg_generic(hw, offset, data);
1515 }
1516
1517 /**
1518 * igc_write_kmrn_reg - Writes register using Kumeran interface
1519 * @hw: pointer to the HW structure
1520 * @offset: the register to write
1521 * @data: the value to write.
1522 *
1523 * Writes a register to the Kumeran interface. Currently no func pointer
1524 * exists and all implementations are handled in the generic version of
1525 * this function.
1526 **/
igc_write_kmrn_reg(struct igc_hw * hw,u32 offset,u16 data)1527 s32 igc_write_kmrn_reg(struct igc_hw *hw, u32 offset, u16 data)
1528 {
1529 return igc_write_kmrn_reg_generic(hw, offset, data);
1530 }
1531
1532 /**
1533 * igc_get_cable_length - Retrieves cable length estimation
1534 * @hw: pointer to the HW structure
1535 *
1536 * This function estimates the cable length and stores them in
1537 * hw->phy.min_length and hw->phy.max_length. This is a function pointer
1538 * entry point called by drivers.
1539 **/
igc_get_cable_length(struct igc_hw * hw)1540 s32 igc_get_cable_length(struct igc_hw *hw)
1541 {
1542 if (hw->phy.ops.get_cable_length)
1543 return hw->phy.ops.get_cable_length(hw);
1544
1545 return IGC_SUCCESS;
1546 }
1547
1548 /**
1549 * igc_get_phy_info - Retrieves PHY information from registers
1550 * @hw: pointer to the HW structure
1551 *
1552 * This function gets some information from various PHY registers and
1553 * populates hw->phy values with it. This is a function pointer entry
1554 * point called by drivers.
1555 **/
igc_get_phy_info(struct igc_hw * hw)1556 s32 igc_get_phy_info(struct igc_hw *hw)
1557 {
1558 if (hw->phy.ops.get_info)
1559 return hw->phy.ops.get_info(hw);
1560
1561 return IGC_SUCCESS;
1562 }
1563
1564 /**
1565 * igc_phy_hw_reset - Hard PHY reset
1566 * @hw: pointer to the HW structure
1567 *
1568 * Performs a hard PHY reset. This is a function pointer entry point called
1569 * by drivers.
1570 **/
igc_phy_hw_reset(struct igc_hw * hw)1571 s32 igc_phy_hw_reset(struct igc_hw *hw)
1572 {
1573 if (hw->phy.ops.reset)
1574 return hw->phy.ops.reset(hw);
1575
1576 return IGC_SUCCESS;
1577 }
1578
1579 /**
1580 * igc_phy_commit - Soft PHY reset
1581 * @hw: pointer to the HW structure
1582 *
1583 * Performs a soft PHY reset on those that apply. This is a function pointer
1584 * entry point called by drivers.
1585 **/
igc_phy_commit(struct igc_hw * hw)1586 s32 igc_phy_commit(struct igc_hw *hw)
1587 {
1588 if (hw->phy.ops.commit)
1589 return hw->phy.ops.commit(hw);
1590
1591 return IGC_SUCCESS;
1592 }
1593
1594 /**
1595 * igc_set_d0_lplu_state - Sets low power link up state for D0
1596 * @hw: pointer to the HW structure
1597 * @active: boolean used to enable/disable lplu
1598 *
1599 * Success returns 0, Failure returns 1
1600 *
1601 * The low power link up (lplu) state is set to the power management level D0
1602 * and SmartSpeed is disabled when active is true, else clear lplu for D0
1603 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1604 * is used during Dx states where the power conservation is most important.
1605 * During driver activity, SmartSpeed should be enabled so performance is
1606 * maintained. This is a function pointer entry point called by drivers.
1607 **/
igc_set_d0_lplu_state(struct igc_hw * hw,bool active)1608 s32 igc_set_d0_lplu_state(struct igc_hw *hw, bool active)
1609 {
1610 if (hw->phy.ops.set_d0_lplu_state)
1611 return hw->phy.ops.set_d0_lplu_state(hw, active);
1612
1613 return IGC_SUCCESS;
1614 }
1615
1616 /**
1617 * igc_set_d3_lplu_state - Sets low power link up state for D3
1618 * @hw: pointer to the HW structure
1619 * @active: boolean used to enable/disable lplu
1620 *
1621 * Success returns 0, Failure returns 1
1622 *
1623 * The low power link up (lplu) state is set to the power management level D3
1624 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1625 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1626 * is used during Dx states where the power conservation is most important.
1627 * During driver activity, SmartSpeed should be enabled so performance is
1628 * maintained. This is a function pointer entry point called by drivers.
1629 **/
igc_set_d3_lplu_state(struct igc_hw * hw,bool active)1630 s32 igc_set_d3_lplu_state(struct igc_hw *hw, bool active)
1631 {
1632 if (hw->phy.ops.set_d3_lplu_state)
1633 return hw->phy.ops.set_d3_lplu_state(hw, active);
1634
1635 return IGC_SUCCESS;
1636 }
1637
1638 /**
1639 * igc_read_mac_addr - Reads MAC address
1640 * @hw: pointer to the HW structure
1641 *
1642 * Reads the MAC address out of the adapter and stores it in the HW structure.
1643 * Currently no func pointer exists and all implementations are handled in the
1644 * generic version of this function.
1645 **/
igc_read_mac_addr(struct igc_hw * hw)1646 s32 igc_read_mac_addr(struct igc_hw *hw)
1647 {
1648 if (hw->mac.ops.read_mac_addr)
1649 return hw->mac.ops.read_mac_addr(hw);
1650
1651 return igc_read_mac_addr_generic(hw);
1652 }
1653
1654 /**
1655 * igc_read_pba_string - Read device part number string
1656 * @hw: pointer to the HW structure
1657 * @pba_num: pointer to device part number
1658 * @pba_num_size: size of part number buffer
1659 *
1660 * Reads the product board assembly (PBA) number from the EEPROM and stores
1661 * the value in pba_num.
1662 * Currently no func pointer exists and all implementations are handled in the
1663 * generic version of this function.
1664 **/
igc_read_pba_string(struct igc_hw * hw,u8 * pba_num,u32 pba_num_size)1665 s32 igc_read_pba_string(struct igc_hw *hw, u8 *pba_num, u32 pba_num_size)
1666 {
1667 return igc_read_pba_string_generic(hw, pba_num, pba_num_size);
1668 }
1669
1670 /**
1671 * igc_read_pba_length - Read device part number string length
1672 * @hw: pointer to the HW structure
1673 * @pba_num_size: size of part number buffer
1674 *
1675 * Reads the product board assembly (PBA) number length from the EEPROM and
1676 * stores the value in pba_num.
1677 * Currently no func pointer exists and all implementations are handled in the
1678 * generic version of this function.
1679 **/
igc_read_pba_length(struct igc_hw * hw,u32 * pba_num_size)1680 s32 igc_read_pba_length(struct igc_hw *hw, u32 *pba_num_size)
1681 {
1682 return igc_read_pba_length_generic(hw, pba_num_size);
1683 }
1684
1685 /**
1686 * igc_read_pba_num - Read device part number
1687 * @hw: pointer to the HW structure
1688 * @pba_num: pointer to device part number
1689 *
1690 * Reads the product board assembly (PBA) number from the EEPROM and stores
1691 * the value in pba_num.
1692 * Currently no func pointer exists and all implementations are handled in the
1693 * generic version of this function.
1694 **/
igc_read_pba_num(struct igc_hw * hw,u32 * pba_num)1695 s32 igc_read_pba_num(struct igc_hw *hw, u32 *pba_num)
1696 {
1697 return igc_read_pba_num_generic(hw, pba_num);
1698 }
1699
1700 /**
1701 * igc_validate_nvm_checksum - Verifies NVM (EEPROM) checksum
1702 * @hw: pointer to the HW structure
1703 *
1704 * Validates the NVM checksum is correct. This is a function pointer entry
1705 * point called by drivers.
1706 **/
igc_validate_nvm_checksum(struct igc_hw * hw)1707 s32 igc_validate_nvm_checksum(struct igc_hw *hw)
1708 {
1709 if (hw->nvm.ops.validate)
1710 return hw->nvm.ops.validate(hw);
1711
1712 return -IGC_ERR_CONFIG;
1713 }
1714
1715 /**
1716 * igc_update_nvm_checksum - Updates NVM (EEPROM) checksum
1717 * @hw: pointer to the HW structure
1718 *
1719 * Updates the NVM checksum. Currently no func pointer exists and all
1720 * implementations are handled in the generic version of this function.
1721 **/
igc_update_nvm_checksum(struct igc_hw * hw)1722 s32 igc_update_nvm_checksum(struct igc_hw *hw)
1723 {
1724 if (hw->nvm.ops.update)
1725 return hw->nvm.ops.update(hw);
1726
1727 return -IGC_ERR_CONFIG;
1728 }
1729
1730 /**
1731 * igc_reload_nvm - Reloads EEPROM
1732 * @hw: pointer to the HW structure
1733 *
1734 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1735 * extended control register.
1736 **/
igc_reload_nvm(struct igc_hw * hw)1737 void igc_reload_nvm(struct igc_hw *hw)
1738 {
1739 if (hw->nvm.ops.reload)
1740 hw->nvm.ops.reload(hw);
1741 }
1742
1743 /**
1744 * igc_read_nvm - Reads NVM (EEPROM)
1745 * @hw: pointer to the HW structure
1746 * @offset: the word offset to read
1747 * @words: number of 16-bit words to read
1748 * @data: pointer to the properly sized buffer for the data.
1749 *
1750 * Reads 16-bit chunks of data from the NVM (EEPROM). This is a function
1751 * pointer entry point called by drivers.
1752 **/
igc_read_nvm(struct igc_hw * hw,u16 offset,u16 words,u16 * data)1753 s32 igc_read_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
1754 {
1755 if (hw->nvm.ops.read)
1756 return hw->nvm.ops.read(hw, offset, words, data);
1757
1758 return -IGC_ERR_CONFIG;
1759 }
1760
1761 /**
1762 * igc_write_nvm - Writes to NVM (EEPROM)
1763 * @hw: pointer to the HW structure
1764 * @offset: the word offset to read
1765 * @words: number of 16-bit words to write
1766 * @data: pointer to the properly sized buffer for the data.
1767 *
1768 * Writes 16-bit chunks of data to the NVM (EEPROM). This is a function
1769 * pointer entry point called by drivers.
1770 **/
igc_write_nvm(struct igc_hw * hw,u16 offset,u16 words,u16 * data)1771 s32 igc_write_nvm(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
1772 {
1773 if (hw->nvm.ops.write)
1774 return hw->nvm.ops.write(hw, offset, words, data);
1775
1776 return IGC_SUCCESS;
1777 }
1778
1779 /**
1780 * igc_write_8bit_ctrl_reg - Writes 8bit Control register
1781 * @hw: pointer to the HW structure
1782 * @reg: 32bit register offset
1783 * @offset: the register to write
1784 * @data: the value to write.
1785 *
1786 * Writes the PHY register at offset with the value in data.
1787 * This is a function pointer entry point called by drivers.
1788 **/
igc_write_8bit_ctrl_reg(struct igc_hw * hw,u32 reg,u32 offset,u8 data)1789 s32 igc_write_8bit_ctrl_reg(struct igc_hw *hw, u32 reg, u32 offset,
1790 u8 data)
1791 {
1792 return igc_write_8bit_ctrl_reg_generic(hw, reg, offset, data);
1793 }
1794
1795 /**
1796 * igc_power_up_phy - Restores link in case of PHY power down
1797 * @hw: pointer to the HW structure
1798 *
1799 * The phy may be powered down to save power, to turn off link when the
1800 * driver is unloaded, or wake on lan is not enabled (among others).
1801 **/
igc_power_up_phy(struct igc_hw * hw)1802 void igc_power_up_phy(struct igc_hw *hw)
1803 {
1804 if (hw->phy.ops.power_up)
1805 hw->phy.ops.power_up(hw);
1806
1807 igc_setup_link(hw);
1808 }
1809
1810 /**
1811 * igc_power_down_phy - Power down PHY
1812 * @hw: pointer to the HW structure
1813 *
1814 * The phy may be powered down to save power, to turn off link when the
1815 * driver is unloaded, or wake on lan is not enabled (among others).
1816 **/
igc_power_down_phy(struct igc_hw * hw)1817 void igc_power_down_phy(struct igc_hw *hw)
1818 {
1819 if (hw->phy.ops.power_down)
1820 hw->phy.ops.power_down(hw);
1821 }
1822
1823 /**
1824 * igc_power_up_fiber_serdes_link - Power up serdes link
1825 * @hw: pointer to the HW structure
1826 *
1827 * Power on the optics and PCS.
1828 **/
igc_power_up_fiber_serdes_link(struct igc_hw * hw)1829 void igc_power_up_fiber_serdes_link(struct igc_hw *hw)
1830 {
1831 if (hw->mac.ops.power_up_serdes)
1832 hw->mac.ops.power_up_serdes(hw);
1833 }
1834
1835 /**
1836 * igc_shutdown_fiber_serdes_link - Remove link during power down
1837 * @hw: pointer to the HW structure
1838 *
1839 * Shutdown the optics and PCS on driver unload.
1840 **/
igc_shutdown_fiber_serdes_link(struct igc_hw * hw)1841 void igc_shutdown_fiber_serdes_link(struct igc_hw *hw)
1842 {
1843 if (hw->mac.ops.shutdown_serdes)
1844 hw->mac.ops.shutdown_serdes(hw);
1845 }
1846