1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _ICE_NVM_H_ 6 #define _ICE_NVM_H_ 7 8 #define ICE_NVM_CMD_READ 0x0000000B 9 #define ICE_NVM_CMD_WRITE 0x0000000C 10 11 /* NVM Access config bits */ 12 #define ICE_NVM_CFG_MODULE_M MAKEMASK(0xFF, 0) 13 #define ICE_NVM_CFG_MODULE_S 0 14 #define ICE_NVM_CFG_FLAGS_M MAKEMASK(0xF, 8) 15 #define ICE_NVM_CFG_FLAGS_S 8 16 #define ICE_NVM_CFG_EXT_FLAGS_M MAKEMASK(0xF, 12) 17 #define ICE_NVM_CFG_EXT_FLAGS_S 12 18 #define ICE_NVM_CFG_ADAPTER_INFO_M MAKEMASK(0xFFFF, 16) 19 #define ICE_NVM_CFG_ADAPTER_INFO_S 16 20 21 /* NVM Read Get Driver Features */ 22 #define ICE_NVM_GET_FEATURES_MODULE 0xE 23 #define ICE_NVM_GET_FEATURES_FLAGS 0xF 24 25 /* NVM Read/Write Mapped Space */ 26 #define ICE_NVM_REG_RW_MODULE 0x0 27 #define ICE_NVM_REG_RW_FLAGS 0x1 28 29 #define ICE_NVM_ACCESS_MAJOR_VER 0 30 #define ICE_NVM_ACCESS_MINOR_VER 5 31 32 /* NVM Access feature flags. Other bits in the features field are reserved and 33 * should be set to zero when reporting the ice_nvm_features structure. 34 */ 35 #define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1) 36 37 /* NVM Access Features */ 38 struct ice_nvm_features { 39 u8 major; /* Major version (informational only) */ 40 u8 minor; /* Minor version (informational only) */ 41 u16 size; /* size of ice_nvm_features structure */ 42 u8 features[12]; /* Array of feature bits */ 43 }; 44 45 /* NVM Access command */ 46 struct ice_nvm_access_cmd { 47 u32 command; /* NVM command: READ or WRITE */ 48 u32 config; /* NVM command configuration */ 49 u32 offset; /* offset to read/write, in bytes */ 50 u32 data_size; /* size of data field, in bytes */ 51 }; 52 53 /* NVM Access data */ 54 union ice_nvm_access_data { 55 u32 regval; /* Storage for register value */ 56 struct ice_nvm_features drv_features; /* NVM features */ 57 }; 58 59 /* NVM Access registers */ 60 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4)) 61 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4)) 62 #define GL_HICR 0x00082040 63 #define GL_HICR_EN 0x00082044 64 #define GLGEN_CSR_DEBUG_C 0x00075750 65 #define GLPCI_LBARCTRL 0x0009DE74 66 #define GLNVM_GENS 0x000B6100 67 #define GLNVM_FLA 0x000B6108 68 69 #define ICE_NVM_ACCESS_GL_HIDA_MAX 15 70 #define ICE_NVM_ACCESS_GL_HIBA_MAX 1023 71 72 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd); 73 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd); 74 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd); 75 enum ice_status 76 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd, 77 union ice_nvm_access_data *data); 78 enum ice_status 79 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd, 80 union ice_nvm_access_data *data); 81 enum ice_status 82 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd, 83 union ice_nvm_access_data *data); 84 enum ice_status 85 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd, 86 union ice_nvm_access_data *data); 87 enum ice_status 88 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access); 89 void ice_release_nvm(struct ice_hw *hw); 90 enum ice_status 91 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length, 92 void *data, bool last_command, bool read_shadow_ram, 93 struct ice_sq_cd *cd); 94 enum ice_status 95 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data, 96 bool read_shadow_ram); 97 enum ice_status 98 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len, 99 u16 module_type); 100 enum ice_status 101 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size); 102 enum ice_status ice_init_nvm(struct ice_hw *hw); 103 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data); 104 enum ice_status 105 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data); 106 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw); 107 #endif /* _ICE_NVM_H_ */ 108