1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <netinet/in.h> 14 #include <sys/queue.h> 15 16 #include <rte_pci.h> 17 #include <rte_ether.h> 18 #include <rte_ethdev_driver.h> 19 #include <rte_rwlock.h> 20 #include <rte_interrupts.h> 21 #include <rte_errno.h> 22 #include <rte_flow.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 30 #include "mlx5_defs.h" 31 #include "mlx5_utils.h" 32 #include "mlx5_os.h" 33 #include "mlx5_autoconf.h" 34 35 36 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 37 38 enum mlx5_ipool_index { 39 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 40 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 41 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 42 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 43 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 44 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 45 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 46 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 47 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 48 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 49 #endif 50 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 51 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 52 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 53 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 54 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 55 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 56 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 57 MLX5_IPOOL_MAX, 58 }; 59 60 /* 61 * There are three reclaim memory mode supported. 62 * 0(none) means no memory reclaim. 63 * 1(light) means only PMD level reclaim. 64 * 2(aggressive) means both PMD and rdma-core level reclaim. 65 */ 66 enum mlx5_reclaim_mem_mode { 67 MLX5_RCM_NONE, /* Don't reclaim memory. */ 68 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 69 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 70 }; 71 72 /* Hash and cache list callback context. */ 73 struct mlx5_flow_cb_ctx { 74 struct rte_eth_dev *dev; 75 struct rte_flow_error *error; 76 void *data; 77 }; 78 79 /* Device attributes used in mlx5 PMD */ 80 struct mlx5_dev_attr { 81 uint64_t device_cap_flags_ex; 82 int max_qp_wr; 83 int max_sge; 84 int max_cq; 85 int max_qp; 86 uint32_t raw_packet_caps; 87 uint32_t max_rwq_indirection_table_size; 88 uint32_t max_tso; 89 uint32_t tso_supported_qpts; 90 uint64_t flags; 91 uint64_t comp_mask; 92 uint32_t sw_parsing_offloads; 93 uint32_t min_single_stride_log_num_of_bytes; 94 uint32_t max_single_stride_log_num_of_bytes; 95 uint32_t min_single_wqe_log_num_of_strides; 96 uint32_t max_single_wqe_log_num_of_strides; 97 uint32_t stride_supported_qpts; 98 uint32_t tunnel_offloads_caps; 99 char fw_ver[64]; 100 }; 101 102 /** Data associated with devices to spawn. */ 103 struct mlx5_dev_spawn_data { 104 uint32_t ifindex; /**< Network interface index. */ 105 uint32_t max_port; /**< Device maximal port index. */ 106 uint32_t phys_port; /**< Device physical port index. */ 107 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 108 struct mlx5_switch_info info; /**< Switch information. */ 109 void *phys_dev; /**< Associated physical device. */ 110 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 111 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 112 }; 113 114 /** Key string for IPC. */ 115 #define MLX5_MP_NAME "net_mlx5_mp" 116 117 118 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 119 120 /* Shared data between primary and secondary processes. */ 121 struct mlx5_shared_data { 122 rte_spinlock_t lock; 123 /* Global spinlock for primary and secondary processes. */ 124 int init_done; /* Whether primary has done initialization. */ 125 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 126 struct mlx5_dev_list mem_event_cb_list; 127 rte_rwlock_t mem_event_rwlock; 128 }; 129 130 /* Per-process data structure, not visible to other processes. */ 131 struct mlx5_local_data { 132 int init_done; /* Whether a secondary has done initialization. */ 133 }; 134 135 extern struct mlx5_shared_data *mlx5_shared_data; 136 137 /* Dev ops structs */ 138 extern const struct eth_dev_ops mlx5_os_dev_ops; 139 extern const struct eth_dev_ops mlx5_os_dev_sec_ops; 140 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; 141 142 struct mlx5_counter_ctrl { 143 /* Name of the counter. */ 144 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 145 /* Name of the counter on the device table. */ 146 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 147 uint32_t dev:1; /**< Nonzero for dev counters. */ 148 }; 149 150 struct mlx5_xstats_ctrl { 151 /* Number of device stats. */ 152 uint16_t stats_n; 153 /* Number of device stats identified by PMD. */ 154 uint16_t mlx5_stats_n; 155 /* Index in the device counters table. */ 156 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 157 uint64_t base[MLX5_MAX_XSTATS]; 158 uint64_t xstats[MLX5_MAX_XSTATS]; 159 uint64_t hw_stats[MLX5_MAX_XSTATS]; 160 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 161 }; 162 163 struct mlx5_stats_ctrl { 164 /* Base for imissed counter. */ 165 uint64_t imissed_base; 166 uint64_t imissed; 167 }; 168 169 /* Default PMD specific parameter value. */ 170 #define MLX5_ARG_UNSET (-1) 171 172 #define MLX5_LRO_SUPPORTED(dev) \ 173 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 174 175 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 176 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 177 178 /* Maximal size of aggregated LRO packet. */ 179 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 180 181 /* Maximal number of segments to split. */ 182 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 183 184 /* LRO configurations structure. */ 185 struct mlx5_lro_config { 186 uint32_t supported:1; /* Whether LRO is supported. */ 187 uint32_t timeout; /* User configuration. */ 188 }; 189 190 /* 191 * Device configuration structure. 192 * 193 * Merged configuration from: 194 * 195 * - Device capabilities, 196 * - User device parameters disabled features. 197 */ 198 struct mlx5_dev_config { 199 unsigned int hw_csum:1; /* Checksum offload is supported. */ 200 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 201 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 202 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 203 unsigned int hw_padding:1; /* End alignment padding is supported. */ 204 unsigned int vf:1; /* This is a VF. */ 205 unsigned int tunnel_en:1; 206 /* Whether tunnel stateless offloads are supported. */ 207 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 208 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 209 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 210 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 211 unsigned int tso:1; /* Whether TSO is supported. */ 212 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 213 unsigned int mr_ext_memseg_en:1; 214 /* Whether memseg should be extended for MR creation. */ 215 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 216 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 217 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 218 unsigned int dv_flow_en:1; /* Enable DV flow. */ 219 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 220 unsigned int lacp_by_user:1; 221 /* Enable user to manage LACP traffic. */ 222 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 223 unsigned int devx:1; /* Whether devx interface is available or not. */ 224 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 225 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 226 unsigned int rt_timestamp:1; /* realtime timestamp format. */ 227 unsigned int sys_mem_en:1; /* The default memory allocator. */ 228 unsigned int decap_en:1; /* Whether decap will be used or not. */ 229 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ 230 struct { 231 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 232 unsigned int stride_num_n; /* Number of strides. */ 233 unsigned int stride_size_n; /* Size of a stride. */ 234 unsigned int min_stride_size_n; /* Min size of a stride. */ 235 unsigned int max_stride_size_n; /* Max size of a stride. */ 236 unsigned int max_memcpy_len; 237 /* Maximum packet size to memcpy Rx packets. */ 238 unsigned int min_rxqs_num; 239 /* Rx queue count threshold to enable MPRQ. */ 240 } mprq; /* Configurations for Multi-Packet RQ. */ 241 int mps; /* Multi-packet send supported mode. */ 242 int dbnc; /* Skip doorbell register write barrier. */ 243 unsigned int flow_prio; /* Number of flow priorities. */ 244 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 245 /* Availibility of mreg_c's. */ 246 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 247 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 248 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 249 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 250 int txqs_inline; /* Queue number threshold for inlining. */ 251 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 252 int txq_inline_max; /* Max packet size for inlining with SEND. */ 253 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 254 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 255 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 256 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 257 struct mlx5_lro_config lro; /* LRO configuration. */ 258 }; 259 260 261 /** 262 * Type of object being allocated. 263 */ 264 enum mlx5_verbs_alloc_type { 265 MLX5_VERBS_ALLOC_TYPE_NONE, 266 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 267 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 268 }; 269 270 /* Structure for VF VLAN workaround. */ 271 struct mlx5_vf_vlan { 272 uint32_t tag:12; 273 uint32_t created:1; 274 }; 275 276 /** 277 * Verbs allocator needs a context to know in the callback which kind of 278 * resources it is allocating. 279 */ 280 struct mlx5_verbs_alloc_ctx { 281 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 282 const void *obj; /* Pointer to the DPDK object. */ 283 }; 284 285 /* Flow drop context necessary due to Verbs API. */ 286 struct mlx5_drop { 287 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 288 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 289 }; 290 291 #define MLX5_COUNTERS_PER_POOL 512 292 #define MLX5_MAX_PENDING_QUERIES 4 293 #define MLX5_CNT_CONTAINER_RESIZE 64 294 #define MLX5_CNT_SHARED_OFFSET 0x80000000 295 #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) 296 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 297 MLX5_CNT_BATCH_OFFSET) 298 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 299 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 300 301 #define MLX5_CNT_LEN(pool) \ 302 (MLX5_CNT_SIZE + \ 303 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 304 #define MLX5_POOL_GET_CNT(pool, index) \ 305 ((struct mlx5_flow_counter *) \ 306 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 307 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 308 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 309 MLX5_CNT_LEN(pool))) 310 /* 311 * The pool index and offset of counter in the pool array makes up the 312 * counter index. In case the counter is from pool 0 and offset 0, it 313 * should plus 1 to avoid index 0, since 0 means invalid counter index 314 * currently. 315 */ 316 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 317 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 318 #define MLX5_CNT_TO_AGE(cnt) \ 319 ((struct mlx5_age_param *)((cnt) + 1)) 320 /* 321 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 322 * defines. The pool size is 512, pool index should never reach 323 * INT16_MAX. 324 */ 325 #define POOL_IDX_INVALID UINT16_MAX 326 327 /* Age status. */ 328 enum { 329 AGE_FREE, /* Initialized state. */ 330 AGE_CANDIDATE, /* Counter assigned to flows. */ 331 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 332 }; 333 334 enum mlx5_counter_type { 335 MLX5_COUNTER_TYPE_ORIGIN, 336 MLX5_COUNTER_TYPE_AGE, 337 MLX5_COUNTER_TYPE_MAX, 338 }; 339 340 /* Counter age parameter. */ 341 struct mlx5_age_param { 342 uint16_t state; /**< Age state (atomically accessed). */ 343 uint16_t port_id; /**< Port id of the counter. */ 344 uint32_t timeout:24; /**< Aging timeout in seconds. */ 345 uint32_t sec_since_last_hit; 346 /**< Time in seconds since last hit (atomically accessed). */ 347 void *context; /**< Flow counter age context. */ 348 }; 349 350 struct flow_counter_stats { 351 uint64_t hits; 352 uint64_t bytes; 353 }; 354 355 /* Shared counters information for counters. */ 356 struct mlx5_flow_counter_shared { 357 uint32_t id; /**< User counter ID. */ 358 }; 359 360 /* Shared counter configuration. */ 361 struct mlx5_shared_counter_conf { 362 struct rte_eth_dev *dev; /* The device shared counter belongs to. */ 363 uint32_t id; /* The shared counter ID. */ 364 }; 365 366 struct mlx5_flow_counter_pool; 367 /* Generic counters information. */ 368 struct mlx5_flow_counter { 369 union { 370 /* 371 * User-defined counter shared info is only used during 372 * counter active time. And aging counter sharing is not 373 * supported, so active shared counter will not be chained 374 * to the aging list. For shared counter, only when it is 375 * released, the TAILQ entry memory will be used, at that 376 * time, shared memory is not used anymore. 377 * 378 * Similarly to none-batch counter dcs, since it doesn't 379 * support aging, while counter is allocated, the entry 380 * memory is not used anymore. In this case, as bytes 381 * memory is used only when counter is allocated, and 382 * entry memory is used only when counter is free. The 383 * dcs pointer can be saved to these two different place 384 * at different stage. It will eliminate the individual 385 * counter extend struct. 386 */ 387 TAILQ_ENTRY(mlx5_flow_counter) next; 388 /**< Pointer to the next flow counter structure. */ 389 struct { 390 struct mlx5_flow_counter_shared shared_info; 391 /**< Shared counter information. */ 392 void *dcs_when_active; 393 /* 394 * For non-batch mode, the dcs will be saved 395 * here when the counter is free. 396 */ 397 }; 398 }; 399 union { 400 uint64_t hits; /**< Reset value of hits packets. */ 401 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 402 }; 403 union { 404 uint64_t bytes; /**< Reset value of bytes. */ 405 void *dcs_when_free; 406 /* 407 * For non-batch mode, the dcs will be saved here 408 * when the counter is free. 409 */ 410 }; 411 void *action; /**< Pointer to the dv action. */ 412 }; 413 414 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 415 416 /* Generic counter pool structure - query is in pool resolution. */ 417 struct mlx5_flow_counter_pool { 418 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 419 struct mlx5_counters counters[2]; /* Free counter list. */ 420 struct mlx5_devx_obj *min_dcs; 421 /* The devx object of the minimum counter ID. */ 422 uint64_t time_of_last_age_check; 423 /* System time (from rte_rdtsc()) read in the last aging check. */ 424 uint32_t index:30; /* Pool index in container. */ 425 uint32_t is_aged:1; /* Pool with aging counter. */ 426 volatile uint32_t query_gen:1; /* Query round. */ 427 rte_spinlock_t sl; /* The pool lock. */ 428 rte_spinlock_t csl; /* The pool counter free list lock. */ 429 struct mlx5_counter_stats_raw *raw; 430 struct mlx5_counter_stats_raw *raw_hw; 431 /* The raw on HW working. */ 432 }; 433 434 /* Memory management structure for group of counter statistics raws. */ 435 struct mlx5_counter_stats_mem_mng { 436 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 437 struct mlx5_counter_stats_raw *raws; 438 struct mlx5_devx_obj *dm; 439 void *umem; 440 }; 441 442 /* Raw memory structure for the counter statistics values of a pool. */ 443 struct mlx5_counter_stats_raw { 444 LIST_ENTRY(mlx5_counter_stats_raw) next; 445 struct mlx5_counter_stats_mem_mng *mem_mng; 446 volatile struct flow_counter_stats *data; 447 }; 448 449 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 450 451 /* Counter global management structure. */ 452 struct mlx5_flow_counter_mng { 453 volatile uint16_t n_valid; /* Number of valid pools. */ 454 uint16_t n; /* Number of pools. */ 455 uint16_t last_pool_idx; /* Last used pool index */ 456 int min_id; /* The minimum counter ID in the pools. */ 457 int max_id; /* The maximum counter ID in the pools. */ 458 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 459 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 460 /* The counter free list lock. */ 461 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 462 /* Free counter list. */ 463 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 464 struct mlx5_counter_stats_mem_mng *mem_mng; 465 /* Hold the memory management for the next allocated pools raws. */ 466 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 467 uint8_t pending_queries; 468 uint16_t pool_index; 469 uint8_t query_thread_on; 470 bool relaxed_ordering_read; 471 bool relaxed_ordering_write; 472 bool counter_fallback; /* Use counter fallback management. */ 473 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 474 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 475 }; 476 477 /* ASO structures. */ 478 #define MLX5_ASO_QUEUE_LOG_DESC 10 479 480 struct mlx5_aso_cq { 481 uint16_t log_desc_n; 482 uint32_t cq_ci:24; 483 struct mlx5_devx_obj *cq; 484 struct mlx5dv_devx_umem *umem_obj; 485 union { 486 volatile void *umem_buf; 487 volatile struct mlx5_cqe *cqes; 488 }; 489 volatile uint32_t *db_rec; 490 uint64_t errors; 491 }; 492 493 struct mlx5_aso_devx_mr { 494 void *buf; 495 uint64_t length; 496 struct mlx5dv_devx_umem *umem; 497 struct mlx5_devx_obj *mkey; 498 bool is_indirect; 499 }; 500 501 struct mlx5_aso_sq_elem { 502 struct mlx5_aso_age_pool *pool; 503 uint16_t burst_size; 504 }; 505 506 struct mlx5_aso_sq { 507 uint16_t log_desc_n; 508 struct mlx5_aso_cq cq; 509 struct mlx5_devx_obj *sq; 510 struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */ 511 union { 512 volatile void *umem_buf; 513 volatile struct mlx5_aso_wqe *wqes; 514 }; 515 volatile uint32_t *db_rec; 516 volatile uint64_t *uar_addr; 517 struct mlx5_aso_devx_mr mr; 518 uint16_t pi; 519 uint32_t head; 520 uint32_t tail; 521 uint32_t sqn; 522 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 523 uint16_t next; /* Pool index of the next pool to query. */ 524 }; 525 526 struct mlx5_aso_age_action { 527 LIST_ENTRY(mlx5_aso_age_action) next; 528 void *dr_action; 529 uint32_t refcnt; 530 /* Following fields relevant only when action is active. */ 531 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 532 struct mlx5_age_param age_params; 533 }; 534 535 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 536 537 struct mlx5_aso_age_pool { 538 struct mlx5_devx_obj *flow_hit_aso_obj; 539 uint16_t index; /* Pool index in pools array. */ 540 uint64_t time_of_last_age_check; /* In seconds. */ 541 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 542 }; 543 544 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 545 546 struct mlx5_aso_age_mng { 547 struct mlx5_aso_age_pool **pools; 548 uint16_t n; /* Total number of pools. */ 549 uint16_t next; /* Number of pools in use, index of next free pool. */ 550 rte_spinlock_t resize_sl; /* Lock for resize objects. */ 551 rte_spinlock_t free_sl; /* Lock for free list access. */ 552 struct aso_age_list free; /* Free age actions list - ready to use. */ 553 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 554 }; 555 556 #define MLX5_AGE_EVENT_NEW 1 557 #define MLX5_AGE_TRIGGER 2 558 #define MLX5_AGE_SET(age_info, BIT) \ 559 ((age_info)->flags |= (1 << (BIT))) 560 #define MLX5_AGE_GET(age_info, BIT) \ 561 ((age_info)->flags & (1 << (BIT))) 562 #define GET_PORT_AGE_INFO(priv) \ 563 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 564 /* Current time in seconds. */ 565 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 566 567 /* Aging information for per port. */ 568 struct mlx5_age_info { 569 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 570 struct mlx5_counters aged_counters; /* Aged counter list. */ 571 struct aso_age_list aged_aso; /* Aged ASO actions list. */ 572 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 573 }; 574 575 /* Per port data of shared IB device. */ 576 struct mlx5_dev_shared_port { 577 uint32_t ih_port_id; 578 uint32_t devx_ih_port_id; 579 /* 580 * Interrupt handler port_id. Used by shared interrupt 581 * handler to find the corresponding rte_eth device 582 * by IB port index. If value is equal or greater 583 * RTE_MAX_ETHPORTS it means there is no subhandler 584 * installed for specified IB port index. 585 */ 586 struct mlx5_age_info age_info; 587 /* Aging information for per port. */ 588 }; 589 590 /* Table key of the hash organization. */ 591 union mlx5_flow_tbl_key { 592 struct { 593 /* Table ID should be at the lowest address. */ 594 uint32_t table_id; /**< ID of the table. */ 595 uint16_t dummy; /**< Dummy table for DV API. */ 596 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ 597 uint8_t direction; /**< 1 - egress, 0 - ingress. */ 598 }; 599 uint64_t v64; /**< full 64bits value of key */ 600 }; 601 602 /* Table structure. */ 603 struct mlx5_flow_tbl_resource { 604 void *obj; /**< Pointer to DR table object. */ 605 uint32_t refcnt; /**< Reference counter. */ 606 }; 607 608 #define MLX5_MAX_TABLES UINT16_MAX 609 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 610 /* Reserve the last two tables for metadata register copy. */ 611 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 612 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 613 /* Tables for metering splits should be added here. */ 614 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3) 615 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) 616 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_METER 617 #define MLX5_MAX_TABLES_FDB UINT16_MAX 618 #define MLX5_FLOW_TABLE_FACTOR 10 619 620 /* ID generation structure. */ 621 struct mlx5_flow_id_pool { 622 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 623 uint32_t base_index; 624 /**< The next index that can be used without any free elements. */ 625 uint32_t *curr; /**< Pointer to the index to pop. */ 626 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 627 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 628 }; 629 630 /* Tx pacing queue structure - for Clock and Rearm queues. */ 631 struct mlx5_txpp_wq { 632 /* Completion Queue related data.*/ 633 struct mlx5_devx_obj *cq; 634 void *cq_umem; 635 union { 636 volatile void *cq_buf; 637 volatile struct mlx5_cqe *cqes; 638 }; 639 volatile uint32_t *cq_dbrec; 640 uint32_t cq_ci:24; 641 uint32_t arm_sn:2; 642 /* Send Queue related data.*/ 643 struct mlx5_devx_obj *sq; 644 void *sq_umem; 645 union { 646 volatile void *sq_buf; 647 volatile struct mlx5_wqe *wqes; 648 }; 649 uint16_t sq_size; /* Number of WQEs in the queue. */ 650 uint16_t sq_ci; /* Next WQE to execute. */ 651 volatile uint32_t *sq_dbrec; 652 }; 653 654 /* Tx packet pacing internal timestamp. */ 655 struct mlx5_txpp_ts { 656 uint64_t ci_ts; 657 uint64_t ts; 658 }; 659 660 /* Tx packet pacing structure. */ 661 struct mlx5_dev_txpp { 662 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 663 uint32_t refcnt; /* Pacing reference counter. */ 664 uint32_t freq; /* Timestamp frequency, Hz. */ 665 uint32_t tick; /* Completion tick duration in nanoseconds. */ 666 uint32_t test; /* Packet pacing test mode. */ 667 int32_t skew; /* Scheduling skew. */ 668 struct rte_intr_handle intr_handle; /* Periodic interrupt. */ 669 void *echan; /* Event Channel. */ 670 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 671 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 672 void *pp; /* Packet pacing context. */ 673 uint16_t pp_id; /* Packet pacing context index. */ 674 uint16_t ts_n; /* Number of captured timestamps. */ 675 uint16_t ts_p; /* Pointer to statisticks timestamp. */ 676 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 677 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 678 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 679 /* Statistics counters. */ 680 uint64_t err_miss_int; /* Missed service interrupt. */ 681 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 682 uint64_t err_clock_queue; /* Clock Queue errors. */ 683 uint64_t err_ts_past; /* Timestamp in the past. */ 684 uint64_t err_ts_future; /* Timestamp in the distant future. */ 685 }; 686 687 /* Supported flex parser profile ID. */ 688 enum mlx5_flex_parser_profile_id { 689 MLX5_FLEX_PARSER_ECPRI_0 = 0, 690 MLX5_FLEX_PARSER_MAX = 8, 691 }; 692 693 /* Sample ID information of flex parser structure. */ 694 struct mlx5_flex_parser_profiles { 695 uint32_t num; /* Actual number of samples. */ 696 uint32_t ids[8]; /* Sample IDs for this profile. */ 697 uint8_t offset[8]; /* Bytes offset of each parser. */ 698 void *obj; /* Flex parser node object. */ 699 }; 700 701 /* 702 * Shared Infiniband device context for Master/Representors 703 * which belong to same IB device with multiple IB ports. 704 **/ 705 struct mlx5_dev_ctx_shared { 706 LIST_ENTRY(mlx5_dev_ctx_shared) next; 707 uint32_t refcnt; 708 uint16_t bond_dev; /* Bond primary device id. */ 709 uint32_t devx:1; /* Opened with DV. */ 710 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 711 uint32_t eqn; /* Event Queue number. */ 712 uint32_t max_port; /* Maximal IB device port index. */ 713 void *ctx; /* Verbs/DV/DevX context. */ 714 void *pd; /* Protection Domain. */ 715 uint32_t pdn; /* Protection Domain number. */ 716 uint32_t tdn; /* Transport Domain number. */ 717 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */ 718 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */ 719 struct mlx5_dev_attr device_attr; /* Device properties. */ 720 int numa_node; /* Numa node of backing physical device. */ 721 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; 722 /**< Called by memory event callback. */ 723 struct mlx5_mr_share_cache share_cache; 724 /* Packet pacing related structure. */ 725 struct mlx5_dev_txpp txpp; 726 /* Shared DV/DR flow data section. */ 727 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 728 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 729 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 730 void *fdb_domain; /* FDB Direct Rules name space handle. */ 731 void *rx_domain; /* RX Direct Rules name space handle. */ 732 void *tx_domain; /* TX Direct Rules name space handle. */ 733 #ifndef RTE_ARCH_64 734 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 735 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 736 /* UAR same-page access control required in 32bit implementations. */ 737 #endif 738 struct mlx5_hlist *flow_tbls; 739 struct mlx5_flow_tunnel_hub *tunnel_hub; 740 /* Direct Rules tables for FDB, NIC TX+RX */ 741 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 742 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 743 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 744 struct mlx5_hlist *modify_cmds; 745 struct mlx5_hlist *tag_table; 746 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */ 747 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */ 748 struct mlx5_cache_list sample_action_list; /* List of sample actions. */ 749 struct mlx5_cache_list dest_array_list; 750 /* List of destination array actions. */ 751 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 752 void *default_miss_action; /* Default miss action. */ 753 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 754 /* Memory Pool for mlx5 flow resources. */ 755 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ 756 /* Shared interrupt handler section. */ 757 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 758 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 759 void *devx_comp; /* DEVX async comp obj. */ 760 struct mlx5_devx_obj *tis; /* TIS object. */ 761 struct mlx5_devx_obj *td; /* Transport domain. */ 762 void *tx_uar; /* Tx/packet pacing shared UAR. */ 763 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; 764 /* Flex parser profiles information. */ 765 void *devx_rx_uar; /* DevX UAR for Rx. */ 766 struct mlx5_aso_age_mng *aso_age_mng; 767 /* Management data for aging mechanism using ASO Flow Hit. */ 768 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 769 }; 770 771 /* Per-process private structure. */ 772 struct mlx5_proc_priv { 773 size_t uar_table_sz; 774 /* Size of UAR register table. */ 775 void *uar_table[]; 776 /* Table of UAR registers for each process. */ 777 }; 778 779 /* MTR profile list. */ 780 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 781 /* MTR list. */ 782 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); 783 784 /* RSS description. */ 785 struct mlx5_flow_rss_desc { 786 uint32_t level; 787 uint32_t queue_num; /**< Number of entries in @p queue. */ 788 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 789 uint64_t hash_fields; /* Verbs Hash fields. */ 790 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 791 uint32_t key_len; /**< RSS hash key len. */ 792 uint32_t tunnel; /**< Queue in tunnel. */ 793 uint32_t shared_rss; /**< Shared RSS index. */ 794 struct mlx5_ind_table_obj *ind_tbl; 795 /**< Indirection table for shared RSS hash RX queues. */ 796 union { 797 uint16_t *queue; /**< Destination queues. */ 798 const uint16_t *const_q; /**< Const pointer convert. */ 799 }; 800 }; 801 802 #define MLX5_PROC_PRIV(port_id) \ 803 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 804 805 /* Verbs/DevX Rx queue elements. */ 806 struct mlx5_rxq_obj { 807 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 808 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 809 int fd; /* File descriptor for event channel */ 810 RTE_STD_C11 811 union { 812 struct { 813 void *wq; /* Work Queue. */ 814 void *ibv_cq; /* Completion Queue. */ 815 void *ibv_channel; 816 }; 817 struct { 818 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */ 819 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */ 820 void *devx_channel; 821 }; 822 }; 823 }; 824 825 /* Indirection table. */ 826 struct mlx5_ind_table_obj { 827 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 828 uint32_t refcnt; /* Reference counter. */ 829 RTE_STD_C11 830 union { 831 void *ind_table; /**< Indirection table. */ 832 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 833 }; 834 uint32_t queues_n; /**< Number of queues in the list. */ 835 uint16_t *queues; /**< Queue list. */ 836 }; 837 838 /* Hash Rx queue. */ 839 __extension__ 840 struct mlx5_hrxq { 841 struct mlx5_cache_entry entry; /* Cache entry. */ 842 uint32_t standalone:1; /* This object used in shared action. */ 843 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 844 RTE_STD_C11 845 union { 846 void *qp; /* Verbs queue pair. */ 847 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 848 }; 849 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 850 void *action; /* DV QP action pointer. */ 851 #endif 852 uint64_t hash_fields; /* Verbs Hash fields. */ 853 uint32_t rss_key_len; /* Hash key length in bytes. */ 854 uint32_t idx; /* Hash Rx queue index. */ 855 uint8_t rss_key[]; /* Hash key. */ 856 }; 857 858 /* Verbs/DevX Tx queue elements. */ 859 struct mlx5_txq_obj { 860 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 861 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 862 RTE_STD_C11 863 union { 864 struct { 865 void *cq; /* Completion Queue. */ 866 void *qp; /* Queue Pair. */ 867 }; 868 struct { 869 struct mlx5_devx_obj *sq; 870 /* DevX object for Sx queue. */ 871 struct mlx5_devx_obj *tis; /* The TIS object. */ 872 }; 873 struct { 874 struct rte_eth_dev *dev; 875 struct mlx5_devx_obj *cq_devx; 876 void *cq_umem; 877 void *cq_buf; 878 int64_t cq_dbrec_offset; 879 struct mlx5_devx_dbr_page *cq_dbrec_page; 880 struct mlx5_devx_obj *sq_devx; 881 void *sq_umem; 882 void *sq_buf; 883 int64_t sq_dbrec_offset; 884 struct mlx5_devx_dbr_page *sq_dbrec_page; 885 }; 886 }; 887 }; 888 889 enum mlx5_rxq_modify_type { 890 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 891 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 892 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 893 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 894 }; 895 896 enum mlx5_txq_modify_type { 897 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 898 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 899 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 900 }; 901 902 /* HW objects operations structure. */ 903 struct mlx5_obj_ops { 904 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); 905 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 906 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 907 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type); 908 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); 909 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 910 struct mlx5_ind_table_obj *ind_tbl); 911 int (*ind_table_modify)(struct rte_eth_dev *dev, 912 const unsigned int log_n, 913 const uint16_t *queues, const uint32_t queues_n, 914 struct mlx5_ind_table_obj *ind_tbl); 915 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 916 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 917 int tunnel __rte_unused); 918 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 919 const uint8_t *rss_key, 920 uint64_t hash_fields, 921 const struct mlx5_ind_table_obj *ind_tbl); 922 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 923 int (*drop_action_create)(struct rte_eth_dev *dev); 924 void (*drop_action_destroy)(struct rte_eth_dev *dev); 925 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 926 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 927 enum mlx5_txq_modify_type type, uint8_t dev_port); 928 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 929 }; 930 931 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 932 933 struct mlx5_priv { 934 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 935 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 936 uint32_t dev_port; /* Device port number. */ 937 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 938 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 939 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 940 /* Bit-field of MAC addresses owned by the PMD. */ 941 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 942 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 943 /* Device properties. */ 944 uint16_t mtu; /* Configured MTU. */ 945 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 946 unsigned int representor:1; /* Device is a port representor. */ 947 unsigned int master:1; /* Device is a E-Switch master. */ 948 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 949 unsigned int mtr_en:1; /* Whether support meter. */ 950 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 951 unsigned int sampler_en:1; /* Whether support sampler. */ 952 uint16_t domain_id; /* Switch domain identifier. */ 953 uint16_t vport_id; /* Associated VF vport index (if any). */ 954 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 955 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 956 int32_t representor_id; /* Port representor identifier. */ 957 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ 958 unsigned int if_index; /* Associated kernel network device index. */ 959 uint32_t bond_ifindex; /**< Bond interface index. */ 960 char bond_name[IF_NAMESIZE]; /**< Bond interface name. */ 961 /* RX/TX queues. */ 962 unsigned int rxqs_n; /* RX queues array size. */ 963 unsigned int txqs_n; /* TX queues array size. */ 964 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 965 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 966 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 967 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 968 unsigned int (*reta_idx)[]; /* RETA index table. */ 969 unsigned int reta_idx_n; /* RETA index size. */ 970 struct mlx5_drop drop_queue; /* Flow drop queues. */ 971 uint32_t flows; /* RTE Flow rules. */ 972 uint32_t ctrl_flows; /* Control flow rules. */ 973 rte_spinlock_t flow_list_lock; 974 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 975 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 976 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 977 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */ 978 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 979 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 980 /* Indirection tables. */ 981 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 982 /* Pointer to next element. */ 983 uint32_t refcnt; /**< Reference counter. */ 984 /**< Verbs modify header action object. */ 985 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 986 uint8_t max_lro_msg_size; 987 /* Tags resources cache. */ 988 uint32_t link_speed_capa; /* Link speed capabilities. */ 989 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 990 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 991 struct mlx5_dev_config config; /* Device configuration. */ 992 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 993 /* Context for Verbs allocator. */ 994 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 995 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 996 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ 997 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 998 struct mlx5_hlist *mreg_cp_tbl; 999 /* Hash table of Rx metadata register copy table. */ 1000 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 1001 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 1002 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 1003 struct mlx5_flow_meters flow_meters; /* MTR list. */ 1004 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 1005 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1006 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1007 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1008 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1009 uint32_t rss_shared_actions; /* RSS shared actions. */ 1010 }; 1011 1012 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1013 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1014 1015 struct rte_hairpin_peer_info { 1016 uint32_t qp_id; 1017 uint32_t vhca_id; 1018 uint16_t peer_q; 1019 uint16_t tx_explicit; 1020 uint16_t manual_bind; 1021 }; 1022 1023 /* mlx5.c */ 1024 1025 int mlx5_getenv_int(const char *); 1026 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1027 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1028 struct rte_eth_udp_tunnel *udp_tunnel); 1029 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 1030 int mlx5_dev_close(struct rte_eth_dev *dev); 1031 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1032 1033 /* Macro to iterate over all valid ports for mlx5 driver. */ 1034 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 1035 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 1036 port_id < RTE_MAX_ETHPORTS; \ 1037 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 1038 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 1039 struct mlx5_dev_ctx_shared * 1040 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1041 const struct mlx5_dev_config *config); 1042 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1043 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1044 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1045 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1046 struct mlx5_dev_config *config); 1047 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1048 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 1049 struct mlx5_dev_config *config); 1050 int mlx5_dev_configure(struct rte_eth_dev *dev); 1051 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1052 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1053 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1054 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1055 struct rte_eth_hairpin_cap *cap); 1056 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1057 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1058 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1059 1060 /* mlx5_ethdev.c */ 1061 1062 int mlx5_dev_configure(struct rte_eth_dev *dev); 1063 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 1064 size_t fw_size); 1065 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 1066 struct rte_eth_dev_info *info); 1067 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1068 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1069 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1070 struct rte_eth_hairpin_cap *cap); 1071 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1072 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1073 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1074 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1075 1076 /* mlx5_ethdev_os.c */ 1077 1078 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1079 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1080 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1081 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1082 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1083 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1084 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1085 struct rte_eth_fc_conf *fc_conf); 1086 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1087 struct rte_eth_fc_conf *fc_conf); 1088 void mlx5_dev_interrupt_handler(void *arg); 1089 void mlx5_dev_interrupt_handler_devx(void *arg); 1090 int mlx5_set_link_down(struct rte_eth_dev *dev); 1091 int mlx5_set_link_up(struct rte_eth_dev *dev); 1092 int mlx5_is_removed(struct rte_eth_dev *dev); 1093 int mlx5_sysfs_switch_info(unsigned int ifindex, 1094 struct mlx5_switch_info *info); 1095 void mlx5_translate_port_name(const char *port_name_in, 1096 struct mlx5_switch_info *port_info_out); 1097 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 1098 rte_intr_callback_fn cb_fn, void *cb_arg); 1099 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1100 char *ifname); 1101 int mlx5_get_module_info(struct rte_eth_dev *dev, 1102 struct rte_eth_dev_module_info *modinfo); 1103 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1104 struct rte_dev_eeprom_info *info); 1105 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1106 const char *ctr_name, uint64_t *stat); 1107 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1108 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1109 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1110 1111 /* mlx5_mac.c */ 1112 1113 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1114 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1115 uint32_t index, uint32_t vmdq); 1116 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1117 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1118 struct rte_ether_addr *mc_addr_set, 1119 uint32_t nb_mc_addr); 1120 1121 /* mlx5_rss.c */ 1122 1123 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1124 struct rte_eth_rss_conf *rss_conf); 1125 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1126 struct rte_eth_rss_conf *rss_conf); 1127 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1128 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1129 struct rte_eth_rss_reta_entry64 *reta_conf, 1130 uint16_t reta_size); 1131 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1132 struct rte_eth_rss_reta_entry64 *reta_conf, 1133 uint16_t reta_size); 1134 1135 /* mlx5_rxmode.c */ 1136 1137 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1138 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1139 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1140 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1141 1142 /* mlx5_stats.c */ 1143 1144 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1145 int mlx5_stats_reset(struct rte_eth_dev *dev); 1146 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1147 unsigned int n); 1148 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1149 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1150 struct rte_eth_xstat_name *xstats_names, 1151 unsigned int n); 1152 1153 /* mlx5_vlan.c */ 1154 1155 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1156 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1157 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1158 1159 /* mlx5_vlan_os.c */ 1160 1161 void mlx5_vlan_vmwa_exit(void *ctx); 1162 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1163 struct mlx5_vf_vlan *vf_vlan); 1164 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1165 struct mlx5_vf_vlan *vf_vlan); 1166 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1167 1168 /* mlx5_trigger.c */ 1169 1170 int mlx5_dev_start(struct rte_eth_dev *dev); 1171 int mlx5_dev_stop(struct rte_eth_dev *dev); 1172 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1173 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1174 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1175 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1176 struct rte_hairpin_peer_info *current_info, 1177 struct rte_hairpin_peer_info *peer_info, 1178 uint32_t direction); 1179 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 1180 struct rte_hairpin_peer_info *peer_info, 1181 uint32_t direction); 1182 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 1183 uint32_t direction); 1184 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 1185 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 1186 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 1187 size_t len, uint32_t direction); 1188 1189 /* mlx5_flow.c */ 1190 1191 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1192 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1193 void mlx5_flow_print(struct rte_flow *flow); 1194 int mlx5_flow_validate(struct rte_eth_dev *dev, 1195 const struct rte_flow_attr *attr, 1196 const struct rte_flow_item items[], 1197 const struct rte_flow_action actions[], 1198 struct rte_flow_error *error); 1199 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1200 const struct rte_flow_attr *attr, 1201 const struct rte_flow_item items[], 1202 const struct rte_flow_action actions[], 1203 struct rte_flow_error *error); 1204 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1205 struct rte_flow_error *error); 1206 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active); 1207 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1208 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1209 const struct rte_flow_action *action, void *data, 1210 struct rte_flow_error *error); 1211 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1212 struct rte_flow_error *error); 1213 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 1214 enum rte_filter_type filter_type, 1215 enum rte_filter_op filter_op, 1216 void *arg); 1217 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1218 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1219 int mlx5_flow_verify(struct rte_eth_dev *dev); 1220 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1221 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1222 struct rte_flow_item_eth *eth_spec, 1223 struct rte_flow_item_eth *eth_mask, 1224 struct rte_flow_item_vlan *vlan_spec, 1225 struct rte_flow_item_vlan *vlan_mask); 1226 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1227 struct rte_flow_item_eth *eth_spec, 1228 struct rte_flow_item_eth *eth_mask); 1229 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1230 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1231 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 1232 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 1233 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1234 uint64_t async_id, int status); 1235 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1236 void mlx5_flow_query_alarm(void *arg); 1237 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1238 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1239 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1240 bool clear, uint64_t *pkts, uint64_t *bytes); 1241 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, 1242 struct rte_flow_error *error); 1243 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1244 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1245 uint32_t nb_contexts, struct rte_flow_error *error); 1246 1247 /* mlx5_mp_os.c */ 1248 1249 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1250 const void *peer); 1251 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1252 const void *peer); 1253 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1254 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1255 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1256 enum mlx5_mp_req_type req_type); 1257 1258 /* mlx5_socket.c */ 1259 1260 int mlx5_pmd_socket_init(void); 1261 1262 /* mlx5_flow_meter.c */ 1263 1264 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1265 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, 1266 uint32_t meter_id); 1267 struct mlx5_flow_meter *mlx5_flow_meter_attach 1268 (struct mlx5_priv *priv, 1269 uint32_t meter_id, 1270 const struct rte_flow_attr *attr, 1271 struct rte_flow_error *error); 1272 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); 1273 1274 /* mlx5_os.c */ 1275 struct rte_pci_driver; 1276 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); 1277 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1278 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 1279 const struct mlx5_dev_config *config, 1280 struct mlx5_dev_ctx_shared *sh); 1281 int mlx5_os_get_pdn(void *pd, uint32_t *pdn); 1282 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1283 struct rte_pci_device *pci_dev); 1284 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1285 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1286 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 1287 mlx5_dereg_mr_t *dereg_mr_cb); 1288 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1289 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1290 uint32_t index); 1291 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1292 struct rte_ether_addr *mac_addr, 1293 int vf_index); 1294 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1295 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1296 int mlx5_os_set_nonblock_channel_fd(int fd); 1297 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1298 1299 /* mlx5_txpp.c */ 1300 1301 int mlx5_txpp_start(struct rte_eth_dev *dev); 1302 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1303 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1304 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1305 struct rte_eth_xstat *stats, 1306 unsigned int n, unsigned int n_used); 1307 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1308 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1309 struct rte_eth_xstat_name *xstats_names, 1310 unsigned int n, unsigned int n_used); 1311 void mlx5_txpp_interrupt_handler(void *cb_arg); 1312 1313 /* mlx5_rxtx.c */ 1314 1315 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1316 1317 /* mlx5_flow_age.c */ 1318 1319 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh); 1320 int mlx5_aso_queue_start(struct mlx5_dev_ctx_shared *sh); 1321 int mlx5_aso_queue_stop(struct mlx5_dev_ctx_shared *sh); 1322 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh); 1323 1324 #endif /* RTE_PMD_MLX5_H_ */ 1325